WO2023020494A1 - Procédé de destruction intelligente basé sur un processeur loongson - Google Patents

Procédé de destruction intelligente basé sur un processeur loongson Download PDF

Info

Publication number
WO2023020494A1
WO2023020494A1 PCT/CN2022/112794 CN2022112794W WO2023020494A1 WO 2023020494 A1 WO2023020494 A1 WO 2023020494A1 CN 2022112794 W CN2022112794 W CN 2022112794W WO 2023020494 A1 WO2023020494 A1 WO 2023020494A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory chip
embedded memory
power supply
voltage
signal
Prior art date
Application number
PCT/CN2022/112794
Other languages
English (en)
Chinese (zh)
Inventor
李修录
尹善腾
朱小聪
吴健全
Original Assignee
深圳市安信达存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市安信达存储技术有限公司 filed Critical 深圳市安信达存储技术有限公司
Publication of WO2023020494A1 publication Critical patent/WO2023020494A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2143—Clearing memory, e.g. to prevent the data from being stolen

Definitions

  • the embodiment of the present invention relates to the technical field of chip processing, and in particular to an intelligent destruction method based on a Godson processor.
  • the purpose of the embodiments of the present invention is to provide a Godson processor-based intelligent destruction method to solve the problems of slow data transmission rate and low data security in the prior art.
  • the embodiment of the present invention shows a method of intelligent destruction based on the Godson processor, the upper board of the Godson processor is pasted with an embedded memory chip, the Godson processor is connected with a bridge, and the embedded The memory chip is electrically connected to the Godson processor through the bridge, and the method includes:
  • the destroy signal is used to instruct the embedded memory chip to erase the storage data stored in the embedded chip by the Godson processor;
  • the destroy signal is transmitted to the embedded memory chip through a preset differential signal transmission channel between the bridge chip and the embedded memory chip, and the destroy signal is a signal transmitted based on the SATA protocol;
  • the method also includes:
  • the embedded memory chip When the embedded memory chip is in the erasing execution state, if any control signal of the Godson processor is received, it will enter the fault processing state from the erasing execution state; any one of the control signals is used Instructing the embedded memory chip to enter a corresponding task execution state;
  • the embedded memory chip generates an error signal in response to any one of the control signals, and returns the error signal to the Godson processor, and the error signal is used to indicate that the embedded memory chip enters the corresponding task execution status failed;
  • the embedded memory chip After sending the error signal, the embedded memory chip enters the erasing execution state from the fault processing state to continue the erasing operation.
  • the method also includes:
  • the embedded memory chip When the embedded memory chip is in the erasing execution state, if it receives a power cycle signal, it enters the erasing suspend state from the erasing execution state, and the power cycle signal is used to indicate that the embedded memory chip The chip performs a power cycle operation;
  • the embedded memory chip performs a power cycle operation according to the power cycle signal
  • the embedded memory chip After the power cycle operation is completed, the embedded memory chip enters the erase execution state from the erase suspend state to continue the erase operation.
  • the embedded memory chip includes multiple sets of first differential signal sending and receiving pin pairs, and the multiple sets of first differential signal sending and receiving pin pairs correspond to multiple sets of second differential signal pairs of the bridge chip one by one. Send and receive pin pairs;
  • the method also includes:
  • the connection between the embedded memory chip and the bridge chip is constructed in advance. Differential signal transmission channel.
  • the embedded memory chip includes a control module, a flash memory module, a cache module and an input/output interface module.
  • control module the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.
  • the embedded memory chip is connected to an external power supply through an external power supply circuit, and the power supply circuit is used to supply power to the embedded memory chip;
  • the method Before receiving the destruction signal transmitted by the Godson processor, the method also includes:
  • the fourth voltage transmitted by the fourth output end of the power supply circuit is received by the flash memory module.
  • first voltage, the second voltage, the third voltage, and the fourth voltage are supplied to the embedded memory chip by the voltage sequence control circuit in the power supply circuit according to the preset power-on sequence. transmitted voltage.
  • the power supply circuit includes a first power supply circuit and a second power supply circuit, the first power supply circuit is used to transmit the first voltage to the control module, and transmit the second voltage to the input and output interface module and transmit the fourth voltage to the flash memory module, the second power supply circuit is used to transmit the third voltage to the cache module;
  • the first power supply circuit is connected with one or more first decoupling capacitors for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage.
  • a coupling capacitor; the second power supply circuit is connected with one or more fourth decoupling capacitors for energy storage;
  • the method also includes:
  • the eighth voltage provided by the fourth decoupling capacitor is received by the cache module.
  • the embedded memory chip is also connected with an intelligent destruction socket, and the intelligent destruction socket is electrically connected with the embedded memory chip; the method includes:
  • the destruction signal generated by the smart socket short circuit is received by the embedded memory chip.
  • the intelligent destruction method based on the Loongson processor provided by the embodiment of the present invention is connected with an embedded memory chip, which increases the storage capacity, and the embedded memory chip board is attached to the Loongson processor. Since the board paste is a point-to-point connection, the The embedded memory chip has good shock resistance; after receiving the destroy signal from the Godson processor, the embedded memory chip can activate the destroy function to destroy the stored data stored in the embedded memory chip, ensuring data security.
  • Figure 1 is a schematic diagram of the environmental application of the intelligent destruction method based on the Godson processor of the present invention.
  • Fig. 2 is a flowchart of an embodiment of the intelligent destruction method based on the Godson processor of the present invention.
  • FIG. 3 is a flow chart of steps S200 to S204 in the embodiment of the intelligent destruction method based on the Godson processor of the present invention.
  • FIG. 4 is a flowchart of steps S300 to S304 in the embodiment of the intelligent destruction method based on the Godson processor of the present invention.
  • FIG. 5 is a flow chart of the intelligent destruction function implemented by the embedded memory chip of the present invention.
  • FIG. 6-1 is a schematic diagram of the corresponding relationship between multiple sets of first differential signal sending and receiving pin pairs and multiple sets of second differential signal sending and receiving pins in an embodiment of the present invention.
  • Fig. 6-2 is a schematic structural diagram of the bridge piece in the embodiment of the present invention.
  • FIG. 7-1 is a schematic structural diagram of an embedded memory chip in an embodiment of the present invention.
  • FIG. 7-2 is an effect diagram of an embedded memory chip packaged by BGA technology in an embodiment of the present invention.
  • FIG. 8 is a general flow chart of the intelligent destruction function implemented by the embedded memory chip in the embodiment of the present invention.
  • Fig. 9-1 is a circuit diagram of the first power supply circuit in the embodiment of the present invention.
  • Fig. 9-2 is a circuit diagram of the second power supply circuit in the embodiment of the present invention.
  • Loongson platform including Loongson 7A1000 bridge chip and Loongson 3A4000 chip (Godson processor).
  • Loongson 3A4000 chip It integrates multiple 64-bit quad-launch high-performance Loongson IP cores for the Loongson 3 high-performance 64-bit multi-core processor.
  • the Loongson 3A4000 chip is mainly oriented to desktop, server, digital signal processing (DSP) and high-end embedded applications. Due to its low power consumption, some chips can also be used in high-performance ruggedized computers and other equipment. It is a nationally produced CPU in China. (Central Processing Unit / Processor, central processing unit).
  • Loongson 7A1000 bridge chip is a supporting bridge chip for Loongson 3 series processors for servers and desktops.
  • Loongson 7A1000 bridge chip has passed The HT3.0 interface connects to Loongson 3 series processors. Godson The main peripheral interfaces of the 7A1000 bridge chip include 3 x8 PCIE 2.0 interface, 2x4 PCIE 2.0 interface, three-way SATA2.0, six-way USB2.0, two-way GMAC, two-way DVO, and various other small interfaces. Because it is pin-to-pin with the later 7A2000 bridge, the circuit of Loongson 7A1000 bridge is designed with a compatibility mode. Compared with 7A1000, it can support SATA3.0 mode.
  • Embedded memory chip preferably AXD SATAIII BGA SSD embedded memory chip, is a self-developed integrated NAND A BGA package embedded memory chip integrating flash memory, DRAM cache, and self-developed controller.
  • the storage disks of domestic chip platforms such as the Loongson platform are all standard solid-state drives, such as: mSATA (mini-SATA, mini-version SATA interface) solid-state drives, 7+15PIN (chip) interface solid-state drives, At least the following defects exist:
  • FIG. 1 schematically shows a schematic diagram of an environment application of a Godson processor-based intelligent destruction method according to an embodiment of the present application.
  • the environmental application schematic diagram includes a Godson processor 10, a bridge 20 and an embedded memory chip 30; the Godson processor 10 is connected to the bridge 20, and the bridge 20 is connected to the bridge The embedded memory chip is connected through the SATA interface, and the Godson processor 10 is connected with the embedded memory chip 30 through the bridge 20; the embedded memory chip 30 is integrated with a flash memory module, a cache module, a control module and Input and output interface modules.
  • This application aims to provide an intelligent destruction scheme based on the Godson processor.
  • This scheme :
  • Serial Advanced Technology Attachment a protocol used when transmitting signals through an industry-standard serial hardware drive interface
  • SATA Serial Advanced Technology Attachment
  • the SSD embedded memory chip is a BGA-packaged embedded memory chip integrating NAND flash memory, DRAM cache (Dynamic Random Access Memory, dynamic random access memory), and a self-developed controller. It is matched with the Godson platform to realize a national production platform , to create a chain that belongs to domestic CPU to domestic storage media.
  • DRAM cache Dynamic Random Access Memory, dynamic random access memory
  • FIG. 2 it shows a flow chart of the steps of the intelligent destruction method based on the Godson processor according to the embodiment of the present invention.
  • an embedded memory chip is pasted on the upper board of the Godson processor, and a bridge is connected to the Godson processor, and the embedded memory chip is electrically connected to the Godson processor through the bridge.
  • Step S100 the Godson processor sends a destroy signal to the bridge chip, the destroy signal is used to instruct the embedded memory chip to erase the stored data stored in the embedded chip by the Godson processor.
  • the embodiment of the present invention pastes the embedded storage chip board on the Godson platform.
  • the Godson processor is used to transmit data with bridge chips.
  • the embodiment of the present invention improves the embedded memory chip, and controls the activation of the intelligent destruction function of the embedded memory chip through the destruction signal sent by the Godson processor.
  • the intelligent destruction function described in this embodiment is to erase the stored data embedded in the memory chip without damaging the embedded memory chip.
  • Step S102 transmit the destroy signal to the embedded memory chip through a preset differential signal transmission channel between the bridge chip and the embedded memory chip, the destroy signal is a signal transmitted based on the SATA protocol.
  • the data is transmitted to the embedded memory chip for storage through the differential signal transmission channel.
  • the data transmission between the Godson processor and the embedded memory chip is based on the SATA protocol.
  • Step S104 receiving the destroy signal through the embedded memory chip.
  • the execution subject of the destruction function is the embedded memory chip, and after receiving the destruction signal, the embedded memory chip starts to change state and starts the data erasing function.
  • Step S106 when the embedded memory chip receives the destroy signal transmitted by the Godson processor, monitor the duration of the destroy signal.
  • the duration of the control signal of the Godson processor is monitored.
  • the duration can be understood as the time during which the embedded memory chip continues to receive the destruction signal.
  • Step S108 the embedded memory chip judges whether the duration meets a preset time.
  • the preset time is preferably up to one second for judging whether to perform the erasing operation.
  • the destruction signal is a low-level signal
  • the embedded memory chip is set to receive the low-level signal, and the smart destruction function is triggered when the low-level signal lasts for one second.
  • Step S110 if the duration of the embedded memory chip satisfies a preset time, determine to enter an erase execution state, and perform an erase operation on the stored data based on the erase execution state.
  • the erase execution status is set, indicating that the erase operation starts to execute.
  • Step S112 the embedded memory chip judges whether the erasing operation is completed according to a preset judgment condition.
  • the judging condition may be judging the erasing execution state, and judging whether it is still in the erasing execution state.
  • Step S114 if the embedded memory chip determines that the erasing operation is completed, enter a standby state.
  • the embedded memory chip After the erasing operation is completed, the embedded memory chip becomes the initialization state, that is, enters the standby state to continue receiving data for storage.
  • the method further includes:
  • Step S200 when the embedded memory chip is in the erasing execution state, if any control signal of the Godson processor is received, enter the fault processing state from the erasing execution state; The control signal is used to instruct the embedded memory chip to enter a corresponding task execution state.
  • Step S202 the embedded memory chip generates an error signal in response to any one of the control signals, and returns the error signal to the Godson processor, and the error signal is used to indicate that the embedded memory chip enters a corresponding The task execution status of Failed.
  • Step S204 after sending the error signal, the embedded memory chip enters the erasing execution state from the fault processing state to continue the erasing operation.
  • the embedded memory chip sets the erase execution state to the highest level.
  • any control signal sent by the processor will not be executed.
  • the embedded memory chip enters a fault processing state, in which an error signal is generated and returned to the processor, and the erasing operation is continued after the error signal is returned to ensure that the stored data is completely erased.
  • the method further includes:
  • Step S300 when the embedded memory chip is in the erasing execution state, if a power cycle signal is received, enter the erasing suspension state from the erasing execution state, and the power cycle signal is used to indicate the Embedded memory chips perform power cycling operations.
  • Step S302 the embedded memory chip executes a power cycle operation according to the power cycle signal.
  • Step S304 after the power cycle operation is completed, the embedded memory chip enters the erase execution state from the erase pause state to continue the erase operation.
  • a power cycle function is configured in the embedded memory chip to provide power to the embedded memory chip in time when the power consumption of the embedded memory chip is insufficient.
  • the embedded memory chip starts the power cycle function, it receives a power cycle signal or a power cycle command.
  • the erase execution state is suspended and enters the erase pause state.
  • the erase execution state is re-entered from the erase pause state to continue the erase operation.
  • FIG. 5 is a flow chart of implementing the smart erasing function of the embedded memory chip in this embodiment. The specific description is as follows.
  • the embedded memory chip is in the QE0 state before starting the smart destruction function.
  • QE0 Device_IDLE: When the embedded memory chip is successfully powered on or successfully executes any command, the embedded memory chip enters this state after completing the initialization process. For example, QE1 The state is also called the standby state.
  • QE1 Quick_Erase_Execute state: QE1 is the erase execution state, and enters the erase execution state when QEE- is declared for the last 1 second. In the erasing execution state, the embedded memory chip starts to search for the stored data in all data blocks, and then erases the stored data. When entering the erasing execution state, QEB- is declared by the device, and QEB is used to judge whether the erasing operation is completed.
  • Transition QE1 QE1 process: It is in the suspended state. When there is a power cycle in the state, the embedded memory chip should continue the erasing process after completing the initialization process.
  • QE2 Quick_Erase_Finish state: It is the end state of erasing, and enters this state after all data blocks are successfully erased. When entering this state, QEB will be canceled by the embedded memory chip.
  • Embedded memory chips need to pay attention to the following when the smart destruction function is activated:
  • the MPtool tool imports the program of the erase function into the embedded memory chip, and sets the embedded memory chip to never enter the sleep mode when the erase function is implemented.
  • MPtool Tools can perform operations such as formatting and mass production of storage devices.
  • the erase function of the embedded memory chip has the highest priority, so in this state, when the embedded memory chip receives any command from any processor, it will not stop executing the erase function, including processing through Godson commands directly transmitted by the device, through the CF / HRST/SRST commands transmitted through the parallel port of the PATA hard disk device and SRST/COMREST commands transmitted through the serial port of the SATA hard disk device.
  • Serial ports and parallel ports are input and output modules.
  • the pin QEE is enabled - the GPIO (General-purpose input/output, general-purpose input and output) pin control, enter the erase function when the embedded memory chip enters the idle state and activates the QEE pin for at least 1 second, and the idle state can be understood as the standby state.
  • GPIO General-purpose input/output, general-purpose input and output
  • Busy time (erasing time * block number) + (program time * block number) + (cleaning pair time * number of pairs now).
  • the erasing time is the erasing time of a pre-tested single data block; the block number is the number of the data block that needs to be erased currently; the program time is the time to start the erasing function program when each data block is erased;
  • the cleaning pair time is the time for erasing each data pair; now the number of pairs is the number of data pairs existing in the embedded memory chip, and the data pair includes multiple data blocks. Because some data requires multiple Data blocks are stored to form data pairs.
  • the busy time of the erasing function can be controlled at least five seconds to improve erasing efficiency.
  • WinHex tool After the smart destruction is completed, the LBA (Logical Block Address) logical block address is all 0, you can use the WinHex tool to check whether the embedded memory chip is completely destroyed, to ensure that the embedded memory chip cannot be restored after being destroyed, and returns to the unused (before leaving the factory) state. WinHex tool is used to check and repair various files, restore deleted files, data loss caused by hard disk damage, etc.
  • the embedded memory chip includes multiple sets of first differential signal sending and receiving pin pairs, and the multiple sets of first differential signal sending and receiving pin pairs correspond one-to-one to the multiple pin pairs of the bridge chip.
  • the method also includes:
  • the connection between the embedded memory chip and the bridge chip is constructed in advance. Differential signal transmission channel.
  • the method further includes pre-establishing a connection between the embedded memory chip and the Godson processor.
  • signal transmission channel may be a differential signal transmission channel.
  • the multiple sets of first differential signal sending and receiving pin pairs set by the embedded memory chip correspond one-to-one to the multiple sets of second differential signal sending and receiving pin pairs set by the Loongson processor.
  • Both the first differential signal sending and receiving pin pair and the second differential signal sending and receiving pin pair are SATA interfaces.
  • FIG. 6-1 it is a schematic diagram of the corresponding relationship between multiple sets of first differential signal sending and receiving pin pairs and multiple sets of second differential signal sending and receiving pins.
  • the embedded memory chip is provided with two sets of first differential signal sending and receiving pin pairs, namely the K8 pin TXN, the K9 pin TXP, the L8 pin RXN and the L9 pin RXP.
  • first differential signal sending and receiving pin pairs namely the K8 pin TXN, the K9 pin TXP, the L8 pin RXN and the L9 pin RXP.
  • Figure 6-2 it is a structural diagram of the bridge chip.
  • the embedded memory chip only needs to be connected to four sets of second differential signal sending and receiving pin pairs of the bridge chip to perform data transmission between the Godson processor and the embedded memory chip.
  • the connection mode of the sending interface pin pair follows the way of RX to TX, where RX means receiving differential signals, TX means sending differential signals, P means positive pole, and N means negative pole. If the Loongson processor is wrongly connected, the embedded memory chip will not be recognized, and it needs to be reworked to re-communicate and connect the differential signal sending and receiving pin pairs.
  • the embedded memory chip includes a control module, a flash memory module, a cache module and an input/output interface module.
  • the embedded memory chip in this embodiment is preferably an AXD SATAIII BGA SSD embedded memory chip, which is a self-developed BGA package embedded memory chip integrating NAND flash memory module, DRAM cache module and self-developed control module .
  • AXD The SATAIII BGA SSD embedded memory chip adopts the SATAIII interface, which can provide a link speed of 6Gbps, making the data transmission rate faster and more efficient.
  • FIG. 7-1 shows a schematic structural diagram of the embedded memory chip.
  • the embedded memory chip includes bus controller, microprocessor, test module JTAG (Joint Test Action Group, joint test working group, mainly used for chip internal testing), security encoder/decoder, UART interface (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver Transmitter), main system buffer, DMA (Direct Memory Access, direct memory access) controller, DRAM (a computer memory specification cache product) controller, DDR3 (a computer Cache products of memory specification) Cache, flash memory controller, flash chip and SATA interface, among them, bus controller connects microprocessor, security encoder/decoder, UART interface, main system buffer, DMA controller, DRAM controller
  • the test module JTAG is connected with the flash memory controller and the microprocessor, the DRAM controller is connected with the DDR3 cache, the flash memory controller is connected with the flash memory chip, and the embedded memory chip is
  • the control module can be a bus controller, a microprocessor and a DMA controller
  • the flash memory module can be a flash memory controller and a flash memory chip
  • the DRAM cache module can be a DRAM controller and a DDR3 cache.
  • the input and output interface module can be a SATA interface and a UART interface.
  • control module the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.
  • BGA Bit Grid Array packaging technology
  • BGA Ball Grid Array packaging technology
  • the pins are ball-shaped and arranged in a grid-like pattern, hence the name BGA.
  • the embedded memory chip packaged with BGA technology can increase the memory capacity of the embedded memory chip by two to three times while maintaining the same volume.
  • BGA has smaller volume, better heat dissipation performance and electrical conductivity. performance.
  • BGA packaging technology has greatly improved the storage capacity per square inch. Under the same capacity, the embedded memory chip using BGA packaging technology is only one third of the volume of TSOP packaging; compared with the traditional TSOP packaging method, BGA packaging There is a more rapid and effective way to dissipate heat.
  • the embedded memory chip is connected to an external power supply through an external power supply circuit, and the power supply circuit is used to supply power to the embedded memory chip;
  • the method Before receiving the destruction signal transmitted by the Godson processor, the method also includes:
  • the fourth voltage transmitted by the fourth output end of the power supply circuit is received by the flash memory module.
  • each module of the embedded memory chip is powered by a power supply circuit.
  • the power supply circuit divides and outputs four voltage output terminals.
  • the first voltage is preferably 1.1V
  • the second voltage is 3.3V
  • the third voltage is 1.5V
  • the fourth voltage is 1.8V. That is, the power supply voltage required by the control module is 1.1V, the power supply voltage required by the NAND flash memory module is 1.8V, the power supply voltage required by the DRAM module cache is 1.5V, and the power supply voltage required by the IO input and output interface module is 3.3V.
  • the first output terminal of the power supply circuit is VCCK
  • the second output terminal of the power supply circuit is VCC3F
  • the third output terminal of the power supply circuit is VCCDQ
  • the fourth output terminal of the power supply circuit is VCCFQ.
  • the first voltage, the second voltage, the third voltage, and the fourth voltage are provided by the voltage sequence control circuit in the power supply circuit according to a preset power-on sequence.
  • the preset power-on sequence is 1.1V>3.3V>1.5V>1.8V, that is, the power-on sequence is preset as 1.1V voltage power-on earlier than 3.3V voltage, 3.3V voltage power-on earlier than 1.5V voltage, 1.5V voltage Power on earlier than 1.8V voltage.
  • the disk will not be recognized, that is, the Loongson processor cannot recognize the embedded memory chip, which ensures the stability of the connection between the Loongson processor and the embedded memory chip, so that the Loongson processor The embedded memory chip can be read normally.
  • the setting of the voltage sequence control circuit can ensure that the external power supply circuit can supply power to each module of the embedded memory chip according to the preset power-on sequence, and uniformly and effectively manage the power-on of each module of the embedded memory chip, effectively Reduce the impact on the power supply grid at the moment when each module is powered on at the same time, ensuring the stability and safety of power consumption.
  • the method further includes: performing an identification test operation on the embedded memory chip after independent research and development in advance, as follows;
  • Step S400 sending a first test differential signal to the Loongson processor through the at least one set of first differential signal sending and receiving pin pairs;
  • Step S402 generating a second test differential signal based on the first test differential signal through at least one set of second differential signal transmit and receive pin pairs corresponding to the at least one set of first differential signal transmit and receive pin pairs;
  • Step S404 when receiving the second test differential signal returned by the Godson processor, determine to establish a signal transmission channel with the Godson processor;
  • Step S406 after establishing the signal transmission channel, receiving multiple voltages transmitted by the power supply circuit, and the voltage values of each voltage are inconsistent;
  • Step S408 judging whether the multiple voltages are received according to the preset power-on sequence
  • Step S410 if the multiple voltages are received according to the preset power-on sequence, determine to establish a connection with the Godson processor, so that the Godson processor can identify the embedded memory chip.
  • the second test differential signal returned by the first test differential signal determines that the signal transmission connection with the Godson processor fails, that is, the embedded memory chip cannot be recognized by the Godson processor, and it is determined that the embedded memory chip enters rework state to reconfigure the embedded memory chip.
  • the connection with the Godson processor fails, that is, the embedded memory chip cannot be powered on normally, resulting in the embedded memory chip being unable to be powered by Godson.
  • the processor identifies and determines that the embedded memory chip enters a rework state, so as to reconfigure the embedded memory chip.
  • the power supply circuit includes a first power supply circuit and a second power supply circuit
  • the first power supply circuit is used to transmit the first voltage to the control module, and transmit the second voltage to the
  • the input and output interface module transmits the fourth voltage to the flash memory module
  • the second power supply circuit is used to transmit the third voltage to the cache module; please refer to Figure 9-1 and Figure 9-2 , FIG. 9-1 schematically shows a schematic diagram of the power supply principle of the first power supply circuit, and FIG. 9-2 schematically shows a schematic diagram of the power supply principle of the second power supply circuit. details as follows:
  • the first power supply circuit As shown in Figure 9-1, the first power supply circuit:
  • the first power supply circuit includes a first power supply chip, and the first power supply chip includes multiple sets of first power input interfaces, such as two sets of VIN1, two sets of VIN2, two sets of VIN3 and VIN, and the multiple sets of first The power input interface is connected to an external power supply.
  • first power input interface is connected to an external power supply.
  • two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through wires, and are all connected to an external power supply VCCIN.
  • Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected to a capacitor and then grounded.
  • the first power supply chip also includes a first output interface VOUT3 and a second output interface, the second output interface includes a second main output interface VOUT1 and a second I/O output interface VOUT2; the first power supply circuit includes The first inductor L6 for voltage stabilization, the second inductor L3 for voltage stabilization, the first capacitor C31 for coupling, the second capacitor C41 for coupling, and the third capacitor C30 for coupling;
  • One end of the first inductor L6 is connected to the first inductor connection port LX3 of the first power supply chip, and the other end of the first inductor L6 is connected to the input terminal VCCK of the control module and the first output interface VOUT3 , the first output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor 31 is grounded;
  • the second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory, the second main output interface VOUT1 is connected to one end of the second capacitor C41, and the other end of the second capacitor C41 is grounded;
  • the second I/O output interface VOUT2 is connected to one end of the second inductor L3, and one end of the second inductor L3 is also connected to the second input end VCCFQ of the flash memory, and the other end of the second inductor L3 is connected to the
  • the second inductor of the first power supply chip is connected to the port LX3, the second I/O output interface VOUT2 is connected to one end of the third capacitor C19, and the other end of the third capacitor C19 is grounded.
  • the second power supply circuit As shown in Figure 9-2, the second power supply circuit:
  • the second power supply circuit includes a second power supply chip, the second power supply chip includes a second power input interface VIN, an enable pin EN, a feedback pin FB and a conversion pin SW, the second power input
  • the interface VIN is connected to the external power supply VCCN, and the enable pin QE is connected to the standby pin DEVSLP of the first power supply chip;
  • the second power supply circuit includes a voltage stabilizing circuit composed of a fourth capacitor C22, a third inductor L4 and a resistor R17.
  • One end of the fourth capacitor C22 is connected to the feedback pin FB, the other end of the fourth capacitor C22 is connected to the third output terminal VCCDQ; one end of the third inductor L4 is connected to the switching pin SW, and the other end of the third inductor L4 is connected to the third output terminal VCCDQ; one end of the first resistor R17 is connected to the feedback pin FB, and the other end of the first resistor R17 is connected to the third output terminal VCCDQ.
  • the connecting end of the first resistor R17, the fourth capacitor C22 and the feedback pin FB is connected to the second resistor R18, and the other end of the second resistor R18 is grounded.
  • the first power supply circuit is connected to one or more A first decoupling capacitor for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage;
  • the second power supply circuit is connected to one or more A fourth decoupling capacitor for energy storage;
  • the method also includes:
  • the eighth voltage provided by the fourth decoupling capacitor is received by the cache module.
  • the interference of other signals is avoided during signal transmission, and the first decoupling capacitor, the second decoupling capacitor, Both the third decoupling capacitor and the fourth decoupling capacitor have the function of buffering energy.
  • the high-frequency device under the influence of the frequency, a large inductance will be generated, which will cause the power supply of each module of the embedded memory chip to be untimely or when the power supply circuit is disconnected from the embedded memory chip.
  • the coupling capacitor supplies power to each module of the embedded memory chip in time to ensure that the embedded memory chip can operate normally.
  • the embedded memory chip is further connected with a smart destruction socket, and the intelligent destruction socket is electrically connected with the embedded memory chip; the method includes:
  • the destruction signal generated by the smart socket short circuit is received by the embedded memory chip.
  • this embodiment also sets an intelligent destroy socket on the Godson processor.
  • the intelligent destruction strip is electrically connected to the enabling pin of the embedded memory chip that starts the intelligent destruction function, and the enabling pin is short-circuited by means of the intelligent destruction strip cap, thereby giving the enabling pin a Low level, to realize the control of enabling the intelligent destruction function of the embedded memory chip.
  • the intelligent destruction function is realized by direct blocking and short-circuiting. If it is a plug-and-plug short-circuiting method, the preset time is preferably up to one second, which can ensure that the destruction time is within 5 seconds, which improves the efficiency of intelligent destruction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un procédé de destruction intelligente basé sur un processeur Loongson. Une puce de stockage intégrée est collée sur une plaque supérieure du processeur Loongson, et est électriquement connectée au processeur Loongson au moyen d'une pièce de pont connectée à la puce de stockage intégrée. Le procédé consiste à : envoyer un signal de destruction à une pièce de pont au moyen d'un processeur Loongson, le signal de destruction étant utilisé pour ordonner à une puce de stockage intégrée d'effacer des données de stockage pré-stockées; permettre à la puce de pont de transmettre, à la puce de stockage intégrée au moyen d'un canal de transmission de signal différentiel prédéfini, le signal de destruction transmis sur la base d'un protocole SATA; au moyen de la puce de stockage intégrée, recevoir le signal de destruction et surveiller une durée du signal de destruction lorsque le signal de destruction est reçu; déterminer si la durée satisfait ou non une durée prédéfinie; si la durée prédéfinie est satisfaite, déterminer d'entrer dans un état d'exécution d'effacement, et réaliser une opération d'effacement sur les données de stockage sur la base de l'état d'exécution d'effacement; déterminer, au moyen d'une condition de détermination prédéfinie, si l'opération d'effacement est achevée; et s'il est déterminé que l'opération d'effacement est achevée, entrer dans un état de veille. Le procédé améliore l'efficacité et la sécurité de la transmission de données.
PCT/CN2022/112794 2021-08-17 2022-08-16 Procédé de destruction intelligente basé sur un processeur loongson WO2023020494A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110942201.3A CN113704836B (zh) 2021-08-17 2021-08-17 基于龙芯处理器的智能销毁方法
CN202110942201.3 2021-08-17

Publications (1)

Publication Number Publication Date
WO2023020494A1 true WO2023020494A1 (fr) 2023-02-23

Family

ID=78652969

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/112794 WO2023020494A1 (fr) 2021-08-17 2022-08-16 Procédé de destruction intelligente basé sur un processeur loongson

Country Status (2)

Country Link
CN (1) CN113704836B (fr)
WO (1) WO2023020494A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117019847A (zh) * 2023-10-08 2023-11-10 北京傲星科技有限公司 一种固态硬盘物理销毁方法以及固态硬盘

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180024763A1 (en) * 2016-07-22 2018-01-25 Toshiba Memory Corporation Memory system storing block protection information
CN108089822A (zh) * 2017-12-20 2018-05-29 北京京存技术有限公司 存储芯片的管理方法、系统、设备及存储介质
CN111143903A (zh) * 2020-01-14 2020-05-12 合肥市卓怡恒通信息安全有限公司 数据销毁电路
CN111833909A (zh) * 2020-07-14 2020-10-27 深圳佰维存储科技股份有限公司 硬盘销毁触发方法、装置、计算机可读存储介质及系统
CN212084143U (zh) * 2020-05-29 2020-12-04 湖南兴天电子科技有限公司 基于龙芯平台的便携式移动终端

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201237788Y (zh) * 2008-08-11 2009-05-13 湖南源科创新科技股份有限公司 基于数据销毁的固态硬盘
US20120151121A1 (en) * 2010-12-14 2012-06-14 Jose Antonio Braga Solid State Non-Volatile Storage Drives Having Self-Erase and Self-Destruct Functionality and Related Methods
KR20150116352A (ko) * 2014-04-07 2015-10-15 삼성전자주식회사 메모리 제어 방법 및 시스템
CN107908981A (zh) * 2017-11-03 2018-04-13 山东超越数控电子股份有限公司 一种具有自销毁的硬盘数据连接系统以及方法
CN110874183A (zh) * 2018-08-31 2020-03-10 深圳市安信达存储技术有限公司 一种可销毁和恢复数据的固态硬盘及方法
US11081187B2 (en) * 2019-12-11 2021-08-03 SanDiskTechnologies LLC Erase suspend scheme in a storage device
CN113076564B (zh) * 2021-04-13 2022-10-14 山东北斗云信息技术有限公司 基于北斗定位的硬盘保护方法、装置、设备及存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180024763A1 (en) * 2016-07-22 2018-01-25 Toshiba Memory Corporation Memory system storing block protection information
CN108089822A (zh) * 2017-12-20 2018-05-29 北京京存技术有限公司 存储芯片的管理方法、系统、设备及存储介质
CN111143903A (zh) * 2020-01-14 2020-05-12 合肥市卓怡恒通信息安全有限公司 数据销毁电路
CN212084143U (zh) * 2020-05-29 2020-12-04 湖南兴天电子科技有限公司 基于龙芯平台的便携式移动终端
CN111833909A (zh) * 2020-07-14 2020-10-27 深圳佰维存储科技股份有限公司 硬盘销毁触发方法、装置、计算机可读存储介质及系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117019847A (zh) * 2023-10-08 2023-11-10 北京傲星科技有限公司 一种固态硬盘物理销毁方法以及固态硬盘
CN117019847B (zh) * 2023-10-08 2023-12-29 北京傲星科技有限公司 一种固态硬盘物理销毁方法以及固态硬盘

Also Published As

Publication number Publication date
CN113704836A (zh) 2021-11-26
CN113704836B (zh) 2022-06-10

Similar Documents

Publication Publication Date Title
CN113704834B (zh) 基于飞腾处理器的智能销毁方法
CN109324991B (zh) 一种pcie设备的热插拔装置、方法、介质及系统
CN103902427A (zh) 一种带外获取硬盘状态的方法
TWI773152B (zh) 伺服器與應用於伺服器的控制方法
CN113704160B (zh) 基于飞腾处理器的数据存储方法、系统及存储主板
CN110619914A (zh) 一种带PCIe接口量产器用于固态硬盘的量产方法
WO2023020494A1 (fr) Procédé de destruction intelligente basé sur un processeur loongson
CN104111801A (zh) 数据存取系统、数据存取装置及数据存取控制器
TWI416418B (zh) 資料傳輸控制器、裝置及其方法
CN111143898B (zh) 可插拔存储器装置数据保护方法
KR20140008550A (ko) 멀티 칩 패키지 메모리 장치의 제어 방법
JP2015084227A (ja) ストレージシステム、格納装置、及びストレージシステムの非信号分析方法
US20230393959A1 (en) Out-of-band management method for storage apparatus, baseboard management controller and storage apparatus
CN112306938A (zh) 一种ocp卡和多主机卡的热插拔方法及装置
CN114840885A (zh) 一种基于赛灵思平台及raid技术的存储主板的智能销毁方法
WO2009115058A1 (fr) Carte mère pour fournir une fonction de mémoire flash et son procédé de stockage
US20230418703A1 (en) Autonomic troubleshooting of a system of devices
JP2005078652A (ja) モジュラコンポーネントを有するメモリカード
TWI773395B (zh) 記憶體控制器與連結識別方法
WO2022160893A1 (fr) Procédé de partage de zone de stockage et dispositif électronique
TWI483125B (zh) 基板管理控制器恢復系統及其使用方法
CN111459863B (zh) 一种基于nvme-mi的机箱管理系统及方法
CN204706031U (zh) 串行外设接口spi总线电路以及电子设备
CN209879498U (zh) 一种m.2硬盘双口转接卡
TWI697783B (zh) 高速介面連接裝置及其方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22857805

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22857805

Country of ref document: EP

Kind code of ref document: A1