WO2023020494A1 - Intelligent destruction method based on loongson processor - Google Patents

Abstract

An intelligent destruction method based on a Loongson processor. An embedded storage chip is pasted on an upper plate of the Loongson processor, and is electrically connected to the Loongson processor by means of a bridge piece connected to the embedded storage chip. The method comprises: sending a destruction signal to a bridge piece by means of a Loongson processor, the destruction signal being used for instructing an embedded storage chip to erase pre-stored storage data; enabling the bridge chip to transmit, to the embedded storage chip by means of a preset differential signal transmission channel, the destruction signal transmitted on the basis of a SATA protocol; by means of the embedded storage chip, receiving the destruction signal and monitoring a duration of the destruction signal when the destruction signal is received; determining whether the duration satisfies a preset duration; if the preset duration is satisfied, determining to enter an erasure execution state, and performing erasure operation on the storage data on the basis of the erasure execution state; determining, by means of a preset determination condition, whether the erasure operation is completed; and if it is determined that the erasure operation is completed, entering a standby state. The method improves the efficiency and security of data transmission.

Description

Intelligent Destruction Method Based on Loongson Processor technical field

The embodiment of the present invention relates to the technical field of chip processing, and in particular to an intelligent destruction method based on a Godson processor.

Background technique

With the development of information technology, higher requirements are put forward for the security and confidentiality of information. The demand for adopting independent platform servers is also expanding, and the requirements for motherboards in specific environments are getting higher and higher.

technical problem

At present, the multi-CPU designs used in most domestic computer products use foreign CPU chips. Since the chips have backdoors, and foreign CPU chips are applied to domestic computer systems, it is difficult to guarantee the security and confidentiality of information. Therefore, localized chips came into being, such as Godson processors. Loongson processors are expanded through external storage products, but the existing storage products: the speed of receiving transmissions from Loongson processors is slow; when the CPU of Loongson processors is attacked, the security of their own data cannot be guaranteed, which increases the risk of data leakage risk.

technical solution

In view of this, the purpose of the embodiments of the present invention is to provide a Godson processor-based intelligent destruction method to solve the problems of slow data transmission rate and low data security in the prior art.

In order to achieve the above object, the embodiment of the present invention shows a method of intelligent destruction based on the Godson processor, the upper board of the Godson processor is pasted with an embedded memory chip, the Godson processor is connected with a bridge, and the embedded The memory chip is electrically connected to the Godson processor through the bridge, and the method includes:

Sending a destroy signal to the bridge chip through the Godson processor, the destroy signal is used to instruct the embedded memory chip to erase the storage data stored in the embedded chip by the Godson processor;

The destroy signal is transmitted to the embedded memory chip through a preset differential signal transmission channel between the bridge chip and the embedded memory chip, and the destroy signal is a signal transmitted based on the SATA protocol;

Perform the following operations through the embedded memory chip:

receiving said destroy signal;

When receiving the destruction signal transmitted by the Godson processor, monitor the duration of the destruction signal;

judging whether the duration meets a preset time;

If the duration satisfies the preset time, determine to enter the erasing execution state, and perform an erasing operation on the stored data based on the erasing execution state;

judging whether the erasing operation is completed through a preset judging condition; and

If it is determined that the erasing operation is completed, enter a standby state.

Further, the method also includes:

When the embedded memory chip is in the erasing execution state, if any control signal of the Godson processor is received, it will enter the fault processing state from the erasing execution state; any one of the control signals is used Instructing the embedded memory chip to enter a corresponding task execution state;

The embedded memory chip generates an error signal in response to any one of the control signals, and returns the error signal to the Godson processor, and the error signal is used to indicate that the embedded memory chip enters the corresponding task execution status failed; and

After sending the error signal, the embedded memory chip enters the erasing execution state from the fault processing state to continue the erasing operation.

Further, the method also includes:

When the embedded memory chip is in the erasing execution state, if it receives a power cycle signal, it enters the erasing suspend state from the erasing execution state, and the power cycle signal is used to indicate that the embedded memory chip The chip performs a power cycle operation;

the embedded memory chip performs a power cycle operation according to the power cycle signal; and

After the power cycle operation is completed, the embedded memory chip enters the erase execution state from the erase suspend state to continue the erase operation.

Further, the embedded memory chip includes multiple sets of first differential signal sending and receiving pin pairs, and the multiple sets of first differential signal sending and receiving pin pairs correspond to multiple sets of second differential signal pairs of the bridge chip one by one. Send and receive pin pairs;

The method also includes:

Through the corresponding relationship between the multiple sets of first differential signal sending and receiving pin pairs and the corresponding multiple sets of second differential signal sending and receiving pin pairs, the connection between the embedded memory chip and the bridge chip is constructed in advance. Differential signal transmission channel.

Further, the embedded memory chip includes a control module, a flash memory module, a cache module and an input/output interface module.

Further, the control module, the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.

Further, the embedded memory chip is connected to an external power supply through an external power supply circuit, and the power supply circuit is used to supply power to the embedded memory chip;

Before receiving the destruction signal transmitted by the Godson processor, the method also includes:

receiving the first voltage transmitted by the first output terminal of the power supply circuit through the control module;

receiving the second voltage transmitted by the second output terminal of the power supply circuit through the input-output interface module;

receiving the third voltage transmitted by the third output terminal of the power supply circuit through the buffer module;

The fourth voltage transmitted by the fourth output end of the power supply circuit is received by the flash memory module.

Further, the first voltage, the second voltage, the third voltage, and the fourth voltage are supplied to the embedded memory chip by the voltage sequence control circuit in the power supply circuit according to the preset power-on sequence. transmitted voltage.

Further, the power supply circuit includes a first power supply circuit and a second power supply circuit, the first power supply circuit is used to transmit the first voltage to the control module, and transmit the second voltage to the input and output interface module and transmit the fourth voltage to the flash memory module, the second power supply circuit is used to transmit the third voltage to the cache module;

The first power supply circuit is connected with one or more first decoupling capacitors for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage. A coupling capacitor; the second power supply circuit is connected with one or more fourth decoupling capacitors for energy storage;

The method also includes:

If the external power supply is disconnected from the power supply circuit, then

receiving a fifth voltage provided by the first decoupling capacitor through the control module;

receiving a sixth voltage provided by the second decoupling capacitor through the input-output interface module;

receiving a seventh voltage provided by the third decoupling capacitor through the flash memory module;

The eighth voltage provided by the fourth decoupling capacitor is received by the cache module.

Further, the embedded memory chip is also connected with an intelligent destruction socket, and the intelligent destruction socket is electrically connected with the embedded memory chip; the method includes:

The destruction signal generated by the smart socket short circuit is received by the embedded memory chip.

The intelligent destruction method based on the Loongson processor provided by the embodiment of the present invention is connected with an embedded memory chip, which increases the storage capacity, and the embedded memory chip board is attached to the Loongson processor. Since the board paste is a point-to-point connection, the The embedded memory chip has good shock resistance; after receiving the destroy signal from the Godson processor, the embedded memory chip can activate the destroy function to destroy the stored data stored in the embedded memory chip, ensuring data security.

Description of drawings

Figure 1 is a schematic diagram of the environmental application of the intelligent destruction method based on the Godson processor of the present invention.

Fig. 2 is a flowchart of an embodiment of the intelligent destruction method based on the Godson processor of the present invention.

FIG. 3 is a flow chart of steps S200 to S204 in the embodiment of the intelligent destruction method based on the Godson processor of the present invention.

FIG. 4 is a flowchart of steps S300 to S304 in the embodiment of the intelligent destruction method based on the Godson processor of the present invention.

FIG. 5 is a flow chart of the intelligent destruction function implemented by the embedded memory chip of the present invention.

FIG. 6-1 is a schematic diagram of the corresponding relationship between multiple sets of first differential signal sending and receiving pin pairs and multiple sets of second differential signal sending and receiving pins in an embodiment of the present invention.

Fig. 6-2 is a schematic structural diagram of the bridge piece in the embodiment of the present invention.

FIG. 7-1 is a schematic structural diagram of an embedded memory chip in an embodiment of the present invention.

FIG. 7-2 is an effect diagram of an embedded memory chip packaged by BGA technology in an embodiment of the present invention.

FIG. 8 is a general flow chart of the intelligent destruction function implemented by the embedded memory chip in the embodiment of the present invention.

Fig. 9-1 is a circuit diagram of the first power supply circuit in the embodiment of the present invention.

Fig. 9-2 is a circuit diagram of the second power supply circuit in the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Explanation of the terms most relevant to the subject matter of the invention:

Loongson platform, including Loongson 7A1000 bridge chip and Loongson 3A4000 chip (Godson processor). Loongson 3A4000 chip: It integrates multiple 64-bit quad-launch high-performance Loongson IP cores for the Loongson 3 high-performance 64-bit multi-core processor. The Loongson 3A4000 chip is mainly oriented to desktop, server, digital signal processing (DSP) and high-end embedded applications. Due to its low power consumption, some chips can also be used in high-performance ruggedized computers and other equipment. It is a nationally produced CPU in China. (Central Processing Unit / Processor, central processing unit). Loongson 7A1000 bridge chip is a supporting bridge chip for Loongson 3 series processors for servers and desktops. Loongson 7A1000 bridge chip has passed The HT3.0 interface connects to Loongson 3 series processors. Godson The main peripheral interfaces of the 7A1000 bridge chip include 3 x8 PCIE 2.0 interface, 2x4 PCIE 2.0 interface, three-way SATA2.0, six-way USB2.0, two-way GMAC, two-way DVO, and various other small interfaces. Because it is pin-to-pin with the later 7A2000 bridge, the circuit of Loongson 7A1000 bridge is designed with a compatibility mode. Compared with 7A1000, it can support SATA3.0 mode.

Embedded memory chip, preferably AXD SATAIII BGA SSD embedded memory chip, is a self-developed integrated NAND A BGA package embedded memory chip integrating flash memory, DRAM cache, and self-developed controller.

The inventor understands that: the storage disks of domestic chip platforms such as the Loongson platform are all standard solid-state drives, such as: mSATA (mini-SATA, mini-version SATA interface) solid-state drives, 7+15PIN (chip) interface solid-state drives, At least the following defects exist:

(1) The solid-state hard drive of the existing Loongson platform takes up a lot of space and has poor shock resistance.

(2) The solid-state hard drive of the existing Loongson platform receives data slowly, which is time-consuming.

(3) The SSD storage of the existing Loongson platform cannot realize the destruction function, and there is a risk of data leakage.

(4) The solid-state hard drive of the existing Godson platform is poorly integrated.

In order to solve the above problems, a number of embodiments will be provided below, and each embodiment provided below can be used to realize the intelligent destruction based on the Godson processor.

FIG. 1 schematically shows a schematic diagram of an environment application of a Godson processor-based intelligent destruction method according to an embodiment of the present application. In an exemplary embodiment, the environmental application schematic diagram includes a Godson processor 10, a bridge 20 and an embedded memory chip 30; the Godson processor 10 is connected to the bridge 20, and the bridge 20 is connected to the bridge The embedded memory chip is connected through the SATA interface, and the Godson processor 10 is connected with the embedded memory chip 30 through the bridge 20; the embedded memory chip 30 is integrated with a flash memory module, a cache module, a control module and Input and output interface modules.

This application aims to provide an intelligent destruction scheme based on the Godson processor. In this scheme:

(1) Through the self-developed AXD SATAIII BGA The SSD embedded memory chip board is pasted on the Godson platform to achieve the effect of small space occupation and good shock resistance.

(1) Data is transmitted through the SATA protocol (Serial Advanced Technology Attachment, a protocol used when transmitting signals through an industry-standard serial hardware drive interface), which improves the data transmission rate.

(3) Self-developed AXD SATAIII BGA In terms of the performance of the SSD embedded memory chip, it can reach the highest reading and writing of the standard SATA protocol, meet the data interaction processing requirements with the Godson platform, and has an intelligent destruction function, which is more secure.

(4) Self-developed AXD SATAIII BGA The SSD embedded memory chip is a BGA-packaged embedded memory chip integrating NAND flash memory, DRAM cache (Dynamic Random Access Memory, dynamic random access memory), and a self-developed controller. It is matched with the Godson platform to realize a national production platform , to create a chain that belongs to domestic CPU to domestic storage media.

Referring to FIG. 2 , it shows a flow chart of the steps of the intelligent destruction method based on the Godson processor according to the embodiment of the present invention. Wherein, an embedded memory chip is pasted on the upper board of the Godson processor, and a bridge is connected to the Godson processor, and the embedded memory chip is electrically connected to the Godson processor through the bridge. It can be understood that the flowchart in this method embodiment is not used to limit the sequence of execution steps. An exemplary description is given below, and the details are as follows.

Step S100, the Godson processor sends a destroy signal to the bridge chip, the destroy signal is used to instruct the embedded memory chip to erase the stored data stored in the embedded chip by the Godson processor.

In order to improve the shock resistance of the external storage chip, the embodiment of the present invention pastes the embedded storage chip board on the Godson platform. In order to increase the amount of data transmission, the Godson processor is used to transmit data with bridge chips.

Further, in order to reduce the risk of data leakage, the embodiment of the present invention improves the embedded memory chip, and controls the activation of the intelligent destruction function of the embedded memory chip through the destruction signal sent by the Godson processor. The intelligent destruction function described in this embodiment is to erase the stored data embedded in the memory chip without damaging the embedded memory chip.

Step S102, transmit the destroy signal to the embedded memory chip through a preset differential signal transmission channel between the bridge chip and the embedded memory chip, the destroy signal is a signal transmitted based on the SATA protocol.

In order to increase the stability of data transmission, the data is transmitted to the embedded memory chip for storage through the differential signal transmission channel. In order to increase the rate of data transmission, the data transmission between the Godson processor and the embedded memory chip is based on the SATA protocol.

Step S104, receiving the destroy signal through the embedded memory chip.

The execution subject of the destruction function is the embedded memory chip, and after receiving the destruction signal, the embedded memory chip starts to change state and starts the data erasing function.

Step S106, when the embedded memory chip receives the destroy signal transmitted by the Godson processor, monitor the duration of the destroy signal.

In order to confirm whether the intelligent destruction function needs to be turned on, the duration of the control signal of the Godson processor is monitored. The duration can be understood as the time during which the embedded memory chip continues to receive the destruction signal.

Step S108, the embedded memory chip judges whether the duration meets a preset time.

In order to improve the efficiency of smart erasing, the preset time is preferably up to one second for judging whether to perform the erasing operation. The destruction signal is a low-level signal, and the embedded memory chip is set to receive the low-level signal, and the smart destruction function is triggered when the low-level signal lasts for one second.

Step S110, if the duration of the embedded memory chip satisfies a preset time, determine to enter an erase execution state, and perform an erase operation on the stored data based on the erase execution state.

In order to ensure the progress of the erase operation, the erase execution status is set, indicating that the erase operation starts to execute.

Step S112, the embedded memory chip judges whether the erasing operation is completed according to a preset judgment condition.

In order to improve the erasing efficiency, it is judged whether the erasing operation is completed through a preset judging condition. The judging condition may be judging the erasing execution state, and judging whether it is still in the erasing execution state.

Step S114, if the embedded memory chip determines that the erasing operation is completed, enter a standby state.

After the erasing operation is completed, the embedded memory chip becomes the initialization state, that is, enters the standby state to continue receiving data for storage.

In an exemplary embodiment, referring to FIG. 3, the method further includes:

Step S200, when the embedded memory chip is in the erasing execution state, if any control signal of the Godson processor is received, enter the fault processing state from the erasing execution state; The control signal is used to instruct the embedded memory chip to enter a corresponding task execution state. Step S202, the embedded memory chip generates an error signal in response to any one of the control signals, and returns the error signal to the Godson processor, and the error signal is used to indicate that the embedded memory chip enters a corresponding The task execution status of Failed. Step S204, after sending the error signal, the embedded memory chip enters the erasing execution state from the fault processing state to continue the erasing operation.

In order to improve data security, the embedded memory chip sets the erase execution state to the highest level. When the embedded memory chip is in the erasing execution state, any control signal sent by the processor will not be executed. At this time, the embedded memory chip enters a fault processing state, in which an error signal is generated and returned to the processor, and the erasing operation is continued after the error signal is returned to ensure that the stored data is completely erased.

In an exemplary embodiment, referring to FIG. 4, the method further includes:

Step S300, when the embedded memory chip is in the erasing execution state, if a power cycle signal is received, enter the erasing suspension state from the erasing execution state, and the power cycle signal is used to indicate the Embedded memory chips perform power cycling operations. Step S302, the embedded memory chip executes a power cycle operation according to the power cycle signal. Step S304, after the power cycle operation is completed, the embedded memory chip enters the erase execution state from the erase pause state to continue the erase operation.

In order to ensure the smooth execution of the erasing operation, a power cycle function is configured in the embedded memory chip to provide power to the embedded memory chip in time when the power consumption of the embedded memory chip is insufficient. When the embedded memory chip starts the power cycle function, it receives a power cycle signal or a power cycle command. At this point, the erase execution state is suspended and enters the erase pause state. After the power cycle operation is completed, the erase execution state is re-entered from the erase pause state to continue the erase operation.

In order to better understand the erasing function, refer to FIG. 5 , which is a flow chart of implementing the smart erasing function of the embedded memory chip in this embodiment. The specific description is as follows.

The embedded memory chip is in the QE0 state before starting the smart destruction function. QE0: Device_IDLE: When the embedded memory chip is successfully powered on or successfully executes any command, the embedded memory chip enters this state after completing the initialization process. For example, QE1 The state is also called the standby state.

Transition QE0:QE1 Procedure: When the embedded memory chip detects that QEE is asserted for at least 1 second, the device shall transition to QE1:Quick_Erase_Execute. QEE is used to monitor the duration of low level.

QE1: Quick_Erase_Execute state: QE1 is the erase execution state, and enters the erase execution state when QEE- is declared for the last 1 second. In the erasing execution state, the embedded memory chip starts to search for the stored data in all data blocks, and then erases the stored data. When entering the erasing execution state, QEB- is declared by the device, and QEB is used to judge whether the erasing operation is completed.

Transition QE1: QE1 process: It is in the suspended state. When there is a power cycle in the state, the embedded memory chip should continue the erasing process after completing the initialization process.

Transition QE1: QE2 Process: When all data blocks are successfully erased, the embedded memory chip should transition to QE2: Quick_Erase_Finish.

Transition QE1: QE3 process: When the Godson processor or other processors issue any command in the erase execution state, the command can be understood as a control signal, and the embedded memory chip should transition to QE3: Command_Error, fault processing state.

QE2: Quick_Erase_Finish state: It is the end state of erasing, and enters this state after all data blocks are successfully erased. When entering this state, QEB will be canceled by the embedded memory chip.

Transition QE2: QE0 process: After finishing erasing all data blocks, the embedded memory chip should transition to QE0: Device_IDLE state.

QE3: Command_Error state: when Godson processor issues any command or CF/ When the PATA hard disk device sends the HRST/SRST command through the parallel port or the SATA hard disk device sends the SRST/COMREST command through the serial port, if the embedded memory chip is in the erasing execution state of erasing all data blocks, it enters this pause state , the embedded memory chip regards the erasing process as the highest priority, and uses ABRT to return the ERR state (fault state) to the Godson processor, where ABRT is an abort signal.

Transition QE3: QE1: When returning to the ERR state, the embedded memory chip should continue the erase process and transition to QE1: Quick_Erase_Execute.

Embedded memory chips need to pay attention to the following when the smart destruction function is activated:

(1) Before the embedded memory chip executes the intelligent destruction function, pass The MPtool tool imports the program of the erase function into the embedded memory chip, and sets the embedded memory chip to never enter the sleep mode when the erase function is implemented. MPtool Tools can perform operations such as formatting and mass production of storage devices.

(2) The erase function of the embedded memory chip has the highest priority, so in this state, when the embedded memory chip receives any command from any processor, it will not stop executing the erase function, including processing through Godson commands directly transmitted by the device, through the CF / HRST/SRST commands transmitted through the parallel port of the PATA hard disk device and SRST/COMREST commands transmitted through the serial port of the SATA hard disk device. Serial ports and parallel ports are input and output modules.

(3) If the pin QEE is enabled - the GPIO (General-purpose input/output, general-purpose input and output) pin control, enter the erase function when the embedded memory chip enters the idle state and activates the QEE pin for at least 1 second, and the idle state can be understood as the standby state.

(4) If the enable pin QEE- is manually controlled, such as accidentally pressing the enable pin, etc., activate the QEE- pin for at least 3 seconds to enter the erase function.

(5) The busy time to erase all data blocks depends on the flash memory configuration:

Busy time = (erasing time * block number) + (program time * block number) + (cleaning pair time * number of pairs now). Among them, the erasing time is the erasing time of a pre-tested single data block; the block number is the number of the data block that needs to be erased currently; the program time is the time to start the erasing function program when each data block is erased; The cleaning pair time is the time for erasing each data pair; now the number of pairs is the number of data pairs existing in the embedded memory chip, and the data pair includes multiple data blocks. Because some data requires multiple Data blocks are stored to form data pairs.

In this embodiment, the busy time of the erasing function can be controlled at least five seconds to improve erasing efficiency.

(6) Status description:

After the smart destruction is completed, the LBA (Logical Block Address) logical block address is all 0, you can use the WinHex tool to check whether the embedded memory chip is completely destroyed, to ensure that the embedded memory chip cannot be restored after being destroyed, and returns to the unused (before leaving the factory) state. WinHex tool is used to check and repair various files, restore deleted files, data loss caused by hard disk damage, etc.

(7) Before realizing the intelligent destruction function, weld the GPIO interface pin of the Loongson memory with the QE enable pin of the embedded memory chip, and the Loongson processor provides a destruction signal to the embedded chip through the GPIO interface pin, and set Enabling the QE pin to be active low triggers the smart destroy function, which erases all previously stored data even during a power cycle, and the device can continue to be used to store data and be reformatted by the host after the function is complete change.

In an exemplary embodiment, the embedded memory chip includes multiple sets of first differential signal sending and receiving pin pairs, and the multiple sets of first differential signal sending and receiving pin pairs correspond one-to-one to the multiple pin pairs of the bridge chip. A second differential signal sending and receiving pin pair;

The method also includes:

Through the corresponding relationship between the multiple sets of first differential signal sending and receiving pin pairs and the corresponding multiple sets of second differential signal sending and receiving pin pairs, the connection between the embedded memory chip and the bridge chip is constructed in advance. Differential signal transmission channel.

In this embodiment, in order to ensure normal signal transmission between the embedded memory chip and the Godson processor, in an exemplary embodiment, the method further includes pre-establishing a connection between the embedded memory chip and the Godson processor. signal transmission channel. In this embodiment, the signal transmission channel may be a differential signal transmission channel. The multiple sets of first differential signal sending and receiving pin pairs set by the embedded memory chip correspond one-to-one to the multiple sets of second differential signal sending and receiving pin pairs set by the Loongson processor. Both the first differential signal sending and receiving pin pair and the second differential signal sending and receiving pin pair are SATA interfaces. As shown in FIG. 6-1 , it is a schematic diagram of the corresponding relationship between multiple sets of first differential signal sending and receiving pin pairs and multiple sets of second differential signal sending and receiving pins. The embedded memory chip is provided with two sets of first differential signal sending and receiving pin pairs, namely the K8 pin TXN, the K9 pin TXP, the L8 pin RXN and the L9 pin RXP. As shown in Figure 6-2, it is a structural diagram of the bridge chip. There are four sets of second differential signal sending and receiving pin pairs on the bridge chip, which are SATA_RXN0 pin ~ SATA_RXN3 pin, SATA_RXP0 pin Pins ~ SATA_RXP 3 pins, SATA_TXP0 pins ~ SATA_RXP 3 pins, and SATA_TXN0 pins ~ SATA_RXP 3 pins. The embedded memory chip only needs to be connected to four sets of second differential signal sending and receiving pin pairs of the bridge chip to perform data transmission between the Godson processor and the embedded memory chip. The connection mode of the sending interface pin pair follows the way of RX to TX, where RX means receiving differential signals, TX means sending differential signals, P means positive pole, and N means negative pole. If the Loongson processor is wrongly connected, the embedded memory chip will not be recognized, and it needs to be reworked to re-communicate and connect the differential signal sending and receiving pin pairs.

In an exemplary embodiment, the embedded memory chip includes a control module, a flash memory module, a cache module and an input/output interface module.

The embedded memory chip in this embodiment is preferably an AXD SATAIII BGA SSD embedded memory chip, which is a self-developed BGA package embedded memory chip integrating NAND flash memory module, DRAM cache module and self-developed control module . AXD The SATAIII BGA SSD embedded memory chip adopts the SATAIII interface, which can provide a link speed of 6Gbps, making the data transmission rate faster and more efficient.

In an exemplary embodiment, in order to better understand the connection relationship between various modules in the embedded memory chip, refer to FIG. 7-1 , which shows a schematic structural diagram of the embedded memory chip. The embedded memory chip includes bus controller, microprocessor, test module JTAG (Joint Test Action Group, joint test working group, mainly used for chip internal testing), security encoder/decoder, UART interface (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver Transmitter), main system buffer, DMA (Direct Memory Access, direct memory access) controller, DRAM (a computer memory specification cache product) controller, DDR3 (a computer Cache products of memory specification) Cache, flash memory controller, flash chip and SATA interface, among them, bus controller connects microprocessor, security encoder/decoder, UART interface, main system buffer, DMA controller, DRAM controller The test module JTAG is connected with the flash memory controller and the microprocessor, the DRAM controller is connected with the DDR3 cache, the flash memory controller is connected with the flash memory chip, and the embedded memory chip is connected with the external processor through the SATA port. The control module can be a bus controller, a microprocessor and a DMA controller, the flash memory module can be a flash memory controller and a flash memory chip, and the DRAM cache module can be a DRAM controller and a DDR3 cache. The input and output interface module can be a SATA interface and a UART interface.

In an exemplary embodiment, the control module, the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.

Refer to Figure 7-2, which is a rendering of an embedded memory chip packaged by BGA technology. BGA (Ball Grid Array) packaging technology is ball grid array packaging technology, high-density surface mount packaging technology. On the bottom of the package, the pins are ball-shaped and arranged in a grid-like pattern, hence the name BGA. The embedded memory chip packaged with BGA technology can increase the memory capacity of the embedded memory chip by two to three times while maintaining the same volume. Compared with TSOP, BGA has smaller volume, better heat dissipation performance and electrical conductivity. performance. BGA packaging technology has greatly improved the storage capacity per square inch. Under the same capacity, the embedded memory chip using BGA packaging technology is only one third of the volume of TSOP packaging; compared with the traditional TSOP packaging method, BGA packaging There is a more rapid and effective way to dissipate heat.

In an exemplary embodiment, the embedded memory chip is connected to an external power supply through an external power supply circuit, and the power supply circuit is used to supply power to the embedded memory chip;

Before receiving the destruction signal transmitted by the Godson processor, the method also includes:

receiving the first voltage transmitted by the first output terminal of the power supply circuit through the control module;

receiving the second voltage transmitted by the second output terminal of the power supply circuit through the input-output interface module;

receiving the third voltage transmitted by the third output terminal of the power supply circuit through the buffer module;

The fourth voltage transmitted by the fourth output end of the power supply circuit is received by the flash memory module.

In order to improve the power supply efficiency of the embedded cache chip, each module of the embedded memory chip is powered by a power supply circuit. The power supply circuit divides and outputs four voltage output terminals. Wherein, in this embodiment, the first voltage is preferably 1.1V, the second voltage is 3.3V, the third voltage is 1.5V, and the fourth voltage is 1.8V. That is, the power supply voltage required by the control module is 1.1V, the power supply voltage required by the NAND flash memory module is 1.8V, the power supply voltage required by the DRAM module cache is 1.5V, and the power supply voltage required by the IO input and output interface module is 3.3V. The first output terminal of the power supply circuit is VCCK, the second output terminal of the power supply circuit is VCC3F, the third output terminal of the power supply circuit is VCCDQ, and the fourth output terminal of the power supply circuit is VCCFQ.

In an exemplary embodiment, the first voltage, the second voltage, the third voltage, and the fourth voltage are provided by the voltage sequence control circuit in the power supply circuit according to a preset power-on sequence. The voltage transmitted by the embedded memory chip. The preset power-on sequence is 1.1V>3.3V>1.5V>1.8V, that is, the power-on sequence is preset as 1.1V voltage power-on earlier than 3.3V voltage, 3.3V voltage power-on earlier than 1.5V voltage, 1.5V voltage Power on earlier than 1.8V voltage. If the preset power-on sequence is not met, the disk will not be recognized, that is, the Loongson processor cannot recognize the embedded memory chip, which ensures the stability of the connection between the Loongson processor and the embedded memory chip, so that the Loongson processor The embedded memory chip can be read normally. The setting of the voltage sequence control circuit can ensure that the external power supply circuit can supply power to each module of the embedded memory chip according to the preset power-on sequence, and uniformly and effectively manage the power-on of each module of the embedded memory chip, effectively Reduce the impact on the power supply grid at the moment when each module is powered on at the same time, ensuring the stability and safety of power consumption.

In order to ensure that the embedded memory chip can be normally identified by the Loongson processor, please refer to Figure 8, the method further includes: performing an identification test operation on the embedded memory chip after independent research and development in advance, as follows;

Step S400, sending a first test differential signal to the Loongson processor through the at least one set of first differential signal sending and receiving pin pairs;

Step S402, generating a second test differential signal based on the first test differential signal through at least one set of second differential signal transmit and receive pin pairs corresponding to the at least one set of first differential signal transmit and receive pin pairs;

Step S404, when receiving the second test differential signal returned by the Godson processor, determine to establish a signal transmission channel with the Godson processor;

Step S406, after establishing the signal transmission channel, receiving multiple voltages transmitted by the power supply circuit, and the voltage values of each voltage are inconsistent;

Step S408, judging whether the multiple voltages are received according to the preset power-on sequence;

Step S410, if the multiple voltages are received according to the preset power-on sequence, determine to establish a connection with the Godson processor, so that the Godson processor can identify the embedded memory chip.

In an exemplary embodiment, if at least one set of second differential signal transmitting and receiving pin pairs corresponding to the at least one set of first differential signal transmitting and receiving pin pairs is not received within a preset time based on the first The second test differential signal returned by the first test differential signal determines that the signal transmission connection with the Godson processor fails, that is, the embedded memory chip cannot be recognized by the Godson processor, and it is determined that the embedded memory chip enters rework state to reconfigure the embedded memory chip.

If the plurality of voltages are not received according to the preset power-on sequence, it is determined that the connection with the Godson processor fails, that is, the embedded memory chip cannot be powered on normally, resulting in the embedded memory chip being unable to be powered by Godson. The processor identifies and determines that the embedded memory chip enters a rework state, so as to reconfigure the embedded memory chip.

In an exemplary embodiment, the power supply circuit includes a first power supply circuit and a second power supply circuit, the first power supply circuit is used to transmit the first voltage to the control module, and transmit the second voltage to the The input and output interface module transmits the fourth voltage to the flash memory module, and the second power supply circuit is used to transmit the third voltage to the cache module; please refer to Figure 9-1 and Figure 9-2 , FIG. 9-1 schematically shows a schematic diagram of the power supply principle of the first power supply circuit, and FIG. 9-2 schematically shows a schematic diagram of the power supply principle of the second power supply circuit. details as follows:

As shown in Figure 9-1, the first power supply circuit:

The first power supply circuit includes a first power supply chip, and the first power supply chip includes multiple sets of first power input interfaces, such as two sets of VIN1, two sets of VIN2, two sets of VIN3 and VIN, and the multiple sets of first The power input interface is connected to an external power supply. Exemplarily, two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through wires, and are all connected to an external power supply VCCIN. Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected to a capacitor and then grounded.

The first power supply chip also includes a first output interface VOUT3 and a second output interface, the second output interface includes a second main output interface VOUT1 and a second I/O output interface VOUT2; the first power supply circuit includes The first inductor L6 for voltage stabilization, the second inductor L3 for voltage stabilization, the first capacitor C31 for coupling, the second capacitor C41 for coupling, and the third capacitor C30 for coupling;

One end of the first inductor L6 is connected to the first inductor connection port LX3 of the first power supply chip, and the other end of the first inductor L6 is connected to the input terminal VCCK of the control module and the first output interface VOUT3 , the first output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor 31 is grounded;

The second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory, the second main output interface VOUT1 is connected to one end of the second capacitor C41, and the other end of the second capacitor C41 is grounded;

The second I/O output interface VOUT2 is connected to one end of the second inductor L3, and one end of the second inductor L3 is also connected to the second input end VCCFQ of the flash memory, and the other end of the second inductor L3 is connected to the The second inductor of the first power supply chip is connected to the port LX3, the second I/O output interface VOUT2 is connected to one end of the third capacitor C19, and the other end of the third capacitor C19 is grounded.

As shown in Figure 9-2, the second power supply circuit:

The second power supply circuit includes a second power supply chip, the second power supply chip includes a second power input interface VIN, an enable pin EN, a feedback pin FB and a conversion pin SW, the second power input The interface VIN is connected to the external power supply VCCN, and the enable pin QE is connected to the standby pin DEVSLP of the first power supply chip; the second power supply circuit includes a voltage stabilizing circuit composed of a fourth capacitor C22, a third inductor L4 and a resistor R17. One end of the fourth capacitor C22 is connected to the feedback pin FB, the other end of the fourth capacitor C22 is connected to the third output terminal VCCDQ; one end of the third inductor L4 is connected to the switching pin SW, and the other end of the third inductor L4 is connected to the third output terminal VCCDQ; one end of the first resistor R17 is connected to the feedback pin FB, and the other end of the first resistor R17 is connected to the third output terminal VCCDQ. The connecting end of the first resistor R17, the fourth capacitor C22 and the feedback pin FB is connected to the second resistor R18, and the other end of the second resistor R18 is grounded.

In order to ensure the normal operation of the embedded memory chip when the power supply circuit cannot supply power to the embedded memory chip or cannot supply power in time, in an exemplary embodiment, the first power supply circuit is connected to one or more A first decoupling capacitor for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage; the second power supply circuit is connected to one or more A fourth decoupling capacitor for energy storage;

The method also includes:

If the external power supply is disconnected from the power supply circuit, then

receiving a fifth voltage provided by the first decoupling capacitor through the control module;

receiving a sixth voltage provided by the second decoupling capacitor through the input-output interface module;

receiving a seventh voltage provided by the third decoupling capacitor through the flash memory module;

The eighth voltage provided by the fourth decoupling capacitor is received by the cache module.

Through the first decoupling capacitor, the second decoupling capacitor, the third decoupling capacitor and the fourth decoupling capacitor, the interference of other signals is avoided during signal transmission, and the first decoupling capacitor, the second decoupling capacitor, Both the third decoupling capacitor and the fourth decoupling capacitor have the function of buffering energy. When the high-frequency device is working, under the influence of the frequency, a large inductance will be generated, which will cause the power supply of each module of the embedded memory chip to be untimely or when the power supply circuit is disconnected from the embedded memory chip. The coupling capacitor supplies power to each module of the embedded memory chip in time to ensure that the embedded memory chip can operate normally.

In an exemplary embodiment, the embedded memory chip is further connected with a smart destruction socket, and the intelligent destruction socket is electrically connected with the embedded memory chip; the method includes:

The destruction signal generated by the smart socket short circuit is received by the embedded memory chip.

When the Godson processor has an emergency and cannot send a destroy signal, in order to ensure the smooth execution of the destroy function of the embedded memory chip in an emergency, this embodiment also sets an intelligent destroy socket on the Godson processor. The intelligent destruction strip is electrically connected to the enabling pin of the embedded memory chip that starts the intelligent destruction function, and the enabling pin is short-circuited by means of the intelligent destruction strip cap, thereby giving the enabling pin a Low level, to realize the control of enabling the intelligent destruction function of the embedded memory chip. The intelligent destruction function is realized by direct blocking and short-circuiting. If it is a plug-and-plug short-circuiting method, the preset time is preferably up to one second, which can ensure that the destruction time is within 5 seconds, which improves the efficiency of intelligent destruction.

The serial numbers of the above embodiments of the present invention are for description only, and do not represent the advantages and disadvantages of the embodiments.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation.

The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technical fields , are all included in the scope of patent protection of the present invention in the same way.

Claims (8)

1. An intelligent destruction method based on a Godson processor, characterized in that an embedded memory chip is pasted on the upper board of the Godson processor, the Godson processor is connected with a bridge, and the embedded memory chip passes through the bridge Electrically connecting the Godson processor, the method includes:

   Sending a destroy signal to the bridge chip through the Godson processor, the destroy signal is used to instruct the embedded memory chip to erase the storage data stored in the embedded chip by the Godson processor;

   The destroy signal is transmitted to the embedded memory chip through a preset differential signal transmission channel between the bridge chip and the embedded memory chip, and the destroy signal is a signal transmitted based on the SATA protocol;

   Perform the following operations through the embedded memory chip:

   receiving said destroy signal;

   When receiving the destruction signal transmitted by the Godson processor, monitor the duration of the destruction signal;

   judging whether the duration meets a preset time;

   If the duration satisfies the preset time, determine to enter the erasing execution state, and perform an erasing operation on the stored data based on the erasing execution state;

   judging whether the erasing operation is completed through a preset judging condition; and

   If it is determined that the erasing operation is completed, enter the standby state;

   The method also includes:

   When the embedded memory chip is in the erasing execution state, if any control signal of the Godson processor is received, it will enter the fault processing state from the erasing execution state; any one of the control signals is used Instructing the embedded memory chip to enter a corresponding task execution state;

   The embedded memory chip generates an error signal in response to any one of the control signals, and returns the error signal to the Godson processor, and the error signal is used to indicate that the embedded memory chip enters the corresponding task execution status failed; and

   After sending the error signal, the embedded memory chip enters the erasing execution state from the fault processing state to continue the erasing operation;

   The method also includes:

   When the embedded memory chip is in the erasing execution state, if it receives a power cycle signal, it enters the erasing suspend state from the erasing execution state, and the power cycle signal is used to indicate that the embedded memory chip The chip performs a power cycle operation;

   the embedded memory chip performs a power cycle operation according to the power cycle signal; and

   After the power cycle operation is completed, the embedded memory chip enters the erase execution state from the erase suspend state to continue the erase operation.
2. The intelligent destruction method based on the Godson processor according to claim 1, wherein the embedded memory chip includes multiple sets of first differential signal sending and receiving pin pairs, and the multiple sets of first differential signal sending and receiving pin pairs The pairs of pins correspond to multiple sets of second differential signal sending and receiving pin pairs of the bridge piece;

   The method also includes:

   Through the corresponding relationship between the multiple sets of first differential signal sending and receiving pin pairs and the corresponding multiple sets of second differential signal sending and receiving pin pairs, the connection between the embedded memory chip and the bridge chip is constructed in advance. Differential signal transmission channel.
3. The intelligent destruction method based on the Godson processor according to claim 1, wherein the embedded memory chip includes a control module, a flash memory module, a cache module and an input/output interface module.
4. The intelligent destruction method based on the Godson processor according to claim 3, wherein the control module, the flash memory module, the cache module and the input/output interface module are packaged in the embedded inside the memory chip.
5. The intelligent destruction method based on the Godson processor according to claim 4, wherein the embedded memory chip is connected to an external power supply through an external power supply circuit, and the power supply circuit is used to supply power to the embedded memory chip;

   Before receiving the destruction signal transmitted by the Godson processor, the method also includes:

   receiving the first voltage transmitted by the first output terminal of the power supply circuit through the control module;

   receiving the second voltage transmitted by the second output terminal of the power supply circuit through the input-output interface module;

   receiving the third voltage transmitted by the third output terminal of the power supply circuit through the buffer module;

   The fourth voltage transmitted by the fourth output end of the power supply circuit is received by the flash memory module.
6. The intelligent destruction method based on the Godson processor according to claim 5, wherein the first voltage, the second voltage, the third voltage and the fourth voltage are the voltages in the power supply circuit The voltage sequence control circuit transmits the voltage to the embedded memory chip according to the preset power-on sequence.
7. The intelligent destruction method based on the Godson processor according to claim 6, wherein the power supply circuit comprises a first power supply circuit and a second power supply circuit, and the first power supply circuit is used to transmit the first voltage to The control module transmits the second voltage to the input-output interface module and transmits the fourth voltage to the flash memory module, and the second power supply circuit is used to transmit the third voltage to the cache module ;

   The first power supply circuit is connected with one or more first decoupling capacitors for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage. A coupling capacitor; the second power supply circuit is connected with one or more fourth decoupling capacitors for energy storage;

   The method also includes:

   If the external power supply is disconnected from the power supply circuit, then

   receiving a fifth voltage provided by the first decoupling capacitor through the control module;

   receiving a sixth voltage provided by the second decoupling capacitor through the input-output interface module;

   receiving a seventh voltage provided by the third decoupling capacitor through the flash memory module;

   The eighth voltage provided by the fourth decoupling capacitor is received by the cache module.
8. The intelligent destruction method based on the Godson processor according to claim 1, wherein the embedded memory chip is also connected with an intelligent destruction socket, and the intelligent destruction socket is electrically connected with the embedded memory chip; The methods include:

   The erasing signal generated by the intelligent erasing row-socket short circuit is received through the embedded memory chip.