WO2023019634A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023019634A1
WO2023019634A1 PCT/CN2021/115370 CN2021115370W WO2023019634A1 WO 2023019634 A1 WO2023019634 A1 WO 2023019634A1 CN 2021115370 W CN2021115370 W CN 2021115370W WO 2023019634 A1 WO2023019634 A1 WO 2023019634A1
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WIPO (PCT)
Prior art keywords
layer
electric field
pixel
display panel
electrode
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PCT/CN2021/115370
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English (en)
French (fr)
Inventor
赵金阳
陈黎暄
石志清
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/600,112 priority Critical patent/US20240057461A1/en
Priority to JP2021553032A priority patent/JP2023541726A/ja
Publication of WO2023019634A1 publication Critical patent/WO2023019634A1/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41MPRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M3/00Printing processes to produce particular kinds of printed work, e.g. patterns
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41MPRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00Duplicating or marking methods; Sheet materials for use therein
    • B41M5/0041Digital printing on surfaces other than ordinary paper
    • B41M5/0047Digital printing on surfaces other than ordinary paper by ink-jet printing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/124Insulating layers formed between TFT elements and OLED elements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80Constructional details
    • H10K59/805Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80Constructional details
    • H10K59/805Electrodes
    • H10K59/8052Cathodes
    • H10K59/80522Cathodes combined with auxiliary electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10Deposition of organic active material
    • H10K71/12Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301Details of OLEDs
    • H10K2102/341Short-circuit prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/123Connection of the pixel electrodes to the thin film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/126Shielding, e.g. light-blocking means over the TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/811Controlling the atmosphere during processing

Definitions

  • the present application relates to the field of display technology, in particular to a display panel.
  • OLED displays prepared by inkjet printing technology have achieved small-scale commercialization in the field of medium-sized OLEDs.
  • fundamental problems in inkjet printing First, due to the capillary phenomenon of the ink, the pixel definition layer needs to be lyophobic to reduce the problem of thicker film thickness at the edge of the pixel caused by edge climbing. Second, the ink needs to have a high boiling point to prevent the volatilization of the solution on the pixel and the nozzle during the printing process, resulting in uneven deposition or clogging the nozzle.
  • the inventors of the present application found that the charged groups in the luminescent functional layer tend to produce coffee rings when the solvent volatilizes during the inkjet printing and vacuum drying process, which affects the quality of the luminescent functional layer .
  • An embodiment of the present application provides a display panel.
  • the structure of the display panel can generate an electric field, and the electric field can be used to assist inkjet printing and vacuum drying to suppress the generation of coffee rings.
  • An embodiment of the present application provides a display panel, including:
  • a pixel electrode layer, the pixel electrode layer is disposed on the array substrate, and the pixel electrode layer includes a plurality of pixel electrodes;
  • An electric field electrode layer is disposed on the array substrate, the electric field electrode layer is insulated from the pixel electrode layer, and the electric field electrode layer includes at least one electric field electrode; wherein, the electric field electrode at least surrounds A portion of the pixel electrode is set.
  • the electric field electrodes correspond to the pixel electrodes one by one, and the electric field electrodes are arranged around the pixel electrodes to form a closed pattern.
  • the pixel electrodes are arranged in multiple rows along the first direction
  • the pixel electrodes are arranged in multiple rows along the second direction
  • the electric field electrode includes a first part and a second part. Two parts, the first part is arranged between two adjacent rows of the pixel electrodes along the first direction, and the second part is arranged between two adjacent rows of the pixel electrodes along the second direction Between, the first part is connected to the second part, and the first direction intersects with the second direction.
  • the pixel electrodes are arranged in multiple rows along the first direction
  • the pixel electrodes are arranged in multiple rows along the second direction
  • the electric field electrodes are arranged in multiple rows along the first direction.
  • the direction is set between multiple rows of the pixel electrodes, or is set between multiple rows of the pixel electrodes along the second direction, and the first direction intersects with the second direction.
  • the size of the gap is between 1 ⁇ m and 10 ⁇ m.
  • the size of the gap is between 2 ⁇ m and 5 ⁇ m.
  • the array substrate further includes a thin film transistor
  • the display panel further includes a planarization layer
  • the pixel electrode layer is disposed on the planarization layer, and is connected to the TFT connection.
  • the thin film transistor includes a stacked semiconductor layer, a gate insulating layer, a gate layer, an interlayer insulating layer, drain wiring and source wiring, the
  • the electric field electrode layer is a signal wiring layer, and the electric field electrode layer is arranged on the same layer as the gate layer, or the electric field electrode layer is arranged on the same layer as the source wiring and the drain wiring.
  • the electric field electrode layer is an auxiliary electrode layer, and the electric field electrode layer is disposed on the same layer as the pixel electrode layer.
  • the display panel further includes a pixel definition layer, the pixel definition layer is arranged on the side of the pixel electrode layer away from the array substrate, and the pixel definition layer is An opening is provided, and the opening is arranged corresponding to the pixel electrode.
  • the side of the pixel definition layer close to the array substrate is lyophilic, and the side of the pixel definition layer away from the array substrate is lyophobic.
  • the array substrate includes a light-shielding layer, a first capacitive plate, a buffer layer, a semiconductor layer, a second capacitive plate, and a gate insulating layer sequentially stacked on one side of the substrate.
  • layer, gate layer, interlayer insulating layer, drain wiring, source wiring, auxiliary cathode wiring, passivation layer and planarization layer; the pixel electrode layer and electric field electrode layer are arranged on the planarization layer.
  • the material used for the electric field electrode layer may be a combination of one or more of gold, silver, copper, aluminum and transparent metal oxides.
  • the embodiment of the present application also provides a display panel, including:
  • a pixel electrode layer, the pixel electrode layer is disposed on the array substrate, and the pixel electrode layer includes a plurality of pixel electrodes;
  • the pixel electrode has a first electrode portion and a second electrode portion, and the first electrode portion is at least partially disposed around the second electrode portion.
  • the array substrate further includes a thin film transistor
  • the display panel further includes a planarization layer
  • the pixel electrode layer is disposed on the planarization layer, and is connected to the TFT connections;
  • each thin film transistor correspondingly controls the voltage of one of the first electrode part or the second electrode part.
  • the pixel electrodes include m rows ⁇ n columns of sub-pixel electrodes, there are gaps between adjacent sub-pixel electrodes, and the sub-pixel electrodes include first sub-pixel electrodes and a second sub-pixel electrode, the first sub-pixel electrode is at least partially disposed around the second sub-pixel electrode; wherein, m and n are positive integers greater than or equal to 3.
  • the display panel further includes a thin film transistor and a planarization layer, and the pixel electrode layer is disposed on the planarization layer and connected to the thin film transistor;
  • each of the thin film transistors corresponds to controlling the voltage of a row of the sub-pixel electrodes, or each of the thin film transistors corresponds to controlling the voltage of a column of the sub-pixel electrodes.
  • the display panel further includes a thin film transistor and a planarization layer, and the pixel electrode layer is disposed on the planarization layer and connected to the thin film transistor;
  • each thin film transistor controls the voltage of one sub-pixel electrode correspondingly.
  • An embodiment of the present application provides a display panel.
  • the display panel can generate an electric field on the pixel electrode by controlling the voltage difference between the pixel electrode layer and the electric field electrode layer, or by controlling the voltage difference generated inside the pixel electrode layer. Since the two poles generating the electric field of the display panel provided by the present application are specially designed, the distances between the two poles generating the electric field are equal. That is, the shapes of the poles generating the electric field are adapted. This increases the uniformity of the electric field.
  • the vertical component of the electric field provides the charged groups in the material of the luminescent functional layer with a force of deposition to the pixel electrode layer, which can promote the deposition of the ink of the luminescent functional material to the pixel electrode layer during inkjet printing.
  • the electric field-assisted deposition of materials for the luminescent functional layer can suppress the generation of coffee rings, effectively improve the film quality of the luminescent functional layer, and further improve the device performance of the display panel.
  • FIG. 1 is a first structural schematic diagram of a display panel provided by an embodiment of the present application
  • Fig. 2 is a first top view structural schematic diagram of a display panel provided by an embodiment of the present application
  • Fig. 3 is a second top view structural schematic diagram of the display panel provided by the embodiment of the present application.
  • Fig. 4 is a third top view structural schematic diagram of the display panel provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a fourth top view structure of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fifth top view structure of a display panel provided by an embodiment of the present application.
  • FIG. 7 is a second structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a third structure of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a sixth top view structural diagram of the display panel provided by the embodiment of the present application.
  • An embodiment of the present application provides a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • FIG. 1 is a schematic diagram of a first structure of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a first top view structural diagram of the display panel provided by the embodiment of the present application.
  • the display panel 10 provided in this application includes an array substrate 1 , a pixel electrode layer 2 and an electric field electrode layer 3 .
  • the pixel electrode layer 2 is disposed on the array substrate 1 .
  • the electric field electrode layer 3 is disposed on the array substrate 1 .
  • the electric field electrode layer 3 is insulated from the pixel electrode layer 2 .
  • the electric field electrode layer 3 includes a plurality of electric field electrodes 3a.
  • the electric field electrode 3 a is arranged around at least part of the pixel electrode layer 2 .
  • the vertical component of the electric field provides the charged groups in the material of the luminescent functional layer with a force of deposition to the pixel electrode layer 2, which can promote the deposition of the ink of the luminescent functional material to the pixel electrode layer 2 during inkjet printing.
  • the use of electric field-assisted inkjet printing and vacuum drying can effectively suppress the coffee ring effect of charged groups in the luminescent functional layer during deposition and solvent volatilization, and improve the film-forming quality of nanoparticles.
  • the display panel 10 provided by the present application is provided with an electric field electrode layer 3 arranged around the pixel electrode layer 2 The distance is equal to the gap D between the pixel electrode layers 2 , and a more uniform electric field can be formed between the pixel electrode layer 2 and the electric field electrode layer 3 .
  • the uniformity of the electric field is improved, and the uniformity of the luminescent functional layer printed under the assistance of the electric field can also be effectively improved, thereby improving the performance of the light emitting device.
  • the array substrate 1 includes a substrate 1'.
  • the substrate 1' refers to a base member for carrying the touch electrode structure.
  • the substrate 1' can be glass, plexiglass, functional glass (sensor glass), hard insulating film material, soft insulating film material or flexible substrate.
  • the material used for the flexible substrate is a polymer material.
  • the material used for the flexible substrate can be polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyethylene terephthalate (PET) or polyethylene naphthalate (PEN).
  • PI polyimide
  • PE polyethylene
  • PP polypropylene
  • PS polystyrene
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • Polymer materials have good flexibility, light weight and impact resistance, and are suitable for flexible display panels.
  • polyimide can also achieve good heat resistance and stability.
  • the pixel electrode layer 2 may be provided by using a transparent metal oxide or a laminated layer of metal and transparent metal oxide.
  • the pixel electrode layer 2 can also be made of graphene material, metal material, transition metal chalcogen compound and other materials.
  • the transition metal sulfide includes molybdenum sulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), tungsten sulfide (WS 2 ) or tungsten selenide (WSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • WS 2 tungsten sulfide
  • WSe 2 tungsten selenide
  • the material used for the transparent metal oxide layer includes indium gallium zinc oxide, indium zinc tin oxide, indium gallium zinc tin oxide, indium tin oxide, indium zinc oxide, indium aluminum zinc oxide, indium gallium tin oxide or Any of the antimony tin oxides.
  • the above materials have good conductivity and transparency, and the thickness is small, which will not affect the overall thickness of the display panel. At the same time, it can also reduce the harmful electronic radiation and ultraviolet and infrared light.
  • the material used for the metal layer is any one of silver, aluminum, nickel, chromium, molybdenum, copper, tungsten or titanium. The metal has good conductivity and low cost, which can reduce the production cost while ensuring the conductivity of the anode.
  • the pixel electrode layer 2 is deposited as a stack of ITO/Silver/Indium Tin Oxide. It can be understood that the pixel electrode layer 2 can be the anode or cathode of the light emitting device. In this application, the pixel electrode layer 2 is taken as an example for illustration.
  • the material used for the electric field electrode layer 3 may be a combination of one or more of gold, silver, copper, aluminum and transparent metal oxides.
  • the insulation means that there is a gap between the pixel electrode layer 2 and the electric field electrode layer 3 .
  • an inorganic film layer such as a passivation layer, an interlayer insulating layer or a buffer layer may be disposed between the pixel electrode layer 2 and the electric field electrode layer 3 for insulation.
  • the specific setting manner can be adaptively changed according to the specific display panel 10 , which will not be repeated here.
  • the pixel electrode layer 2 and the electric field electrode layer 3 are arranged on the array substrate 1 means that the pixel electrode layer 2 and the electric field electrode layer 3 are arranged on the same side of the array substrate 1 . It is not limited that the pixel electrode layer 2 and the electric field electrode layer 3 are disposed close to the surface of the array substrate 1 .
  • the relative positional relationship between the pixel electrode layer 2 and the electric field electrode layer 3 in the figure is only for illustration and is not intended to limit the present application.
  • the array substrate 1 further includes a thin film transistor 5 .
  • the display panel 10 also includes a planarization layer 23 .
  • the pixel electrode layer is disposed on the planarization layer 23 and connected to the thin film transistor 5 .
  • the thin film transistor 5 includes a semiconductor layer 14 , a gate insulating layer 16 , a gate layer 17 , an interlayer insulating layer 18 , a drain wiring 19 and a source wiring 20 .
  • the array substrate 1 further includes a light-shielding layer 11, a first capacitive plate 12, a buffer layer 13, a semiconductor layer 14, a second capacitive plate 15, a gate insulating layer 16, a electrode layer 17 , interlayer insulating layer 18 , drain wiring 19 , source wiring 20 , auxiliary cathode wiring 21 , passivation layer 22 and planarization layer 23 .
  • the pixel electrode layer 2 and the electric field electrode layer 3 are disposed on the planarization layer 23 .
  • the electric field electrode layer 3 is an auxiliary cathode layer.
  • the semiconductor layer 14 includes a drain region 141 , an active region 142 and a source region 143 .
  • An opening 4 a is provided on the pixel definition layer 4 .
  • FIG. 1 is a schematic diagram taking the thin film transistor 5 as an example with a top-gate structure. It can be understood that the present application does not limit the structure of the thin film transistor 5 included in the display panel 10, which may be a top-gate thin film transistor, or a bottom-gate thin film transistor, which may be a double-gate thin film transistor, It may also be a single-gate thin film transistor. The specific structure of the thin film transistor will not be repeated in this application.
  • the electric field electrode layer 3 is an auxiliary electrode layer, and the electric field electrode layer 3 is disposed on the same layer as the pixel electrode layer 2 .
  • the auxiliary electrode layer can be used as an auxiliary cathode layer connected to the surface cathode to reduce the voltage drop of the surface cathode.
  • the potential of the auxiliary cathode layer, that is, the electric field electrode layer 3 is controlled by the auxiliary cathode wiring 21, so that a voltage difference is formed between the electric field electrode layer 3 and the pixel electrode layer 2, and then an electric field is formed between the pixel electrode layer 2 and the electric field electrode layer 3 .
  • the auxiliary cathode layer and the pixel electrode 2a are in the same sub-pixel, and the distance between the auxiliary cathode layer and the pixel electrode 2a is very small.
  • Using the auxiliary cathode layer as the electric field electrode layer 3 to form an electric field with the pixel electrode 2a can increase the strength of the electric field forming the electric field, so as to obtain a greater assisting effect of the electric field force during inkjet printing.
  • the size of the gap D is between 1 ⁇ m and 10 ⁇ m. Further, the size of the gap D is between 2 ⁇ m and 5 ⁇ m. Specifically, the size of the gap D can be 1 ⁇ m, 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m or 10 ⁇ m. Setting the size of the gap D between 1 ⁇ m and 10 ⁇ m is a comprehensive consideration of the available process accuracy and the formed electric field intensity. If the gap D is too wide, a sufficiently strong electric field cannot be formed between the pixel electrode layer 2 and the electric field electrode layer 3 .
  • the size range of the gap d provided in this application is the optimal size of the gap D for generating an electric field between the pixel electrode layer 2 and the electric field electrode layer 3 to assist in the deposition of the light-emitting functional layer.
  • the value of the gap D affects the intensity of the electric field, thereby affecting the uniformity of the deposition of the luminescent functional layer.
  • the range of the size of the gap D is to obtain a uniform electric field with appropriate strength, which is obtained after many tests, and is not a commonly used and easy-to-think technical means for those skilled in the art.
  • the display panel 10 further includes a pixel definition layer 4 .
  • the pixel definition layer 4 is disposed on the side of the pixel electrode layer 2 away from the array substrate 1 .
  • An opening 4 a is provided on the pixel definition layer 4 .
  • the opening 4a is disposed corresponding to the pixel electrode 2a.
  • the side of the pixel definition layer 4 close to the array substrate 1 is lyophilic, and the side of the pixel definition layer 4 away from the array substrate 1 is lyophobic.
  • Lyophilicity means that the surface of a material is easily wetted or melted by a liquid medium.
  • Lyophobicity also called lyophobicity
  • lyophobicity is the opposite of lyophilicity
  • lyophobicity means that the surface of a material is not easily wetted or melted by a liquid medium.
  • the lyophilic and lyophobic properties of the material surface are mainly determined by the properties of its surface structure or functional groups.
  • the lyophilicity and repellency of the pixel definition layer 4 can be changed and adjusted by adjusting process parameters. For example, parameters of the developing process and curing process are adjusted. Change and adjust the lyophilicity and repellency of the pixel definition layer 4 .
  • the pixel definition layer 4 set in this way can adapt to different printing processes, types of inks and film thicknesses, making the pixel definition layer 4 more easily adaptable to the requirements of different display panels.
  • the thickness of the pixel definition layer 4 will affect the lyophobicity of the material, for example, when the lyophobic material is very thin, it will not have lyophobicity.
  • the oxygen (O 2 ) or nitrogen (N 2 ) plasma treatment of the material can make the lyophobic to lyophilic
  • the fluorine (F) plasma treatment of the material can make the lyophilic to lyophobic sex.
  • the electric field electrode 3a may be arranged around a part of the pixel electrode 2a.
  • the electric field electrode 3a is arranged around half of the pixel electrode 2a in a semicircular shape.
  • the electric field electrode 3a is arranged around the pixel electrode 2a in a U-shape.
  • the electric field electrodes 3 a correspond to the pixel electrodes 2 a one by one.
  • the electric field electrode 3a is arranged around the pixel electrode 2a to form a closed pattern.
  • the electric field electrode 3a is arranged around the pixel electrode 2a and forms a closed pattern. Since an electric field is formed between the electric field electrode 3a and the pixel electrode 2a, voltages are applied to the electric field electrode 3a and the pixel electrode 2a respectively.
  • the electric field electrode 3a forms a closed pattern around the pixel electrode 2a, and when the gap D between the electric field electrode 3a and the pixel electrode 2a is the same in size, that is, the distance between the two poles forming the electric field is consistent, the uniformity of the electric field can be improved. .
  • the electric field electrodes 3a are in one-to-one correspondence with the pixel electrodes 2a and are provided independently.
  • This structure can form an independent electric field on each pixel electrode 2a when forming an electric field. After the independent electric field is formed, it is more convenient to independently manufacture pixels of different colors in the light-emitting functional layer, and the electric field of each pixel electrode can be independently adjusted. In this way, the display panel 10 is more suitable for fabrication of light-emitting functional layers with different pixel arrangement requirements.
  • the electric field electrodes 3 a are respectively one-to-one corresponding to the pixel electrodes 2 a for illustration.
  • the electric field electrode layer 3 comprises a continuous pattern forming a plurality of electric field electrodes 3a.
  • FIG. 3 is a second top view structural diagram of the display panel provided by the embodiment of the present application.
  • a voltage is applied to the electric field electrodes 3a in the same row at the same time, and then the voltage of the pixel electrodes 2a corresponding to the row is controlled to form an electric field in the row.
  • the same row of pixels is the same color light emitting functional layer, the production efficiency of the light emitting functional layer can be improved.
  • FIG. 4 is a schematic structural diagram of a third top view of a display panel provided by an embodiment of the present application.
  • the pixel electrode layers 2 are arranged in multiple rows along the first direction x, and the pixel electrode layers 2 are arranged in multiple rows along the second direction y. There are gaps S between the pixel electrode layers 2 .
  • the electric field electrode 3a includes a first portion 31a and a second portion 32a.
  • the first part 31a is arranged between two adjacent rows of pixel electrodes 2a along the first direction x, and the second part 32a is arranged between multiple rows of pixel electrodes 2a along the second direction y.
  • the first part 31a is connected to the second part 32a.
  • the first direction x intersects the second direction y.
  • the first direction x is a direction extending along the x-axis
  • the second direction y is a direction extending along the y-axis. Therefore, in this application, the first direction x and the second direction y are used for description.
  • the first direction x and the second direction y are perpendicular to each other for illustration. In fact, the first direction x and the second direction y may be any two directions that intersect.
  • the pixel electrode layer 2 in FIG. 2 and FIG. 3 is arranged in an oval shape, and the pixel electrode layer 2 in FIG. 4 is arranged in a rectangular shape, and the pixel electrode layer 2 can also be arranged in other shapes.
  • the pixel electrode layer 2 may be arranged in a pattern such as a circle or a rhombus to facilitate pixel arrangement, which is not limited in the present application.
  • the electric field electrodes 3a are arranged between multiple rows of pixel electrodes 2a along the first direction x, and between multiple rows of pixel electrodes 2a along the second direction y. Then the electric field electrodes 3 a can be arranged in the gaps in a mesh shape along the first direction x and the second direction y as shown in FIG. 4 .
  • FIG. 5 is a fourth top view structural diagram of the display panel provided by the embodiment of the present application.
  • the pixel electrode layers 2 are arranged in multiple rows along the first direction x, and the pixel electrode layers 2 are arranged in multiple rows along the second direction y. There are gaps S between the pixel electrode layers 2 .
  • the electric field electrodes 3a are arranged between multiple rows of pixel electrodes 2a along the first direction x, or between multiple rows of pixel electrodes 2a along the second direction y. That is, the electric field electrode 3a can also be arranged in the gap in the shape of a strip along one of the first direction x or the second direction y.
  • a part of the electric field electrode 3a is arranged in a certain layer along the first direction x, and another part of the electric field electrode 3a is arranged in another film layer along the second direction y.
  • the first direction x and the second direction y may be any two directions that intersect.
  • the electric field electrode layer 3 is a signal wiring layer.
  • the electric field electrode layer 3 and the gate layer 17 are provided in the same layer.
  • the electric field electrode layer 3 is set on the same layer as the source wiring 20 and the drain wiring 19 .
  • the signal wiring layer includes scanning signal wiring 31 and data signal wiring 32 .
  • the electric field electrode layer 3 can be the scanning signal wiring 31 or the data signal wiring 32 , or the electric field electrode layer 3 can be formed by surrounding the pixel electrode layer 2 by the scanning signal wiring 31 and the data signal wiring 32 .
  • the electric field electrode layer 3 when the electric field electrode layer 3 is the scanning signal wiring 31 , it may be arranged in the space S between the pixel electrodes 2 a along the first direction x. Voltages are respectively applied to the scanning signal wiring 31 and the pixel electrode 2a to form a uniform horizontal electric field along the second direction y between the scanning signal wiring 31 and the pixel electrode 2a.
  • the method of forming an electric field between the data signal wire 32 and the pixel electrode 2a is similar to the above, and will not be repeated here.
  • the electric field electrode layer 3 when the electric field electrode layer 3 is the scanning signal wiring 31 and the data signal wiring 32, the electric field electrode layer 3 can be arranged in a grid between the pixel electrodes 2a along the first direction x and the second direction y. in the gap S.
  • the electric field formed by the electric field electrode layer 3 and the pixel electrode 2a is a uniform electric field in which electric field lines travel from the electric field electrode layer 3 to the pixel electrode 2a.
  • the electric field formed by the electric field electrode layer 3 and the pixel electrode 2 a is a uniform electric field in which electric field lines travel from the pixel electrode 2 a to the electric field electrode layer 3 .
  • the electric field is formed by using the signal wires in the thin film transistor 5 and the pixel electrodes.
  • the electric field between the pixel electrode layer 2 and the electric field electrode layer 3 can be selected for inkjet printing.
  • the thickness of the film layer formed by the surrounding light-emitting functional layer can prevent the pixel electrode layer 2 from forming an electrical shield, affecting the effect of the electric field force, ensuring the printing effect of the sub-pixel light-emitting functional layer, and making ink deposition more uniform.
  • the electric field electrode layer 3 may also be other wires in the display panel 10 , such as reset signal wires, etc., which is not limited in this application.
  • FIG. 6 is a fifth top view structural diagram of the display panel provided by the embodiment of the present application.
  • the display panel 10 provided by the embodiment of the present application includes an array substrate 1 and a pixel electrode layer 2 .
  • the pixel electrode layer 2 is disposed on the array substrate 1 .
  • the pixel electrode layer 2 includes a plurality of pixel electrodes 2a.
  • the pixel electrode 2 a has a first electrode portion 2A and a second electrode portion 2B.
  • the first electrode portion 2A is provided around at least part of the second electrode portion 2B.
  • the embodiment shown in FIG. 8 provides a display panel 10, which directly utilizes the first electrode portion 2A and the second electrode portion 2B of the pixel electrode 2a to form an electric field, and there is no need to control the voltage values of other electrodes.
  • An electric field is formed in the pixel electrode 2a, and when the electric field assists the deposition of the luminescent functional layer, the force of the generated electric field is relatively large, which can make the deposition of the luminescent functional layer more uniform.
  • the first electrode part 2A is arranged around the second electrode part 2B, it is beneficial to improve the uniformity of the electric field generated by the first electrode part 2A and the second electrode part 2B.
  • FIG. 7 is a second structural schematic diagram of the display panel provided by the embodiment of the present application.
  • the display panel 10 also includes a thin film transistor 5 and a planarization layer 23 .
  • the pixel electrode layer 2 is disposed on the planarization layer 23 and connected to the thin film transistor 5 .
  • FIG. 8 is a schematic diagram of a third structure of a display panel provided by an embodiment of the present application.
  • Each thin film transistor 5 correspondingly controls the voltage of a first electrode portion 2A or a second electrode portion 2B.
  • Each thin film transistor 5 correspondingly controls the voltage of one electrode portion, so that a voltage difference is formed between the first electrode portion 2A or the second electrode portion 2B. This arrangement can fine-tune the potential difference and the electric field in the sub-pixel.
  • FIG. 9 is a sixth top view structural diagram of the display panel provided by the embodiment of the present application.
  • the pixel electrode 2a includes m rows ⁇ n columns of sub-pixel electrodes 2a'. There is a gap between adjacent sub-pixel electrodes 2a'.
  • the subpixel electrode 2a' includes a plurality of first subpixel electrodes 21a' and at least one second subpixel electrode 22a'.
  • the first sub-pixel electrode 21a' is arranged around at least part of the second sub-pixel electrode 22a'.
  • m and n are positive integers greater than or equal to 3.
  • the sub-pixel electrodes 2a' are insulated from each other, and are only divided by black solid lines in the figure.
  • the sub-pixel electrodes 2a' in the row and column directions are formed in the pixel electrode 2a, the manufacturing process is simple, and no complicated patterning method is required. Moreover, such an arrangement of the sub-pixel electrodes 2a' is more convenient for the manufacture of the corresponding thin film transistors. Moreover, the distance between the sub-pixel electrodes 2a' is relatively close, which can generate a strong electric field force, further improve the electrodeposition effect, shorten the time required for the electric field-assisted deposition of the light-emitting functional layer, and improve the film formation quality.
  • each thin film transistor 5 correspondingly controls the voltage of a row of sub-pixel electrodes 2a'. Or, each thin film transistor 5 correspondingly controls the voltage of a column of sub-pixel electrodes 2a'. Or, each thin film transistor 5 correspondingly controls the voltage of one sub-pixel electrode 2a'. Only two thin film transistors 5 are shown in each sub-pixel area in FIG. 9 , but this is not a limitation to the present application.
  • Each thin film transistor 5 controls the voltage of a row of sub-pixel electrodes 2a' or correspondingly controls the voltage of a column of sub-pixel electrodes 2a', which can form high and low potentials in the sub-pixel.
  • the high and low potentials between the rows and columns cause a voltage difference between the sub-pixel electrodes 2a' and the sub-pixel electrodes 2a', further forming an electric field.
  • the thin film transistor 5 controls the voltage of one row or one column of subpixel electrodes 2a', the centermost row of subpixel electrodes 2a' can be used as the second electrode part 2B, and the surrounding subpixel electrodes 2a' can be used as the first electrode part 2A.
  • the electric field strength between the sub-pixel electrodes 2a' is relatively large, which can provide sufficient electric field force to assist the printing process of the light-emitting functional layer. Moreover, this way requires fewer thin film transistor devices 6 , which can reduce the difficulty and precision of the manufacturing process.
  • Each thin film transistor device 6 correspondingly controls the voltage of a sub-pixel electrode 2a', so that a voltage difference is formed between the sub-pixel electrode 2a' and the sub-pixel electrode 2a'.
  • This arrangement can fine-tune the potential difference and the electric field in the sub-pixel.
  • the pixel electrode 2a is divided into 3 ⁇ 3 nine sub-pixel electrodes 2a'.
  • the sub-pixel electrode 2a' in FIG. 7 can be taken as an example where a is equal to 1, the outermost circle of sub-pixel electrodes 2a' is used to form the first electrode part 2A, and one sub-pixel electrode 2a' in the center is used to form the second electrode Part 2B.
  • the first sub-pixel electrode 21a' is used as the first electrode portion 2A
  • the second sub-pixel electrode 22a' is used as the second electrode portion 2B.
  • the display panel 10 provided in the embodiment of the present application can generate an electric field on the pixel electrode 2 a by controlling the voltage difference between the pixel electrode layer 2 and the electric field electrode layer 3 , or controlling the voltage difference generated inside the pixel electrode layer 2 .
  • the two poles generating the electric field of the display panel 10 provided by the present application are specially designed, the distances between the two poles generating the electric field are equal. That is, the shapes of the poles generating the electric field are adapted. This increases the uniformity of the electric field.
  • the vertical component of the electric field provides the charged groups in the material of the luminescent functional layer with a force of deposition to the pixel electrode layer 2, which can promote the deposition of the ink of the luminescent functional material to the pixel electrode layer 2 during inkjet printing.
  • the electric field assisted deposition of materials for the luminescent functional layer can suppress the coffee ring effect, effectively improve the film quality of the luminescent functional layer, and further improve the device performance of the display panel 10 .
  • the electric field generated in the display panel 10 of the present application can also be used when the light-emitting functional layer material is drying.
  • the charged groups in the solution of the light-emitting function layer are fixed by the uniform electric field on the pixel electrode layer 2 .
  • using the electric field in the drying stage to fix the charged groups does not require strict air extraction control during the solvent volatilization process, and the drying process is carried out, which greatly simplifies the vacuum drying process and improves the processing efficiency.
  • the shapes of the two electrodes forming the electric field are designed, and the distances between the gaps D or gaps G between the electrodes are equal.
  • the two electrodes can generate a uniform electric field, which optimizes the dispersion path of the movement of charged groups during electric field-assisted deposition or electric field-assisted drying, making the film deposition more uniform.
  • the display effect and device performance of the display panel 10 can be improved.
  • the structure of the display panel 10 provided in this application can also be used for deposition and drying of other film layers.
  • the solute in the film layer is suitable for the solute in the film layer to be one or more combinations of inorganic nanoparticles, noble metal nanoparticles, colloidal nanosheets and colloidal nanorod nanofilm layers.
  • the nanoparticles can be barium sulfate (BaSO 4 ), calcium carbonate (CaCO 3 ), cesium zinc oxide (ZnSe), cadmium sulfide (CdS), titanium dioxide (TiO 2 ), barium titanate (BaTiO 3 ), zinc sulfide
  • barium sulfate BaSO 4
  • CaCO 3 calcium carbonate
  • ZnSe cesium zinc oxide
  • CdS cadmium sulfide
  • TiO 2 titanium dioxide
  • BaTiO 3 barium titanate
  • zinc sulfide One or more combinations of (ZnS), zirconia (ZrO 2 ), silicon nitride (Si 3 N 4 ), tin oxide (SnO) and zinc oxide (ZnO).
  • the solute in the solution of the luminescent functional layer in this application may be a quantum dot material.
  • the luminescent core material of the quantum dot material is one or more combinations of ZnCdSe 2 , InP, Cd 2 SSe, CdSe, Cd 2 SeTe and InAs.
  • the inorganic protective shell material of the quantum dot material is a combination of one or more of CdS, ZnSe, ZnCdS2, ZnS, and ZnO.
  • Quantum dot materials may also include hydrogel-loaded quantum dot structures, CdSe- SiO2 quantum dots, and perovskite quantum dots.
  • the surface ligands of quantum dot materials include one or more combinations of amines, acids, mercaptools and organic phosphorus.
  • the solvent in the light-emitting functional layer and the solution can be a colorless, transparent, low-boiling organic or inorganic solvent.
  • the solvent may be one or a combination of deionized water, methanol, ethanol, ethylene glycol, propylene glycol, ethyl acetate, petroleum ether or n-hexane.
  • the target pixel electrode 2a where the quantum dot material is deposited is positively charged.
  • the target pixel electrode 2a where the quantum dot material is deposited is negatively charged. In this way, the best effect of deposition is guaranteed.
  • the time for applying the voltage can be selected after the solution of the luminescent functional layer completely covers the pixel electrode 2a, so that under the action of a uniform electric field, the charged groups in the luminescent functional layer can be deposited more uniformly and completely cover the pixel electrode 2a.

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Abstract

本申请实施例提供一种显示面板。显示面板在像素电极上产生电场。在本申请提供的显示面板中,由于对产生电场的两极进行了特殊设计,使得产生电场的两极之间各处的距离相等,提高了电场的均匀性。电场辅助发光功能层材料沉积和发光功能层干燥,可以抑制咖啡环效应。

Description

显示面板 技术领域
本申请涉及显示技术领域,具体涉及显示面板。
背景技术
喷墨打印技术制备的有机发光二极管(Organic Light-Emitting Diode, OLED)显示器,已经在中尺寸OLED领域实现了小规模商品化。但是喷墨打印存在根本性的问题:第一、由于墨水的毛细现象,需要像素定义层具有疏液性,以降低边缘攀爬导致的像素边缘膜厚偏厚的问题。第二、需要墨水具有高沸点,防止打印过程中像素上和喷头上的溶液挥发导致沉积不均匀或堵塞喷头。
在对现有技术的研究和实践过程中,本申请的发明人发现,在喷墨打印和真空干燥过程发光功能层中的带电基团在溶剂挥发时易产生咖啡环,影响发光功能层的品质。
技术问题
本申请实施例提供一种显示面板,显示面板的结构可以产生电场,利用电场辅助喷墨打印和真空干燥,抑制咖啡环的产生。
技术解决方案
本申请实施例提供一种显示面板,包括:
阵列基板;
像素电极层,所述像素电极层设置在所述阵列基板上,所述像素电极层包括多个像素电极;
电场电极层,所述电场电极层设置在所述阵列基板上,所述电场电极层与所述像素电极层绝缘设置,所述电场电极层包括至少一个电场电极;其中,所述电场电极至少围绕所述像素电极的部分设置。
可选的,在本申请的一些实施例中,所述电场电极与所述像素电极之间具有间隙,所述电场电极绕设所述像素电极的部分与所述像素电极之间的间隙距离相等。
可选的,在本申请的一些实施例中,所述电场电极与所述像素电极一一对应,所述电场电极围绕所述像素电极设置形成一封闭图案。
可选的,在本申请的一些实施例中,所述像素电极沿第一方向排布有多排,所述像素电极沿第二方向排布有多行,所述电场电极包括第一部分和第二部分,所述第一部分沿所述第一方向设置在相邻的两排所述像素电极之间,所述第二部分沿所述第二方向设置在相邻的两行所述像素电极之间,所述第一部分与所述第二部分相连,所述第一方向与所述第二方向相交。
可选的,在本申请的一些实施例中,所述像素电极沿第一方向排布有多排,所述像素电极沿第二方向排布有多行,所述电场电极沿所述第一方向设置在多排所述像素电极之间,或沿所述第二方向设置在多行所述像素电极之间,所述第一方向与所述第二方向相交。
可选的,在本申请的一些实施例中,所述间隙的大小介于1μm至10μm之间。
可选的,在本申请的一些实施例中,所述间隙的大小介于2μm至5μm之间。
可选的,在本申请的一些实施例中,所述阵列基板还包括薄膜晶体管,所述显示面板还包括平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接。
可选的,在本申请的一些实施例中,所述薄膜晶体管包括层叠设置的半导体层、栅极绝缘层、栅极层、层间绝缘层、漏极走线以及源极走线,所述电场电极层为信号走线层,所述电场电极层与所述栅极层同层设置,或所述电场电极层与所述源极走线、所述漏极走线同层设置。
可选的,在本申请的一些实施例中,所述电场电极层为辅助电极层,所述电场电极层与所述像素电极层同层设置。
可选的,在本申请的一些实施例中,所述显示面板还包括像素定义层,所述像素定义层设置在所述像素电极层远离所述阵列基板的一侧,所述像素定义层上设置有开口,所述开口与所述像素电极对应设置。
可选的,在本申请的一些实施例中,所述像素定义层靠近所述阵列基板的一侧具有亲液性,所述像素定义层远离所述阵列基板的一侧具有疏液性。
可选的,在本申请的一些实施例中,所述阵列基板包括依次层叠设置在基板一侧的遮光层、第一电容极板、缓冲层、半导体层、第二电容极板、栅极绝缘层、栅极层、层间绝缘层、漏极走线、源极走线、辅助阴极走线、钝化层以及平坦化层;像素电极层和电场电极层设置在平坦化层上。
可选的,在本申请的一些实施例中,所述电场电极层采用的材料可以为金、银、铜、铝和透明金属氧化物中一种或多种的组合。
本申请实施例还提供一种显示面板,包括:
阵列基板;
像素电极层,所述像素电极层设置在所述阵列基板上,所述像素电极层包括多个像素电极;
其中,所述像素电极具有第一电极部以及第二电极部,所述第一电极部至少围绕所述第二电极部的部分设置。
可选的,在本申请的一些实施例中,所述第一电极部与所述第二电极部之间具有缝隙,所述第一电极部绕设所述第二电极部的部分与所述第二电极部之间的缝隙距离相等。
可选的,在本申请的一些实施例中,所述阵列基板还包括薄膜晶体管,所述显示面板还包括平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
其中,每个所述薄膜晶体管对应控制一个所述第一电极部或所述第二电极部的电压。
可选的,在本申请的一些实施例中,所述像素电极包括m行×n列子像素电极,相邻的所述子像素电极之间具有空隙,所述子像素电极包括第一子像素电极和第二子像素电极,所述第一子像素电极至少围绕所述第二子像素电极的部分设置;其中,m和n为大于或等于3的正整数。
可选的,在本申请的一些实施例中,所述显示面板还包括薄膜晶体管以及平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
其中,每个所述薄膜晶体管对应控制一行所述子像素电极的电压,或每个所述薄膜晶体管对应控制一列所述子像素电极的电压。
可选的,在本申请的一些实施例中,所述显示面板还包括薄膜晶体管以及平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
其中,每个所述薄膜晶体管对应控制一个所述子像素电极的电压。
有益效果
本申请实施例提供一种显示面板。显示面板可以通过控制像素电极层与电场电极层之间的电压差,或者控制像素电极层内部产生电压差,以在像素电极上产生电场。由于本申请提供的显示面板产生电场的两极进行了特殊设计,使产生电场的两极之间各处的距离相等。即,使产生电场两极的形状适配。由此提高电场的均匀性。电场的垂直分量向发光功能层材料中的带电基团提供了往像素电极层沉积的作用力,可以在喷墨打印时,促进发光功能材料的墨水向像素电极层沉积。电场辅助发光功能层材料沉积可以抑制咖啡环的产生,有效提高发光功能层的薄膜质量,进而提高显示面板的器件性能。
附图说明
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的第一种结构示意图;
图2是本申请实施例提供的显示面板的第一俯视结构示意图;
图3是本申请实施例提供的显示面板的第二俯视结构示意图;
图4是本申请实施例提供的显示面板的第三俯视结构示意图;
图5是本申请实施例提供的显示面板的第四俯视结构示意图;
图6是本申请实施例提供的显示面板的第五俯视结构示意图;
图7是本申请实施例提供的显示面板的第二种结构示意图;
图8是本申请实施例提供的显示面板的第三种结构示意图;
图9是本申请实施例提供的显示面板的第六俯视结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。此外,应当理解的是,此处所描述的具体实施方式仅用于说明和解释本申请,并不用于限制本申请。在本申请中,在未作相反说明的情况下,使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下,具体为附图中的图面方向;而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种显示面板。以下分别进行详细说明。需说明的是,以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1至图2,图1是本申请实施例提供的显示面板的第一种结构示意图。图2是本申请实施例提供的显示面板的第一俯视结构示意图。本申请提供的显示面板10包括阵列基板1、像素电极层2以及电场电极层3。像素电极层2设置在阵列基板1上。电场电极层3设置在阵列基板1上。电场电极层3与像素电极层2绝缘设置。电场电极层3包括多个电场电极3a。电场电极3a至少围绕像素电极层2的部分设置。
在像素电极层2上制作发光功能层的时候,为了增大发光功能层的膜层均匀性,可对像素电极层2与电场电极层3施加不同电压形成电压差,以在像素电极层2和电场电极层3之间形成电场。像素电极层2与电场电极层3之间形成的电场具有一个水平分量和一个垂直分量。电场的垂直分量向发光功能层材料中的带电基团提供了往像素电极层2沉积的作用力,可以在喷墨打印时,促进发光功能材料的墨水向像素电极层2沉积。利用电场辅助喷墨打印和真空干燥过程,则可以有效的抑制发光功能层中的带电基团在沉积时和溶剂挥发时的咖啡环效应,提升纳米粒子成膜品质。
其中,电场电极3a与像素电极2a之间具有间隙D。电场电极3a绕设像素电极2a的部分与像素电极2a之间的间隙D距离相等。
为了更好的抑制咖啡环效应,提高纳米粒子成膜品质,电场辅助喷墨打印和真空干燥时电场的均匀性尤为重要,本申请提供的显示面板10围绕像素电极层2设置的电场电极层3与像素电极层2之间的间隙D距离相等,能够在像素电极层2和电场电极层3之间形成均匀性更高的电场。电场均匀性提高,在电场辅助下打印的发光功能层的均匀性也能有效提高,进而提高发光器件的性能。
其中,阵列基板1包括基板1’。基板1’指的是用于承载该触控电极结构的基体构件。例如,基板1’可以为玻璃、有机玻璃、功能玻璃(sensor glass)、硬质绝缘膜材、软质绝缘膜材或柔性衬底。
其中,功能玻璃是在超薄玻璃上溅射透明金属氧化物导电薄膜镀层,并经过高温退火处理得到的。柔性衬底采用的材料为聚合物材料。具体地,柔性衬底采用的材料可以为聚酰亚胺(PI)、聚乙烯(PE)、聚丙烯(PP)、聚苯乙烯(PS)、聚对苯二甲酸乙二醇酯(PET)或聚萘二甲酸乙二醇酯(PEN)。聚合物材料的柔韧性好、质量轻、耐冲击,适用于柔性显示面板。其中,聚酰亚胺还能够实现良好的耐热性和稳定性。
其中,像素电极层2可以采用透明金属氧化物或金属与透明金属氧化物的叠层进行设置。像素电极层2还可以采用石墨烯材料、金属材料以及过渡金属硫属化合物等材料。
具体的,过渡金属硫化物包括硫化钼(MoS 2)、硒化钼(MoSe 2)、硫化钨(WS 2)或硒化钨(WSe 2)。
透明金属氧化物层采用的材料包括铟镓锌氧化物、铟锌锡氧化物、铟镓锌锡氧化物、铟锡氧化物、铟锌氧化物、铟铝锌氧化物、铟镓锡氧化物或锑锡氧化物中的任一种。以上材料具有很好的导电性和透明性,并且厚度较小,不会影响显示面板的整体厚度。同时,还可以减少对人体有害的电子辐射及紫外、红外光。金属层采用的材料为银、铝、镍、铬、钼、铜、钨或钛中的任一种。金属的导电性好,成本较低,在保证阳极的导电性的同时可以降低生产成本。
在一种实施例中,像素电极层2沉积为铟锡氧化物/银/铟锡氧化物的叠层。可以理解的是,像素电极层2可以为发光器件的阳极或阴极。在本申请中,以像素电极层2为阳极作为示例进行说明。
其中,电场电极层3采用的材料可以为金、银、铜、铝和透明金属氧化物中一种或多种的组合。绝缘设置是指像素电极层2与电场电极层3之间具有空隙。例如,像素电极层2与电场电极层3之间可设置有钝化层、层间绝缘层或缓冲层等无机膜层进行绝缘。具体的设置方式可以根据具体的显示面板10进行适应性改动,在此不再赘述。需要说明的是,本申请所述像素电极层2和电场电极层3设置在阵列基板1上,是指像素电极层2和电场电极层3设置在阵列基板1的同一侧。并不是限定像素电极层2和电场电极层3紧挨阵列基板1表面设置。另外,图中的像素电极层2和电场电极层3的相对位置关系仅为示意,并不作为对本申请的限制。
可选的,阵列基板1还包括薄膜晶体管5。显示面板10还包括平坦化层23。像素电极层设置在平坦化层23上,并与薄膜晶体管5连接。进一步的,薄膜晶体管5包括半导体层14、栅极绝缘层16、栅极层17、层间绝缘层18、漏极走线19以及源极走线20。
其中,阵列基板1还包括依次层叠设置在基板1’一侧的遮光层11、第一电容极板12、缓冲层13、半导体层14、第二电容极板15、栅极绝缘层16、栅极层17、层间绝缘层18、漏极走线19、源极走线20、辅助阴极走线21、钝化层22以及平坦化层23。像素电极层2和电场电极层3设置在平坦化层23。在图1所示的实施例中,电场电极层3为辅助阴极层。其中,半导体层14包括漏极区141、有源区142以及源极区143。像素定义层4上设置有开口4a。
图1以薄膜晶体管5为顶栅结构为例进行示意。可以理解的是,本申请不限定显示面板10中所包含的薄膜晶体管5的结构,其可以为顶栅型薄膜晶体管,也可以为底栅型薄膜晶体管,其可以为双栅极型薄膜晶体管,也可以为单栅极型薄膜晶体管。对于薄膜晶体管的具体结构在本申请中不再赘述。
在图1所示的显示面板10中,电场电极层3为辅助电极层,电场电极层3与像素电极层2同层设置。辅助电极层可以作为辅助阴极层连接面阴极,用于降低面阴极的电压降。通过辅助阴极走线21控制辅助阴极层,即电场电极层3的电位,使电场电极层3与像素电极层2之间形成电压差,进而在像素电极层2与电场电极层3之间形成电场。辅助阴极层与像素电极2a在同一个子像素中,辅助阴极层与像素电极2a的间距很小。采用辅助阴极层作为电场电极层3与像素电极2a形成电场,能够增大形成电场的电场强度,使喷墨打印时得到更大的电场力辅助作用。
可选的,间隙D的大小介于1μm至10μm之间。进一步的,间隙D的大小介于2μm至5μm之间。具体的,间隙D的大小可以为1μm、2μm、3μm、4μm、5μm、6μm、7μm、8μm、9μm或10μm。将间隙D的大小设置为1μm至10μm之间,是综合考虑可用的工艺精度以及形成的电场强度。间隙D过宽的话,无法在像素电极层2与电场电极层3之间形成足够强的电场。间隙D过窄的话,制程工艺的精度很难达到,容易造成短路,影响发光器件的工作。本申请提供的间隙d的大小范围,是像素电极层2与电场电极层3之间产生电场以辅助发光功能层沉积的最佳间隙D大小。间隙D的值影响到电场的强度,进而影响发光功能层沉积的均匀性。间隙D的大小范围是为了得到均匀且强度合适的电场,经过多次试验得出,并非本领域技术人员常用且容易想到的技术手段。
可选的,显示面板10还包括像素定义层4。像素定义层4设置在像素电极层2远离阵列基板1的一侧。像素定义层4上设置有开口4a。开口4a对应像素电极2a设置。
其中,像素定义层4靠近阵列基板1的一侧具有亲液性,像素定义层4远离阵列基板1的一侧具有疏液性。
亲液性是指材料表面易被液体介质润湿或溶化。疏液性(也可称为憎液性)与亲液性相反,疏液性是指材料表面不易被液体介质润湿或溶化。材料表面的亲液和憎液性质主要由其表面结构或官能团的性质所决定。本申请中可以通过调节制程工艺参数对像素定义层4的亲疏液性进行改变和调整。例如,调整显影工艺和固化工艺的参数。对像素定义层4的亲疏液性进行改变和调整。这样设置的像素定义层4可以适配不同打印工艺、墨水的种类以及膜层的厚度,使像素定义层4更容易适应不同显示面板的要求。
具体地,像素定义层4的厚度会影响材料的亲疏液性,例如,当疏液材料很薄的情况下,则不具有疏液性。另外,对材料进行氧气(O 2)或氮气(N 2)等离子体处理可以使疏液性变为亲液性,对材料进行氟气(F)等离子体处理可以使亲液性变为疏液性。
可选的,本申请实施例提供的显示面板10中,电场电极3a可以围绕像素电极2a的部分设置。例如,当像素电极2a为圆形时,电场电极3a呈半圆形围绕像素电极2a的一半设置。又例如,当像素电极2a为椭圆形时,电场电极3a呈U型围绕像素电极2a设置。
可选的,如图2所示,电场电极3a与像素电极2a一一对应。电场电极3a围绕像素电极2a设置形成一封闭图案。
本实施例中,电场电极3a围绕像素电极2a设置,并形成了封闭图案。由于在电场电极3a和像素电极2a之间形成电场时,是通过分别对电场电极3a和像素电极2a施加电压。当电场电极3a围绕像素电极2a形成了封闭图案,且各处电场电极3a与像素电极2a的间隙D大小一致时,也就是形成电场的两极之间的距离是一致的,则能够提高电场均匀性。
另外,电场电极3a与像素电极2a一一对应,且独立设置。这种结构能够在形成电场时,在每个像素电极2a上形成独立的电场。形成独立电场后,更便于发光功能层不同颜色像素的独立制作,对各个像素电极的电场可独立调控。由此,使显示面板10更适应不同像素排列要求的发光功能层制作。
需要说明的是,图2中以电场电极3a分别一一对应像素电极2a为例进行说明。在一些实施例中,电场电极层3包括形成多个电场电极3a的连续图案。请参阅图3,图3是本申请实施例提供的显示面板的第二俯视结构示意图。将围绕像素电极2a的电场电极3a设置为连续图案,能够对电场电极层3中的多个电场电极3a同时施加电压。例如,对同一行电场电极3a同时施加电压,再控制该行对应的像素电极2a的电压,以在该行形成电场。由此,可在同一行像素为同一颜色发光功能层的时候,提高发光功能层的制作效率。
请参阅图4,图4是本申请实施例提供的显示面板的第三俯视结构示意图。像素电极层2沿第一方向x排布有多排,像素电极层2沿第二方向y排布有多行。像素电极层2之间均具有空隙S。电场电极3a包括第一部分31a和第二部分32a。第一部分31a沿第一方向x设置在相邻的两排像素电极2a之间,第二部分32a沿第二方向y设置多行像素电极2a之间。第一部分31a与第二部分32a相连。第一方向x与第二方向y相交。本申请中,第一方向x为沿x轴延伸的方向,第二方向y为沿y轴延伸的方向,因此,在本申请中,以第一方向x、第二方向y进行描述。图3中以第一方向x与第二方向y垂直为例进行示意,实际上,第一方向x和第二方向y可以是相交的任意两个方向。另外,图2、图3中像素电极层2设置为椭圆形,图4中像素电极层2是设置为矩形,像素电极层2还可以设置为其他形状。例如,可以将像素电极层2设置为圆形、菱形等便于像素排列的图形,本申请对此不作限制。
需要说明的是,电场电极3a沿第一方向x设置在多排像素电极2a之间,并沿第二方向y设置多行像素电极2a之间。则电场电极3a可以如图4所示沿第一方向x和第二方向y两个方向呈网状设置在空隙中。
其中,请参阅图5,图5是本申请实施例提供的显示面板的第四俯视结构示意图。像素电极层2沿第一方向x排布有多排,像素电极层2沿第二方向y排布有多行。像素电极层2之间均具有空隙S。电场电极3a沿第一方向x设置在多排像素电极2a之间,或沿第二方向y设置多行像素电极2a之间。即,电场电极3a还可以沿第一方向x或第二方向y中的某一方向呈长条形设置在空隙中。或者,电场电极3a的一部分沿第一方向x设置在某一层中,电场电极3a的另一部分沿第二方向y设置在另一膜层中。同样,第一方向x和第二方向y可以是相交的任意两个方向。
可选的,电场电极层3为信号走线层。电场电极层3与栅极层17同层设置。或电场电极层3与源极走线20、漏极走线19同层设置。即,信号走线层包括扫描信号走线31和数据信号走线32。电场电极层3可以为扫描信号走线31或者数据信号走线32,或者电场电极层3可以为扫描信号走线31和数据信号走线32围设像素电极层2形成。
例如,当电场电极层3为扫描信号走线31时,可以沿第一方向x排布在像素电极2a之间的空隙S中。在对扫描信号走线31和像素电极2a分别施加电压,以在扫描信号走线31和像素电极2a之间形成电场线沿第二方向y的均匀水平电场。数据信号走线32与像素电极2a形成电场的方法与上述类似,在此不再赘述。
可以理解的是,当电场电极层3为扫描信号走线31和数据信号走线32时,电场电极层3可以沿第一方向x和第二方向y呈网状排布在像素电极2a之间的空隙S中。电场电极层3与像素电极2a形成的电场是电场线由电场电极层3向像素电极2a的均匀电场。或者,电场电极层3与像素电极2a形成的电场是电场线由像素电极2a向电场电极层3的均匀电场。
在本实施例中,电场是利用薄膜晶体管5中的信号走线与像素电极形成的。在打印某一个子像素的发光功能层时,如果其周围的子像素发光功能层均已打印好,可以选择像素电极层2与电场电极层3之间的电场进行喷墨打印。这样可以避免周围的发光功能层形成的膜层厚度对像素电极层2形成电屏蔽,影响电场力的作用,可保证子像素发光功能层的打印效果,使墨水沉积更均匀。另外,电场电极层3还可以是显示面板10中的其他走线,例如复位信号走线等,本申请对此不做限制。
请参阅图6,图6是本申请实施例提供的显示面板的第五俯视结构示意图。本申请实施例提供的显示面板10包括阵列基板1以及像素电极层2。像素电极层2设置在阵列基板1上。像素电极层2包括多个像素电极2a。
其中,像素电极2a具有第一电极部2A以及第二电极部2B。第一电极部2A至少围绕第二电极部2B的部分设置。
其中,第一电极部2A与第二电极部2B之间具有缝隙G。各处第一电极部2A与第二电极部2B之间的缝隙G距离相等。
图8所示的实施例提供一种显示面板10,直接利用像素电极2a中第一电极部2A和第二电极部2B形成电场,则不需要控制其他电极的电压值。在像素电极2a中形成电场,在电场辅助发光功能层沉积时,产生的电场作用力较大,能够使发光功能层沉积更均匀。另外,由于第一电极部2A是围绕第二电极部2B设置,有利于提高第一电极部2A与第二电极部2B产生的电场的均匀性。
请参阅图7,图7是本申请实施例提供的显示面板的第二种结构示意图。显示面板10还包括薄膜晶体管5以及平坦化层23。像素电极层2设置在平坦化层23上,并与薄膜晶体管5连接。
其中,请参阅图8,图8是本申请实施例提供的显示面板的第三种结构示意图。每个薄膜晶体管5对应控制一个第一电极部2A或第二电极部2B的电压。每个薄膜晶体管5对应控制一个电极部的电压,以使第一电极部2A或第二电极部2B之间形成电压差。这种设置方式能够精细调控子像素内的电位差以及电场。
请参阅图9,图9是本申请实施例提供的显示面板的第六俯视结构示意图。像素电极2a包括m行×n列子像素电极2a’。相邻的子像素电极2a’之间具有空隙。子像素电极2a’包括多个第一子像素电极21a’和至少一个第二子像素电极22a’。第一子像素电极21a’至少围绕第二子像素电极22a’的部分设置。其中,m和n为大于或等于3的正整数。子像素电极2a’之间相互绝缘,图中仅以黑色实线进行划分。
需要说明的是,对像素电极2a进行适当的分割,分割区域面积在整个像素电极2a面积中的占比是可控的。因此,将一像素电极2a分为m行×n列子像素电极2a’,对发光效果不会产生影响。
在像素电极2a中形成行列方向的子像素电极2a’,制程简便,无需复杂的图案化方法。并且,这样的子像素电极2a’的排布,也更方便其对应的薄膜晶体管的制作。并且,子像素电极2a’之间的间距较近,能够产生较强的电场作用力,可以进一步改善电沉积效果,缩短电场辅助沉积发光功能层所需的时间,提升成膜质量。
其中,每个薄膜晶体管5对应控制一行子像素电极2a’的电压。或,每个薄膜晶体管5对应控制一列子像素电极2a’的电压。或,每个薄膜晶体管5对应控制一个子像素电极2a’的电压。图9中仅在每个子像素区域中示意了两个薄膜晶体管5,但不作为对本申请的限制。
每个薄膜晶体管5控制一行子像素电极2a’的电压或对应控制一列子像素电极2a’的电压,已经可以在子像素中形成高低电位。行列之间的高低电位使子像素电极2a’与子像素电极2a’之间形成电压差,进一步形成了电场。当薄膜晶体管5控制一行或一列子像素电极2a’的电压时,可以以最中心的一行子像素电极2a’作为第二电极部2B,周围的子像素电极2a’作为第一电极部2A。子像素电极2a’之间的电场强度较大,能够提供足够的电场作用力辅助发光功能层的打印制程。并且,这种方式需要的薄膜晶体管器件6较少,能够降低制程难度和精度。
每个薄膜晶体管器件6对应控制一个子像素电极2a’的电压,以使子像素电极2a’与子像素电极2a’之间形成电压差。这种设置方式能够精细调控子像素内的电位差以及电场。图9中以m等于3、n等于3为例,将像素电极2a划分为3×3九个子像素电极2a’。并且,图7中的子像素电极2a’可以以a等于1为例,最外一圈子像素电极2a’用于形成第一电极部2A,中心的一个子像素电极2a’用于形成第二电极部2B。
本实施例中,第一子像素电极21a’用作第一电极部2A,第二子像素电极22a’用作第二电极部2B。通过将像素电极2a分为多个子像素电极2a’,再通过控制不同位置的子像素电极2a’的电压形成电场,便于调控第一电极部2A和第二电极部2B的相对位置和相对面积,则更便于调控需要形成的均匀电场的形态。
本申请实施例提供的显示面板10可以通过控制像素电极层2与电场电极层3之间的电压差,或者控制像素电极层2内部产生电压差,以在像素电极2a上产生电场。并且,由于本申请提供的显示面板10产生电场的两极进行了特殊设计,使产生电场的两极之间各处的距离相等。即,使产生电场两极的形状适配。由此提高电场的均匀性。电场的垂直分量向发光功能层材料中的带电基团提供了往像素电极层2沉积的作用力,可以在喷墨打印时,促进发光功能材料的墨水向像素电极层2沉积。电场辅助发光功能层材料沉积可以抑制咖啡环效应,有效提高发光功能层的薄膜质量,进而提高显示面板10的器件性能。
另外,本申请的显示面板10中产生的电场还可以用在发光功能层材料干燥时。在对发光功能层材料进行干燥处理时,以像素电极层2上的均匀电场固定发光功能层溶液中的带电基团。由此抑制溶剂挥发时溶剂带动带电基团运动,从而得到膜厚均匀的发光功能层,避免咖啡环现象的产生,可得到高品质的薄膜。并且,利用干燥阶段电场固定带电基团,则在溶剂挥发的过程中不需要严格的抽气控制,进行干燥处理,极大的简化了真空干燥工艺,提升了加工效率。
并且,本申请提供的显示面板10中,形成电场的两个电极进行了形状的设计,且电极相邻的各处间隙D或缝隙G的距离相等。由此,两个电极可以产生均匀的电场,优化了电场辅助沉积或电场辅助干燥时,带电基团运动的分散路径,使得膜层沉积更加均匀。进一步的,可提高显示面板10的显示效果和器件性能。
需要说明的是,本申请提供的显示面板10结构还可以用于其他膜层沉积以及干燥。具体的,适用于膜层中溶质为无机纳米颗粒、贵金属纳米粒子、胶体纳米片以及胶体纳米棒纳米膜层中的一种或多种组合。进一步的,纳米颗粒可以为硫酸钡(BaSO 4)、碳酸钙(CaCO 3)、铯化锌(ZnSe)、硫化镉(CdS)、二氧化钛(TiO 2)、钛酸钡(BaTiO 3)、硫化锌(ZnS)、氧化锆(ZrO 2)、氮化硅(Si 3N 4)、氧化锡(SnO)以及氧化锌(ZnO)中的一种或多种组合。
本申请中发光功能层溶液中的溶质可以为量子点材料。具体的,量子点材料的发光核材料为ZnCdSe 2、InP、Cd 2SSe、CdSe、Cd 2SeTe以及InAs中一种或多种组合。量子点材料的无机保护壳层材料为CdS、ZnSe、ZnCdS2、ZnS、ZnO中一种或多种的组合。量子点材料还可以包括水凝胶装载量子点结构、CdSe-SiO 2量子点以及钙钛矿量子点。量子点材料的表面配体包括胺、酸、巯醇以及有机磷中一种或多种的组合。发光功能层、溶液中的溶剂可以为无色透明低沸点的有机或无机溶剂。例如,溶剂可以为去离子水、甲醇、乙醇、乙二醇、丙二醇、乙酸乙酯、石油醚或正己烷中的一种或多种的组合。
当量子点材料带负电时,对沉积量子点材料的目标像素电极2a加正电。当量子点材料带正电时,对沉积量子点材料的目标像素电极2a加负电。以此保障沉积的最佳效果。施加电压的时间可以选择发光功能层溶液完全覆盖像素电极2a后,这样可以在均匀电场作用下,发光功能层中的带电基团沉积更均匀,且完整覆盖像素电极2a。
以上对本申请实施例所提供的一种显示面板进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的方法及其核心思想;同时,对于本领域的技术人员,依据本申请的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板,其包括:
    阵列基板;
    像素电极层,所述像素电极层设置在所述阵列基板上,所述像素电极层包括多个像素电极;
    电场电极层,所述电场电极层设置在所述阵列基板上,所述电场电极层与所述像素电极层绝缘设置,所述电场电极层包括至少一个电场电极;其中,所述电场电极至少围绕所述像素电极的部分设置。
  2. 根据权利要求1所述的显示面板,其中,所述电场电极与所述像素电极之间具有间隙,所述电场电极绕设所述像素电极的部分与所述像素电极之间的间隙距离相等。
  3. 根据权利要求1所述的显示面板,其中,所述电场电极与所述像素电极一一对应,所述电场电极围绕所述像素电极设置形成一封闭图案。
  4. 根据权利要求1所述的显示面板,其中,所述像素电极沿第一方向排布有多排,所述像素电极沿第二方向排布有多行,所述电场电极包括第一部分和第二部分,所述第一部分沿所述第一方向设置在相邻的两排所述像素电极之间,所述第二部分沿所述第二方向设置在相邻的两行所述像素电极之间,所述第一部分与所述第二部分相连,所述第一方向与所述第二方向相交。
  5. 根据权利要求1所述的显示面板,其中,所述像素电极沿第一方向排布有多排,所述像素电极沿第二方向排布有多行,所述电场电极沿所述第一方向设置在相邻的两排所述像素电极之间,或沿所述第二方向设置在相邻的两行所述像素电极之间,所述第一方向与所述第二方向相交。
  6. 根据权利要求1所述的显示面板,其中,所述间隙的大小介于1μm至10μm之间。
  7. 根据权利要求1所述的显示面板,其中,所述间隙的大小介于2μm至5μm之间。
  8. 根据权利要求1所述的显示面板,其中,所述阵列基板还包括薄膜晶体管,所述显示面板还包括平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接。
  9. 根据权利要求8所述的显示面板,其中,所述薄膜晶体管包括层叠设置的半导体层、栅极绝缘层、栅极层、层间绝缘层、漏极走线以及源极走线,所述电场电极层为信号走线层,所述电场电极层与所述栅极层同层设置,或所述电场电极层与所述源极走线、所述漏极走线同层设置。
  10. 根据权利要求8所述的显示面板,其中,所述电场电极层为辅助电极层,所述电场电极层与所述像素电极层同层设置。
  11. 根据权利要求1所述的显示面板,其中,所述显示面板还包括像素定义层,所述像素定义层设置在所述像素电极层远离所述阵列基板的一侧,所述像素定义层上设置有开口,所述开口与所述像素电极对应设置。
  12. 根据权利要求11所述的显示面板,其中,所述像素定义层靠近所述阵列基板的一侧具有亲液性,所述像素定义层远离所述阵列基板的一侧具有疏液性。
  13. 根据权利要求1所述的显示面板,其中,所述阵列基板包括依次层叠设置在基板一侧的遮光层、第一电容极板、缓冲层、半导体层、第二电容极板、栅极绝缘层、栅极层、层间绝缘层、漏极走线、源极走线、辅助阴极走线、钝化层以及平坦化层;像素电极层和电场电极层设置在平坦化层上。
  14. 根据权利要求1所述的显示面板,其中,所述电场电极层采用的材料可以为金、银、铜、铝和透明金属氧化物中一种或多种的组合。
  15. 一种显示面板,其包括:
    阵列基板;
    像素电极层,所述像素电极层设置在所述阵列基板上,所述像素电极层包括多个像素电极;
    其中,所述像素电极具有第一电极部以及第二电极部,所述第一电极部至少围绕所述第二电极部的部分设置。
  16. 根据权利要求15所述的显示面板,其中,所述第一电极部与所述第二电极部之间具有缝隙,所述第一电极部绕设所述第二电极部的部分与所述第二电极部之间的缝隙距离相等。
  17. 根据权利要求15所述的显示面板,其中,所述阵列基板还包括薄膜晶体管,所述显示面板还包括平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
    其中,每个所述薄膜晶体管对应控制一个所述第一电极部或所述第二电极部的电压。
  18. 根据权利要求15所述的显示面板,其中,所述像素电极包括m行×n列子像素电极,相邻的所述子像素电极之间具有空隙,所述子像素电极包括多个第一子像素电极和至少一个第二子像素电极,所述第一子像素电极至少围绕所述第二子像素电极的部分设置;其中,m和n为大于或等于3的正整数。
  19. 根据权利要求18所述的显示面板,其中,所述显示面板还包括薄膜晶体管以及平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
    其中,每个所述薄膜晶体管对应控制一行所述子像素电极的电压,或每个所述薄膜晶体管对应控制一列所述子像素电极的电压。
  20. 根据权利要求18所述的显示面板,其中,所述显示面板还包括薄膜晶体管以及平坦化层,所述像素电极层设置在所述平坦化层上,并与所述薄膜晶体管连接;
    其中,每个所述薄膜晶体管对应控制一个所述子像素电极的电压。
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