WO2023015672A1 - 一种半导体薄膜形成方法、半导体结构及存储器 - Google Patents

一种半导体薄膜形成方法、半导体结构及存储器 Download PDF

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WO2023015672A1
WO2023015672A1 PCT/CN2021/118849 CN2021118849W WO2023015672A1 WO 2023015672 A1 WO2023015672 A1 WO 2023015672A1 CN 2021118849 W CN2021118849 W CN 2021118849W WO 2023015672 A1 WO2023015672 A1 WO 2023015672A1
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thin film
semiconductor
layer
forming
chamber
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PCT/CN2021/118849
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English (en)
French (fr)
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黄飞飞
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Definitions

  • the present disclosure relates to the field of semiconductor process technology.
  • bitline sidewalls are formed by chemical mechanical polishing and etching.
  • Si 3 N 4 In the structure above the sidewall of the existing DRAM bit line, there are two layers of Si 3 N 4 and SiO 2 . Among them, Si 3 N 4 has a dense structure and strong anti-diffusion ability and can be used as an excellent barrier layer. However, Si 3 N 4 has a large dielectric constant and generates large parasitic capacitance, which affects the performance of DRAM. On the other hand, the stress of Si 3 N 4 is large, and there are cases where the contact with SiO 2 is not good.
  • the purpose of the embodiments of the present disclosure is to provide a method for forming a semiconductor thin film, a semiconductor structure and a memory, so as to alleviate the existing technical problems.
  • the first aspect of the present disclosure provides a method for forming a semiconductor thin film, which includes: introducing a precursor into a chamber, and the precursor is adsorbed on a semiconductor substrate; purging the chamber to remove unadsorbed precursor; The plasma containing oxygen ions and nitrogen ions is introduced into the chamber, and reacts with the precursor to deposit the first film; the chamber is purged to remove unreacted plasma; the plasma containing oxygen ions is introduced into the chamber, and adsorbed on Precursor reacts to deposit the second film on the semiconductor substrate; the above steps are repeated until the total thickness of the first film and the second film reaches a predetermined value.
  • the second aspect of the present disclosure provides a semiconductor structure, including the first thin film and the second thin film formed by the semiconductor thin film forming method of the first aspect of the present disclosure, including: a first deposition formed on a semiconductor substrate layer and a second deposition layer, the first deposition layer is a stop layer for chemical mechanical polishing, and the second deposition layer is alternately formed by the first thin film and the second thin film.
  • the third aspect of the present disclosure provides a memory, including the first thin film and the second thin film formed by the semiconductor thin film forming method of the first aspect of the present disclosure, including: a first deposition layer formed on the sidewall of the memory bit line and the second deposition layer, the first deposition layer is a chemical mechanical polishing stop layer, and the second deposition layer is alternately formed by the first thin film and the second thin film
  • Embodiments of the present disclosure can/at least have the following advantages, by reacting the plasma containing oxygen ions and nitrogen ions with the precursor adsorbed on the semiconductor substrate to deposit the first film, the first film is nitrogen containing nitrogen and oxygen elements Oxide, the first film is the intermediate phase of nitride and oxide, which can effectively reduce the parasitic capacitance of the interface between nitride and oxide, and alleviate the technical problem of poor contact; then, by combining the plasma containing oxygen ions, and The precursor adsorbed on the semiconductor substrate reacts to deposit the second film, thereby realizing the deposition of the first film and the second film in the same process.
  • FIG. 1(A)-FIG. 1(E) are schematic diagrams of the formation process of memory bit line sidewalls in the prior art
  • Figure 1(A) is a schematic diagram of a memory bit line without sidewalls
  • Figure 1(B) is a schematic diagram of a memory bit line deposited by ALD in Figure 1(A)
  • Figure 1(C) is a schematic diagram of Figure 1(B) Schematic diagram of the memory bit line deposited by ALD SiO2
  • Figure 1 (D) is a schematic diagram of the memory bit line of Figure 1 (C) after SOD (Spin-on Dielectrics, spin-on dielectric)
  • Figure 1 (E) is Figure 1 ( D) Schematic diagram of memory bit lines after chemical mechanical polishing and etching.
  • FIG. 2 is a schematic flow diagram of a method for forming a semiconductor thin film according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the timing sequence of a thin film forming process of a method for forming a semiconductor thin film according to an embodiment of the present disclosure
  • 4(A)-FIG. 4(E) is a schematic diagram of the thin film formation process of a method for forming a semiconductor thin film according to an embodiment of the present disclosure
  • FIG. 4 (A) is a schematic diagram of a semiconductor structure memory bit line without forming a sidewall film
  • Fig. 4 (B) is a schematic diagram of a semiconductor structure memory bit line after the first deposition layer is formed in Fig. 4 (A)
  • Fig. 4 (C ) is a schematic diagram of the bit line of the semiconductor structure memory after forming the second deposition layer in FIG. 4(B)
  • FIG. 4(D) is a schematic diagram of the bit line of the semiconductor structure memory after chemical mechanical grinding and etching in FIG. (E) is a partially enlarged view of FIG. 4(D).
  • FIG. 5 is a schematic diagram of the influence of the ratio of O2 to N2 gas flow rate on the parasitic capacitance of a semiconductor device in a method for forming a semiconductor thin film according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the influence of the ratio of the thickness of the first deposition layer to the thickness of the second deposition layer on the parasitic capacitance of a semiconductor device in a method for forming a semiconductor thin film according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a memory structure according to an embodiment of the present disclosure.
  • bit line insulating layer 21: bit line intermediate layer; 31: bit line conductive layer; 41: Si3N4 layer; 1: bit line insulating layer; 2: bit line intermediate layer; 3: bit line conductive layer; 4: Si3N4 layer; 5: SiO2 layer; 6: SOD schematic; 7: second deposition layer; 71: first film; 72: second film; 10: precursor introduction; 20: chamber purging; 30: nitrogen-containing ions 40: radio frequency signal; 50: plasma injection of oxygen-containing ions; 100: semiconductor substrate.
  • FIG. 1 A schematic diagram of a layer structure according to an embodiment of the present disclosure is shown in the accompanying drawings.
  • the figures are not necessarily to scale, with certain details exaggerated and certain details possibly omitted for clarity.
  • the shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.
  • FIG. 1(A)-FIG. 1(E) are schematic diagrams of the process of forming sidewalls of memory bit lines in the prior art.
  • FIG. 1(A) is a schematic diagram of a memory bit line without sidewalls
  • FIG. 1(B) is a schematic diagram of a memory bit line deposited with Si 3 N 4 by ALD in FIG. 1(A)
  • FIG. (B) Schematic diagram of the memory bit line deposited by ALD
  • Fig. 1(D) is a schematic diagram of the memory bit line after SOD (Spin-On Dielectrics, spin-on dielectric) in Fig. 1(C)
  • Fig. 1(E) It is a schematic diagram of memory bit lines after chemical mechanical polishing and etching in FIG. 1(D).
  • the memory bit line is composed of three parts: a bit line insulating layer 10 , a bit line intermediate layer 20 and a bit line conductive layer 30 .
  • the memory bit lines are deposited by an ALD process to form a Si 3 N 4 layer 41 .
  • the memory bit lines are deposited by an ALD process to form a SiO 2 layer 5 .
  • complete memory bit line sidewalls in FIG. 1(E) are formed by chemical mechanical polishing and etching. Referring to FIG. 1(E), the complete memory bit line sidewall includes Si 3 N 4 layer 41 and SiO 2 layer 5 .
  • CMP chemical mechanical polishing
  • Its principle is a processing technology that combines chemical corrosion and mechanical removal. It is a process that can achieve global surface planarization in mechanical processing technology. Etching is a technique for removing materials by chemical reaction or physical impact.
  • Si 3 N 4 has a dense structure and strong anti-diffusion ability and can be used as an excellent barrier layer. However, Si 3 N 4 has a large dielectric constant and generates a large parasitic capacitance, which affects the performance of the memory. On the other hand, Si 3 N 4 has a large stress and has a poor contact surface with SiO 2 .
  • Parasitic capacitance generally refers to the capacitive characteristics of non-capacitive devices under high-frequency conditions. DRAM stores information by charging and discharging internal parasitic capacitance. The capacitor is charged as logic 1 and not charged as logic 0.
  • the Si 3 N 4 layer 41 and the SiO 2 layer 5 in FIG. 1(E) make the memory bit line parasitic capacitance large, and the Si 3 N 4 layer 41 and the SiO 2 layer 5 have poor contact surfaces.
  • FIG. 2 is a schematic flowchart of a method for forming a semiconductor thin film according to an embodiment of the present disclosure.
  • the method for forming a semiconductor thin film mainly includes seven steps, and the seven steps will be described in detail below.
  • Step S1 adsorbing the precursor on the semiconductor substrate.
  • the precursor is introduced into the chamber, and the precursor is adsorbed on the semiconductor substrate.
  • a precursor is a pre-product that can achieve a target product after certain steps, and the precursor is the basis of the ALD deposition process.
  • the first step is to adsorb or saturate the precursor of the reaction on the semiconductor substrate.
  • the precursor is a compound or mixture of silicon and hydrogen.
  • it may be silane (SiH 4 , silicon tetrahydrogen), which is a colorless gas that can be adsorbed on a semiconductor substrate.
  • the compound of silicon and hydrogen is selected from tetrakis(dimethylamino)silane (TDMAS), isopropylaminosilane (DIPAS), bis(diethylamide)silane (BDEAS), bis(tert-butyl Any one of amino) silanes (BTBAS), or a mixture of any combination thereof.
  • TDMAS tetrakis(dimethylamino)silane
  • DIPAS isopropylaminosilane
  • BDEAS bis(diethylamide)silane
  • BBAS bis(tert-butyl Any one of amino) silanes
  • BDEAS bis(diethylamide)silane
  • the adsorption time between the precursor and the semiconductor substrate is set to 2-10 seconds. Setting the length of the adsorption time can ensure the degree of adsorption of the precursor in the substrate. For example, when the adsorption time is greater than a certain value, the precursor is saturated adsorption.
  • Step S2 purging the chamber to remove the unadsorbed precursor.
  • the unadsorbed precursors will react with the subsequent reactive substances, which will affect the reaction of the adsorbed precursors and affect the Thin film deposition process for adsorbed precursors.
  • the chamber is purged with an inert gas.
  • an inert gas argon (Ar) is introduced to purge and remove excess precursor. It should be noted that the gas for purging to remove excess precursor cannot react with the precursor, so an inert gas is selected. In addition, any gas that does not react with the precursor can be used to purge excess precursor.
  • Step S3 reacting to form a first thin film.
  • the plasma containing oxygen ions and nitrogen ions is introduced into the chamber, and reacts with the precursor adsorbed on the semiconductor substrate to deposit the first film.
  • reaction of ALD or PEALD is self-limiting (Self-Limiting), that is, the precursor is input to the semiconductor substrate and kept on the surface by adsorption or saturated adsorption; when the subsequent reaction substance is passed into the reaction chamber, It will react with the precursor that has been adsorbed on the surface of the semiconductor substrate.
  • a substitution reaction will occur between the precursor and the reactive substance and produce corresponding by-products until the precursor on the surface of the semiconductor substrate is completely consumed, the reaction will automatically stop and the required atomic layer film will be deposited on the surface of the semiconductor substrate.
  • the precursor is a compound of silicon and hydrogen
  • a plasma containing oxygen ions and nitrogen ions is introduced into the chamber, and the plasma containing oxygen ions and nitrogen ions reacts with the compound of silicon and hydrogen to form silicon oxynitride SiON .
  • the plasma containing oxygen ions and nitrogen ions is generated by ionizing O 2 and N 2 or NH 3 at a gas flow ratio of 1:1-1:20.
  • the plasma is generated in the plasma reaction chamber by reaction gases such as O 2 and N 2 or NH 3 , and then enters the chamber to react with the precursor after generation.
  • the plasma is generated by exciting reactive gases such as O 2 and N 2 or NH 3 by a radio frequency generator.
  • the gas flow ratio of O2 to N2 is 1:9.
  • the ratio of nitrogen and oxygen elements in the first film is precisely controlled by controlling the flow ratio of O 2 and N 2 or NH 3 plasma source into the reaction chamber, so as to control the generated parasitic capacitance.
  • the time for passing the plasma is set to be 1-10 seconds.
  • the nitrogen-containing plasma is generated by N 2 , set the plasma on-stream time to 5 seconds. It should be noted that, the time of entering the plasma is different, and the content of the plasma in the chamber is different.
  • Step S4 purging the chamber to remove unreacted plasma.
  • the unreacted plasma needs to be purged out of the chamber.
  • the chamber is purged with an inert gas.
  • the inert gas argon (Ar) is blown to remove unreacted plasma. It should be noted that the gas for purging unreacted plasma cannot react with plasma, so an inert gas is selected. In addition, any gas that does not react with the plasma or the first thin film can be used to purge the unreacted plasma.
  • Step S5 reacting to form a second thin film.
  • steps S1 and S2 introducing plasma containing oxygen ions into the chamber, and reacting with the precursor adsorbed on the semiconductor substrate to deposit the second film
  • the precursor is a compound of silicon and hydrogen
  • a plasma containing oxygen ions is introduced into the chamber, and the plasma containing oxygen ions reacts with the compound of silicon and hydrogen to form silicon dioxide SiO 2 .
  • step S5 the precursor adsorption time is set to 3 seconds.
  • the temperature of the chamber is set at 40° C. to 110° C. during the deposition stages of the first thin film and the second thin film.
  • Step S6, execute step S4. After the deposition of the second film is completed, step S4 is performed to purge unreacted plasma out of the chamber.
  • Step S7 return to step S1, and execute the above steps in a loop until the total thickness of the first film and the second film reaches a predetermined value.
  • FIG. 3 is a schematic diagram of the timing sequence of a thin film forming process of a method for forming a semiconductor thin film according to an embodiment of the present disclosure.
  • one process cycle includes two stages of first thin film deposition and second thin film deposition.
  • first film deposition stage there are four stages including precursor feeding 10, chamber purging 20, plasma containing nitrogen ions and oxygen ions 30, and chamber purging 20, each stage is performed sequentially in chronological order .
  • the second film deposition stage four stages are included: precursor introduction 10 , chamber purge 20 , plasma containing oxygen ions 50 , chamber purge 20 , and each stage is performed sequentially in chronological order.
  • the plasma is excited by a radio frequency signal, so during the passage of gas O 2 and N 2 or NH 3 , the radio frequency signal 40 excites O 2 and N 2 or NH 3 to generate plasma containing ions and oxygen ions, or A plasma containing oxygen ions.
  • steps S1 to S7 are repeated until the total thickness of the first film and the second film reaches a predetermined value, that is, a plurality of process cycles are repeated to deposit the first film and the second film with a desired thickness. film.
  • ALD or PEALD has higher control precision than traditional metal-organic chemical vapor deposition, molecular beam epitaxy and physical vapor deposition, and can precisely control the thickness of the film by controlling the number of reaction cycles.
  • 30-60 process cycles are repeated to achieve the desired film thickness.
  • the method for forming a semiconductor thin film further includes: step S8, performing chemical mechanical grinding and etching on the semiconductor substrate.
  • step S8 performing chemical mechanical grinding and etching on the semiconductor substrate.
  • chemical mechanical polishing and etching are performed to flatten the semiconductor film, or to remove excess portions.
  • FIG. 4(A)-FIG. 4(E) are schematic diagrams of the thin film forming process of a method for forming a semiconductor thin film according to an embodiment of the present disclosure.
  • FIG. 4(A) is a schematic diagram of a bit line of a semiconductor structure memory without forming a sidewall film.
  • FIG. 4(B) is a schematic diagram of the bit line of the semiconductor structure memory after the first deposition layer is formed in FIG. 4(A),
  • FIG. 4(C) is a schematic diagram of the bit line of the semiconductor structure memory after the second deposition layer is formed in FIG. 4(B),
  • FIG. 4(D) is a schematic diagram of the bit line of the semiconductor structure memory after chemical mechanical polishing and etching in FIG. 4(C).
  • Fig. 4(A)-Fig. 4(D) schematically show the structural changes in the process of forming the bit line of the semiconductor structure memory.
  • the semiconductor substrate includes a memory bit line
  • the first deposition layer and the second deposition layer are formed on the sidewall of the memory bit line
  • the first deposition layer is a stop layer for chemical mechanical polishing
  • the second deposition layer is formed by the first deposition layer.
  • the thin film and the second thin film are alternately formed. Referring to Fig. 4 (D), three parts of the bit line insulating layer 1, the bit line intermediate layer 2 and the bit line conductive layer 3 constitute the memory bit line in the semiconductor substrate structure, the first deposition layer 4 and the second deposition layer 7 deposited on the sidewalls of the memory bit lines.
  • the first deposition layer 4 is deposited by ALD or PEALD.
  • FIG. 4(E) is a partially enlarged view of FIG. 4(D).
  • the second deposition layer 7 is formed alternately by first thin films 71 and second thin films 72 .
  • steps S1 to S7 are repeated until the thickness ratio of the first deposition layer 4 to the second deposition layer 7 is 1.5:1 to 3:1. For example, if the steps are repeated N times, N first thin films 71 and N second thin films 72 will be formed. It should be noted that steps S1-S4 are used to form the first thin film 71, and step S5 is used to form the second thin film 72. Therefore, in the process of repeating steps S1 to S7, the first thin film 71 and the second thin film 72 are alternately formed .
  • the first thin film 71 is silicon oxynitride SiON, and the first thin film 71 is an intermediate phase between silicon nitride and silicon dioxide, which can effectively reduce the parasitic capacitance at the interface between silicon nitride and silicon dioxide, and ease the nitriding process.
  • FIG 5 is a schematic diagram of the influence of the ratio of O 2 to N 2 gas flow rate on the parasitic capacitance of a semiconductor device in a method for forming a semiconductor thin film according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the influence of the ratio of the thickness of the first deposition layer to the thickness of the second deposition layer on the parasitic capacitance of a semiconductor device in a method for forming a semiconductor thin film according to an embodiment of the present disclosure.
  • steps S1 to S7 are repeated until the thickness ratio of the first deposition layer to the second deposition layer is 1.5:1 to 3:1. As shown in FIG. 6 , when the thickness ratio of the first deposition layer to the second deposition layer is 1.5:1 to 3:1, the parasitic capacitance of the semiconductor device is the smallest. It should be noted that the thickness of the first deposition layer remains unchanged, and the thickness of the second deposition layer is changed by repeating steps S1 to S7, so as to realize the control of the ratio of the thickness of the first deposition layer to the second deposition layer.
  • the first deposited layer is deposited from Si 3 N 4 .
  • Si 3 N 4 is a superhard substance, inherently lubricious, and wear-resistant, so it is suitable as a barrier layer and a grinding stop layer for CMP.
  • FIG. 7 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure.
  • a first deposition layer 4 and a second deposition layer 7 are formed on the semiconductor substrate 100, the first deposition layer 4 is a stop layer for chemical mechanical polishing, and the second deposition layer 7 is formed by the first deposition layer 4.
  • the thin films 71 and the second thin films 72 are alternately formed.
  • the thickness ratio of the first deposition layer 4 to the second deposition layer 7 in the semiconductor structure is 1.5:1 to 3:1.
  • the first deposited layer 4 in the semiconductor structure is composed of Si 3 N 4 .
  • FIG. 8 is a schematic diagram of a memory structure according to an embodiment of the present disclosure.
  • bit line insulating layer 1 three parts of the bit line insulating layer 1, the bit line intermediate layer 2 and the bit line conductive layer 3 constitute the memory bit line, and the first deposition layer 4 and the second deposition layer 7 are deposited on the storage device.
  • the sidewall of the bit line, the first deposited layer 4 is a stop layer for chemical mechanical polishing.
  • the second deposited layer 7 is alternately formed of first thin films 71 and second thin films 72 .

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Abstract

本公开实施例公开了一种半导体薄膜形成方法、半导体结构及存储器。该方法包括：将前驱体引入腔室，前驱体在半导体衬底上吸附；吹扫腔室以除去未吸附的前驱体；将含有氧离子和氮离子的等离子体引入腔室，并与前驱体反应沉积第一薄膜；吹扫腔室以除去未反应的等离子体；将含有氧离子的等离子体引入腔室，与吸附在半导体衬底上前驱体反应沉积第二薄膜；循环执行上述步骤，直至第一薄膜和第二薄膜的总厚度达到预定值。本公开通过在半导体衬底上形成第一薄膜和第二薄膜，有效降低氮化物和氧化物界面的寄生电容，缓解接触不佳的技术问题。

Description

一种半导体薄膜形成方法、半导体结构及存储器
交叉引用
本公开基于申请号为202110925579.2、申请日为2021年08月12日、发明名称为“一种半导体薄膜形成方法、半导体结构及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体工艺技术领域。
背景技术
在半导体生产领域，在深沟槽DRAM(Dynamic Random Access Memory，动态随机存取存储器)的内连线制作过程中，位线侧壁形成过程如图1(A)～图1(E)所示。首先，在位线沉积Si 3N 4作为阻挡层和化学机械研磨的停止层。其次，通过ALD(Atomic Layer Deposition，原子层沉积)技术沉积一层厚度小于5nm的SiO 2作为连接层，以便与随后填充的DHPS(聚全氢硅烷)密集接触。最后，通过化学机械研磨和蚀刻形成完整的位线侧壁。
在现有的DRAM位线侧壁之上的结构中，包含Si 3N 4和SiO 2两层。其中Si 3N 4结构致密，抗扩散能力强可以作为优良的阻挡层，但Si 3N 4的介电常数较大，所产生的寄生电容大，从而影响DRAM的性能。另一方面，Si 3N 4的应力较大，存在与SiO 2接触不佳的情况。
发明内容
鉴于此，本公开实施例的目的是提供一种半导体薄膜形成方法、半导体结构及存储器，以缓解现有的技术问题。
根据一些实施例，本公开第一方面提供了一种半导体薄膜形成方法，其包括：将前驱体引入腔室，前驱体在半导体衬底上吸附；吹扫腔室以除去未吸附的前驱体；将含有氧离子和氮离子的等离子体引入腔室，并与前驱体反应沉积第一薄膜；吹扫腔室以除去未反应的等离子体；将含有氧离子的等离子体引入腔室，与吸附在半导体衬底上前驱体反应沉积第二薄膜；循环执行上述步骤，直至第一薄膜和第二薄膜的总厚度达到预定值。
根据一些实施例，本公开第二方面提供了一种半导体结构，包含本公开第一方面半导体薄膜形成方法形成的第一薄膜和第二薄膜，包括：形成在半导体衬底之上的第一沉积层和第二沉积层，第一沉积层为化学机械研磨的停止层，第二沉积层由第一薄膜和第二薄膜交替形成。
根据一些实施例，本公开第三方面提供了一种存储器，包含本公开第一方面半导体薄膜形成方法形成的第一薄膜和第二薄膜，包括：形成在存储器位线侧壁的第一沉积层和第二沉积层，第一沉积层为化学机械研磨的停止层，第二沉积层由第一薄膜和第二薄膜交替形成
本公开实施例可以/至少具有以下优点，通过将含有氧离子和氮离子的等离子体，与吸附在半导体衬底上的前驱体反应沉积第一薄膜，第一薄膜为含有氮、氧元素的氮氧化物，第一薄膜是氮化物和氧化物的中间相，可有效降低氮化物和氧化物界面的寄生电容，缓解接触不佳的技术问题；其后，通过将含有氧离子的等离子体，与吸附在半导体衬底上的前驱体反应沉积第二薄膜，从而在同一制程内实现了第一薄膜和第二薄膜的沉积。
附图说明
图1(A)—图1(E)是现有技术中存储器位线侧壁形成过程示意图；
其中，图1(A)是未形成侧壁的存储器位线示意图，图1(B)是图1(A)经ALD沉积Si3N4的存储器位线示意图，图1(C)是图1(B)经ALD沉积SiO2的存储器位线示意图，图1(D)是图1(C)经SOD(Spin-on Dielectrics，旋涂式电介质)后的存储器位线示意图，图1(E)是图1(D)经过化学机械研磨和刻蚀后的存储器位线示意图。
图2是本公开实施例一种半导体薄膜形成方法流程示意图；
图3是本公开实施例一种半导体薄膜形成方法薄膜形成过程时序示意图；
图4(A)—图4(E)是本公开实施例一种半导体薄膜形成方法薄膜形成过程示意图；
其中，图4(A)是未形成侧壁薄膜的半导体结构存储器位线示意图，图4(B)是图4(A)形成第一沉积层后的半导体结构存储器位线示意图，图4(C)是图4(B)形成第二沉积层后的半导体结构存储器位线示意图，图4(D)是图4(C)经过化学机械研磨和刻蚀后的半导体结构存储器位线示意图，图4(E)是图4(D)的局部放大图。
图5是本公开实施例一种半导体薄膜形成方法O2与N2气体流量之比对半导体器件寄生电容影响示意图；
图6是本公开实施例一种半导体薄膜形成方法第一沉积层与第二沉积层厚度之比对半导体器件寄生电容影响示意图；
图7是本公开实施例一种半导体结构示意图；
图8是本公开实施例一种存储器结构示意图。
附图标记：
11：位线绝缘层；21：位线中间层；31：位线导电层；41：Si3N4层；1：位线绝缘层；2：位线中间层；3：位线导电层；4：Si3N4层；5：SiO2层；6：SOD示意；7：第二沉积层；71：第一薄膜；72：第 二薄膜；10：前驱体通入；20：腔室吹扫；30：含氮离子和氧离子的等离子体通入；40：射频信号；50：含氧离子的等离子体通入；100：半导体衬底。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本公开进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的层结构示意图。这些图并不一定是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
图1(A)—图1(E)是现有技术中存储器位线侧壁形成过程示意图。
其中，图1(A)是未形成侧壁的存储器位线示意图，图1(B)是图1(A)经ALD沉积Si 3N 4的存储器位线示意图，图1(C)是图1 (B)经ALD沉积SiO 2的存储器位线示意图，图1(D)是图1(C)经SOD(Spin-On Dielectrics，旋涂式电介质)后的存储器位线示意图，图1(E)是图1(D)经过化学机械研磨和刻蚀后的存储器位线示意图。
参考图1(A)，存储器位线由位线绝缘层10、位线中间层20及位线导电层30三个部分构成。在图1(B)中，存储器位线经ALD工艺沉积后形成Si 3N 4层41。在图1(C)中，存储器位线经ALD工艺沉积后形成SiO 2层5。在经过图1(D)SOD进行间隙填充6之后，通过化学机械研磨和刻蚀后的形成图1(E)中完整的存储器位线侧壁。参考图1(E)，完整的存储器位线侧壁包含Si 3N 4层41和SiO 2层5。
需要进行说明的是，化学机械研磨(Chemical Mechanical Polish，CMP)亦称为化学机械抛光，其原理是化学腐蚀作用和机械去除作用相结合的加工技术，是机械加工中可以实现表面全局平坦化的技术。蚀刻(Etching)是将材料使用化学反应或物理撞击作用而移除的技术。
Si 3N 4结构致密，抗扩散能力强可以作为优良的阻挡层，但是Si 3N 4的介电常数较大，所产生的寄生电容大，从而影响存储器的性能。另一方面，Si 3N 4的应力较大与SiO 2存在接触面不佳的情况。寄生电容一般是指非电容器件在高频情况下表现出来的电容特性，DRAM靠内部寄生电容充放电来记忆信息，电容充有电荷为逻辑1，不充电为逻辑0。但在另一方面,由于DRAM频率的不断提高,致使引线寄生电感、寄生电容的影响愈加严重,对器件造成更大的电应力，具体表现为过电压、过电流的毛刺。对于DRAM而言，寄生电容大会影响DRAM的性能。因此，图1(E)中Si 3N 4层41和SiO 2层5，使得存储器位线寄生电容大，且Si 3N 4层41与SiO 2层5存在接触面不佳的情况。
图2是本公开实施例一种半导体薄膜形成方法流程示意图。
如图2所示，本公开实施例提供的半导体薄膜形成方法主要包括7个步骤，以下对7个步骤进行详细说明。
步骤S1，将前驱体在半导体衬底上吸附。
具体地，将前驱体引入腔室，前驱体在半导体衬底上吸附。需要进行说明的是，在半导体制备技术领域，前驱体是经过某些步骤就可实现目标产物的前级产物，前驱体是ALD沉积工艺的基础。无论是ALD还是PEALD(Plasma Enhanced Atomic Layer Deposition，等离子体增强原子层沉积)的第一个步骤，都是将反应的前驱体在半导体衬底上进行吸附或者饱和吸附。
在一些实施例中，前驱体为硅与氢的化合物或混合物。示例性地，可以是硅烷(SiH 4，四氢化硅)，硅烷是一种无色的气体，可以吸附在半导体衬底上。
在一些实施例中，硅与氢的化合物选自四(二甲胺基)硅烷(TDMAS)、异丙氨基硅烷(DIPAS)、双(二乙基酰胺)硅烷(BDEAS)、双(叔丁基氨基)硅烷(BTBAS)中的任一种，或其任意组合的混合物。在一些实施例中，硅与氢的化合物选择双(二乙基酰胺)硅烷(BDEAS)。
在一些实施例的步骤S1中，设置前驱体与半导体衬底的吸附时间为2-10秒。设置吸附时间的长短，可以确保前驱体在衬底中的吸附程度。例如，吸附时间大于某一数值时，前驱体为饱和吸附。
步骤S2，吹扫腔室以除去未吸附的所述前驱体。
在ALD或者PEALD薄膜沉积工艺中，如果不将未吸附的前驱体吹扫出腔室，未吸附的前驱体会与后续通入的反应物质进行反应，从而影响已吸附的前驱体的反应，影响已吸附前驱体的薄膜沉积工艺。
在一个可选的实施例中，采用惰性气体吹扫腔室。可选的，通入惰性气体氩气(Ar)吹扫除去多余的前驱体。需要进行说明的是，吹扫除去多余的前驱体的气体，不能与前驱体反应，因此选择惰性气体。 此外，只要不与前驱体反应的气体，都可以用来吹扫多余的前驱体。
步骤S3，反应形成第一薄膜。
具体地，将含有氧离子和氮离子的等离子体引入腔室，并与吸附在半导体衬底上前驱体反应沉积第一薄膜。
需要进行说明的是，ALD或者PEALD的反应具有自限制性(Self-Limiting)，即前驱体输入到半导体衬底，通过吸附或饱和吸附保持在表面；当后续的反应物质通入反应腔室，就会与已吸附于半导体衬底表面的前驱体发生反应。前驱体与反应物质之间会发生置换反应并产生相应的副产物，直到半导体衬底表面的前驱体完全消耗，反应会自动停止并形成需要的原子层薄膜沉积在半导体衬底表面。
在一些实施例中，前驱体为硅与氢的化合物，将含有氧离子和氮离子的等离子体引入腔室，含有氧离子和氮离子的等离子体同硅与氢的化合物反应生成氮氧化硅SiON。
在一些实施例中，含有氧离子和氮离子的等离子体，由气体流量比例为1:1-1:20的O 2与N 2或NH 3电离生成。可选的，等离子体由O 2与N 2或NH 3等反应气体在等离子体反应腔室中产生，产生后通入腔室与前驱体进行反应。示例性地，等离子体由射频发生器激发O 2与N 2或NH 3等反应气体产生。在一个实施例中，O 2与N 2的气体流量比例1：9。通过控制通入反应腔体的O 2与N 2或NH 3等离子体源流量比来精准控制第一薄膜中的氮与氧元素的比例，以控制产生的寄生电容大小。
在一些实施例中，设置等离子体的通入时间为1-10秒。可选地，当含氮元素的等离子体由N 2产生时，设置等离子体的通入时间5秒。需要进行说明的是，等离子体的通入时间不同，等离子体在腔室内的含量不同。
步骤S4，吹扫腔室以除去未反应的等离子体。
同样，为了使未反应的等离子体不与后续过程中通入的反应物质进行反应，需要将未反应的等离子体吹扫出腔室。
在一个可选的实施例中，采用惰性气体吹扫腔室。可选的，通入惰性气体氩气(Ar)吹扫除去未反应的等离子体。需要进行说明的是，吹扫除去未反应的等离子体的气体，不能与等离子体反应，因此选择惰性气体。此外，只要不与等离子体，及第一薄膜反应的气体，都可以用来吹扫未反应的等离子体。
步骤S5，反应形成第二薄膜。
具体地，执行步骤S1和S2，将含有氧离子的等离子体引入腔室，与吸附在半导体衬底上前驱体反应沉积第二薄膜
在一些实施例中，前驱体为硅与氢的化合物，将含有氧离子的等离子体引入腔室，含有氧离子的等离子体同硅与氢的化合物反应生成二氧化硅SiO 2。
可选的，步骤S5中，设置前驱体吸附时间为3秒。
在一些实施例中，在步骤S3中和S5中，第一薄膜和第二薄膜的沉积阶段，设置腔室的温度为40℃至110℃。
步骤S6，执行步骤S4。第二薄膜沉积完成后，执行步骤S4，将未反应的等离子体吹扫出腔室。
步骤S7，返回步骤S1，循环执行上述步骤，直至第一薄膜和第二薄膜的总厚度达到预定值。
图3是本公开实施例一种半导体薄膜形成方法薄膜形成过程时序示意图。
如图3所示，在一个制程周期内包含第一薄膜沉积和第二薄膜沉积两个阶段。在第一薄膜沉积阶段，包括前驱体通入10、腔室吹扫20、含氮离子和氧离子的等离子体通入30、腔室吹扫20四个阶段， 每个阶段按时间顺序依次进行。
在第二薄膜沉积阶段，包括前驱体通入10、腔室吹扫20、含氧离子的等离子体通入50、腔室吹扫20四个阶段，每个阶段按时间顺序依次进行。可选的，等离子体由射频信号激发产生，因此在气体O 2与N 2或NH 3通入期间，射频信号40激发O 2与N 2或NH 3产生含离子和氧离子的等离子体、或含氧离子的等离子体。
参考图3，在一些实施例中，重复步骤S1至S7中，直至第一薄膜和第二薄膜的总厚度达到预定值，即重复多个制程周期，以沉积预期厚度的第一薄膜和第二薄膜。需要进行说明的是，ALD或者PEALD相比传统的金属有机物化学气相沉积、分子束外延和物理气相沉积等沉积工艺具有较高的控制精度，可通过控制反应周期数精确地控制薄膜的厚度。可选地，重复30-60个制程周期以达到所需的薄膜厚度。
在一个可选的实施例中，半导体薄膜形成方法还包括：步骤S8，对半导体衬底进行化学机械研磨和蚀刻。可选地，进行化学机械研磨和蚀刻，以使半导体薄膜平坦，或去除多余的部分。
图4(A)—图4(E)是本公开实施例一种半导体薄膜形成方法薄膜形成过程示意图。
其中，图4(A)是未形成侧壁薄膜的半导体结构存储器位线示意图。
图4(B)是图4(A)形成第一沉积层后的半导体结构存储器位线示意图，
图4(C)是图4(B)形成第二沉积层后的半导体结构存储器位线示意图，
图4(D)是图4(C)经过化学机械研磨和刻蚀后的半导体结构存储器位线示意图。图4(A)—图4(D)示意性示出了半导体结构 存储器位线形成过程中的结构变化图。
在一些实施例中，半导体衬底包含存储器位线，第一沉积层和第二沉积层形成在存储器位线侧壁，第一沉积层为化学机械研磨的停止层，第二沉积层由第一薄膜和第二薄膜交替形成。参考图4(D)，位线绝缘层1、位线中间层2及位线导电层3三个部分在半导体衬底结构中构成了存储器位线，第一沉积层4和第二沉积层7沉积在存储器位线侧壁。
在一些实施例中，第一沉积层4通过ALD或PEALD沉积而成。
图4(E)是图4(D)的局部放大图，参考图4(E)，第二沉积层7由第一薄膜71和第二薄膜72交替形成。
在一些实施例中，在第一沉积层4形成后，重复步骤S1至S7，直至第一沉积层4与第二沉积层7的厚度之比为1.5:1至3:1。例如，重复步骤N次，则会形成有N个第一薄膜71和N个第二薄膜72。需要进行说明的是，步骤S1-S4用于形成第一薄膜71，步骤S5用于形成第二薄膜72，因此在重复步骤S1至S7的过程中，第一薄膜71和第二薄膜72交替形成。
在一些实施例中，第一薄膜71为氮氧化硅SiON，第一薄膜71是氮化硅和二氧化物硅中间相，可有效降低氮化硅和二氧化硅界面的寄生电容，缓解氮化硅和二氧化硅接触不佳的技术问题；其后，通过将含有氧离子的等离子体，与吸附在半导体衬底上的前驱体反应沉积第二薄膜72，从而在同一制程内实现了第一薄膜71和第二薄膜72的沉积
图5是本公开实施例一种半导体薄膜形成方法O 2与N 2气体流量之比对半导体器件寄生电容影响示意图。
不同的O 2与N 2气体流量之比，则产生的含有氧离子和氮离子的 等离子体中的两种元素之比不同，进而产生的第一薄膜中氧离子和氮离子的比例也不同，对半导体器件产生的寄生电容也不同。可选地，第一薄膜为氮氧化硅SiNO、第二薄膜为二氧化硅SiO 2时，参考图5和下表，当O 2与N 2气体流量之比为1：9，对半导体器件产生的寄生电容最小，此时第一薄膜与第二薄膜的厚度之和为7.51nm，薄膜含氧比例27％，含氮比例39％。
Figure PCTCN2021118849-appb-000001
图6是本公开实施例一种半导体薄膜形成方法第一沉积层与第二沉积层厚度之比对半导体器件寄生电容影响示意图。
在一些实施例中，重复步骤S1至S7，直至第一沉积层与第二沉积层的厚度之比为1.5:1至3:1。如图6所示，第一沉积层与第二沉积层厚度之比为1.5:1至3:1时，半导体器件寄生电容最小。需要进行说明的是，第一沉积层的厚度不变，重复步骤S1至S7改变第二沉积层的厚度，从而实现对第一沉积层与第二沉积层厚度之比的控制。
在一些实施例中，第一沉积层由Si 3N 4沉积而成。Si 3N 4是一种超硬物质，本身具有润滑性，并且耐磨损，因此适合于作为阻挡层和CMP的研磨停止层。
图7是本公开实施例一种半导体结构示意图。
如图7所示的半导体结构中，半导体衬底100之上形成第一沉积层4和第二沉积层7，第一沉积层4为化学机械研磨的停止层，第二沉积层7由第一薄膜71和第二薄膜72交替形成。
在一些实施例中，半导体结构中第一沉积层4与第二沉积层7的厚度之比为1.5:1至3:1。
在一些实施例中，半导体结构中第一沉积层4由Si 3N 4构成。
图8是本公开实施例一种存储器结构示意图。
如图8所示的存储器结构中，位线绝缘层1、位线中间层2及位线导电层3三个部分构成了存储器位线，第一沉积层4和第二沉积层7沉积在存储器位线侧壁，第一沉积层4为化学机械研磨的停止层。参考图7，第二沉积层7由第一薄膜71和第二薄膜72交替形成。
应当理解的是，本公开的上述具体实施方式仅仅用于示例性说明或解释本公开的原理，而不构成对本公开的限制。因此，在不偏离本公开的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。此外，本公开所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (15)

  1. 一种半导体薄膜形成方法，包括：
    将前驱体引入腔室，所述前驱体在半导体衬底上吸附；
    吹扫腔室以除去未吸附的所述前驱体；
    将含有氧离子和氮离子的等离子体引入腔室，并与所述前驱体反应沉积第一薄膜；
    吹扫腔室以除去未反应的等离子体；
    将含有氧离子的等离子体引入腔室，与吸附在半导体衬底上所述前驱体反应沉积第二薄膜；
    循环执行上述步骤，直至所述第一薄膜和第二薄膜的总厚度达到预定值。
  2. 根据权利要求1所述的半导体薄膜形成方法，其中，所述前驱体为硅与氢的化合物。
  3. 根据权利要求2所述的半导体薄膜形成方法，其中，所述硅与氢的化合物选自四(二甲胺基)硅烷(TDMAS)、异丙氨基硅烷(DIPAS)、双(二乙基酰胺)硅烷(BDEAS)、双(叔丁基氨基)硅烷(BTBAS)中的任一，或其任意组合的混合物。
  4. 根据权利要求1所述的半导体薄膜形成方法，其中，在中，设置所述前驱体与半导体衬底的吸附时间为2-10秒。
  5. 根据权利要求1所述的半导体薄膜形成方法，其中，所述含有氧离子和氮离子的等离子体，由气体流量比例为1:1-1:20的O 2与N 2或NH 3电离生成。
  6. 根据权利要求1所述的半导体薄膜形成方法，其中，设置所述等离子体的通入时间为1-10秒。
  7. 根据权利要求1所述的半导体薄膜形成方法，其中，所述第一薄膜和第二薄膜的沉积阶段，设置所述腔室的温度为40℃至110℃。
  8. 根据权利要求1所述的半导体薄膜形成方法，其中，还包括：对所述半导体衬底进行化学机械研磨和蚀刻。
  9. 根据权利要求1所述的半导体薄膜形成方法，其中，所述的半导体衬底包含存储器位线，第一沉积层和第二沉积层形成在所述存储器位线侧壁，所述第一沉积层为化学机械研磨的停止层，所述第二沉积层由第一薄膜和第二薄膜交替形成。
  10. 根据权利要求9所述的半导体薄膜形成方法，其中，所述第一沉积层与第二沉积层的厚度之比为1.5:1至3:1。
  11. 根据权利要求9所述的半导体薄膜形成方法，其中，所述第一沉积层由Si 3N 4沉积而成。
  12. 一种半导体结构，包含权利要求1所述的半导体薄膜形成方法形成的第一薄膜和第二薄膜，包括：形成在半导体衬底之上的第一沉积层和第二沉积层，所述第一沉积层为化学机械研磨的停止层，所述第二沉积层由第一薄膜和第二薄膜交替形成。
  13. 根据权利要求12所述的半导体结构，其中，所述第一沉积层与第二沉积层的厚度之比为1.5:1至3:1。
  14. 根据权利要求12所述的半导体结构，其中，所述第一沉积层由Si 3N 4构成。
  15. 一种存储器，包含权利要求1所述的半导体薄膜形成方法形成的第一薄膜和第二薄膜，包括：形成在存储器位线侧壁的第一沉积层和第二沉积层，所述第一沉积层为化学机械研磨的停止层，所述第二沉积层由第一薄膜和第二薄膜交替形成。
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