WO2023015637A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2023015637A1
WO2023015637A1 PCT/CN2021/116844 CN2021116844W WO2023015637A1 WO 2023015637 A1 WO2023015637 A1 WO 2023015637A1 CN 2021116844 W CN2021116844 W CN 2021116844W WO 2023015637 A1 WO2023015637 A1 WO 2023015637A1
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Prior art keywords
layer
source
drain
segment
area
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PCT/CN2021/116844
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English (en)
French (fr)
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闫宇
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武汉华星光电技术有限公司
武汉华星光电半导体显示技术有限公司
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Priority to US17/608,146 priority Critical patent/US20240023372A1/en
Publication of WO2023015637A1 publication Critical patent/WO2023015637A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/30—Coordination compounds
    • H10K85/331—Metal complexes comprising an iron-series metal, e.g. Fe, Co, Ni
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures

Definitions

  • the present application relates to the display field, in particular to an array substrate, a manufacturing method thereof, and a display device.
  • Low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LPTO) is similar to low temperature polysilicon (Low Temperature Poly-silicon, LTPS), has high electron mobility, and it can also have the advantages of Indium Gallium Zinc Oxide (IGZO), The effect of realizing higher charge mobility with low production cost is achieved, and the display panel is provided with strong stability and scalability.
  • the display screen using LTPO technology can greatly reduce the refresh rate without requiring additional devices, so that the device can save a lot of power by reducing the refresh rate.
  • a potential barrier layer is often formed.
  • the doping concentration of the semiconductor reaches a certain level, electrons can pass through the potential barrier through the tunnel effect, theoretically forming a low-resistance ohmic contact layer.
  • doping has a negative effect.
  • the doping is too much, the density of acceptors increases to form a high surface state semiconductor, resulting in the Fermi level pinning effect.
  • the Fermi level in semiconductors is a parameter that is easy to change.
  • Adding donor impurities can move the Fermi level to the bottom of the conduction band, and the semiconductor becomes an n-type semiconductor; adding acceptor impurities can move the Fermi level to the top of the valence band, and the semiconductor becomes a p-type semiconductor.
  • the excessively doped impurities cannot be activated, nor can they provide carriers, so they cannot change the position of the Fermi level. In this case, Fermi level pinning occurs. . This effect will greatly reduce the electron mobility between the metal and the semiconductor, thereby weakening the display effect of the display panel.
  • the embodiment of the present application provides a dimming layer and a display module for a display module to solve the problem that when the LTPO array substrate is too much doped, the acceptor density becomes larger and a high surface state semiconductor is formed to form a Fermi level pinning effect. technical problem.
  • An embodiment of the present application provides an array substrate, including
  • the active layer disposed on the substrate, the active layer comprising an active segment and a connecting segment disposed on at least one side of the active segment;
  • a source-drain layer disposed on the connecting segment and connected in contact with the connecting segment;
  • the area of the contact surface between the source-drain layer and the connecting segment is greater than the area of the orthographic projection of the contact surface between the source-drain layer and the connecting segment on the substrate.
  • the contact surface of the connection segment in contact with the source and drain layer includes at least one first protrusion, and the source and drain layer includes a first recess.
  • a support layer is provided between the active layer and the substrate, and the support layer is provided at a position corresponding to the first protrusion to match the first protrusion.
  • the support is raised.
  • the material of the supporting layer is any one of silicon oxide and silicon nitride.
  • the contact surface of the active layer that is in contact with the source and drain layer includes at least one second recess, and the source and drain layer includes a second convex portion.
  • an insulating layer is disposed on the source-drain layer, the insulating layer covers the active layer and the source-drain layer, and a gate groove is formed on the insulating layer, so A gate layer is formed in the gate groove, and a side of the insulating layer away from the source-drain layer is coplanar with a side of the gate layer away from the source-drain layer.
  • the connecting section includes a first connecting section and a second connecting section respectively connected to the active section
  • the source-drain layer includes a source layer arranged on the first connecting section. pole and a drain disposed on the second connection section, the contact area between the source and the first connection section is larger than the contact area between the source and the first connection section on the substrate
  • the area of the orthographic projection of the drain electrode and the second connecting segment is larger than the area of the orthographic projection of the contact surface of the drain electrode and the second connecting segment on the substrate.
  • the source and drain layers include a metal oxide layer and a metal layer, the metal layer is connected to the connecting segment through the metal oxide layer, and the contact between the metal oxide layer and the connecting segment The surface area is smaller than the contact surface area between the metal oxide layer and the source-drain layer.
  • the thickness of the metal oxide layer is less than 5 nm, and the material of the metal oxide layer is one of titanium oxide, cobalt oxide or nickel oxide.
  • the present application also provides a method for manufacturing an array substrate, comprising the following steps:
  • the active layer including an active segment and a connecting segment disposed on at least one side of the active segment;
  • the area of the contact surface between the source-drain layer and the connecting segment is greater than the area of the orthographic projection of the contact surface between the source-drain layer and the connecting segment on the substrate.
  • the present application also provides a display device, including an array substrate, and the array substrate includes:
  • the active layer disposed on the substrate, the active layer comprising an active segment and a connecting segment disposed on at least one side of the active segment;
  • a source-drain layer disposed on the connecting segment and connected in contact with the connecting segment;
  • the area of the contact surface between the source-drain layer and the connecting segment is greater than the area of the orthographic projection of the contact surface between the source-drain layer and the connecting segment on the substrate.
  • the contact surface of the connecting segment in contact with the source and drain layer includes at least one first protrusion, and the source and drain layer includes a first recess.
  • a support layer is provided between the active layer and the substrate, and the support layer is provided at a position corresponding to the first protrusion to match the first protrusion.
  • the support is raised.
  • the material of the supporting layer is any one of silicon oxide and silicon nitride.
  • the contact surface of the active layer that is in contact with the source and drain layer includes at least one second recess, and the source and drain layer includes a second convex portion.
  • an insulating layer is disposed on the source-drain layer, the insulating layer covers the active layer and the source-drain layer, and a gate groove is formed on the insulating layer, so A gate layer is formed in the gate groove, and a side of the insulating layer away from the source-drain layer is coplanar with a side of the gate layer away from the source-drain layer.
  • the connecting section includes a first connecting section and a second connecting section respectively connected to the active section
  • the source-drain layer includes a source layer arranged on the first connecting section. pole and a drain disposed on the second connection section, the contact area between the source and the first connection section is larger than the contact area between the source and the first connection section on the substrate
  • the area of the orthographic projection of the drain electrode and the second connecting segment is larger than the area of the orthographic projection of the contact surface of the drain electrode and the second connecting segment on the substrate.
  • the source and drain layers include a metal oxide layer and a metal layer, the metal layer is connected to the connection segment through the metal oxide layer, and the contact between the metal oxide layer and the connection segment The surface area is smaller than the contact surface area between the metal oxide layer and the source-drain layer.
  • the thickness of the metal oxide layer is less than 5 nm, and the material of the metal oxide layer is one of titanium oxide, cobalt oxide or nickel oxide.
  • the material of the metal oxide layer is nickel oxide.
  • the active layer and the source-drain layer are sequentially arranged, the source-drain layer is connected to the connection section of the active layer, and the area of the contact surface between the source-drain layer and the connection section is larger than that of the source-drain layer
  • the area of the orthographic projection of the contact surface with the connection section on the substrate effectively increases the contact area between the metal and the semiconductor, and can effectively alleviate the formation of high acceptor density on the semiconductor surface due to excessive doping of the semiconductor.
  • the problem of Fermi level pinning caused by the surface state improves the Fermi level pinning effect of the LTPO array substrate, improves the electron mobility between the metal and the semiconductor, and further improves the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a connection section including a plurality of first protrusions in an array substrate provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a connecting section including a first convex portion and a second concave portion in an array substrate provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • FIG. 6 is a schematic structural view of an array substrate whose source and drain layers include a metal oxide layer according to another embodiment of the present application;
  • FIG. 7 is a schematic diagram of the manufacturing process of the array substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the manufacturing process of an array substrate provided by another embodiment of the present application.
  • FIG. 9 is a flow chart of manufacturing an array substrate provided by an embodiment of the present application.
  • the present application provides an array substrate, a manufacturing method of the array substrate, and a display device.
  • a manufacturing method of the array substrate and a display device.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.
  • Embodiments of the present application provide an array substrate, a manufacturing method of the array substrate, and a display device. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • a potential barrier layer is often formed.
  • the doping concentration of the semiconductor reaches a certain level, electrons can pass through the potential barrier through the tunnel effect, theoretically forming a low-resistance ohmic contact layer.
  • an array substrate as shown in Figure 1, including:
  • an active layer disposed on the substrate 100, the active layer comprising an active segment and a connecting segment 201 disposed on at least one side of the active segment;
  • the source-drain layer 202 is disposed on the connection segment 201 and is in contact with the connection segment 201;
  • the area of the contact surface between the source-drain layer 202 and the connecting segment 201 is greater than the area of the orthographic projection of the contact surface between the source-drain layer 202 and the connecting segment 201 on the substrate 100 .
  • the substrate 100 includes a base 101 and a buffer layer 102 disposed on the base 101, the active layer includes an active segment and a connection segment 201 disposed on at least one side of the active segment, the connection The section 201 can have two sections, and the two connecting sections 201 can be respectively arranged on both sides of the active section, or can be arranged on the same side of the active section, and the material of the active section can be a semiconductor material, specifically It can be a low-temperature polysilicon material, and the semiconductor material can be doped with donor impurities to form an n-type semiconductor, or can be doped with acceptor impurities to form a p-type semiconductor.
  • a channel is formed on the active segment, and the channel is filled with a metal oxide, and the metal oxide may be IGZO.
  • the active layer can be formed by chemical vapor deposition. After the film-formed semiconductor layer is obtained, ion implantation is performed to obtain the doped semiconductor connection segment 201, and then physical vapor deposition is performed. The oxide layer is formed by film formation, and the field oxygen 204 is formed by etching the oxide layer.
  • the source-drain layer 202 formed on the active layer may be made of a metal material, and the source-drain layer 202 may include a source and a drain, and the source is connected to a connecting segment on the active layer. 201, the drain is connected to the connecting segment 201 on another active layer, and the source and the drain may be made of the same metal or different metals.
  • a dielectric layer 303 may be formed on the active layer, the source and drain layers 202 are formed on the dielectric layer 303 , and the corresponding connecting segment 201 on the dielectric layer 303 A via hole is opened at the position, and the source-drain layer 202 is connected to the connection section 201 through the via hole.
  • the area of the contact surface between the source-drain layer 202 and the connecting segment 201 is greater than the area of the orthographic projection of the contact surface between the source-drain layer 202 and the connecting segment 201 on the substrate 100 , it can be understood that the contact surface between the source and drain electrodes and the connecting section 201 is an undulating curved surface with radians, and the cross-section of the contact surface can be zigzag, wavy, or stepped, as long as it can Enlarging the area of the contact surface between the source-drain layer 202 and the connection segment 201 is within the protection scope of the present application.
  • the array substrate further includes a gate layer, the gate layer may be disposed below the active layer, or disposed above the active layer, and the gate layer and the active layer The layers are arranged at intervals through the gate insulating layer 301 .
  • the contact surface of the connection segment 201 in contact with the source and drain layer 202 includes at least one first protrusion 201a, and the source and drain layer 202 includes a The first concave part matched with the first convex part 201a.
  • the number of the first protrusions 201a is not limited, there may be one or more, and the height of the first protrusions 201a is not limited, and may have the same height or different heights , the shape of the first protrusion 201a is not limited, and its cross-section can be a semi-ellipse with a certain curvature, or a square, as long as the contact area between the source-drain layer 202 and the connecting segment 201 can be increased. , are all within the protection scope of this application.
  • the first protrusion 201a may be provided on the side of the connection section 201 connected to the source-drain layer 202, and the corresponding source-drain layer 202 is provided with the first protrusion.
  • the first convex portion 201a can also be set on the side of the source-drain layer 202 connected to the connecting segment 201, and the corresponding connecting segment 201 is connected to the connecting segment 201
  • the first convex portion 201a matches the first concave portion.
  • the contact surface connecting the connection segment 201 with the source-drain layer 202 includes at least one first protrusion 201a
  • the source-drain layer 202 includes a
  • FIG. 3 is an embodiment where the contact surface of the connection segment 201 and the source-drain layer 202 includes two first protrusions 201a, so that when the array substrate is fabricated , the manufacturing process is simpler and the difficulty of production is reduced.
  • a support layer 203 is provided between the active layer and the substrate 100, and the support layer 203 is provided with a
  • the first protrusion 201a matches the supporting protrusion 203a.
  • the support layer 203 is disposed between the active layer and the substrate 100, specifically, when the first protrusion 201a is disposed on the connecting segment 201, at this time, the connecting segment There is no concave portion on 201, and they are all first convex portions 201a.
  • a supporting protrusion 203a is formed at the position of the supporting layer 203 corresponding to the first concave portion.
  • the shape of the supporting protrusion 203a is similar to that of the first protrusion.
  • the material of the support layer 203 is an insulating material, which may be one of silicon oxide and silicon nitride.
  • the material of the support layer 203 is easier to perform etching and shaping operations than the material of the active layer, and the production cost is low.
  • the connection section 201 is covered on the support protrusion 203a of the support layer 203, adopting this solution, it is easier to form in industrial production
  • the active layer has a curved surface, and is more practical in production, and the production cost is low. Compared with the production process of the common array substrate, there are fewer steps added, and the conduction rate of ions is higher.
  • the contact surface of the active layer that is in contact with the source-drain layer 202 includes at least one second recess 201b, and the source-drain layer 202 includes a The second convex part matched with the second concave part 201b.
  • the contact surface on the active layer that is in contact with the source and drain layer 202 also includes a second concave portion 201b, which can be understood as the connection between the connecting segment 201 and the source and drain layer 202
  • a second concave portion 201b can be understood as the connection between the connecting segment 201 and the source and drain layer 202
  • the contact area between the active layer and the source-drain layer 202 is further increased, and the The Fermi level pinning effect of the LTPO array substrate improves the electron mobility between the metal and the semiconductor, thereby improving the display effect of the display panel.
  • an insulating layer is disposed on the source-drain layer 202, the insulating layer covers the active layer and the source-drain layer 202, and the insulating layer is formed on the There is a gate groove, a gate layer is formed in the gate groove, the side of the insulating layer away from the source and drain layer 202 is coplanar with the side of the gate layer away from the source and drain layer 202 set up.
  • the structure of the array substrate is a top-gate structure, wherein the gate 302 is located above the active layer, the insulating layer is the gate insulating layer 301, and the gate insulating layer 301 is provided The upper surface thereof is in a planar state, so that the gate insulating layer 301 not only plays the role of flatness, but also plays the role of the gate insulating layer 301, further reducing the thickness of the array substrate.
  • the connecting section 201 includes a first connecting section and a second connecting section respectively connected to the active section
  • the source-drain layer 202 includes a source layer disposed on the first connecting section. pole and a drain disposed on the second connection section, the contact area between the source and the first connection section is larger than the contact area between the source and the first connection section in the substrate 100
  • the area of the orthographic projection on the substrate 100, and/or the contact area between the drain and the second connecting segment is larger than the orthographic projection of the contact surface between the drain and the second connecting segment on the substrate 100 area.
  • the contact area between the source and the first connection segment is larger than the area of the orthographic projection of the contact surface between the source and the first connection segment on the substrate 100, that is, the first At least one first sub-protrusion may be provided on the connecting section, and a first sub-recess corresponding to the first sub-protrusion may be provided on the corresponding source; and/or the drain and the first sub-convex
  • the contact area of the two connection segments is greater than the area of the orthographic projection of the contact surface between the drain and the second connection segment on the substrate 100, that is, at least one second sub-section may be provided on the second connection segment. Convex portion; a second sub-recess corresponding to the second sub-protrusion is provided on the corresponding drain.
  • the first sub-protrusion can be provided on the first connection section alone, the second sub-projection can also be provided on the second connection section alone, or the first sub-projection can be provided on the first connection section
  • the second sub-protrusion is set on the first sub-protrusion and the second connection section, and the above-mentioned technical solution further effectively increases the contact area between the metal and the semiconductor, and can effectively alleviate the damage caused by excessive doping of the semiconductor.
  • Bulk density increases, forming high surface states on the surface of semiconductors to generate Fermi level pinning, which improves the Fermi level pinning effect of LTPO array substrates, improves the electron mobility between metals and semiconductors, and then improves The display effect of the display panel.
  • the source-drain layer 202 includes a metal oxide layer 205 and a metal layer, the metal layer is connected to the connection segment 201 through the metal oxide layer 205, and the metal oxide layer The area of the contact surface between the layer 205 and the connection segment 201 is smaller than the area of the contact surface between the metal oxide layer 205 and the source-drain layer 202 .
  • the material of the metal oxide layer 205 may be titanium oxide, and the material of the metal oxide layer 205 may also be cobalt oxide or nickel oxide.
  • the metal oxide layer 205 has a lower conduction band step, so the metal oxide layer 205 can effectively reduce the density of states in the forbidden band of the connecting segment 201 of the active layer, thereby effectively reducing
  • the appearance of the metal-induced gap state phenomenon can effectively suppress the phenomenon of Fermi level pinning at the interface between the source-drain layer 202 and the active layer connection section 201, thereby helping to reduce the gap between the source-drain layer 202 and the active layer.
  • the contact resistance between the connection segments 201 is beneficial to improve the performance of the formed semiconductor structure.
  • the thickness of the metal oxide layer 205 is less than 5 nm, and the material of the metal oxide layer 205 is one of titanium oxide, cobalt oxide or nickel oxide.
  • the metal oxide layer 205 can improve the connection between the source and drain layers 202 and the active layer.
  • the present application also provides a method for manufacturing an array substrate, as shown in Figure 7 and Figure 9, comprising the following steps:
  • a gate insulating layer 301 is formed on the source-drain layer 202 , and a gate 302 is formed on the gate insulating layer 301 , so that a top gate structure can be formed.
  • a substrate 100 is formed
  • an active layer is formed on the substrate 100, the active layer includes an active segment and a connecting segment 201 disposed on at least one side of the active segment;
  • a source-drain layer 202 is formed on the connection section 201 , and the source-drain layer 202 is in contact with the connection section 201 ; wherein, the source-drain layer 202
  • the area of the contact surface with the connecting segment 201 is greater than the area of the orthographic projection of the contact surface of the source-drain layer 202 and the connecting segment 201 on the substrate 100;
  • a gate insulating layer 301 is further formed on the source-drain layer 202 , and a gate 302 is formed on the gate insulating layer 301 , which can form a top grid structure.
  • the method for manufacturing the array substrate includes the following steps:
  • a substrate 100 is formed.
  • the substrate 100 includes a base 101 and a buffer layer 102 disposed on the base 101.
  • the base 101 can be formed by coating with a polyimide resin, and the chemical vapor phase
  • the buffer layer 102 is formed by depositing a film-forming means.
  • a support layer 203 is formed, and the material of the support layer 203 may be silicon nitride, and a support protrusion 203a is provided on the support layer 203 corresponding to the position of the active layer connecting section 201;
  • an active layer is formed on the support layer 203 and the substrate 100, the active layer includes an active segment and a connection provided on at least one side of the active segment Section 201; wherein, the connecting section 201 can have two sections, and the two connecting sections 201 can be respectively arranged on both sides of the active section, and before the active layer is formed, the semiconductor material is first implanted with ions, and the doping operation is performed , and then deposit a doped semiconductor on the support layer 203, etch on the doped semiconductor layer to form an oxide channel, and deposit and form a field oxygen 204 in the oxide channel.
  • a source-drain layer 202 is formed on the connection section 201 , and the source-drain layer 202 is in contact with the connection section 201 ; wherein, the source-drain layer 202 is connected to the connection section 201
  • the area of the contact surface of the connection segment 201 is greater than the area of the orthographic projection of the contact surface of the source-drain layer 202 and the connection segment 201 on the substrate 100 .
  • an insulating layer may also be formed above the source and drain electrodes, the insulating layer covers the active layer and the source and drain layers 202, and on the insulating layer A gate layer is formed, and a second insulating layer covering the gate layer and the insulating layer is formed on the gate layer.
  • the area of the orthographic projection effectively increases the contact area between the metal and the semiconductor, and can effectively alleviate the problem of Fermi level pinning caused by the formation of high surface states on the surface of the semiconductor due to the increase in the acceptor density when the semiconductor is overdoped , the Fermi level pinning effect of the LTPO array substrate is improved, the electron mobility between the metal and the semiconductor is improved, and the display effect of the display panel is improved.
  • the present invention also provides a display device, which includes the array substrate described in any one of the above-mentioned embodiments.
  • the present application sets the area of the contact surface between the source-drain layer and the connecting segment larger than the area of the orthographic projection of the contact surface of the source-drain layer and the connecting segment on the substrate in the direction perpendicular to the substrate. , which effectively increases the contact area between the metal and the semiconductor, which can effectively alleviate the problem of Fermi level pinning caused by the formation of high surface states on the semiconductor surface due to the increase of the acceptor density when the semiconductor is overdoped, and improves the LTPO
  • the Fermi level pinning effect of the array substrate improves the electron mobility between the metal and the semiconductor, thereby improving the display effect of the display panel.

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Abstract

本申请公开了一种阵列基板及其制作方法、显示装置，阵列基板包括衬底、有源层、源漏极层、栅极绝缘层和栅极，有源层包括有源段和连接段，源漏极层设置于连接段上且与连接段接触连接；源漏极层与连接段的接触面的面积大于源漏极层与连接段的接触面在衬底上的正投影的面积。

Description

阵列基板及其制作方法、显示装置 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板及其制作方法、显示装置。
 背景技术
低温多晶氧化物（Low Temperature Polycrystalline Oxide，LPTO）与低温多晶硅（Low Temperature Poly-silicon，LTPS）性质类似，具有较高的电子迁移率，同时其还能够兼具氧化铟镓锌（Indium Gallium Zinc Oxide，IGZO）的优点，达到以低生产成本实现更高的电荷迁移率的效果，并为显示面板提供较强的稳定性和可扩展性。应用LTPO技术的显示屏可以大幅度降低刷新率，而不需要额外的器件，这样设备可以通过降低刷新率节省大量电量。
目前，半导体与金属接触时，多会形成势垒层，当半导体掺杂浓度到达一定程度时，电子可借隧道效应穿过势垒，理论上会形成低阻值的欧姆接触层。但掺杂具有反作用，掺杂过多时受体密度变大会形成高表面态半导体，造成费米能级钉扎效应。原本半导体中的费米能级是一个容易发生变化的参量。掺入施主杂质即可使费米能级移向导带底，半导体变成为n型半导体；掺入受主杂质可使费米能级移向价带顶，半导体就变成为p型半导体。但是，掺杂大量的施主或者受主后，过量掺杂的杂质不能被激活，也不能提供载流子，因此也不能改变费米能级的位置，这种情况即产生费米能级钉扎。这一效应将极大降低金属与半导体之间的电子迁移率，从而弱化显示面板的显示效果。
 技术问题
本申请实施例提供一种用于显示模组的调光层及显示模组，以解决LTPO阵列基板掺杂过多时,受体密度变大会形成高表面态半导体形成费米能级钉扎效应的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，包括
衬底；
有源层，设置于所述衬底上，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
源漏极层，设置于所述连接段上且与所述连接段接触连接；
其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
在本申请的阵列基板中，所述连接段与所述源漏极层相接触的接触面包括至少一第一凸部，所述源漏极层上包括与所述第一凸部相配合的第一凹部。
在本申请的阵列基板中，所述有源层与所述衬底之间设有一支撑层，所述支撑层在对应所述第一凸部的位置设有与所述第一凸部相匹配的支撑凸起。
在本申请的阵列基板中，所述支撑层的材料为氧化硅和氮化硅中的任一种。
在本申请的阵列基板中，所述有源层上与所述源漏极层相接触的接触面包括至少一第二凹部，所述源漏极层上包括与所述第二凹部相配合的第二凸部。
在本申请的阵列基板中，所述源漏极层上设置有绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层，所述绝缘层上形成有栅极槽，所述栅极槽内形成栅极层，所述绝缘层背离所述源漏极层的一侧面和所述栅极层背离所述源漏极层的一侧面共平面设置。
在本申请的阵列基板中，所述连接段包括分别与所述有源段连接的第一连接段和第二连接段，所述源漏极层包括设置于所述第一连接段上的源极和设置于所述第二连接段上的漏极，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底上的正投影的面积，和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底上的正投影的面积。
在本申请的阵列基板中，所述源漏极层包括氧化金属层和金属层，所述金属层通过所述氧化金属层连接所述连接段，所述氧化金属层与所述连接段的接触面的面积小于所述氧化金属层与所述源漏极层的接触面的面积。
在本申请的阵列基板中，所述氧化金属层的厚度小于5nm，所述氧化金属层的材质为氧化钛、氧化钴或氧化镍中的一种。
本申请还提供一种阵列基板的制作方法，包括以下步骤：
形成衬底；
在所述衬底上形成有源层，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
在所述连接段上形成源漏极层，所述源漏极层与所述连接段接触连接；
其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
本申请还提供一种显示装置，包括阵列基板，所述阵列基板包括：
衬底；
有源层，设置于所述衬底上，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
源漏极层，设置于所述连接段上且与所述连接段接触连接；
其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
在本申请的显示装置中，所述连接段与所述源漏极层相接触的接触面包括至少一第一凸部，所述源漏极层上包括与所述第一凸部相配合的第一凹部。
在本申请的显示装置中，所述有源层与所述衬底之间设有一支撑层，所述支撑层在对应所述第一凸部的位置设有与所述第一凸部相匹配的支撑凸起。
在本申请的显示装置中，所述支撑层的材料为氧化硅和氮化硅中的任一种。
在本申请的显示装置中，所述有源层上与所述源漏极层相接触的接触面包括至少一第二凹部，所述源漏极层上包括与所述第二凹部相配合的第二凸部。
在本申请的显示装置中，所述源漏极层上设置有绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层，所述绝缘层上形成有栅极槽，所述栅极槽内形成栅极层，所述绝缘层背离所述源漏极层的一侧面和所述栅极层背离所述源漏极层的一侧面共平面设置。
在本申请的显示装置中，所述连接段包括分别与所述有源段连接的第一连接段和第二连接段，所述源漏极层包括设置于所述第一连接段上的源极和设置于所述第二连接段上的漏极，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底上的正投影的面积，和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底上的正投影的面积。
在本申请的显示装置中，所述源漏极层包括氧化金属层和金属层，所述金属层通过所述氧化金属层连接所述连接段，所述氧化金属层与所述连接段的接触面的面积小于所述氧化金属层与所述源漏极层的接触面的面积。
在本申请的显示装置中，所述氧化金属层的厚度小于5nm，所述氧化金属层的材质为氧化钛、氧化钴或氧化镍中的一种。
在本申请的显示装置中，所述氧化金属层的材质为氧化镍。
 有益效果
本申请在垂直阵列基板方向上，依次设置有源层和源漏极层，源漏极层连接有源层的连接段，设置源漏极层与连接段的接触面的面积大于源漏极层与连接段的接触面在衬底上的正投影的面积，有效增大了金属与半导体之间的接触面积，能有效缓解因半导体掺杂过多时，受体密度变大，在半导体表面形成高表面态产生费米能级钉扎的问题，改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
 附图说明
图1是本申请实施例提供的阵列基板的结构示意图；
图2是本申请另一实施例提供的阵列基板的结构示意图；
图3是本申请一实施例提供的阵列基板中连接段包括多个第一凸部的结构示意图；
图4是本申请一实施例提供的阵列基板中连接段包括第一凸部和第二凹部的结构示意图；
图5是本申请另一实施例提供的阵列基板的结构示意图；
图6是本申请另一实施例提供的源漏极层包含氧化金属层的阵列基板的结构示意图；
图7是本申请一实施例提供的阵列基板的制作流程示意图；
图8是本申请另一实施例提供的阵列基板的制作流程示意图；
图9是本申请一实施例提供的阵列基板的制作流程图。
 本发明的实施方式
本申请提供一种阵列基板、阵列基板的制作方法及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种阵列基板、阵列基板的制作方法及显示装置。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
目前，半导体与金属接触时，多会形成势垒层，当半导体掺杂浓度到达一定程度时，电子可借隧道效应穿过势垒，理论上会形成低阻值的欧姆接触层。
但是，掺杂具有反作用，掺杂过多时受体密度变大会形成高表面态半导体，造成费米能级钉扎效应。原本半导体中的费米能级是一个容易发生变化的参量。掺入施主杂质即可使费米能级移向导带底，半导体变成为n型半导体；掺入受主杂质可使费米能级移向价带顶，半导体就变成为p型半导体。但是，掺杂大量的施主或者受主后，过量掺杂的杂质不能被激活，也不能提供载流子，因此也不能改变费米能级的位置，这种情况即产生费米能级钉扎。这一效应将极大降低金属与半导体之间的电子迁移率，从而弱化显示面板的显示效果。
本发明为了解决上述技术问题，提供了一种阵列基板，如图1所示，包括：
衬底100；
有源层，设置于所述衬底100上，所述有源层包括有源段和设置于所述有源段至少一侧的连接段201；
源漏极层202，设置于所述连接段201上且与所述连接段201接触连接；
其中，所述源漏极层202与所述连接段201的接触面的面积大于所述源漏极层202与所述连接段201的接触面在所述衬底100上的正投影的面积。
具体地，所述衬底100包括基底101和设置在基底101上的缓冲层102，所述有源层包括有源段和设置于所述有源段至少一侧的连接段201，所述连接段201可以有两段，两连接段201可以分别设置于所述有源段的两侧，也可以设置于所述有源段的同一侧，所述有源段的材质可以为半导体材料，具体可以为低温多晶硅材质，该半导体材质可以参杂施主杂质形成n型半导体，也可以参杂受主杂质形成为p型半导体。
具体地，所述有源段上还形成有沟道，所述沟道内填充金属氧化物，所述金属氧化物可以为IGZO。
具体地，所述有源层可以采用化学气相沉积成膜的方式形成，在得到成膜后的半导体层后，再进行离子植入的方式得到参杂的半导体连接段201，再进行物理气相沉积成膜形成氧化物层，通过刻蚀氧化物层形成场氧204。
具体地，所述有源层上形成的源漏极层202具体可以为金属材质，所述源漏极层202可以包括源极和漏极，所述源极连接一有源层上的连接段201，所述漏极连接另一有源层上的连接段201，所述源极和所述漏极可以采用同种金属也可以采用不同种金属。
具体地，如图5所示，所述有源层上可以形成一介电层303，所述介电层303上形成源漏极层202，介电层303上对应的所述连接段201的位置开设过孔，所述源漏极层202通过所述过孔与所述连接段201连接。
具体地，所述源漏极层202与所述连接段201的接触面的面积大于所述源漏极层202与所述连接段201的接触面在所述衬底100上的正投影的面积，可以理解为所述源漏极与所述连接段201的接触面为具有弧度的起伏的曲面，其接触面的截面可以为锯齿形，可以为波浪形，也可以为阶梯状结构，只要能够增大源漏极层202与连接段201的接触面的面积即在本申请的保护范围内。
具体地，所述阵列基板还包括栅极层，所述栅极层可以设置在所述有源层下方，也可以设置在所述有源层的上方，所述栅极层和所述有源层之间通过栅极绝缘层301间隔设置。
可以理解的是，在垂直阵列基板方向上，通过设置源漏极层202与连接段201的接触面的面积大于源漏极层202与连接段201的接触面在衬底100上的正投影的面积，有效增大了金属与半导体之间的接触面积，能有效缓解因半导体掺杂过多时，受体密度变大，在半导体表面形成高表面态产生费米能级钉扎的问题，改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
在一实施例中，如图1所示，所述连接段201与所述源漏极层202相接触的接触面包括至少一第一凸部201a，所述源漏极层202上包括与所述第一凸部201a相配合的第一凹部。
具体地，所述第一凸部201a的数量不作限制，可以有一个也可以有多个，所述第一凸部201a的高度也不作限制，可以为具有相同的高度，也可以具有不同的高度，所述第一凸部201a的形状不做限制，其截面可以为具有一定弧度的半椭圆形，也可以为方形，只要能够使得源漏极层202与连接段201的接触面积增大的方案，均在本申请的保护范围内。
具体地，所述第一凸部201a可以设置在所述连接段201与所述源漏极层202连接的一侧面上，对应的所述源漏极层202上则为与该第一凸部201a相匹配的第一凹部；所述第一凸部201a也可以设置在所述源漏极层202与所述连接段201连接的一侧面上，对应的所述连接段201上则为与该第一凸部201a相匹配的第一凹部。
可以理解的是，将连接段201与所述源漏极层202相接触的接触面包括至少一第一凸部201a，所述源漏极层202上包括与所述第一凸部201a相配合的第一凹部，如图3所示，图3为所述连接段201与所述源漏极层202相接触的接触面包括两个第一凸部201a的实施例，使得在进行阵列基板制作时，制作工序更简单，降低生产难度。
在一实施例中，如图2所示，所述有源层与所述衬底100之间设有一支撑层203，所述支撑层203在对应所述第一凸部201a的位置设有与所述第一凸部201a相匹配的支撑凸起203a。
具体地，所述支撑层203设置在所述有源层和所述衬底100之间，具体为所述第一凸部201a设置在所述连接段201上时，此时，所述连接段201上没有凹部，均为第一凸部201a，在所述支撑层203对应所述第一凹部的位置形成支撑凸起203a，该支撑凸起203a的形状与所述第一凸起类似，此时所述支撑凸起203a上的有源层的厚度相等，所述支撑层203的材料为绝缘材料，可以为氧化硅、氮化硅等中的一种。
可以理解的是，通过设置支撑层203，支撑层203的材料相比较有源层的材料更容易进行刻蚀和塑形操作，而且生产成本低，在形成具有支撑凸起203a的支撑层203后，在支撑层203上对应位置形成有源层的连接段201，可以理解为所述连接段201覆盖在所述支撑层203的支撑凸起203a上，采用该方案，在工业生产上更容易形成具有曲面的有源层，而且在生产上更加实用，生产成本低，相较普通的阵列基板的生产工艺而言增加的步骤少，离子的导通率更高。
在一实施例中，如图4所示，所述有源层上与所述源漏极层202相接触的接触面包括至少一第二凹部201b，所述源漏极层202上包括与所述第二凹部201b相配合的第二凸部。
可以理解的是，在所述有源层上与所述源漏极层202相接触的接触面还包括第二凹部201b，可以理解为所述连接段201上与所述源漏极层202的接触面上既有第一凸部201a，又有第二凹部201b，相比只设置第一凸部201a而言，进一步增大了有源层与源漏极层202的接触面积，进一步改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
在一实施例中，如图1所示，所述源漏极层202上设置有绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层202，所述绝缘层上形成有栅极槽，所述栅极槽内形成栅极层，所述绝缘层背离所述源漏极层202的一侧面和所述栅极层背离所述源漏极层202的一侧面共平面设置。
可以理解的是，在本技术方案中，该阵列基板的结构为顶栅结构，其中，栅极302位于有源层的上方，所述绝缘层为栅极绝缘层301，设置栅极绝缘层301使得其上表面呈平面状态，使得栅极绝缘层301既起到平坦的作用，又起到了栅极绝缘层301的作用，进一步降低了阵列基板的厚度。
在一实施例中，所述连接段201包括分别与所述有源段连接的第一连接段和第二连接段，所述源漏极层202包括设置于所述第一连接段上的源极和设置于所述第二连接段上的漏极，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底100上的正投影的面积，和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底100上的正投影的面积。
具体地，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底100上的正投影的面积，即所述第一连接段上可以设置有至少一个第一子凸部，对应的所述源极上设置有与所述第一子凸部相对应的第一子凹部；和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底100上的正投影的面积，即所述第二连接段上可以设置有至少一个第二子凸部；对应的所述漏极上设置有与所述第二子凸部相对应的第二子凹部。
可以理解的是，可以单独在所述第一连接段上设置第一子凸部，也可以单独在所述第二连接段上设置第二子凸部，或者在所述第一连接段上设置第一子凸部和所述第二连接段上设置第二子凸部，采用上述技术方案，进一步有效增大了金属与半导体之间的接触面积，能有效缓解因半导体掺杂过多时，受体密度变大，在半导体表面形成高表面态产生费米能级钉扎的问题，改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
在一实施例中，如图6所示，所述源漏极层202包括氧化金属层205和金属层，所述金属层通过所述氧化金属层205连接所述连接段201，所述氧化金属层205与所述连接段201的接触面的面积小于所述氧化金属层205与所述源漏极层202的接触面的面积。
具体地，所述氧化金属层205的材料可以为氧化钛，所述氧化金属层205的材料还可以为氧化钴或氧化镍。
可以理解的是，所述氧化金属层205具有较低的导带带阶，因此所述氧化金属层205能够有效的降低有源层的连接段201禁带中的态密度，从而能够有效的减少金属诱导间隙态现象的出现，能够有效的抑制源漏极层202与有源层连接段201的界面处费米能级钉扎的现象，从而有利于降低源漏极层202和有源层的连接段201之间的接触电阻，有利于提高所形成半导体结构的性能。
在一实施例中，所述氧化金属层205的厚度小于5nm，所述氧化金属层205的材质为氧化钛、氧化钴或氧化镍中的一种。
具体地，由于所述氧化金属层205的厚度较小，因此电子能够在氧化金属层205内发生隧穿效应，从而使所述氧化金属层205起到改善源漏极层202与有源层连接段201的界面性能的作用，而不影响源漏极层202与有源层连接段201之间的导电性能，有效的抑制插塞与源漏掺杂区界面处费米能级钉扎的现象，有利于降低所述插塞和所述源漏掺杂区之间的接触电阻，有利于提高所形成半导体结构的性能。
本申请还提供一种阵列基板的制作方法，如图7和图9所示，包括以下步骤：
S1、形成衬底100；
S2、在所述衬底100上形成有源层，所述有源层包括有源段和设置于所述有源段至少一侧的连接段201；
S3、在所述连接段201上形成源漏极层202，所述源漏极层202与所述连接段201接触连接；其中，所述源漏极层202与所述连接段201的接触面的面积大于所述源漏极层202与所述连接段201的接触面在所述衬底100上的正投影的面积。
具体地，在所述源漏极层202上还形成有栅极绝缘层301，在所述栅极绝缘层301上形成有栅极302，可以形成顶栅结构。
具体地，针对图7制作流程图进行说明：
如图7中的（a）所示，形成衬底100；
如图7中的（b）所示，在所述衬底100上形成有源层，所述有源层包括有源段和设置于所述有源段至少一侧的连接段201；
如图7中的（c）所示，在所述连接段201上形成源漏极层202，所述源漏极层202与所述连接段201接触连接；其中，所述源漏极层202与所述连接段201的接触面的面积大于所述源漏极层202与所述连接段201的接触面在所述衬底100上的正投影的面积；
具体地，如图7中的（d）所示，在所述源漏极层202上还形成有栅极绝缘层301，在所述栅极绝缘层301上形成有栅极302，可以形成顶栅结构。
在另一实施例中，所述阵列基板的制作方法，如图8所示，包括如下步骤：
如图8中（a）所示，形成衬底100，所述衬底100包括基底101和设置在基底101上的缓冲层102，可以采用聚酰亚胺树脂涂布形成基底101，采用化学气相沉积成膜的手段形成缓冲层102。
如图8中（b）所示，形成一层支撑层203，支撑层203的材料可以为氮化硅，所述支撑层203上对应有源层连接段201的位置设置支撑凸起203a;
如图8中（c）所示，在所述支撑层203和所述衬底100上形成有源层，所述有源层包括有源段和设置于所述有源段至少一侧的连接段201；其中，所述连接段201可以有两段，两连接段201可以分别设置于所述有源段的两侧，在有源层形成之前先对半导体材料进行离子注入，进行参杂操作，然后在支撑层203上沉积参杂后的半导体，在参杂后的半导体层上进行刻蚀形成氧化物沟道，在所述氧化物沟道内沉积形成场氧204。
如图8中（d）所示,在所述连接段201上形成源漏极层202，所述源漏极层202与所述连接段201接触连接；其中，所述源漏极层202与所述连接段201的接触面的面积大于所述源漏极层202与所述连接段201的接触面在所述衬底100上的正投影的面积。
具体地，如图8中（e）所示,还可以在所述源漏极上方形成绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层202，所述绝缘层上形成栅极层，在所述栅极层上形成覆盖所述栅极层和所述绝缘层的第二绝缘层。
可以理解的是，通过在垂直衬底100的方向上，通过设置源漏极层202与连接段201的接触面的面积大于源漏极层202与连接段201的接触面在衬底100上的正投影的面积，有效增大了金属与半导体之间的接触面积，能有效缓解因半导体掺杂过多时，受体密度变大，在半导体表面形成高表面态产生费米能级钉扎的问题，改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
本发明还提供了一种显示装置，所述显示装置中包括采用上述任一实施例所述的阵列基板。
综上所述，本申请通过在垂直衬底的方向上，通过设置源漏极层与连接段的接触面的面积大于源漏极层与连接段的接触面在衬底上的正投影的面积，有效增大了金属与半导体之间的接触面积，能有效缓解因半导体掺杂过多时，受体密度变大，在半导体表面形成高表面态产生费米能级钉扎的问题，改善了LTPO阵列基板的费米能级钉扎效应，提高了金属与半导体之间的电子迁移率，进而提升了显示面板的显示效果。
以上对本申请实施例所提供的一种阵列基板及其制作方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，包括
    衬底；
    有源层，设置于所述衬底上，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
    源漏极层，设置于所述连接段上且与所述连接段接触连接；
    其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
  2. 如权利要求1所述的阵列基板，其中，所述连接段与所述源漏极层相接触的接触面包括至少一第一凸部，所述源漏极层上包括与所述第一凸部相配合的第一凹部。
  3. 如权利要求2所述的阵列基板，其中，所述有源层与所述衬底之间设有一支撑层，所述支撑层在对应所述第一凸部的位置设有与所述第一凸部相匹配的支撑凸起。
  4. 如权利要求3所述的阵列基板，其中，所述支撑层的材料为氧化硅和氮化硅中的任一种。
  5. 如权利要求2所述的阵列基板，其中，所述有源层上与所述源漏极层相接触的接触面包括至少一第二凹部，所述源漏极层上包括与所述第二凹部相配合的第二凸部。
  6. 如权利要求2所述的阵列基板，其中，所述源漏极层上设置有绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层，所述绝缘层上形成有栅极槽，所述栅极槽内形成栅极层，所述绝缘层背离所述源漏极层的一侧面和所述栅极层背离所述源漏极层的一侧面共平面设置。
  7. 如权利要求1所述的阵列基板，其中，所述连接段包括分别与所述有源段连接的第一连接段和第二连接段，所述源漏极层包括设置于所述第一连接段上的源极和设置于所述第二连接段上的漏极，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底上的正投影的面积，和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底上的正投影的面积。
  8. 如权利要求1所述的阵列基板，其中，所述源漏极层包括氧化金属层和金属层，所述金属层通过所述氧化金属层连接所述连接段，所述氧化金属层与所述连接段的接触面的面积小于所述氧化金属层与所述源漏极层的接触面的面积。
  9. 如权利要求8所述的阵列基板，其中，所述氧化金属层的厚度小于5nm，所述氧化金属层的材质为氧化钛、氧化钴或氧化镍中的一种。
  10. 一种阵列基板的制作方法，其中，包括以下步骤：
    形成衬底；
    在所述衬底上形成有源层，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
    在所述连接段上形成源漏极层，所述源漏极层与所述连接段接触连接；
    其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
  11. 一种显示装置，其中，包括阵列基板，所述阵列基板包括：
    衬底；
    有源层，设置于所述衬底上，所述有源层包括有源段和设置于所述有源段至少一侧的连接段；
    源漏极层，设置于所述连接段上且与所述连接段接触连接；
    其中，所述源漏极层与所述连接段的接触面的面积大于所述源漏极层与所述连接段的接触面在所述衬底上的正投影的面积。
  12. 如权利要求11所述的显示装置，其中，所述连接段与所述源漏极层相接触的接触面包括至少一第一凸部，所述源漏极层上包括与所述第一凸部相配合的第一凹部。
  13. 如权利要求12所述的显示装置，其中，所述有源层与所述衬底之间设有一支撑层，所述支撑层在对应所述第一凸部的位置设有与所述第一凸部相匹配的支撑凸起。
  14. 如权利要求13所述的显示装置，其中，所述支撑层的材料为氧化硅和氮化硅中的任一种。
  15. 如权利要求12所述的显示装置，其中，所述有源层上与所述源漏极层相接触的接触面包括至少一第二凹部，所述源漏极层上包括与所述第二凹部相配合的第二凸部。
  16. 如权利要求11所述的显示装置，其中，所述源漏极层上设置有绝缘层，所述绝缘层覆盖所述有源层和所述源漏极层，所述绝缘层上形成有栅极槽，所述栅极槽内形成栅极层，所述绝缘层背离所述源漏极层的一侧面和所述栅极层背离所述源漏极层的一侧面共平面设置。
  17. 如权利要求11所述的显示装置，其中，所述连接段包括分别与所述有源段连接的第一连接段和第二连接段，所述源漏极层包括设置于所述第一连接段上的源极和设置于所述第二连接段上的漏极，所述源极与所述第一连接段的接触面积大于所述源极与所述第一连接段的接触面在所述衬底上的正投影的面积，和/或所述漏极与所述第二连接段的接触面积大于所述漏极与所述第二连接段的接触面在所述衬底上的正投影的面积。
  18. 如权利要求11所述的显示装置，其中，所述源漏极层包括氧化金属层和金属层，所述金属层通过所述氧化金属层连接所述连接段，所述氧化金属层与所述连接段的接触面的面积小于所述氧化金属层与所述源漏极层的接触面的面积。
  19. 如权利要求18所述的显示装置，其中，所述氧化金属层的厚度小于5nm，所述氧化金属层的材质为氧化钛、氧化钴或氧化镍中的一种。
  20. 如权利要求19所述的显示装置，其中，所述氧化金属层的材质为氧化镍。
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