WO2023010808A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023010808A1
WO2023010808A1 PCT/CN2022/070591 CN2022070591W WO2023010808A1 WO 2023010808 A1 WO2023010808 A1 WO 2023010808A1 CN 2022070591 W CN2022070591 W CN 2022070591W WO 2023010808 A1 WO2023010808 A1 WO 2023010808A1
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Prior art keywords
layer
barrier layer
substrate
trench
semiconductor structure
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English (en)
French (fr)
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申松梅
张俊逸
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/156,470 priority Critical patent/US12506031B2/en
Publication of WO2023010808A1 publication Critical patent/WO2023010808A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof.
  • adjacent wires 80 and the insulating material 97 between the wires 80 form a parasitic capacitance, which is proportional to the dielectric constant of the insulating material 97 and inversely proportional to the distance between the two wires 80 .
  • the parasitic capacitance increases continuously, which in turn causes capacitance-resistance delay (RC delay) of electrical signals on the chip and affects the operating frequency of the chip.
  • insulating materials of low dielectric constant (low-k) materials are usually used to reduce parasitic capacitance.
  • the insulating material of low dielectric constant material is prone to over-etching phenomenon, the electrical performance of the semiconductor structure is poor, and the stability of the semiconductor structure is poor.
  • embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to reduce the parasitic capacitance of the semiconductor structure and improve the electrical performance and stability of the semiconductor structure.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, which includes: forming a support layer on a substrate, and forming a first dielectric layer on the support layer, the support layer and the first A first groove is formed in the dielectric layer, and the first groove exposes the substrate;
  • first barrier layer covering the sidewalls and bottom of the first trench, and the top surface of the first dielectric layer
  • a wire is formed in the first trench, and the wire is electrically connected to the substrate.
  • the first barrier layer and the second barrier layer form the top wall and side wall of the cavity by utilizing the dielectric constant of air
  • the dielectric constant of the first dielectric layer is lower than that of the first dielectric layer, so as to reduce the dielectric constant of the structure between the wires, thereby reducing the parasitic capacitance between the wires, thereby improving the electrical performance of the semiconductor structure.
  • the bottom of the cavity is a support layer, and the support layer supports the first barrier layer and the second barrier layer on it. On the basis of ensuring the height of the wire, the depth of the cavity is reduced, thereby reducing the thickness of the first barrier layer. and the risk of collapse of the second barrier layer, thereby improving the stability of the semiconductor structure.
  • an embodiment of the present application provides a semiconductor structure, which includes: a substrate, and a support structure disposed on the substrate, the support structure is provided with a plurality of accommodation grooves passing through the support structure, each Each of the accommodating grooves is filled with wires, and the wires are electrically connected to the substrate; wherein, the support structure located between adjacent wires includes: a support layer, and the support layer is arranged on the On the substrate; the first barrier layer is buckled outside the support layer, the first barrier layer and the support layer form a cavity, the inner sidewall of the first barrier layer and the outer sidewall of the support layer and the first barrier layer is provided with a first etching hole communicating with the cavity; the second barrier layer is buckled outside the first barrier layer, and the inside of the second barrier layer The surface is attached to the outer surface of the first barrier layer.
  • a closed cavity is provided in the support structure between adjacent wires, and the first barrier layer and the second barrier layer form the side wall and the top wall of the cavity, and the air is used as an intermediary.
  • the electrical constant is 1, so as to reduce the dielectric constant of the structure between the wires, thereby reducing the parasitic capacitance between the wires, thereby improving the electrical performance of the semiconductor structure.
  • the bottom of the cavity is a support layer, and the support layer supports the first barrier layer and the second barrier layer on it. On the basis of ensuring the height of the wire, the depth of the cavity is reduced, thereby reducing the thickness of the first barrier layer. and the risk of collapse of the second barrier layer, thereby improving the stability of the semiconductor structure.
  • the supporting layer is further provided with a second etching hole facing and matching the first etching hole.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram after forming a first trench in an embodiment of the present application.
  • FIG. 4 is a schematic structural view after forming the first barrier layer in the embodiment of the present application.
  • FIG. 5 is a schematic structural view after forming an etching hole in an embodiment of the present application.
  • FIG. 6 is a schematic structural view after forming a second photoresist layer in the embodiment of the present application.
  • FIG. 7 is a schematic structural view of a cavity formed in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a structure after forming a second barrier layer in an embodiment of the present application.
  • FIG. 9 is a schematic structural view after removing part of the first barrier layer in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of a structure after forming a conductive layer in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a conductive layer in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure after forming an anti-reflection layer in the embodiment of the present application.
  • FIG. 13 is a schematic structural view after forming the first photoresist layer in the embodiment of the present application.
  • Fig. 14 is a schematic diagram of another structure after forming the second barrier layer in the embodiment of the present application.
  • FIG. 15 is a schematic structural view after forming a third photoresist layer in the embodiment of the present application.
  • Fig. 16 is a schematic structural diagram after removing part of the first barrier layer and part of the second barrier layer in the embodiment of the present application;
  • FIG. 17 is another structural schematic diagram after forming a conductive layer in the embodiment of the present application.
  • FIG. 18 is a schematic diagram of the structure after the wires are formed in the embodiment of the present application.
  • the embodiment of the present application provides a method for manufacturing a semiconductor structure.
  • the electrical constant is 1, which reduces the dielectric constant of the structure between the wires, thereby reducing the parasitic capacitance between the wires, thereby improving the electrical performance of the semiconductor structure.
  • the bottom of the cavity is a support layer, and the support layer supports the first barrier layer and the second barrier layer on it. On the basis of ensuring the height of the wire, the depth of the cavity is reduced, thereby reducing the thickness of the first barrier layer. and the risk of collapse of the second barrier layer, thereby improving the stability of the semiconductor structure.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, which includes the following steps:
  • Step S101 forming a support layer on the substrate, and forming a first dielectric layer on the support layer, a first groove is formed in the support layer and the first dielectric layer, and the first groove exposes the substrate.
  • the substrate 10 provides support, and its material can be semiconductors such as silicon, germanium, silicon germanium, silicon carbide, silicon on insulator (Silicon on Insulator, SOI for short) or germanium on insulator (Germanium on Insulator, GOI for short). one or more of the materials.
  • Semiconductor devices (not shown in the figure) are usually arranged on the substrate 10 to realize specific functions.
  • the semiconductor device may include one or more of resistors, capacitors, diodes, triodes, field effect transistors (Field Effect Transistor, FET for short), fuses or wires.
  • the support layer 20 is formed on the substrate 10 .
  • the support layer 20 is formed on the substrate 10 through chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PCD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD) and other deposition processes , so that the formed supporting layer 20 has good density and flatness.
  • CVD chemical Vapor Deposition
  • PCD Physical vapor deposition
  • ALD atomic layer deposition
  • the first dielectric layer 30 is formed on the supporting layer 20 .
  • the first dielectric layer 30 may be formed on the supporting layer 20 through a deposition process.
  • the first dielectric layer 30 and the supporting layer 20 may have a larger selection ratio, for example, the selection ratio of the first dielectric layer 30 and the supporting layer 20 is greater than or equal to 2. So arranged, when the first dielectric layer 30 is subsequently removed, the support layer 20 can also be used as an etch stop layer (Etch Stop Layer), to prevent damage to the substrate 10 and/or the substrate 10 when the first dielectric layer 30 is etched. semiconductor devices.
  • Etch Stop Layer etch stop Layer
  • a first trench 40 is formed in the support layer 20 and the first dielectric layer 30, as shown in FIG. Lead wires 80 are subsequently formed within 40 (see FIG. 18 ). It can be understood that the sum of the thickness of the support layer 20 and the thickness of the first dielectric layer 30 is the height of the wire 80, and the first dielectric layer 30 will be removed later, and the cavity 60 will be formed in this region, and the cavity 60
  • the dielectric constant of air is 1, and its dielectric constant is the lowest, so as to reduce the parasitic capacitance between the two wires 80 .
  • the dielectric constant of the support layer 20 can be less than the dielectric constant of the first dielectric layer 30, and the support layer 20 with a lower dielectric constant can be used to replace part of the first dielectric layer 30, which can further reduce the dielectric constant of the support layer 20 and the first dielectric layer 30.
  • the first dielectric layer 30 may be a silicon oxide layer
  • the support layer 20 may be a hydrosilicate polymer layer or a porous silicide layer or the like.
  • the dielectric constant of the support layer 20 can also be greater than or equal to the dielectric constant of the first dielectric layer 30, at this time, by adjusting the thickness of the support layer 20 and the thickness of the first dielectric layer 30, to reduce the support layer 20 and subsequent The overall dielectric constant of the cavity 60 formed.
  • the first dielectric layer 30 is a silicon oxide layer
  • the supporting layer 20 is a silicon nitride layer or a silicon oxynitride layer
  • the ratio of the thickness of the first dielectric layer 30 to the thickness of the supporting layer 20 is greater than or equal to 2
  • the first dielectric layer The ratio of the thickness of layer 30 to the thickness of support layer 20 is equal to three.
  • the above-mentioned silicon oxide layer can be formed by decomposing and depositing orthoethyl silicate (TEOS), and the above-mentioned silicon oxynitride layer can be formed by nitriding the silicon nitride layer.
  • TEOS orthoethyl silicate
  • Step S102 forming a first barrier layer, the first barrier layer covers the sidewall and bottom of the first trench, and the top surface of the first dielectric layer.
  • the first barrier layer 50 is deposited on the sidewall 41 and bottom 42 of the first trench 40 and the top surface of the first dielectric layer 30 .
  • the top surface of the first dielectric layer 30 refers to the surface of the first dielectric layer 30 facing away from the substrate 10 , that is, the upper surface of the first dielectric layer 30 shown in FIG. 4 .
  • Step S103 etching the first barrier layer and the first dielectric layer to form etching holes.
  • the etching hole 51 penetrates the first barrier layer 50 and extends into the first dielectric layer 30, so as to increase the exposed surface area of the first dielectric layer 30 in the etching hole 51, thereby facilitating subsequent removal of the first dielectric layer 30.
  • the etching hole 51 penetrates through the first dielectric layer 30 .
  • the etching hole 51 may also extend into the supporting layer 20 , that is, the bottom of the etching hole 51 is located in the supporting layer 20 . With such an arrangement, an air gap is formed in the support layer 20 , which can reduce the dielectric constant of the support layer 20 and further reduce the RC delay in the semiconductor structure.
  • the width of the etching hole 51 may be 3-5nm, wherein the width direction of the etching hole 51 is the same as the width direction of the first trench 40, such as the horizontal direction (X direction) as shown in FIG. 5 .
  • the etched hole 51 in the first barrier layer 50 is conveniently sealed by the second barrier layer 70 , which can reduce the sealing material falling into the etched hole 51 during the sealing process, thereby ensuring the effect of reducing the RC delay of the cavity.
  • the step of etching the first barrier layer 50 and the first dielectric layer 30 to form the etching hole 51 includes:
  • a second photoresist layer 94 is formed on the first barrier layer 50 and in the first trench 40, the second photoresist layer 94 fills the first trench 40 and covers the surface of the first barrier layer 50 facing away from the substrate 10 . As shown in FIGS. 5 and 6 , the sidewall 41 and the bottom 42 of the first trench 40 are covered with the first barrier layer 50 , and the second photoresist layer 94 is filled in the area enclosed by the first barrier layer 50 , And cover the top surface of the first barrier layer 50 .
  • the second photoresist layer 94 is a patterned second photoresist layer 94 , and the top surface of the second photoresist layer 94 may be flush, that is, the surface of the second photoresist layer 94 facing away from the substrate 10 is plane.
  • the first barrier layer 50 and the first dielectric layer 30 are etched using the second photoresist layer 94 as a mask to form etching holes 51 .
  • the regions not covered by the second photoresist layer 94 in the first barrier layer 50 and the first dielectric layer 30 are removed, and the etching stops at the surface of the support layer 20 away from the substrate 10 or the support layer 20 middle. Dry etching may be used during etching, and the etching gas includes fluorine-containing gas, oxygen and inert gas (such as nitrogen or argon).
  • the second photoresist layer 94 is removed.
  • the second photoresist layer 94 can be removed through an ashing process, and after the second photoresist layer 94 is removed, the first barrier layer 50 is exposed.
  • Step S104 removing the first dielectric layer exposed in the etching hole to form a cavity.
  • a cavity 60 is formed in the area surrounded by the first barrier layer 50 and the supporting layer 20 , and the etching hole 51 in the first barrier layer 50 communicates with the cavity 60 .
  • the first dielectric layer 30 exposed in the etching hole 51 is removed by dry etching or wet etching, and the first dielectric layer 30 is reacted with the etching solution or etching gas, so that the first dielectric layer Layer 30 is removed.
  • the material of the first dielectric layer 30 is silicon oxide
  • the etching gas may include fluorine-containing gas such as octafluorocyclobutane (C 4 F 8 )
  • the etching solution may include dilute hydrofluoric acid (Dilute Hydrofluoric Acid, referred to as DHF).
  • Step S105 forming a second barrier layer on the first barrier layer, and the second barrier layer closes the etching hole at the top of the cavity.
  • the second barrier layer 70 is deposited on the first barrier layer 50 , and the process parameters of the second barrier layer 70 , such as deposition rate or temperature, are controlled so that the second barrier layer 70 closes the etching hole 51 .
  • the second barrier layer 70 may only cover the surface of the first barrier layer 50 away from the substrate 10 .
  • the second barrier layer 70 may also cover the first barrier layer 50 located in the first trench 40 .
  • the materials of the first barrier layer 50, the second barrier layer 70 and the support layer 20 can be the same, so that the first barrier layer 50, the second barrier layer 70 and the support layer 20 form an integrated structure, preventing the support layer 20 from Delamination occurs in areas in contact with the first barrier layer 50 , the first barrier layer 50 and the second barrier layer 70 .
  • the materials of the first barrier layer 50 , the second barrier layer 70 and the supporting layer 20 are all silicon nitride.
  • Step S106 removing part of the first barrier layer in the first trench, so that the first trench exposes the substrate.
  • the substrate 10 is exposed, so that the wire 80 subsequently formed in the first trench 40 can be in contact with the substrate 10 to realize electrical contact. connect.
  • the first barrier layer 50 on the bottom 42 of the first trench 40 is removed by anisotropic etching, and the first barrier layer 50 on the sidewall of the first trench 40 remains.
  • Step S107 forming wires in the first trench, and electrically connecting the wires to the substrate.
  • wires are formed in the first trench 40 and electrically connected to the substrate 10 to electrically connect the substrate 10 to other film layers, so as to transmit electrical signals along a direction perpendicular to the substrate 10 .
  • forming a wire in the first trench 40, and the step of electrically connecting the wire to the substrate 10 includes:
  • a conductive layer 81 is deposited in the first trench 40 , the conductive layer 81 fills the first trench 40 and covers the top surface of the second barrier layer 70 .
  • the conductive layer 81 includes a third barrier layer 82 and a conductive material layer 83 that are laminated, and the third barrier layer 82 is located on a side of the conductive layer 81 close to the substrate 10 .
  • the third barrier layer 82 is used to reduce or prevent the conductive material layer 83 from diffusing into the first barrier layer 50 , the second barrier layer 70 , the supporting layer 20 and the substrate 10 .
  • the third barrier layer 82 includes one or more layers of a titanium layer, a titanium nitride layer, a tantalum layer or a tantalum nitride layer.
  • the conductive material layer 83 may be a copper layer or a tungsten layer or the like.
  • the formation process of the conductive layer 81 in the embodiment of the present application is not limited, for example, the conductive layer 81 may also be formed by an electroplating process.
  • the conductive layer 81 on the second barrier layer 70 is removed, and the remaining conductive layer 81 forms a wire.
  • the conductive layer 81 located on the second barrier layer 70 is removed by planarizing the surface of the conductive layer 81 away from the substrate 10 . Specifically, chemical mechanical polishing (CMP) is performed on the top surface of the conductive layer 81 to expose the second barrier layer 70 .
  • CMP chemical mechanical polishing
  • the first barrier layer 50 and the second barrier layer 70 form the top wall and side walls of the cavity 60
  • the wall utilizes that the dielectric constant of the air is lower than that of the first dielectric layer 30 to reduce the dielectric constant of the structure between the wires, thereby reducing the parasitic capacitance between the wires, thereby improving the electrical performance of the semiconductor structure.
  • the bottom 42 of the cavity 60 is the support layer 20, and the support layer 20 supports the first barrier layer 50 and the second barrier layer 70 on it, and reduces the depth of the cavity 60 on the basis of ensuring the height of the wire. , increasing the contact area with the substrate 10 , thereby reducing the risk of collapse of the first barrier layer 50 and the second barrier layer 70 , thereby improving the stability of the semiconductor structure.
  • a first trench 40 are formed in the first dielectric layer 30, and the step of exposing the substrate 10 by the first trench 40 may include:
  • Step S1021 forming a supporting layer 20 , a first dielectric layer 30 , a hard mask layer 91 , an anti-reflection layer 92 and a first photoresist layer 93 on the substrate 10 in sequence.
  • a support layer 20 , a first dielectric layer 30 , a hard mask layer 91 , an anti-reflection layer 92 and a first photoresist layer 93 are formed on the substrate 10 .
  • the support layer 20, the first dielectric layer 30, the hard mask (Hard Mask) layer and the anti-reflection layer 92 can be formed by a deposition process.
  • the supporting layer 20 is deposited on the substrate 10
  • the first dielectric layer 30 is deposited on the supporting layer 20
  • the hard mask layer 91 is deposited on the first dielectric layer 30, and the hard mask layer 91 is formed on the hard mask layer 91.
  • the anti-reflection layer 92 is formed by deposition.
  • the first photoresist layer 93 can be formed by a patterning process, for example, the first photoresist layer 93 is formed on the antireflection layer 92 by a spin coating process; the first photoresist layer 93 is exposed and developed to expose part of the antireflection layer. layer 92, so that the first photoresist layer 93 is formed with a desired pattern.
  • the anti-reflection layer 92 is used to reduce the standing wave when the first photoresist layer 93 is exposed, and prevent light from being diffusely reflected at the bottom of the first photoresist layer 93, so as to ensure the accuracy of the pattern of the first photoresist layer 93 .
  • the hard mask layer 91 is used to transfer the pattern of the first photoresist layer 93 , and the material of the hard mask layer 91 is different from that of the antireflection layer 92 .
  • the material of the hard mask layer 91 is silicon nitride or silicon dioxide
  • the material of the anti-reflection layer 92 is silicon oxynitride
  • the material of the first photoresist layer 93 can be positive resist, or Can be negative glue.
  • Step S1022 using the first photoresist layer 93 as a mask to etch the anti-reflection layer 92 and the hard mask layer 91 .
  • the anti-reflection layer 92 and the hard mask layer 91 are anisotropically etched with etching gas.
  • the etching gas may include carbon tetrafluoride (CF 4 ), octafluorocyclobutane (C 4 F 8 ), or octafluorocyclopentene (C 5 F 8 ).
  • the first photoresist layer 93 is completely consumed and there is no residue. In some other possible examples, during the process of etching the anti-reflection layer 92 and the hard mask layer 91 , the first photoresist layer 93 is not completely consumed, but remains. At this time, the first photoresist layer 93 needs to be removed separately, for example, the remaining first photoresist layer 93 is removed by ashing or etching.
  • Step S1023 using the etched antireflection layer 92 and hard mask layer 91 as a mask, etch the first dielectric layer 30 and the support layer 20 to form the first trench 40 .
  • the antireflection layer 92 and the hard mask layer 91 can be removed by dry etching, and carbon tetrafluoride (CF 4 ), argon (Ar) and oxygen ( O 2 ) is the etching gas, and octafluorocyclopentene (C 5 F 8 ), argon (Ar) and oxygen (O 2 ) can be used as the etching gas during dry etching of the hard mask layer 91 .
  • fluorine-containing gas carbon tetrafluoride, octafluorocyclopentene
  • oxygen is mainly used to adjust the etching rate, selectivity, uniformity, etc.
  • argon is mainly used to reduce the loading effect (Loading Effect)
  • the loading effect refers to the phenomenon that the etching rate decreases with the increase of the etching area.
  • the anti-reflection layer 92 and the hard mask layer 91 will also be etched. After the first trench 40 is formed, if the anti-reflection layer 92 or the hard mask layer 91 still remains, the anti-reflection layer 92 and the hard mask layer 91 need to be removed. Exemplarily, the anti-reflection layer 92 and the hard mask layer 91 are removed by a chemical mechanical polishing process.
  • Step 51 includes: forming a second barrier layer 70 covering the first barrier layer 50 , and the second barrier layer 70 located in the first trench 40 forms a second trench 71 .
  • the second barrier layer 70 covers the top surface of the first barrier layer 50 and the first barrier layer 50 in the first trench 40 , and the second barrier layer in the first trench 40 70 surrounds and synthesizes the second trench 71 .
  • the first barrier layer 50 and the second barrier layer 70 on the sidewall of the first groove 40 form the sidewall of the cavity 60, and the thickness of the sidewall of the cavity 60 can be increased to reduce or prevent the sidewall of the cavity 60 from The walls collapse, further increasing the stability of the semiconductor structure.
  • the step of removing part of the first barrier layer 50 in the first trench 40 so that the first trench 40 exposes the substrate 10 includes: removing the bottom 42 of the second trench 71 The second barrier layer 70 and the first barrier layer 50 expose the substrate 10 through the second trench 71 .
  • the second barrier layer 70 and the first barrier layer 50 are etched along the second trench 71, so that the second trench 71 extends to the substrate 10, and the lining is exposed in the second trench 71. Bottom 10.
  • the second barrier layer 70 and the first barrier layer 50 at the bottom 42 of the second trench 71 are removed, and the step of exposing the substrate 10 by the second trench 71 includes:
  • a third photoresist layer 95 is formed on the second barrier layer 70, the third photoresist layer 95 has a first opening 96, and the orthographic projection of the first opening 96 on the substrate 10 is the same as that of the second groove 71 on the substrate.
  • the orthographic projections on 10 coincide.
  • the third photoresist layer 95 is formed on the top surface of the second barrier layer 70 by a spin-coating process, the third photoresist layer 95 is a patterned third photoresist layer 95, which There is a first opening 96 , the first opening 96 is located directly above the second trench 71 , and the orthographic projection of the first opening 96 on the substrate 10 coincides with the orthographic projection of the second trench 71 on the substrate 10 .
  • the second barrier layer 70 and the first barrier layer 50 are etched using the third photoresist layer 95 as a mask. As shown in FIGS. 15 and 16 , dry or wet etch the second barrier layer 70 and the first barrier layer 50 along the first opening 96 of the third photoresist layer 95 to expose the substrate 10 . During the etching process, the third photoresist layer 95 is also completely removed, or after the etching is completed, the remaining third photoresist layer 95 is removed by ashing or other processes.
  • the step of forming a wire 80 in the first trench 40 and electrically connecting the wire 80 to the substrate 10 includes: forming a wire 80 in the second trench 71, filling the second trench 71 with the wire 80 groove 71 .
  • the wire 80 in the second trench 71 filling the second trench 71 with the wire 80 groove 71 .
  • a conductive layer 81 is formed in the second trench 71 and on the second barrier layer 70 , the conductive layer 81 fills the second trench 71 and covers the second barrier layer 70 away from The surface of the substrate 10; as shown in Figure 17 and Figure 18, the conductive layer 81 on the second barrier layer 70 is planarized, so that the surface of the conductive layer 81 away from the substrate 10 is away from the second barrier layer 70 The surface of the substrate 10 is flush, and the conductive layer 81 forms a plurality of wires 80 spaced apart from each other, and the wires 80 fill up the second groove 71 .
  • the semiconductor structure includes: a substrate 10 , a support structure and a wire 80 .
  • the substrate 10 provides support, and its material may be one or more of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator, or germanium-on-insulator.
  • a semiconductor device is generally disposed on the substrate 10 , and the semiconductor device may include one or more of resistors, capacitors, diodes, triodes, field effect transistors, fuses or wires.
  • the support structure is disposed on the substrate 10 and is in contact with the substrate 10 .
  • the support structure is provided with a plurality of accommodation grooves passing through the support structure, and the plurality of accommodation grooves are arranged at intervals.
  • Each containing groove exposes the substrate 10, so that the wire 80 filled in each containing groove is in contact with the substrate 10, so as to realize the electrical connection between the wire 80 and the substrate 10, thereby connecting the film layer on the supporting structure with the substrate.
  • the substrate 10 is electrically connected to realize the transmission of electrical signals along a direction perpendicular to the substrate 10 .
  • the support structure located between two adjacent wires 80 may include a support layer 20 , a first barrier layer 50 and a second barrier layer 70 .
  • the support layer 20 is disposed on the substrate 10
  • the first barrier layer 50 is buckled outside the support layer 20
  • the first barrier layer 50 and the support layer 20 enclose a cavity 60
  • part of the inner sidewall of the first barrier layer 50 is connected to the cavity 60.
  • the outer sidewalls of the support layer 20 are attached to each other, and the dielectric constant of the support structure can be reduced by using the dielectric constant of air as 1, thereby reducing the parasitic capacitance between the wires 80 .
  • the first barrier layer 50 is also provided with a first etching hole located on the top of the cavity 60 and communicating with the cavity 60, that is, the first etching hole penetrates the first barrier layer 50.
  • the first etching hole is Through hole.
  • the width of the first etching hole may be 3-5 nm, and the cross-sectional shape of the first etching hole may be rectangle, square or trapezoid, so as to facilitate fabrication.
  • the cross-sectional shape of the first etching hole may also be other irregular shapes.
  • the cross-sectional shape refers to a shape obtained by taking a plane perpendicular to the surface of the substrate 10 as a cross-section.
  • the second barrier layer 70 is buckled outside the first barrier layer 50, and the inner surface of the second barrier layer 70 is attached to the outer surface of the first barrier layer 50. As shown in Figure 18, the second barrier layer 70 will first engraved The etch hole 51 is closed such that the cavity 60 forms a closed structure. In addition, the first barrier layer 50 and the second barrier layer 70 jointly form the sidewall of the cavity 60, thereby increasing the thickness of the sidewall of the cavity 60 to prevent the sidewall of the cavity 60 from collapsing and improving the stability of the semiconductor structure. sex.
  • the materials of the first barrier layer 50, the second barrier layer 70 and the support layer 20 can be the same, for example, all are silicon nitride, so that the first barrier layer 50, the second barrier layer 70 and the support layer 20 form an integrated structure, preventing the support Delamination occurs in areas where layer 20 is in contact with first barrier layer 50 and first barrier layer 50 is in contact with second barrier layer 70 .
  • the ratio of the height of the cavity 60 to the thickness of the support layer 20 is greater than or equal to 2, wherein the thickness of the support layer 20 refers to the distance between the top surface of the support layer 20 and the substrate 10, and the height of the cavity 60 refers to The distance between the inner top wall of the cavity 60 and the top surface of the supporting layer 20 .
  • the supporting layer 20 is also provided with a second etching hole that is directly opposite to and adapted to the first etching hole.
  • the dielectric constant of the supporting layer 20 can be reduced. Further reduce RC delays in semiconductor structures.
  • the orthographic projection of the first etching hole on the substrate 10 coincides with the orthographic projection of the second etching hole on the substrate 10 .
  • the conductive wire 80 is filled in the receiving groove, and the surface of the conductive wire 80 away from the substrate 10 may be flush with the surface of the second barrier layer 70 .
  • the wire 80 includes a third barrier layer 82, and a conductive material layer 83 disposed on the third barrier layer 82, the third barrier layer 82 is disposed on the sidewall and the bottom 42 of the receiving groove, so as to reduce or prevent the conductive material layer 83 Diffused in the bottom 10 and the second barrier layer 70.
  • the third barrier layer 82 may include a tantalum nitride layer and a tantalum layer. The tantalum layer is located on a side of the tantalum nitride layer away from the third barrier layer 82 .
  • the conductive material layer 83 may be made of copper or tungsten.
  • a closed cavity 60 is provided in the supporting structure between adjacent wires 80 , and the first barrier layer 50 and the second barrier layer 70 form the side wall and the top wall of the cavity 60 , using the dielectric constant of air as 1 to reduce the dielectric constant of the structure between the wires 80 , thereby reducing the parasitic capacitance between the wires 80 , thereby improving the electrical performance of the semiconductor structure.
  • the bottom 42 of the cavity 60 is the support layer 20, and the support layer 20 supports the first barrier layer 50 and the second barrier layer 70 on it. On the basis of ensuring the depth of the wire 80, the cavity 60 is reduced. depth, thereby reducing the risk of collapse of the first barrier layer 50 and the second barrier layer 70, thereby improving the stability of the semiconductor structure.

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Abstract

一种半导体结构及其制作方法，涉及半导体技术领域，用于解决半导体结构的电性能和稳定性较差的技术问题。该制作方法包括：在衬底（10）上形成层叠的支撑层（20）和第一介质层（30），支撑层（20）和第一介质层（30）中形成有第一沟槽（40）；形成覆盖第一沟槽（40）的侧壁（41）和底部（42）、第一介质层（30）的顶表面的第一阻挡层（50）；刻蚀第一阻挡层（50）和第一介质层（30），形成刻蚀孔（51）；去除暴露在刻蚀孔（51）内的第一介质层（30），形成空腔（60）；形成第二阻挡层（70），第二阻挡层（70）封闭空腔（60）顶部的刻蚀孔（51）；去除第一沟槽（40）内的部分第一阻挡层（50），以使第一沟槽（40）暴露衬底（10）；在第一沟槽（40）内形成导线。通过形成空腔（60）以减少导线之间的寄生电容，提高半导体结构的电性能，并通过设置支撑层（20）减少空腔（60）的深度，从而降低半导体结构的风险，提高半导体结构的稳定性。

Description

半导体结构及其制作方法
本申请要求于2021年08月05日提交中国专利局、申请号为202110894824.8、申请名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
随着半导体技术的发展，芯片上的半导体器件的集成度不断提高，各半导体器件之间的间距不断缩小，进而使得半导体器件中相邻的导电器件(例如导线)的间距也不断缩小。参考图1，相邻的导线80以及位于导线80之间的绝缘材料97形成寄生电容，寄生电容与绝缘材料97的介电常数成正比，与两导线80之间的距离成反比。随着导线80的间距的缩小，寄生电容不断增大，进而导致芯片上的电信号的电容电阻延迟(RC延迟)，影响芯片的工作频率。
相关技术中，通常采用低介电常数(low-k)材质的绝缘材料，以降低寄生电容。然而，低介电常数材质的绝缘材料易出现过刻蚀现象，半导体结构的电性能较差，且半导体结构的稳定性较差。
发明内容
鉴于上述问题，本申请实施例提供一种半导体结构及其制作方法，用于降低半导体结构的寄生电容，提高半导体结构的电性能和稳定性。
为了实现上述目的，本申请实施例提供如下技术方案：
第一方面，本申请实施例提供一种半导体结构的制作方法，其包括：在衬底上形成支撑层，并在所述支撑层上形成第一介质层，所述支撑层和所述第一介质层内形成有第一沟槽，所述第一沟槽暴露所述衬底；
形成第一阻挡层，所述第一阻挡层覆盖所述第一沟槽的侧壁和底部， 以及所述第一介质层的顶表面；
刻蚀所述第一阻挡层和所述第一介质层，以形成刻蚀孔；
去除暴露在所述刻蚀孔内的所述第一介质层，以形成空腔；
在所述第一阻挡层上形成第二阻挡层，所述第二阻挡层封闭所述空腔顶部的所述刻蚀孔；
去除所述第一沟槽内的部分所述第一阻挡层，以使所述第一沟槽暴露所述衬底；
在所述第一沟槽内形成导线，所述导线与所述衬底电连接。
本申请实施例提供的半导体结构的制作方法至少具有如下优点：
本申请实施例的半导体结构的制作方法中，通过在导线之间的结构中形成密闭的空腔，第一阻挡层和第二阻挡层形成空腔的顶壁和侧壁利用空气的介电常数低于第一介质层的介电常数，以减少导线之间的结构的介电常数，从而减少导线之间的寄生电容，进而提高半导体结构的电性能。此外，空腔的底部为支撑层，支撑层对其上的第一阻挡层和第二阻挡层进行支撑，在保证导线的高度的基础上，减少了空腔的深度，从而降低第一阻挡层和第二阻挡层坍塌的风险，进而提高了半导体结构的稳定性。
第二方面，本申请实施例的提供一种半导体结构，其包括：衬底，以及设置所述衬底上的支撑结构，所述支撑结构设置有贯穿所述支撑结构的多个容纳槽，每个所述容纳槽内填充有导线，所述导线与所述衬底电连接；其中，位于相邻的所述导线之间的所述支撑结构包括：支撑层，所述支撑层设置在所述衬底上；扣设在所述支撑层外的第一阻挡层，所述第一阻挡层和所述支撑层形成空腔，所述第一阻挡层的内侧壁与所述支撑层的外侧壁相贴合，且所述第一阻挡层设置有与所述空腔连通的第一刻蚀孔；扣设在所述第一阻挡层外的第二阻挡层，所述第二阻挡层的内表面与所述第一阻挡层的外表面相贴合。
本申请实施例的半导体结构至少具有如下优点：
本申请实施例的半导体结构中，位于相邻的导线之间的支撑结构中设置有密闭的空腔，第一阻挡层和第二阻挡层形成空腔的侧壁和顶壁，利用空气的介电常数为1，以减少导线之间的结构的介电常数，从而减少导线之间的寄生电容，进而提高半导体结构的电性能。此外，空腔的底部为支撑层，支撑层对其上的第一阻挡层和第二阻挡层进行支撑，在保证导线的 高度的基础上，减少了空腔的深度，从而降低第一阻挡层和第二阻挡层坍塌的风险，进而提高了半导体结构的稳定性。
如上所述的半导体结构中，所述支撑层还设置有与所述第一刻蚀孔正对且适配的第二刻蚀孔。
附图说明
图1为相关技术中的半导体结构的结构示意图；
图2为本申请实施例中的半导体结构的制作方法的流程图；
图3为本申请实施例中的形成第一沟槽后的结构示意图；
图4为本申请实施例中的形成第一阻挡层后的结构示意图；
图5为本申请实施例中的形成刻蚀孔后的结构示意图；
图6为本申请实施例中的形成第二光刻胶层后的结构示意图；
图7为本申请实施例中的形成空腔后的结构示意图；
图8为本申请实施例中的形成第二阻挡层后的一种结构示意图；
图9为本申请实施例中的去除部分第一阻挡层后的结构示意图；
图10为本申请实施例中的形成导电层后的一种结构示意图；
图11为本申请实施例中的导电层的结构示意图；
图12为本申请实施例中的形成抗反射层后的结构示意；
图13为本申请实施例中的形成第一光刻胶层后的结构示意图；
图14为本申请实施例中的形成第二阻挡层后的另一种结构示意；
图15为本申请实施例中的形成第三光刻胶层后的结构示意图；
图16为本申请实施例中的去除部分第一阻挡层和部分第二阻挡层后的结构示意图；
图17为本申请实施例中的形成导电层后的另一种结构示意图；
图18为本申请实施例中的形成导线后的结构示意图。
具体实施方式
为了减小半导体结构的寄生电容，提高半导体结构的电性能和稳定性，本申请实施例提供一种半导体结构的制作方法，通过在导线之间的结构中形成密闭的空腔，利用空气的介电常数为1，减少导线之间的结构的介电 常数，从而减少导线之间的寄生电容，进而提高半导体结构的电性能。此外，空腔的底部为支撑层，支撑层对其上的第一阻挡层和第二阻挡层进行支撑，在保证导线的高度的基础上，减少了空腔的深度，从而降低第一阻挡层和第二阻挡层坍塌的风险，进而提高了半导体结构的稳定性。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
实施例一
参照图2，本申请实施例提供一种半导体结构的制作方法，具有包括以下步骤：
步骤S101、在衬底上形成支撑层，并在支撑层上形成第一介质层，支撑层和第一介质层内形成有第一沟槽，第一沟槽暴露衬底。
参考图3，衬底10提供支撑，其材质可以为硅、锗、锗化硅、碳化硅、绝缘体上硅(Silicon on Insulator，简称SOI)或者绝缘体上锗(Germanium on Insulator，简称GOI)等半导体材料中的一种或者多种。衬底10上通常设置有半导体器件(图中未标示出)，以实现特定功能。半导体器件可以包括电阻器、电容器、二极管、三极管、场效应晶体管(Field Effect Transistor，简称FET)、熔丝或者导线中的一种或者多种。
支撑层20形成在衬底10上。例如，支撑层20通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PCD)或者原子层沉积(Atomic Layer Deposition，简称ALD)等沉积工艺形成在衬底10上，以使形成的支撑层20致密度和平整度都较好。
第一介质层30形成在支撑层20上。第一介质层30可以通过沉积工艺形成在支撑层20上。第一介质层30与支撑层20可以具有较大的选择比，例如，第一介质层30与支撑层20的选择比大于或者等于2。如此设置，后续去除第一介质层30时，支撑层20还可以用作刻蚀停止层(Etch Stop Layer)，以防止刻蚀第一介质层30时损伤衬底10和/或衬底10上的半导 体器件。
支撑层20和第一介质层30中形成有第一沟槽40，如图3所示，第一沟槽40贯穿支撑层20和第一介质层30，以暴露衬底10，第一沟槽40内后续形成有导线80(参考图18)。可以理解的是，支撑层20的厚度与第一介质层30的厚度之和为导线80的高度，第一介质层30在后续会被去除，该区域后续形成空腔60，空腔60内的空气的介电常数为1，其介电常数最低，以降低两导线80之间的寄生电容。
支撑层20的介电常数可以小于第一介质层30的介电常数，采用介电常数较小的支撑层20替代部分第一介质层30，可以进一步降低支撑层20和第一介质层30的总体的介电常数。示例性的，第一介质层30可以为氧化硅层，支撑层20可以为氢硅酸盐聚合物层或者多孔性硅化物层等。当然，支撑层20的介电常数也可以大于或者等于第一介质层30的介电常数，此时，通过调整支撑层20的厚度与第一介质层30的厚度，以降低支撑层20和后续形成的空腔60的总体的介电常数。具体的，第一介质层30为氧化硅层，支撑层20为氮化硅层或者氮氧化硅层，第一介质层30的厚度与支撑层20的厚度的比值大于等于2，例如第一介质层30的厚度与支撑层20的厚度的比值等于3。上述氧化硅层可以通过正硅酸乙酯(TEOS)分解并沉积形成，上述氮氧化硅层可以通过对氮化硅层渗氮处理形成。
步骤S102、形成第一阻挡层，第一阻挡层覆盖第一沟槽的侧壁和底部，以及第一介质层的顶表面。
参考图4，第一阻挡层50沉积形成在第一沟槽40的侧壁41和底部42，以及第一介质层30的顶表面。其中，第一介质层30的顶表面是指第一介质层30背离衬底10的表面，即图4所示的第一介质层30的上表面。
步骤S103、刻蚀第一阻挡层和第一介质层，以形成刻蚀孔。
参考图5，刻蚀孔51贯穿第一阻挡层50并延伸至第一介质层30内，以使增加第一介质层30在刻蚀孔51暴露出的表面积，从而便于后续去除第一介质层30。在一些可能的示例中，刻蚀孔51贯穿第一介质层30。更进一步的，刻蚀孔51还可以延伸至支撑层20内，即刻蚀孔51的孔底位于支撑层20内。如此设置，在支撑层20内形成空气隙，可以减少支撑层20的介电常数，进一步减少半导体结构中的RC延迟。
刻蚀孔51的宽度可以为3-5nm，其中，刻蚀孔51的宽度方向与第一 沟槽40的宽度方向相同，如图5所示的水平方向(X方向)。如此设置，第一阻挡层50中的刻蚀孔51便于通过第二阻挡层70封口，可以减少封口过程中封口材料落入刻蚀孔51内，从而保证空腔对RC延迟的降低效果。
在一些可能的示例中，参考图5和图6，刻蚀第一阻挡层50和第一介质层30，以形成刻蚀孔51的步骤包括：
在第一阻挡层50上和第一沟槽40内形成第二光刻胶层94，第二光刻胶层94填充满第一沟槽40且覆盖第一阻挡层50背离衬底10的表面。如图5和图6所示，第一沟槽40的侧壁41和底部42覆盖有第一阻挡层50，第二光刻胶层94填充在第一阻挡层50所围合的区域内，并覆盖第一阻挡层50的顶表面。第二光刻胶层94为图形化的第二光刻胶层94，第二光刻胶层94的顶表面可以齐平，即第二光刻胶层94背离衬底10的表面为平面。
形成第二光刻胶层94后，以第二光刻胶层94为掩膜，刻蚀第一阻挡层50和第一介质层30，以形成刻蚀孔51。如图6所示，第一阻挡层50和第一介质层30中未被第二光刻胶层94覆盖的区域被去除，刻蚀停止于支撑层20背离衬底10的表面或者支撑层20中。刻蚀时可以采用干法刻蚀，刻蚀气体包括含氟气体、氧气和惰性气体(例如氮气或者氩气)。
形成刻蚀孔51后，去除第二光刻胶层94。其中，第二光刻胶层94可以通过灰化工艺去除，去除第二光刻胶层94后，第一阻挡层50暴露。
步骤S104、去除暴露在刻蚀孔内的第一介质层，以形成空腔。
参考图7，去除第一介质层30后，第一阻挡层50和支撑层20围合的区域形成空腔60，第一阻挡层50中的刻蚀孔51与空腔60相连通。示例性的，通过干法刻蚀或者湿法刻蚀去除暴露在刻蚀孔51内的第一介质层30，通过刻蚀液或者刻蚀气体与第一介质层30反应，从而将第一介质层30去除。在一些可能的示例中，第一介质层30的材质为氧化硅，刻蚀气体可以包括八氟环丁烷(C 4F 8)等含氟气体，或者，刻蚀液可以包括稀氢氟酸(Dilute Hydrofluoric Acid，简称DHF)。
步骤S105、在第一阻挡层上形成第二阻挡层，第二阻挡层封闭空腔顶部的刻蚀孔。
参考图8，在第一阻挡层50上沉积形成第二阻挡层70，通过控制第二阻挡层70的工艺参数，例如沉积速率或者温度等，以使第二阻挡层70封闭刻蚀孔51。示例性的，如图8所示，第二阻挡层70可以只覆盖第一阻 挡层50背离衬底10的表面。当然，如图15所示，第二阻挡层70还可以覆盖位于第一沟槽40内的第一阻挡层50。
需要说明的是，第一阻挡层50、第二阻挡层70和支撑层20的材质可以相同，以使第一阻挡层50、第二阻挡层70和支撑层20形成一体结构，防止支撑层20与第一阻挡层50、第一阻挡层50与第二阻挡层70相接触的区域的出现分层。示例性的，第一阻挡层50、第二阻挡层70和支撑层20的材质均为氮化硅。
步骤S106、去除第一沟槽内的部分第一阻挡层，以使第一沟槽暴露衬底。
参考图9，通过去除第一沟槽40内的部分第一阻挡层50，将衬底10暴露，从而使得后续形成在第一沟槽40内的导线80可以与衬底10相接触而实现电连接。示例性的，通过各向异性刻蚀，去除第一沟槽40的底部42的第一阻挡层50，保留第一沟槽40侧壁的第一阻挡层50。
步骤S107、在第一沟槽内形成导线，导线与衬底电连接。
参考图9至图11，导线形成在第一沟槽40内且与衬底10电连接，以将衬底10与其他膜层电连接，实现电信号沿垂直于衬底10的方向传递。在一些可能的示例中，在第一沟槽40内形成导线，导线与衬底10电连接的步骤包括：
在第一沟槽40内沉积导电层81，导电层81填充满第一沟槽40且覆盖第二阻挡层70的顶表面。其中，导电层81包括层叠设置的第三阻挡层82和导电材料层83，第三阻挡层82位于导电层81靠近衬底10的一侧。第三阻挡层82用于减少或者防止导电材料层83向第一阻挡层50、第二阻挡层70、支撑层20以及衬底10中扩散。第三阻挡层82包括钛层、氮化钛层、钽层或者氮化钽层中的一层或者多层。导电材料层83可以为铜层或者钨层等。本申请实施例中对导电层81的形成工艺不是限定的，例如，导电层81还可以通过电镀工艺形成。
形成导电层81后，去除位于第二阻挡层70上的导电层81，保留的导电层81形成导线。示例性的，通过对导电层81背离衬底10的表面进行平坦化处理，以去除位于第二阻挡层70上的导电层81。具体的，对导电层81的顶表面进行化学机械研磨(Chemical Mechanical Polishing，简称CMP)，以暴露第二阻挡层70。
综上，本申请实施例的半导体结构的制作方法中，通过在导线之间的结构中形成密闭的空腔60，第一阻挡层50和第二阻挡层70形成空腔60的顶壁和侧壁利用空气的介电常数低于第一介质层30的介电常数，以减少导线之间的结构的介电常数，从而减少导线之间的寄生电容，进而提高半导体结构的电性能。此外，空腔60的底部42为支撑层20，支撑层20对其上的第一阻挡层50和第二阻挡层70进行支撑，在保证导线的高度的基础上，减少了空腔60的深度，增加了与衬底10的接触面积，从而降低第一阻挡层50和第二阻挡层70坍塌的风险，进而提高了半导体结构的稳定性。
需要说明的是，在本申请一种可能的示例中，参考图3、图12和图13，在衬底10上形成支撑层20，并在支撑层20上形成第一介质层30，支撑层20和第一介质层30内形成有第一沟槽40，第一沟槽40暴露衬底10的步骤可以包括：
步骤S1021、在衬底10上依次形成支撑层20、第一介质层30、硬掩模层91、抗反射层92和第一光刻胶层93。
参考图12和图13，在衬底10上形成层叠的支撑层20、第一介质层30、硬掩模层91、抗反射层92和第一光刻胶层93。其中，支撑层20、第一介质层30、硬掩模版(Hard Mask)层和抗反射层92可以通过沉积工艺形成。具体的，在衬底10上沉积形成支撑层20，在支撑层20上沉积形成第一介质层30，在第一介质层30上沉积形成硬掩模层91，并在硬掩模层91上沉积形成抗反射层92。第一光刻胶层93可以通过图形化工艺形成，例如采用旋涂工艺在抗反射层92上形成第一光刻胶层93；对第一光刻胶层93曝光显影，以暴露部分抗反射层92，使得第一光刻胶层93形成有所需图案。
抗反射层92用于减少第一光刻胶层93曝光时的驻波，防止光线在第一光刻胶层93的底部发生漫反射，以保证第一光刻胶层93的图案的准确性。硬掩模层91用于转移第一光刻胶层93的图案，硬掩模层91的材质与抗反射层92的材质不同。在一种可能的示例中，硬掩模层91的材质为氮化硅或者二氧化硅，抗反射层92的材质为氮氧化硅，第一光刻胶层93的材质可以为正胶，也可以为负胶。
步骤S1022、以第一光刻胶层93为掩膜，刻蚀抗反射层92和硬掩模层91。
以图形化后的第一光刻胶层93为掩膜，利用刻蚀气体各向异性刻蚀抗反射层92和硬掩模层91。其中，刻蚀气体可以包括四氟化碳(CF 4)、八氟环丁烷(C 4F 8)或者八氟环戊烯(C 5F 8)等。
在一些可能的示例中，在刻蚀抗反射层92和硬掩模层91的过程中，第一光刻胶层93全部耗损，没有残余。在另一些可能的示例中，在刻蚀抗反射层92和硬掩模层91的过程中，第一光刻胶层93没有全部耗损，仍有残余。此时，需要将第一光刻胶层93单独去除，例如，通过灰化或者刻蚀去除剩余的第一光刻胶层93。
步骤S1023、以刻蚀后的抗反射层92和硬掩模层91为掩膜，刻蚀第一介质层30和支撑层20，以形成第一沟槽40。
以刻蚀后的抗反射层92和硬掩模层91为掩膜，刻蚀第一介质层30和支撑层20，形成第一沟槽40，第一沟槽40贯穿第一介质层30和支撑层20，以暴露衬底10。示例性的，抗反射层92和硬掩模层91可以通过干法刻蚀去除，干法刻蚀抗反射层92时可以采用四氟化碳(CF 4)、氩气(Ar)和氧气(O 2)为刻蚀气体，干法刻蚀硬掩模层91时可以采用八氟环戊烯(C 5F 8)、氩气(Ar)和氧气(O 2)为刻蚀气体。其中，含氟气体(四氟化碳、八氟环戊烯)为主要的刻蚀气体，氧气主要用于调整刻蚀速率、选择比、均匀性等，氩气主要用于降低负载效应(Loading Effect)负载效应是指刻蚀速率随刻蚀面积的增加而减小的现象。
需要说明的是，形成第一沟槽40的过程中，抗反射层92和硬掩模层91也会被刻蚀。形成第一沟槽40后，如果抗反射层92或者硬掩模层91仍有残留，需要将抗反射层92和硬掩模层91去除。示例性的，通过化学机械研磨工艺去除抗反射层92和硬掩模层91。
需要说明的是，参考图7和图14，在本申请一种可能的示例中，在第一阻挡层50上形成第二阻挡层70，第二阻挡层70封闭空腔60顶部的刻蚀孔51的步骤包括：形成覆盖第一阻挡层50的第二阻挡层70，位于第一沟槽40内的第二阻挡层70围合成第二沟槽71。
如图7和图14所示，第二阻挡层70覆盖第一阻挡层50的顶表面，以 及第一沟槽40内的第一阻挡层50，位于第一沟槽40内的第二阻挡层70围合成第二沟槽71。如此设置，第一沟槽40侧壁的第一阻挡层50和第二阻挡层70形成空腔60的侧壁，可以增加空腔60的侧壁的厚度，以减少或者防止空腔60的侧壁坍塌，进一步提高半导体结构的稳定性。
相应的，参考图14至图16，去除第一沟槽40内的部分第一阻挡层50，以使第一沟槽40暴露衬底10的步骤包括：去除第二沟槽71的底部42的第二阻挡层70和第一阻挡层50，第二沟槽71暴露衬底10。
如图14至图16所示，沿第二沟槽71刻蚀第二阻挡层70和第一阻挡层50，以使第二沟槽71延伸至衬底10，第二沟槽71内暴露衬底10。在一些可能的示例中，去除第二沟槽71的底部42的第二阻挡层70和第一阻挡层50，第二沟槽71暴露衬底10的步骤包括：
在第二阻挡层70上形成第三光刻胶层95，第三光刻胶层95具有第一开口96，第一开口96在衬底10上的正投影与第二沟槽71在衬底10上的正投影相重合。如图15所示，第三光刻胶层95通过旋涂工艺形成在第二阻挡层70的顶表面上，第三光刻胶层95为图形化后的第三光刻胶层95，其具有第一开口96，第一开口96位于第二沟槽71的正上方，且第一开口96在衬底10上的正投影与第二沟槽71在衬底10上的正投影相重合。
形成第三光刻胶层95后，以第三光刻胶层95为掩膜，刻蚀第二阻挡层70和第一阻挡层50。如图15和图16所示，沿第三光刻胶层95的第一开口96干法刻蚀或者湿法刻蚀第二阻挡层70和第一阻挡层50，以暴露衬底10。刻蚀过程中，第三光刻胶层95也被完全去除，或者刻蚀完成后，通过灰化等工艺去除剩余的第三光刻胶层95。
相应的，参考图17和图18，在第一沟槽40内形成导线80，导线80与衬底10电连接的步骤包括：在第二沟槽71内形成导线80，导线80填充于第二沟槽71。示例性的，如图17和图18所示，在第二沟槽71内和第二阻挡层70上形成导电层81，导电层81填充满第二沟槽71且覆盖第二阻挡层70背离衬底10的表面；如图17和图18所示，再对第二阻挡层70上的导电层81进行平坦化处理，以使导电层81背离衬底10的表面与第二阻挡层70背离衬底10的表面齐平，导电层81形成多个彼此间隔的导线80，导线80填充满第二沟槽71。
实施例二
本申请还提供一种半导体结构，参考图18，该半导体结构包括：衬底10、支撑结构和导线80。其中，衬底10提供支撑，其材质可以为硅、锗、锗化硅、碳化硅、绝缘体上硅或绝缘体上锗中的一种或者多种。衬底10上通常设置有半导体器件，半导体器件可以包括电阻器、电容器、二极管、三极管、场效应晶体管、熔丝或者导线中的一种或者多种。
支撑结构设置在衬底10上且与衬底10相接触，支撑结构设置有贯穿支撑结构的多个容纳槽，多个容纳槽间隔设置。每个容纳槽暴露衬底10，以使填充在每个容纳槽内的导线80与衬底10相接触，而实现导线80与衬底10的电连接，从而将支撑结构上的膜层与衬底10电连接，实现电信号沿垂直于衬底10的方向的传递。
位于相邻的两个导线80之间的支撑结构可以包括支撑层20、第一阻挡层50和第二阻挡层70。其中，支撑层20设置在衬底10上，第一阻挡层50扣设在支撑层20外，第一阻挡层50和支撑层20围合成空腔60，第一阻挡层50的部分内侧壁与支撑层20的外侧壁相贴合，利用空气的介电常数为1，可以降低支撑结构的介电常数，从而降低导线80之间的寄生电容。
第一阻挡层50还设置有位于空腔60的顶部且与空腔60连通的第一刻蚀孔，即第一刻蚀孔贯穿第一阻挡层50，示例性的，第一刻蚀孔为直通孔。第一刻蚀孔的宽度可以为3-5nm，第一刻蚀孔的截面形状可以为矩形、正方形或者梯形，以便于制作。当然，在不同的工艺参数情况下，第一刻蚀孔的截面形状还可能是其他不规则图形。其中，截面形状是指以垂直于衬底10的表面的平面为截面所获得的形状。
第二阻挡层70扣设在第一阻挡层50外，第二阻挡层70的内表面与第一阻挡层50的外表面相贴合，如图18所示，第二阻挡层70将第一刻蚀孔51封闭，从而使得空腔60形成封闭结构。此外，第一阻挡层50和第二阻挡层70共同形成空腔60的侧壁，从而增加了空腔60的侧壁的厚度，以防止空腔60的侧壁坍塌，提高了半导体结构的稳定性。
第一阻挡层50、第二阻挡层70和支撑层20的材质可以相同，例如均为氮化硅，以使第一阻挡层50、第二阻挡层70和支撑层20形成一体结构，防止支撑层20与第一阻挡层50、第一阻挡层50与第二阻挡层70相接触的区域的出现分层。空腔60的高度与支撑层20的厚度与的比值大或者等 于2，其中，支撑层20的厚度是指支撑层20的顶表面与衬底10之间的距离，空腔60的高度是指空腔60的内侧顶壁与支撑层20的顶表面之间的距离。
在一些可能的示例中，支撑层20还设置有与第一刻蚀孔正对且适配的第二刻蚀孔，通过以空气替代部分支撑层20，可以减少支撑层20的介电常数，进一步减少半导体结构中的RC延迟。如图18所示，第一刻蚀孔在衬底10上的正投影与第二刻蚀孔在衬底10上的正投影相重合。
导线80填充在容纳槽内，导线80背离衬底10的表面可以与第二阻挡层70的表面齐平。导线80包括第三阻挡层82，以及设置在第三阻挡层82上的导电材料层83，第三阻挡层82设置在容纳槽的侧壁和底部42，以减少或者防止导电材料层83向衬底10和第二阻挡层70中扩散。第三阻挡层82可以包括氮化钽层和钽层，钽层位于氮化钽层背离第三阻挡层82的一侧，导电材料层83的材质可以为铜或者钨等。
本申请实施例的半导体结构中，位于相邻的导线80之间的支撑结构中设置有密闭的空腔60，第一阻挡层50和第二阻挡层70形成空腔60的侧壁和顶壁，利用空气的介电常数为1，以减少导线80之间的结构的介电常数，从而减少导线80之间的寄生电容，进而提高半导体结构的电性能。此外，空腔60的底部42为支撑层20，支撑层20对其上的第一阻挡层50和第二阻挡层70进行支撑，在保证导线80的深度的基础上，减少了空腔60的深度，从而降低第一阻挡层50和第二阻挡层70坍塌的风险，进而提高了半导体结构的稳定性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制作方法，包括：
    在衬底上形成支撑层，并在所述支撑层上形成第一介质层，所述支撑层和所述第一介质层内形成有第一沟槽，所述第一沟槽暴露所述衬底；
    形成第一阻挡层，所述第一阻挡层覆盖所述第一沟槽的侧壁和底部，以及所述第一介质层的顶表面；
    刻蚀所述第一阻挡层和所述第一介质层，以形成刻蚀孔；
    去除暴露在所述刻蚀孔内的所述第一介质层，以形成空腔；
    在所述第一阻挡层上形成第二阻挡层，所述第二阻挡层封闭所述空腔顶部的所述刻蚀孔；
    去除所述第一沟槽内的部分所述第一阻挡层，以使所述第一沟槽暴露所述衬底；
    在所述第一沟槽内形成导线，所述导线与所述衬底电连接。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，通过干法刻蚀或者湿法刻蚀去除暴露在所述刻蚀孔内的所述第一介质层。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一介质层为氧化硅层，所述支撑层为氮化硅层或者氮氧化硅层，所述第一介质层的厚度与所述支撑层的厚度的比值大于或者等于2。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，所述刻蚀孔的孔底位于所述支撑层中。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，在衬底上形成支撑层，并在所述支撑层上形成第一介质层，所述支撑层和所述第一介质层内形成有第一沟槽，所述第一沟槽暴露所述衬底的步骤包括：
    在所述衬底上依次形成所述支撑层、所述第一介质层、硬掩模层、抗反射层和第一光刻胶层；
    以所述第一光刻胶层为掩膜，刻蚀所述抗反射层和所述硬掩模层；
    以刻蚀后的所述抗反射层和所述硬掩模层为掩膜，刻蚀所述第一介质层和所述支撑层，以形成所述第一沟槽。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，刻蚀所述第一阻挡层和所述第一介质层，以形成刻蚀孔的步骤包括：
    在所述第一阻挡层上和所述第一沟槽内形成第二光刻胶层，所述第二光刻胶层填充满所述第一沟槽且覆盖所述第一阻挡层背离所述衬底的表面；
    以所述第二光刻胶层为掩膜，刻蚀所述第一阻挡层和所述第一介质层，以形成所述刻蚀孔；
    去除所述第二光刻胶层。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，在所述第一沟槽内形成导线，所述导线与所述衬底电连接的步骤包括：
    在所述第一沟槽内沉积导电层，所述导电层填充满所述第一沟槽且覆盖所述第二阻挡层的顶表面；
    去除位于所述第二阻挡层上的所述导电层，保留的所述导电层形成所述导线。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，通过化学机械研磨去除位于所述第二阻挡层上的所述导电层。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，所述导电层包括层叠设置的第三阻挡层和导电材料层，所述第三阻挡层位于所述导电层靠近所述衬底的一侧。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，在所述第一阻挡层上形成第二阻挡层，所述第二阻挡层封闭所述空腔顶部的所述刻蚀孔的步骤包括：
    形成覆盖所述第一阻挡层的第二阻挡层，位于所述第一沟槽内的所述第二阻挡层围合成第二沟槽。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，去除所述第一沟槽内的部分所述第一阻挡层，以使所述第一沟槽暴露所述衬底的步骤包括：
    去除所述第二沟槽的底部的所述第二阻挡层和所述第一阻挡层，所述第二沟槽暴露所述衬底。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，去除所述第二沟槽的底部的所述第二阻挡层和所述第一阻挡层，所述第二沟槽暴露所述衬底的步骤包括：
    在所述第二阻挡层上形成第三光刻胶层，所述第三光刻胶层具有第一开口，所述第一开口在所述衬底上的正投影与所述第二沟槽在所述衬底上 的正投影相重合；
    以所述第三光刻胶层为掩膜，刻蚀所述第二阻挡层和所述第一阻挡层。
  13. 根据权利要求11所述的半导体结构的制作方法，其中，在所述第一沟槽内形成导线，所述导线与所述衬底电连接的步骤包括：
    在所述第二沟槽内形成所述导线，所述导线填充于所述第二沟槽。
  14. 一种半导体结构，包括：衬底，以及设置所述衬底上的支撑结构，所述支撑结构设置有贯穿所述支撑结构的多个容纳槽，每个所述容纳槽内填充有导线，所述导线与所述衬底电连接，其中，位于相邻的所述导线之间的所述支撑结构包括：
    支撑层，所述支撑层设置在所述衬底上；
    扣设在所述支撑层外的第一阻挡层，所述第一阻挡层和所述支撑层形成空腔，所述第一阻挡层的内侧壁与所述支撑层的外侧壁相贴合，且所述第一阻挡层设置有与所述空腔连通的第一刻蚀孔；
    扣设在所述第一阻挡层外的第二阻挡层，所述第二阻挡层的内表面与所述第一阻挡层的外表面相贴合。
  15. 根据权利要求14所述的半导体结构，其中，所述支撑层还设置有与所述第一刻蚀孔正对且适配的第二刻蚀孔。
PCT/CN2022/070591 2021-08-05 2022-01-06 半导体结构及其制作方法 Ceased WO2023010808A1 (zh)

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