WO2023005778A1 - 自适应过冲电压抑制电路、基准电路、芯片及通信终端 - Google Patents

自适应过冲电压抑制电路、基准电路、芯片及通信终端 Download PDF

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Publication number
WO2023005778A1
WO2023005778A1 PCT/CN2022/106888 CN2022106888W WO2023005778A1 WO 2023005778 A1 WO2023005778 A1 WO 2023005778A1 CN 2022106888 W CN2022106888 W CN 2022106888W WO 2023005778 A1 WO2023005778 A1 WO 2023005778A1
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Prior art keywords
voltage
nmos transistor
circuit
reference circuit
current
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PCT/CN2022/106888
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English (en)
French (fr)
Inventor
王永寿
陈成
李春领
高晨阳
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唯捷创芯(天津)电子技术股份有限公司
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Priority to KR1020247000277A priority Critical patent/KR20240015139A/ko
Publication of WO2023005778A1 publication Critical patent/WO2023005778A1/zh
Priority to US18/408,534 priority patent/US20240143006A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to an adaptive overshoot voltage suppression circuit, and also relates to a reference circuit including the adaptive overshoot voltage suppression circuit, an integrated circuit chip and a corresponding communication terminal, belonging to the technical field of integrated circuits.
  • the system in order to obtain a fast system response, the system will generate a large overshoot voltage or current to achieve, but in the PA system, when the supply voltage or current provided for it has a large overshoot, it will seriously affect its lifespan and performance.
  • the PA system is powered by a low-dropout linear regulator circuit, and the reference voltage required by the circuit is provided by a reference circuit. It is of great significance for the voltage circuit to provide a stable power supply voltage for the PA system.
  • the primary technical problem to be solved by the present invention is to provide an adaptive overshoot voltage suppression circuit.
  • Another technical problem to be solved by the present invention is to provide a reference circuit, a chip and a communication terminal including an adaptive overshoot voltage suppression circuit.
  • an adaptive overshoot voltage suppression circuit including an overshoot voltage suppression unit and a voltage-current conversion unit, the input end of the overshoot voltage suppression unit is connected to the reference circuit to be tested A preset sampling point, the output terminal of the overshoot voltage suppression unit is connected to the input terminal of the voltage-current conversion unit, and the output terminal of the voltage-current conversion unit is connected to the preset adjustment on the reference circuit to be tested point;
  • the overshoot voltage suppression unit generates a transient high-frequency induced voltage according to the sampling voltage obtained from the reference circuit to be tested, which is converted by the voltage-current conversion unit into The corresponding pull-up current is injected into the reference circuit to be tested, and superposed with the pull-down start-up current of the reference circuit to be tested, so as to reduce the non-linear start-up current at the start-up moment of the reference circuit to be tested.
  • the overshoot voltage suppression unit includes a capacitor, a first NMOS transistor, and a second NMOS transistor.
  • One end of the capacitor is connected to the sampling point and the gate of the first NMOS transistor.
  • the other end is connected to the drains of the first NMOS transistor and the second NMOS transistor, the gate of the second NMOS transistor is connected to an external enabling circuit, and the gates of the first NMOS transistor and the second NMOS transistor are The source is connected to the common ground terminal voltage.
  • the voltage-current conversion unit includes a third NMOS transistor, a first resistor, a first PMOS transistor, and a second PMOS transistor, and the gate of the third NMOS transistor is connected to the first NMOS transistor, the The drain of the second NMOS transistor and the other end of the capacitor, the source of the third NMOS transistor is connected to one end of the first resistor, and the drain of the third NMOS transistor is connected to the first PMOS transistor The drain, gate and gate of the second PMOS transistor, the drain of the second PMOS transistor is connected to the adjustment point, and the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage, and the other end of the first resistor is connected to the common ground voltage.
  • a reference circuit including a start-up module, a reference core module, and the above-mentioned adaptive overshoot voltage suppression circuit, the input terminal of the adaptive overshoot voltage suppression circuit is connected to the reference The preset sampling point on the core module, the output terminal of the adaptive overshoot voltage suppression circuit is connected to the preset adjustment point on the startup module.
  • the adjustment point is a position where the startup module outputs startup current to the reference core module.
  • the sampling point is a position where the sampling voltage sampled from the reference core module makes the gate of the first NMOS transistor turn on.
  • an integrated circuit chip is provided, and the integrated circuit chip includes the above-mentioned reference circuit.
  • a communication terminal is provided, and the communication terminal includes the above-mentioned reference circuit.
  • the self-adaptive overshoot voltage suppression circuit, reference circuit, chip and communication terminal provided by the present invention generate a transient high-frequency induced voltage according to the sampling voltage output by the reference circuit to be tested in real time during the start-up process of the reference circuit to be tested , and converted into the corresponding pull-up current, injected into the reference circuit to be tested, and superimposed with the pull-down start-up current of the reference circuit to be tested, so as to reduce the non-linear start-up current at the start-up moment of the reference circuit to be tested, thus ensuring to a certain extent While the reference circuit satisfies the timing requirement, it effectively suppresses the overshooting fast response of the reference voltage output by the reference circuit.
  • FIG. 1 is a schematic circuit diagram of an adaptive overshoot voltage suppression circuit provided by an embodiment of the present invention
  • FIG. 2 is a functional block diagram of a reference circuit provided by an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of a startup module and a reference core module in the reference circuit provided by an embodiment of the present invention
  • Fig. 4 is the curve diagram of current change in the embodiment of the present invention.
  • FIG. 5 is a start-up simulation waveform diagram of the reference circuit obtained in the embodiment of the present invention.
  • an embodiment of the present invention provides an adaptive overshoot voltage suppression circuit 100, which includes at least An overshoot voltage suppression unit 1001, a voltage-current conversion unit 1002, the input terminal of the overshoot voltage suppression unit 1001 is connected to a preset sampling point on the reference circuit to be tested, and the output terminal of the overshoot voltage suppression unit 1001 is connected to the voltage-current conversion unit The input terminal of 1002 and the output terminal of the voltage-current conversion unit 1002 are connected to the preset regulation point on the reference circuit to be tested.
  • the overshoot voltage suppression unit 1001 generates a transient high-frequency induced voltage according to the sampling voltage obtained from the reference circuit to be tested, and converts it into a corresponding pull-up current through the voltage-current conversion unit 1002, Injected into the reference circuit to be tested, superimposed with the pull-down start-up current of the reference circuit to be tested, so as to reduce the non-linear start-up current at the start-up moment of the reference circuit to be tested, thereby suppressing the overshoot of the reference voltage output by the reference circuit to be tested.
  • the overshoot voltage suppression unit 1001 includes a capacitor C1, a first NMOS transistor MN1, and a second NMOS transistor MN2; one end of the capacitor C1 is used as the input terminal of the overshoot voltage suppression unit 1001 for connecting to the reference circuit to be tested
  • the preset sampling point and the gate of the first NMOS transistor MN1, the other end of the capacitor C1 is connected to the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the gate of the second NMOS transistor MN2 is connected to an external enable
  • the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the common ground terminal voltage VSS.
  • the voltage-current conversion unit 1002 includes a third NMOS transistor MN3, a first resistor R1, a first PMOS transistor MP1, and a second PMOS transistor MP2; the gate of the third NMOS transistor MN3 is connected to the first NMOS transistor MN1 , the drain of the second NMOS transistor MN2 and the other end of the capacitor C1, the source of the third NMOS transistor MN3 is connected to one end of the first resistor R1, the drain of the third NMOS transistor MN3 is connected to the drain of the first PMOS transistor MP1,
  • the gate and the gate of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 as an overshoot voltage suppression unit 1001 is connected to the preset adjustment point on the reference circuit to be tested, the first PMOS transistor MP1 and the second PMOS transistor MP2
  • the source of the first resistor R1 is connected to the power supply voltage VDD, and the other end of the first resistor R1 is connected to the common ground terminal voltage VSS.
  • the adaptive overshoot voltage suppression circuit 100 provided by the embodiment of the present invention is mainly used in a reference circuit, the following describes in detail the adaptive overshoot voltage suppression circuit 100 for the reference circuit provided with the adaptive overshoot voltage suppression circuit 100 working principle.
  • the reference circuit includes an adaptive overshoot voltage suppression circuit 100, a startup module 201 and a reference core module 202, and the input end of the adaptive overshoot voltage suppression circuit 100 is connected to a preset sampling point on the reference core module 202, The output terminal of the adaptive overshoot voltage suppression circuit 100 is connected to the preset adjustment point on the start-up module 201 .
  • the preset adjustment point on the reference circuit is the position where the starting module 201 outputs the starting current to the reference core module 202; the preset sampling point on the reference circuit is that the sampling voltage sampled from the reference core module 202 can make the first The position where the gate of the NMOS transistor MN1 is turned on.
  • the startup module 201 includes a third PMOS transistor MP20, a fourth PMOS transistor MP21, a fifth PMOS transistor MP22, a sixth PMOS transistor MP26, a fourth NMOS transistor MN20, a fifth NMOS transistor MN21, and a sixth NMOS transistor.
  • the reference core module 202 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a seventh PMOS transistor MP23, an eighth PMOS transistor MP24, and a ninth PMOS transistor MP25 , the seventh NMOS transistor MN23 , the eighth NMOS transistor MN24 , the ninth NMOS transistor MN25 , the tenth NMOS transistor MN26 , the third resistor R22 , the fourth resistor R23 , the fifth resistor R24 and the sixth resistor R25 .
  • the circuit structure of the start-up module 201 and the reference core module 202 is an existing mature technology, and the connection relationship thereof will not be repeated here.
  • the start-up module 201 is used to provide a current when the system is turned on or enabled, so that the reference core module 202 can quickly get rid of the initial state, so as to work in the designed working state.
  • the reference core module 202 is used to generate the reference voltage (also referred to as reference voltage) required by the system.
  • the working principle of the reference circuit after adding the adaptive overshoot voltage suppression circuit 100 is as follows:
  • the enable EN is the ground voltage VSS
  • the enable ENB is the power supply voltage VDD.
  • the third PMOS transistor MP20 and the sixth PMOS transistor MP26 are in the on state
  • the fourth NMOS transistor MN20 is in the off state.
  • the ninth NMOS transistor MN25 and the tenth NMOS transistor MN26 are in the conduction state, and the gate voltages of the seventh NMOS transistor MN23 and the eighth NMOS transistor MN24 and the sampling points obtained from the reference core module 202
  • the voltage V_monitor is all reduced to the ground voltage VSS; at the same time, the gate voltages of the seventh PMOS transistor MP23, the eighth PMOS transistor MP24 and the ninth PMOS transistor MP25 are increased to the power supply voltage VDD, so that the branch where it is located is turned off, that is, the current is zero;
  • the second NMOS transistor MN2 is in the conduction state, the potential of the electrode plate connected to the second NMOS transistor MN2 of the capacitor C1 is the ground voltage VSS, and the sampling voltage V_monitor is also grounded at this time Voltage VSS, the first NMOS transistor MN1 and the third NMOS transistor MN3 are in the off state,
  • the gate voltage of the PMOS transistor is turned on when it is at a low level, and the gate voltage of the NMOS transistor is turned on when it is at a high level, it is required that the third PMOS transistor MP20, the fourth NMOS transistor MN20, and the sixth PMOS transistor
  • the enabling signals provided by MP26, the ninth NMOS transistor MN25 and the tenth NMOS transistor MN26 need to ensure the required on-off state of these MOS transistors under the corresponding environment in the present invention.
  • the enable EN jumps from the ground voltage VSS to the power supply voltage VDD
  • the enable ENB jumps from the power supply voltage VDD to the ground voltage VSS.
  • the third PMOS transistor MP20, the sixth PMOS transistor MP26, the ninth NMOS transistor MN25, The tenth NMOS transistor MN26 transitions from the on state to the off state
  • the fourth NMOS transistor MN20 transitions from the off state to the on state; since the gate of the fifth PMOS transistor MP22 passes through the second resistor R21 and the fourth NMOS The transistor MN20 is connected to the ground voltage VSS, therefore, the gate voltage of the fifth PMOS transistor MP22 is close to the ground voltage VSS after enabling EN to jump from the ground voltage VSS to the power supply voltage VDD, so that the fifth PMOS transistor MP22 is at In the conduction state, at this time, the series branch of the fifth PMOS transistor MP22 and the fifth NMOS transistor MN21 of the branch where it is located is turned on to generate a pull-down starting current I
  • the pull-down current flowing in the sixth NMOS transistor MN22 is k*IDN0 (k is a proportional coefficient).
  • the series branch of the sixth NMOS transistor MN22 and the fourth PMOS transistor MP21 is turned on, resulting in the conduction of the fourth PMOS transistor MP21 and the fourth PMOS transistor MP21.
  • the gate voltages of the seventh PMOS transistor MP23, the eighth PMOS transistor MP24, and the ninth PMOS transistor MP25 start to drop from the power supply voltage VDD until they reach the threshold voltages of the seventh PMOS transistor MP23, the eighth PMOS transistor MP24, and the ninth PMOS transistor MP25.
  • the seventh PMOS transistor MP23, the eighth PMOS transistor MP24, and the ninth PMOS transistor MP25 are turned on, and the start-up current flowing through the eighth PMOS transistor MP24 is k*IDN0 (equivalent to the sixth NMOS transistor MN22 injected into the eighth PMOS transistor MP24), because the fourth PMOS transistor MP21, the seventh PMOS transistor MP23, the eighth PMOS transistor MP24, and the ninth PMOS transistor MP25 jointly form a PMOS proportional mirror current mirror, so the seventh PMOS transistor MP23 and the ninth PMOS transistor MP25
  • the start-up current IDN0 needs to be increased, so that the current in the reference core module 202 reaches the designed current value faster.
  • the start-up current IDN0 is non-linear, increasing the output current of the fifth PMOS transistor MP22 will cause a large overshoot of the reference voltage Vref output by the reference core module 202 .
  • the greater the start-up current injected by the sixth NMOS transistor MN22 into the eighth PMOS transistor MP24 the higher the instantaneous overshoot voltage of the sampling voltage V_monitor will be.
  • the adaptive overshoot voltage suppression circuit 100 when the adaptive overshoot voltage suppression circuit 100 enables EN to jump from the ground voltage VSS to the power supply voltage VDD and detects the overshoot voltage generated instantaneously by the sampling voltage V_monitor, the high-frequency signal of the sampling voltage V_monitor will pass through
  • the capacitor C1 is coupled to the drain terminal of the first NMOS transistor MN1.
  • the sampling voltage V_monitor input to the gate of the first NMOS transistor MN1 is greater than the threshold voltage VTHN1 of the first NMOS transistor MN1, and the sampling voltage V_monitor is the same as the first NMOS transistor MN1
  • the difference of the drain voltage of the first NMOS transistor MN1 is less than the threshold voltage VTHN1 of the first NMOS transistor MN1
  • the first NMOS transistor MN1 is in the saturation region.
  • the overcharge voltage of the sampled sampling voltage V_monitor increases the equivalent load capacitance at the sampling point (corresponding to the sampling voltage V_monitor) of the reference core module 202 by A times, thereby reducing the overshoot voltage during the startup process of the reference circuit;
  • the drain voltage VD1 of the first NMOS transistor MN1 will increase to the sampling voltage V_monitor, and as the drain voltage VD1 of the first NMOS transistor MN1 increases, the gate voltage of the
  • I MP1 represents the current in the first PMOS transistor MP1
  • ⁇ represents the proportional coefficient
  • V TH3 represents the threshold voltage of the third NMOS transistor MN3
  • ⁇ n represents the channel mobility of carriers
  • C ox represents the capacitance of the gate oxide layer per unit area
  • the injection of V_fb is superposed with the current in the sixth NMOS transistor MN22.
  • the sixth NMOS transistor MN22 Since the current in the sixth NMOS transistor MN22 is equal to the sum of the current in the second PMOS transistor MP2 and the starting current injected into the eighth PMOS transistor MP24, the sixth NMOS transistor The current in MN22 remains unchanged, because the current in the second PMOS transistor MP2 reflects the voltage overshoot of the sampling voltage V_monitor, when the voltage overshoot of the sampling voltage V_monitor, the current in the second PMOS transistor MP2 increases accordingly to reduce The start-up current injected by the sixth NMOS transistor MN22 into the eighth PMOS transistor MP24 is reduced, thereby suppressing the overshoot of the reference voltage output by the reference circuit.
  • the change of the start-up current injected by the sixth NMOS transistor MN22 to the eighth PMOS transistor MP24, I S0 in the figure indicates that when the adaptive overshoot voltage suppression circuit 100 is not used during the start-up process of the reference circuit, the sixth NMOS transistor The startup current injected by MN22 to the eighth PMOS transistor MP24; I S represents the startup current injected by the sixth NMOS transistor MN22 to the eighth PMOS transistor MP24 when the adaptive overshoot voltage suppression circuit 100 is used in the startup process of the reference circuit; it is not difficult to find , the startup current injected by the sixth NMOS transistor MN22 into the eighth PMOS transistor MP24 can be reduced by using the adaptive overshoot voltage suppression circuit 100 .
  • the fifth PMOS transistor MP22 When the power supply voltage VDD When the difference from the gate voltage Vs of the fifth PMOS transistor MP22 is less than the threshold voltage VTHP of the fifth PMOS transistor MP22, the fifth PMOS transistor MP22 is in an off state, so that the currents in the fifth NMOS transistor MN21 and the sixth NMOS transistor MN22 is zero, the sixth NMOS transistor MN22 is in the off state, no start-up current is injected into the eighth PMOS transistor MP24, and the current in the eighth PMOS transistor MP24 is only controlled by the seventh PMOS transistor MP23 and the eighth PMOS transistor MP23 of the reference core module 202.
  • the loop formed by the transistor MP24, the seventh NMOS transistor MN23 and the eighth NMOS transistor MN24 provides the normal startup of the reference circuit to output a stable reference voltage Vref.
  • FIG. 5 shows the simulated waveform of the reference voltage Vref output during the start-up process of the reference circuit under the condition of normal temperature and pressure. It is not difficult to find that the overshoot of the reference voltage Vref output by the reference circuit can be effectively suppressed by using the adaptive overshoot voltage suppression circuit 100 .
  • the self-adaptive overshoot voltage suppression circuit provided by the present invention can also be applied to fast-start related circuits to detect voltage in real time and effectively suppress the rapid response of voltage overshoot, which will not be described in detail here.
  • the adaptive overshoot voltage suppression circuit provided by the embodiment of the present invention can be used in an integrated circuit chip.
  • the specific structure of the power suppression circuit in the integrated circuit chip will not be described in detail here.
  • the above adaptive overshoot voltage suppression circuit can also be used in a communication terminal as an important part of a radio frequency integrated circuit.
  • the communication terminal mentioned here refers to computer equipment that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, including mobile phones, notebook computers, tablet computers, and vehicle-mounted computers.
  • the technical solution provided by the present invention is also applicable to other applications of radio frequency integrated circuits, such as communication base stations and the like.
  • the self-adaptive overshoot voltage suppression circuit, reference circuit, chip and communication terminal provided by the present invention generate a transient high-frequency induced voltage according to the sampling voltage output by the reference circuit to be tested in real time during the start-up process of the reference circuit to be tested , and converted into the corresponding pull-up current, injected into the reference circuit to be tested, and superimposed with the pull-down start-up current of the reference circuit to be tested, so as to reduce the non-linear start-up current at the start-up moment of the reference circuit to be tested, thus ensuring to a certain extent While the reference circuit satisfies the timing requirement, it effectively suppresses the overshooting fast response of the reference voltage output by the reference circuit.

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Abstract

一种自适应过冲电压抑制电路（100）、基准电路、芯片及通信终端。该自适应过冲电压抑制电路（100）包括过冲电压抑制单元（1001）、电压-电流转换单元（1002），过冲电压抑制单元（1001）的输入端连接待测基准电路上预设的采样点，过冲电压抑制单元（1001）的输出端连接电压-电流转换单元（1002）的输入端，电压-电流转换单元（1002）的输出端连接待测基准电路上预设的调节点。根据实时检测的待测基准电路输出的采样电压，产生瞬态高频感应的电压，并转换成相应的上拉电流，注入到待测基准电路中，与待测基准电路的下拉启动电流叠加，以减小待测基准电路启动瞬间的非线性启动电流，从而在保证基准电路满足时序要求的同时，对基准电路输出的参考电压过冲快速响应进行有效抑制。

Description

自适应过冲电压抑制电路、基准电路、芯片及通信终端 技术领域
本发明涉及一种自适应过冲电压抑制电路，同时也涉及包括该自适应过冲电压抑制电路的基准电路、集成电路芯片及相应的通信终端，属于集成电路技术领域。
背景技术
随着集成电路的工艺节点不断地推进以及5G技术的推广和发展，在5G系统中对设备时序响应的要求越来越高，从而对设备内部各个电路模块响应时间提出了挑战。尤其在PA(Power Amplifer，功率放大器)系统中，不仅需要满足严苛的响应时间，而且要求为其提供的供电电压不能有较大的过冲。
通常在电路系统中，为了获得快速的系统响应，系统会产生较大的过冲电压或电流来实现，但是在PA系统中，当为其提供的供电电压或电流有较大过冲时，会对其寿命和性能造成严重影响。众所周知，PA系统由低压差线性稳压电路提供供电电压，而该电路所需的参考电压由基准电路提供，因此，设计一个能快速响应，且过冲较小的基准电路，对低压差线性稳压电路为PA系统提供稳定的供电电压具有非常大的意义。
发明内容
本发明所要解决的首要技术问题在于提供一种自适应过冲电压抑制电路。
本发明所要解决的另一技术问题在于提供一种包括自适应过冲电压抑制电路的基准电路、芯片及通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种自适应过冲电压抑制电路，包括过冲电压抑制单元、电压-电流转换单元，所述过冲电压抑制单元的输入端连接待测基准电路上预设的采样点，所述过冲电压抑制单元的输出端连接所述电压-电流转换单元的输入端，所述电压-电流转换单元的输出端连接所述待测基准电路上预设的调节点；
在所述待测基准电路启动过程中，所述过冲电压抑制单元根据从所述待测基准电路获取的采样电压，产生瞬态高频感应的电压，经过所述电压-电流转换单元转换为相应的上拉电流，注入到所述待测基准电路中，与所述待测基准电路的下拉启动电流叠加，减小所述待测基准电路启动瞬间的非线性启动电流。
其中较优地，所述过冲电压抑制单元包括电容、第一NMOS管、第二NMOS管，所述电容的一端连接所述采样点和所述第一NMOS管的栅极，所述电容的另一端连接所述第一NMOS管、所述第二NMOS管的漏极，所述第二NMOS管的栅极连接外部的使能电路，所述第一NMOS管、所述第二NMOS管的源极连接公共接地端电压。
其中较优地，所述电压-电流转换单元包括第三NMOS管、第一电阻、第一PMOS管和第二PMOS管，所述第三NMOS管的栅极连接所述第一NMOS管、所述第二NMOS管的漏极和所述电容的另一端，所述第三NMOS管的源极连接所述第一电阻的一端，所述第三NMOS管的漏极连接所述第一PMOS管的漏极、栅极和所述第二PMOS管的栅极，所述第二PMOS管的漏极连接所述调节点，所述第一PMOS管和所述第二PMOS管的源极连接电源电压，所述第一电阻的另一端连接所述公共接地端电压。
根据本发明实施例的第二方面，提供一种基准电路，包括启动模块、基准核心模块和上述的自适应过冲电压抑制电路，所述自适应过冲电压抑制电路的输入端连接所述基准核心模块上预设的采样点，所述自适应过冲电压抑制电路的输出端连接所述启动模块上预设的调节点。
其中较优地，所述调节点为所述启动模块向所述基准核心模块输出启动电流的位置。
其中较优地，所述采样点为从所述基准核心模块上采样的采样电压使得第一NMOS管栅极导通的位置。
根据本发明实施例的第三方面，提供一种集成电路芯片，所述集成电路芯片包括上述的基准电路。
根据本发明实施例的第四方面，提供一种通信终端，所述通信终端中包括上述的基准电路。
本发明所提供的自适应过冲电压抑制电路、基准电路、芯片及通信终端在待测基准电路启动过程中，根据实时检测的待测基准电路输出的采样电压，产生瞬态高频感应的电压，并转换成相应的上拉电流，注入到待测基准电路中，与待测基准电路的下拉启动电流叠加，以减小待测基准电路启动瞬间的非线性启动电流，从而在一定程度上保证基准电路满足时序要求的同时，对基准电路输出的参考电压过冲快速响应进行有效抑制。
附图说明
图1为本发明实施例提供的自适应过冲电压抑制电路的电路原理图；
图2为本发明实施例提供的基准电路的原理框图；
图3为本发明实施例提供的基准电路中，启动模块和基准核心模块的电路原理图；
图4为本发明实施例中电流变化曲线图；
图5为本发明实施例所得到的基准电路启动仿真波形图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
在基准电路启动过程中，为了实现对该电路输出的参考电压过冲快速响应并进行有效抑制，如图1所示，本发明实施例提供了一种自适应过冲电压抑制电路100，至少包括过冲电压抑制单元1001、电压-电流转换单元1002，过冲电压抑制单元1001的输入端连接待测基准电路上预设的采样点，过冲电压抑制单元1001的输出端连接电压-电流转换单元1002的输入端，电压-电流转换单元1002的输出端连接待测基准电路上预设的调节点。
在待测基准电路启动过程中，过冲电压抑制单元1001根据从待测基准电路获取的采样电压，产生瞬态高频感应的电压，经过电压-电流转换单元1002转换为相应的上拉电流，注入到待测基准电路中，与待测基准电路的下拉启动电流叠加，以减小待测基准电路启动瞬间的非线性启动电流，从而抑制待测基准电路输出的参考电压的过冲。
如图1所示，过冲电压抑制单元1001包括电容C1、第一NMOS管 MN1、第二NMOS管MN2；电容C1的一端作为过冲电压抑制单元1001的输入端，用于连接待测基准电路上预设的采样点和第一NMOS管MN1的栅极，电容C1的另一端连接第一NMOS管MN1、第二NMOS管MN2的漏极，第二NMOS管MN2的栅极连接外部的使能电路，第一NMOS管MN1、第二NMOS管MN2的源极连接公共接地端电压VSS。
如图1所示，电压-电流转换单元1002包括第三NMOS管MN3、第一电阻R1、第一PMOS管MP1和第二PMOS管MP2；第三NMOS管MN3的栅极连接第一NMOS管MN1、第二NMOS管MN2的漏极和电容C1的另一端，第三NMOS管MN3的源极连接第一电阻R1的一端，第三NMOS管MN3的漏极连接第一PMOS管MP1的漏极、栅极和第二PMOS管MP2的栅极，第二PMOS管MP2的漏极作为过冲电压抑制单元1001连接待测基准电路上预设的调节点，第一PMOS管MP1和第二PMOS管MP2的源极连接电源电压VDD，第一电阻R1的另一端连接公共接地端电压VSS。
由于本发明实施例提供的自适应过冲电压抑制电路100主要应用在基准电路中，下面针对设置有该自适应过冲电压抑制电路100的基准电路，详细说明自适应过冲电压抑制电路100的工作原理。
如图2所示，基准电路包括自适应过冲电压抑制电路100、启动模块201和基准核心模块202，自适应过冲电压抑制电路100的输入端连接基准核心模块202上预设的采样点，自适应过冲电压抑制电路100的输出端连接启动模块201上预设的调节点。
本发明中，基准电路上预设的调节点为启动模块201向基准核心模块202输出启动电流的位置；基准电路上预设的采样点为从基准核心模块202上采样的采样电压可以使得第一NMOS管MN1栅极导通的位置。
如图3所示，启动模块201包括第三PMOS管MP20、第四PMOS管MP21、第五PMOS管MP22、第六PMOS管MP26、第四NMOS管MN20、第五NMOS管MN21、第六NMOS管MN22和第二电阻R21；基准核心模块202包括第一三极管Q1、第二三极管Q2、第三三极管Q3、第七PMOS管MP23、第八PMOS管MP24、第九PMOS管MP25、第七NMOS管MN23、第八NMOS管MN24、第九NMOS管MN25、第十NMOS管MN26、第三电阻R22、第四电阻R23、第五电阻R24和第六电阻R25。其中，启动模块 201和基准核心模块202的电路结构为现有成熟技术，不再赘述其连接关系。
其中，启动模块201，用于在系统开机或者使能的时候，提供一个电流，使得基准核心模块202能够快速摆脱初始状态，从而工作在所设计的工作状态。基准核心模块202，用于产生系统所需要的参考电压(也称基准电压)。
加入自适应过冲电压抑制电路100后的基准电路的工作原理如下：
当使能EN为接地电压VSS时，使能ENB为电源电压VDD，此时在启动模块201中，第三PMOS管MP20和第六PMOS管MP26处于导通状态，第四NMOS管MN20处于关断状态；使得流过第二电阻R21的电流增加，进而将第五PMOS管MP22的栅极电压增加到电源电压VDD，从而关断第五PMOS管MP22所在支路，由于第五NMOS管MN21和第六NMOS管MN22构成比例镜像电流源，因此，第五NMOS管MN21和第六NMOS管MN22中电流为零；同时，由于第四NMOS管MN20处于关断状态，使得其所在支路电流也为零。在基准核心模块202中，第九NMOS管MN25与第十NMOS管MN26处于导通状态，将第七NMOS管MN23、第八NMOS管MN24的栅极电压以及从基准核心模块202采样点获取的采样电压V_monitor全部减小至接地电压VSS；同时第七PMOS管MP23、第八PMOS管MP24和第九PMOS管MP25的栅极电压被增加到电源电压VDD，使其所在的支路关断，即电流为零；在自适应过冲电压抑制电路100中，第二NMOS管MN2处于导通状态，电容C1与第二NMOS管MN2相连的极板电位为接地电压VSS，此时采样电压V_monitor也为接地电压VSS，第一NMOS管MN1与第三NMOS管MN3处于截止状态，由于第一PMOS管MP1和第二PMOS管MP2构成比例镜像电流源，因此第一PMOS管MP1和第二PMOS管MP2中电流为零。
其中，由于PMOS管的栅极电压为低电平时会导通，NMOS管的栅极电压为高电平时会导通，因此要求为第三PMOS管MP20、第四NMOS管MN20、第六PMOS管MP26、第九NMOS管MN25与第十NMOS管MN26提供的使能信号，需要保证这些MOS管在本发明中相应环境下所需处于的通断状态。
当使能EN由接地电压VSS跳变到电源电压VDD时，使能ENB由电 源电压VDD跳变到接地电压VSS，此时第三PMOS管MP20、第六PMOS管MP26、第九NMOS管MN25、第十NMOS管MN26由导通状态跳变为关断状态，第四NMOS管MN20由关断状态跳变到导通状态；由于第五PMOS管MP22的栅极通过第二电阻R21和第四NMOS管MN20接到接地电压VSS，因此，第五PMOS管MP22的栅电压在使能EN由接地电压VSS跳变到电源电压VDD之后，其栅极电压接近接地电压VSS，使得第五PMOS管MP22处于导通状态，此时其所在支路第五PMOS管MP22、第五NMOS管MN21串联支路导通，产生下拉启动电流IDN0，第五NMOS管MN21和第六NMOS管MN22构成比例镜像电流源，因此第六NMOS管MN22中流过的下拉电流为k*IDN0(k为比例系数)，此时第六NMOS管MN22与第四PMOS管MP21所在串联支路导通，导致第四PMOS管MP21、第七PMOS管MP23、第八PMOS管MP24、第九PMOS管MP25的栅极电压从电源电压VDD开始下降，直到达到第七PMOS管MP23、第八PMOS管MP24、第九PMOS管MP25的阈值电压，使得第七PMOS管MP23、第八PMOS管MP24、第九PMOS管MP25导通，并且流过第八PMOS管MP24的启动电流为k*IDN0(相当于第六NMOS管MN22注入到了第八PMOS管MP24中)，由于第四PMOS管MP21、第七PMOS管MP23、第八PMOS管MP24、第九PMOS管MP25共同组成PMOS比例镜像电流镜，因此第七PMOS管MP23和第九PMOS管MP25中的电流为ID23＝ID25＝k*IDN0，第四PMOS管MP21中的电流为ID21＝k2*IDN0(k2为比例系数)。从上面分析可以得出，如果提升基准电路输出电压的建立速度，就需要将启动电流IDN0增大，从而更快地使基准核心模块202中的电流达到所设计的电流值。但是，启动电流IDN0是非线性的，增大第五PMOS管MP22的输出电流，会导致基准核心模块202输出的参考电压Vref产生较大的过冲。并且，第六NMOS管MN22向第八PMOS管MP24中注入的启动电流越大，会导致采样电压V_monitor在瞬间产生的过冲电压越高。
如图1所示，自适应过冲电压抑制电路100在使能EN由接地电压VSS跳变到电源电压VDD检测到采样电压V_monitor瞬间产生的过冲电压时，采样电压V_monitor的高频信号会通过电容C1耦合在第一NMOS管MN1的漏端，此时若输入到第一NMOS管MN1栅极的采样电压V_monitor大于第一NMOS管MN1的阈值电压VTHN1,且采样电压 V_monitor与第一NMOS管MN1的漏极电压的差值小于第一NMOS管MN1的阈值电压VTHN1时，第一NMOS管MN1处于饱和区，此时由于第一NMOS管MN1具有较高的增益A＝gm1*ro1(其中，gm1为第一NMOS管MN1的跨导，ro1为第一NMOS管MN1的输出阻抗)以及miller效应的作用，使得电容C1在第一NMOS管MN1的栅极等效电容被增大了A倍，因此采样到的采样电压V_monitor的过充电压将基准核心模块202的采样点(对应采样电压V_monitor)处的等效负载电容增大了A倍，从而减小基准电路启动过程中的的过冲电压；另外，在这一过程中，由于电容C1两端的电压不能发生突变，因此第一NMOS管MN1的漏极电压VD1会增大到采样电压V_monitor，并且随着第一NMOS管MN1的漏极电压VD1的增大，使得第三NMOS管MN3的栅极电压增大，达到第三NMOS管MN3的阈值电压后，第三NMOS管MN3会导通，第三NMOS管MN3与第一电阻R1构成共源放大器(第一电阻R1用于防止第三NMOS管MN3中的电流随第一NMOS管MN1的漏极电压VD1的增大而上升过快)，将第一NMOS管MN1的漏极电压VD1转换为电流,该电流会流入第一PMOS管MP1中，如式(1)所示。
Figure PCTCN2022106888-appb-000001
上式中，I MP1表示第一PMOS管MP1中的电流，α表示比例系数，V TH3表示第三NMOS管MN3的阈值电压，
Figure PCTCN2022106888-appb-000002
μ n表示载流子的沟道迁移率，C ox表示单位面积的栅氧化层电容，
Figure PCTCN2022106888-appb-000003
表示第三NMOS管MN3的宽长比。
由于第一PMOS管MP1和第二PMOS管MP2构成比例镜像电流源，因此第二PMOS管MP2中电流为IDP2＝k3*IMP1，该电流为上拉电流，其会从启动模块201上的调节点V_fb注入，与第六NMOS管MN22中的电流进行叠加，由于第六NMOS管MN22中的电流等于第二PMOS管MP2中电流与注入到第八PMOS管MP24的启动电流之和，第六NMOS管MN22中的电流不变，由于第二PMOS管MP2中电流反映的是采样电压V_monitor的电压过冲，当采样电压V_monitor的电压过冲时，第二PMOS管MP2中的电流相应增大，以减小第六NMOS管MN22向第八PMOS 管MP24注入的启动电流，从而抑制基准电路输出的参考电压的过冲。
如图4示出的第六NMOS管MN22向第八PMOS管MP24注入的启动电流的变化，图中I S0表示基准电路启动过程中未使用自适应过冲电压抑制电路100时，第六NMOS管MN22向第八PMOS管MP24注入的启动电流；I S表示基准电路启动过程中使用自适应过冲电压抑制电路100时，第六NMOS管MN22向第八PMOS管MP24注入的启动电流；不难发现，使用自适应过冲电压抑制电路100可以降低第六NMOS管MN22向第八PMOS管MP24注入的启动电流。
在实现抑制基准电路输出的参考电压的过冲后，当第七PMOS管MP23、第八PMOS管MP24中电流达到所设计的稳态电流值IB时，第四PMOS管MP21中的电流ID21在第二电阻R21和第四NMOS管MN20上产生电压为第五PMOS管MP22的栅极电压Vs＝k2*IB*(R21+Rds20)，Rds20为第四NMOS管MN20的导通电阻，当电源电压VDD与第五PMOS管MP22的栅极电压Vs之差小于第五PMOS管MP22的阈值电压VTHP时，第五PMOS管MP22处于关断状态，使得第五NMOS管MN21和第六NMOS管MN22中的电流为零，第六NMOS管MN22处于关断状态，不再向第八PMOS管MP24中注入启动电流，第八PMOS管MP24中的电流仅由基准核心模块202的第七PMOS管MP23、第八PMOS管MP24、第七NMOS管MN23和第八NMOS管MN24所组成的回路提供，使得基准电路正常启动，以输出稳定的参考电压Vref。
图5所示为在常温常压的情况下，基准电路启动过程中输出的参考电压Vref的仿真波形。不难发现，使用自适应过冲电压抑制电路100可以对基准电路输出的参考电压Vref的过冲进行有效抑制。
需要强调的是，本发明所提供的自适应过冲电压抑制电路还可以应用到快速启动的相关电路中，实时检测电压且能够对电压过冲快速响应进行有效抑制，在此不再详述。
另外，本发明实施例提供的自适应过冲电压抑制电路可以被用在集成电路芯片中。对于该集成电路芯片中电源抑制电路的具体结构，在此不再一一详述。
上述自适应过冲电压抑制电路还可以被用在通信终端中，作为射频集成电路的重要组成部分。这里所说的通信终端是指可以在移动环 境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他射频集成电路应用的场合，例如通信基站等。
本发明所提供的自适应过冲电压抑制电路、基准电路、芯片及通信终端在待测基准电路启动过程中，根据实时检测的待测基准电路输出的采样电压，产生瞬态高频感应的电压，并转换成相应的上拉电流，注入到待测基准电路中，与待测基准电路的下拉启动电流叠加，以减小待测基准电路启动瞬间的非线性启动电流，从而在一定程度上保证基准电路满足时序要求的同时，对基准电路输出的参考电压过冲快速响应进行有效抑制。
以上对本发明所提供的自适应过冲电压抑制电路、基准电路、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (8)

  1. 一种自适应过冲电压抑制电路，其特征在于包括过冲电压抑制单元、电压-电流转换单元，所述过冲电压抑制单元的输入端连接待测基准电路上预设的采样点，所述过冲电压抑制单元的输出端连接所述电压-电流转换单元的输入端，所述电压-电流转换单元的输出端连接所述待测基准电路上预设的调节点；
    在所述待测基准电路启动过程中，所述过冲电压抑制单元根据从所述待测基准电路获取的采样电压，产生瞬态高频感应的电压，经过所述电压-电流转换单元转换为相应的上拉电流，注入到所述待测基准电路中，与所述待测基准电路的下拉启动电流叠加，以减小所述待测基准电路启动瞬间的非线性启动电流。
  2. 如权利要求1所述的自适应过冲电压抑制电路，其特征在于：
    所述过冲电压抑制单元包括电容、第一NMOS管、第二NMOS管，所述电容的一端连接所述采样点和所述第一NMOS管的栅极，所述电容的另一端连接所述第一NMOS管、所述第二NMOS管的漏极，所述第二NMOS管的栅极连接外部的使能电路，所述第一NMOS管、所述第二NMOS管的源极连接公共接地端电压。
  3. 如权利要求2所述的自适应过冲电压抑制电路，其特征在于：
    所述电压-电流转换单元包括第三NMOS管、第一电阻、第一PMOS管和第二PMOS管，所述第三NMOS管的栅极连接所述第一NMOS管、所述第二NMOS管的漏极和所述电容的另一端，所述第三NMOS管的源极连接所述第一电阻的一端，所述第三NMOS管的漏极连接所述第一PMOS管的漏极、栅极和所述第二PMOS管的栅极，所述第二PMOS管的漏极连接所述调节点，所述第一PMOS管和所述第二PMOS管的源极连接电源电压，所述第一电阻的另一端连接所述公共接地端电压。
  4. 一种基准电路，其特征在于包括启动模块、基准核心模块和权利要求1～3中任意一项所述的自适应过冲电压抑制电路，所述自适应过冲电压抑制电路的输入端连接所述基准核心模块上预设的采样点，所述自适应过冲电压抑制电路的输出端连接所述启动模块上预设的调节点。
  5. 如权利要求4所述的基准电路，其特征在于：
    所述调节点为所述启动模块向所述基准核心模块输出启动电流的位置。
  6. 如权利要求4所述的基准电路，其特征在于：
    所述采样点为从所述基准核心模块上采样的采样电压使得第一NMOS管栅极导通的位置。
  7. 一种集成电路芯片，其特征在于包括权利要求4～6中任意一项所述的基准电路。
  8. 一种通信终端，其特征在于包括权利要求4～6中任意一项所述的基准电路。
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