WO2023005806A1 - 一种具有电源抑制功能的ldo电路、芯片及通信终端 - Google Patents

一种具有电源抑制功能的ldo电路、芯片及通信终端 Download PDF

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WO2023005806A1
WO2023005806A1 PCT/CN2022/107152 CN2022107152W WO2023005806A1 WO 2023005806 A1 WO2023005806 A1 WO 2023005806A1 CN 2022107152 W CN2022107152 W CN 2022107152W WO 2023005806 A1 WO2023005806 A1 WO 2023005806A1
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Prior art keywords
pmos transistor
transistor
drain
resistor
power supply
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PCT/CN2022/107152
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English (en)
French (fr)
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高晨阳
林升
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唯捷创芯 （天津）电子技术股份有限公司
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Priority to KR1020247000379A priority Critical patent/KR20240016433A/ko
Priority to EP22848411.9A priority patent/EP4379496A1/en
Publication of WO2023005806A1 publication Critical patent/WO2023005806A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to an LDO circuit with a power supply suppression function, and also relates to an integrated circuit chip including the LDO circuit and a corresponding communication terminal, belonging to the technical field of integrated circuits.
  • a communication terminal includes a CPU, a power management chip, a memory chip, a clock chip, a peripheral circuit and a radio frequency chip, and all parts are powered by the same power supply.
  • the CPU, power management chip, memory chip, clock chip and peripheral circuits will generate some intermediate frequency signals (100KHz ⁇ 10MHz), these intermediate frequency signals will enter the voltage bias circuit of the RF chip through the power supply, and then interfere and deteriorate the modulation spectrum of the RF chip , switching spectrum and noise performance, which seriously limit the development of radio frequency communication technology.
  • a low dropout regulator is a commonly used voltage bias circuit for RF chips. Its main function is to provide a DC voltage operating point for RF chips. In order to reduce the interference of the internal frequency signal of the communication terminal to the radio frequency chip and enhance the suppression ability of the power supply to the intermediate frequency signal, it is necessary to provide a high-performance intermediate frequency power supply rejection (Power Supply Rejection, PSR for short) LDO circuit.
  • PSR Power Supply Rejection
  • the primary technical problem to be solved by the present invention is to provide an LDO circuit with power supply suppression function.
  • Another technical problem to be solved by the present invention is to provide a chip and a communication terminal including an LDO circuit with a power supply suppression function.
  • an LDO circuit with a power supply suppression function including a bandgap reference module provided with an intermediate frequency zero adjustment unit, an amplification module provided with an intermediate frequency zero generation unit, and a power output module, the The bandgap reference module is connected to the amplifying module, and the amplifying module is connected to the power output module;
  • the bandgap reference module utilizes the frequency of the intermediate frequency zero point adjusted by the intermediate frequency zero point adjustment unit to generate a reference voltage with a preset temperature coefficient and output it to the amplification module; wherein, the reference voltage is used as the reference voltage of the LDO circuit
  • the reference voltage cooperates with the zero point generated by the intermediate frequency zero point generation unit, the frequency of the zero point is an intermediate frequency, and adjusts the power supply suppression of the LDO circuit at the intermediate frequency.
  • the bandgap reference module includes a startup unit, a PTAT current generation unit, an output unit, and an intermediate frequency zero point adjustment unit; the output terminals of the startup unit and the intermediate frequency zero point adjustment unit are connected to the PTAT current generation unit
  • the input terminal, the output terminal of the PTAT current generating unit is connected to the input terminal of the output unit, and the output terminal of the output unit is connected to the input terminal of the amplification module.
  • the startup unit includes a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third The NMOS transistor and the fourth NMOS transistor; the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage, the drain of the second PMOS transistor is connected to one end of the first resistor, and the first PMOS transistor is connected to the first resistor.
  • the other end of the resistor is connected to the drain of the first PMOS transistor, the gate of the fourth PMOS transistor and one end of the second resistor, and the other end of the second resistor is connected to the gate of the first NMOS transistor electrode and drain, the drain of the fourth PMOS transistor is connected to the gate and drain of the third NMOS transistor, the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor, the The source of the fourth PMOS transistor and the drain of the third PMOS transistor are connected to each other, and the gate of the second PMOS transistor is connected to the PTAT current generating unit, the first PMOS transistor, the first PMOS transistor.
  • the gates of the two NMOS transistors and the third PMOS transistor are connected to an external enable signal, the sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to a power supply voltage, and the first PMOS transistor is connected to a power supply voltage.
  • the PTAT current generating unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third resistor, a fourth resistor, a fifth NMOS transistor, The sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the fifth resistor, the first bipolar transistor, and the second bipolar transistor; the gate of the fifth PMOS transistor is connected to an external enable signal, so The drain of the fifth PMOS transistor, the gates of the sixth PMOS transistor, the seventh PMOS transistor and the second PMOS transistor, the drain of the ninth PMOS transistor, and one end of the third resistor connected to the output unit, the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor, the drain of the seventh PMOS transistor is connected to the source of the ninth PMOS transistor, The gates of the eighth PMOS transistor and the ninth PMOS transistor, the drain of the third PMOS transistor, the source of the fourth PMOS transistor, the other end of the third
  • the drain of the NMOS transistor the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the sixth NMOS transistor is connected to the emitter of the first bipolar transistor, and the source of the sixth NMOS transistor is connected to the emitter of the first bipolar transistor.
  • the source of the eighth NMOS transistor is connected to the emitter of the second bipolar transistor through the fifth resistor, and the sources of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are connected to power supply voltage, the bases and collectors of the first bipolar transistor and the second bipolar transistor are grounded.
  • the output unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a sixth resistor, a third bipolar transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor; the tenth PMOS transistor
  • the gate of the twelfth PMOS transistor is connected to the drain of the ninth PMOS transistor and the intermediate frequency zero point adjustment unit, the drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor,
  • the drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor, and the gate of the eleventh PMOS transistor and the thirteenth PMOS transistor are connected to the other end of the third resistor and
  • the drain of the eleventh PMOS transistor is connected to the amplification module with one end of the sixth resistor, and the other end of the sixth resistor is connected to the emitter of the third bipolar transistor. pole, the drain of the thirteenth PMOS transistor is connected to the amplification module, the source of the ten
  • the intermediate frequency zero point adjustment unit includes a first capacitor and a second capacitor, one end of the first capacitor and the second capacitor are connected to the power supply voltage, and the other end of the first capacitor is connected to the The gates of the sixth PMOS transistor, the seventh PMOS transistor, the tenth PMOS transistor, and the twelfth PMOS transistor, and the other end of the second capacitor is connected to the eighth PMOS transistor, the ninth PMOS transistor PMOS transistors, gates of the eleventh PMOS transistor and the thirteenth PMOS transistor.
  • the amplifying module includes a first-stage amplifying unit, a second-stage amplifying unit, and the intermediate frequency zero generating unit arranged between the first-stage amplifying unit and the second-stage amplifying unit, the The first stage amplifying unit is connected to the second stage amplifying unit and the power output module.
  • the intermediate frequency zero generating unit is composed of a tenth resistor and a fourth capacitor connected in series to ground.
  • an integrated circuit chip includes the above-mentioned LDO circuit with a power supply suppression function.
  • a communication terminal which includes the above-mentioned LDO circuit with a power supply suppression function.
  • the LDO circuit with power supply suppression function provided by the present invention aims at the power supply suppression at the intermediate frequency, cooperates with adjusting the intermediate frequency zero point adjustment unit in the bandgap reference module and the intermediate frequency zero point generation unit in the LDO circuit, so that the intermediate frequency power supply suppression performance is better. Optimization.
  • Using the LDO circuit suppressing the intermediate frequency power supply as the voltage bias circuit of the radio frequency chip can enhance the ability of the radio frequency chip power supply to suppress the intermediate frequency signal, thereby improving the working performance of the radio frequency chip.
  • Fig. 1 is the schematic diagram of the LDO circuit with power supply suppression function provided by the embodiment of the present invention
  • Fig. 2 is the circuit schematic diagram of the bandgap reference module in the LDO circuit with power supply suppression function provided by the embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of an amplification module and a power output module in an LDO circuit with a power supply suppression function provided by an embodiment of the present invention
  • Fig. 4 is the comparison diagram of the power supply suppression simulation results of the reference voltage output terminal of the bandgap reference module
  • FIG. 5 is a comparison diagram of power supply suppression simulation results of the voltage output terminal VOUT of the LDO circuit
  • FIG. 6 is an example diagram of a communication terminal using the LDO circuit with power supply suppression function.
  • the embodiment of the present invention provides an LDO circuit with a power supply suppression function, including an intermediate frequency zero point
  • the bandgap reference module 101 uses the intermediate frequency zero point adjustment unit 109 to adjust the frequency of the intermediate frequency zero point, generates a reference voltage with a preset temperature coefficient and has intermediate frequency power supply suppression, and outputs it to the amplification module 102 as a reference voltage for the LDO circuit, matching the intermediate frequency zero point
  • the frequency generated by the generation unit 105 for changing the frequency response of the amplifying module 102 at the intermediate frequency is the zero point of the intermediate frequency, so as to improve the performance of the intermediate frequency power supply suppression of the LDO circuit.
  • the bandgap reference module 101 includes a starting unit 106, a PTAT (Proportional To Absolute Temperature, proportional to absolute temperature) current generating unit 107, an output unit 108 and an intermediate frequency zero adjustment unit 109; the starting unit 106 and the intermediate frequency zero
  • the output end of the adjustment unit 109 is connected to the input end of the PTAT current generation unit 107
  • the output end of the PTAT current generation unit 107 is connected to the input end of the output unit 108
  • the output end of the output unit 108 is connected to the amplification module 102 .
  • the implementation process of the bandgap reference module 101 providing the amplifier module 102 with a preset temperature coefficient (generally zero temperature coefficient) and a reference voltage VREF suppressed by the intermediate frequency power supply is described in detail, and The fact that the bandgap reference module 101 also provides the bias current for the amplification module 102 is known in the art and will not be described in detail here.
  • the starting unit 106 is used to make the PTAT current generating unit 107 avoid the degeneracy point where the current is 0, so as to ensure that the PTAT current generating unit 107 starts normally and is stable.
  • the startup unit 106 includes a first PMOS transistor 201, a second PMOS transistor 202, a first resistor 203, a second resistor 204, a first NMOS transistor 205, a second NMOS transistor 206, a third PMOS transistor 207, The fourth PMOS transistor 208 , the third NMOS transistor 209 and the fourth NMOS transistor 210 .
  • each part of the startup unit 106 is as follows: the sources of the first PMOS transistor 201 and the second PMOS transistor 202 are connected to the power supply voltage VDD, the drain of the second PMOS transistor 202 is connected to one end of the first resistor 203, and the other end of the first resistor 203 One end is connected to the drain of the first PMOS transistor 201, the gate of the fourth PMOS transistor 208 and one end of the second resistor 204, the other end of the second resistor 204 is connected to the gate and drain of the first NMOS transistor 205, and the fourth PMOS
  • the drain of the tube 208 is connected to the gate and drain of the third NMOS tube 209, the gate of the fourth NMOS tube 210, the drain of the fourth NMOS tube 210, the source of the fourth PMOS tube 208 and the third PMOS tube 207
  • the drains of the transistors are connected to each other, and the gate of the second PMOS transistor 202 is connected to the corresponding position of the PTAT current generating unit
  • the gates of the first PMOS transistor 201, the second NMOS transistor 206 and the third PMOS transistor 207 are connected to the external Enable signal EN, the sources of the first PMOS transistor 201, the second PMOS transistor 202 and the third PMOS transistor 207 are connected to the power supply voltage VDD, the sources of the second NMOS transistor 206, the third NMOS transistor 209 and the fourth NMOS transistor 210 grounded.
  • the PTAT current generating unit 107 includes a fifth PMOS transistor 211, a sixth PMOS transistor 212, a seventh PMOS transistor 213, an eighth PMOS transistor 214, a ninth PMOS transistor 215, a third resistor 216, a fourth resistor 217 , fifth NMOS transistor 218 , sixth NMOS transistor 219 , seventh NMOS transistor 220 , eighth NMOS transistor 221 , fifth resistor 222 , first bipolar transistor 223 and second bipolar transistor 224 .
  • each part of the PTAT current generation unit 107 is as follows: the gate of the fifth PMOS transistor 211 is connected to an external enable signal, the drain of the fifth PMOS transistor 211, the sixth PMOS transistor 212, the seventh PMOS transistor 213 and the second PMOS transistor 213 The gate of the transistor 202, the drain of the ninth PMOS transistor 215, one end of the third resistor 216 and the corresponding position of the output unit 108 are connected to each other, the drain of the sixth PMOS transistor 212 is connected to the source of the eighth PMOS transistor 214, The drain of the seventh PMOS transistor 213 is connected to the source of the ninth PMOS transistor 215, the gates of the eighth PMOS transistor 214 and the ninth PMOS transistor 215, the drain of the third PMOS transistor 207, and the source of the fourth PMOS transistor 208 , the other end of the third resistor 216, the drain of the seventh NMOS transistor 220 and the corresponding position of the output unit 108 are connected to each other, the drain of the eighth PMOS transistor 214 is
  • the first PMOS transistor 201 , the second NMOS transistor 206 , the third PMOS transistor 207 and the fifth PMOS transistor 211 are used as enable control transistors to control the on and off of the bandgap reference module 101 .
  • the enable signal EN When the enable signal EN is at low level, the first PMOS transistor 201 , the third PMOS transistor 207 and the fifth PMOS transistor 211 are turned on, the second NMOS transistor 206 is turned off, and the bandgap reference module 101 is turned off.
  • the enable signal EN changes from low level to high level, the first PMOS transistor 201 , the third PMOS transistor 207 and the fifth PMOS transistor 211 are turned off, and the second NMOS transistor 206 is turned on.
  • the branch composed of the second PMOS transistor 202, the first resistor 203, the second resistor 204, the first NMOS transistor 205, and the second NMOS transistor 206 is turned on, the voltage VA at the node A is pulled down, and the fourth PMOS transistor 208
  • the third NMOS transistor 209 and the fourth NMOS transistor 210 form a current mirror, the fourth NMOS transistor 210 is turned on, the voltage VB at the node B is pulled down, the eighth PMOS transistor 214 and the ninth PMOS transistor 215
  • the output unit 108 generates a reference voltage VREF and a reference current IBIAS based on the current proportional to temperature generated by the PTAT current generating unit 107 .
  • the output unit 108 includes a tenth PMOS transistor 227 , an eleventh PMOS transistor 228 , a sixth resistor 229 , a third bipolar transistor 230 , a twelfth PMOS transistor 231 and a thirteenth PMOS transistor 232 .
  • each part of the output unit 108 is as follows: the gates of the tenth PMOS transistor 227 and the gate of the twelfth PMOS transistor 231 are connected to the drain of the ninth PMOS transistor 215 and the intermediate frequency zero point adjustment unit 109, and the drain of the tenth PMOS transistor 227 is connected to the twelfth PMOS transistor 227.
  • the source of the eleventh PMOS transistor 228, the drain of the twelfth PMOS transistor 231 is connected to the source of the thirteenth PMOS transistor 232, the gates of the eleventh PMOS transistor 228 and the thirteenth PMOS transistor 232 are connected to the third resistor 216
  • the other end of the intermediate frequency zero point adjustment unit 109, the drain of the eleventh PMOS transistor 228 and one end of the sixth resistor 229 are connected to the amplification module 102 for providing it with a reference voltage VREF, and the other end of the sixth resistor 229 is connected to the third
  • the emitter of the bipolar transistor 230 and the drain of the thirteenth PMOS transistor 232 are connected to the amplifying module 102 for transmitting the reference current IBIAS to the amplifying module 102 to provide a bias current for it.
  • the tenth PMOS transistor 227 is connected to the amplifying module 102.
  • the sources of the twelve PMOS transistors 231 are connected to the power supply voltage VDD, and the base and collector of
  • the twelfth PMOS transistor 231 and the thirteenth PMOS transistor 232 respectively constitute a current mirror, copy the PTAT current of the PTAT current generating unit 107, and obtain the reference current IBIAS, which is used for Provide the amplification module 102 as a bias current.
  • the reference voltage VREF can be expressed as Where V BE is the base-emitter voltage of the third bipolar transistor 230, which is a voltage with a negative temperature coefficient, so adjusting the ratio of the fifth resistor 222 and the sixth resistor 229 can make the reference voltage VREF a zero
  • the temperature voltage is used to provide the amplification module 102 as a reference voltage.
  • the intermediate frequency zero point adjusting unit 109 is configured to adjust the frequency of the intermediate frequency zero point of the bandgap reference module 101 to improve the intermediate frequency power supply suppression performance of the bandgap reference module 101 .
  • the intermediate frequency zero point adjustment unit 109 includes a first capacitor 225 and a second capacitor 226. One end of the first capacitor 225 and the second capacitor 226 are connected to the power supply voltage VDD, and the other end of the first capacitor 225 is connected to the sixth PMOS transistor.
  • the gates of the seventh PMOS transistor 213, the tenth PMOS transistor 227, and the twelfth PMOS transistor 231, and the other end of the second capacitor 226 is connected to the eighth PMOS transistor 214, the ninth PMOS transistor 215, and the eleventh PMOS transistor 228 and the gate of the thirteenth PMOS transistor 232 .
  • the power supply voltage VDD passes through each PMOS transistor connected to the other end of the first capacitor 225 and the second capacitor 226, and the parasitic capacitances Cgs and Cgd of the gates have a branch to the reference voltage output terminal, and the branch will be produces a zero point.
  • the frequency of the zero point is determined by the product of the resistance (resistance of the PMOS transistor) and the capacitance on the branch.
  • the capacitance of the first capacitor 225 and the second capacitor 226 and the ratio of the two jointly determine the frequency of the intermediate frequency zero point, and adjust the capacitance and the capacitance of the first capacitor 225 and the second capacitor 226 for power supply suppression at the intermediate frequency.
  • the size of the ratio can achieve a better optimization effect, specifically through the following formula.
  • Rbg is the resistance on the intermediate frequency zero-point branch of the bandgap reference module 101
  • Cbg is the capacitance on the intermediate-frequency zero-point branch of the bandgap reference module 101
  • rds_227 is the equivalent AC resistance between the drain and source of the tenth PMOS transistor 227
  • r ds_228 is the equivalent AC resistance between the drain and source of the eleventh PMOS transistor 228,
  • C gs1_227 is the parasitic capacitance between the gate and source of the tenth PMOS transistor 227
  • C 225 is the capacitance of the first capacitor 225
  • C gd1_227 is the capacitance of the first capacitor 225.
  • the parasitic capacitance between the drain, // is the parallel symbol in the circuit.
  • the amplifying module 102 includes a first-stage amplifying unit 110, a second-stage amplifying unit 111, and an intermediate frequency zero generation unit 105 arranged between the first-stage amplifying unit 110 and the second-stage amplifying unit 111, the first
  • the stage amplifying unit 110 is connected to the second stage amplifying unit 111 and the power output module 103 .
  • the power output module 103 includes a power transistor 312, a sixteenth NMOS transistor 320, a third capacitor 315, a seventh resistor 316, and a feedback resistor network 112 composed of an eighth resistor Rf1 and a ninth resistor Rf2.
  • the gate of the power transistor 312 is connected to The drain of the sixteenth NMOS transistor 320, one end of the third capacitor 315 and the second-stage amplifying unit 111, the other end of the third capacitor 315 is connected to one end of the seventh resistor 316, and the other end of the seventh resistor 316 is connected to the power transistor 312 Drain, one end of the eighth resistor Rf1, the other end of the eighth resistor Rf1 is connected to one end of the ninth resistor Rf2, the first-stage amplifying unit 110, the other end of the ninth resistor Rf2 is grounded, the power transistor 312 and the sixteenth NMOS transistor
  • the source of the 320 is connected to the power supply voltage VDD, and the gate of the sixteenth NMOS transistor 320 is connected to an external enable signal.
  • the first-stage amplifying unit 110 includes an inverter 301, a ninth NMOS transistor 302, a tenth NMOS transistor 303, an eleventh NMOS transistor 304, a twelfth NMOS transistor 305, and a thirteenth NMOS transistor 306. , the fourteenth NMOS transistor 307 , the fourteenth PMOS transistor 308 , the fifteenth PMOS transistor 309 , and the sixteenth PMOS transistor 319 .
  • each part of the first-stage amplifying unit 110 is as follows: the input terminal of the inverter 301 is connected to the external enable signal, the output terminal of the inverter 301 is connected to the gate of the twelfth NMOS transistor 305, the ninth NMOS transistor 302 and The gate of the sixteenth PMOS transistor 319 is connected to an external enable signal, the drain of the ninth NMOS transistor 302 is connected to the drain of the thirteenth PMOS transistor 232 of the output unit 108, and the source of the ninth NMOS transistor 302 is connected to the tenth
  • the gate and drain of the NMOS transistor 303, the gate of the eleventh NMOS transistor 304, the second-stage amplifying unit 111, the drain of the twelfth NMOS transistor 305, and the drain of the eleventh NMOS transistor 304 is connected to the thirteenth NMOS transistor.
  • the sources of the NMOS transistor 306 and the fourteenth NMOS transistor 307, the gate of the thirteenth NMOS transistor 306 are connected to the drain of the eleventh PMOS transistor 228 of the output unit 108 and one end of the sixth resistor 229, the thirteenth NMOS transistor
  • the drain of 306 is connected to the gate and drain of the fourteenth PMOS transistor 308, the gate of the fifteenth PMOS transistor 309, the drain of the sixteenth PMOS transistor 319, and the drain of the fifteenth PMOS transistor 309 is connected to the tenth
  • the drains of the four NMOS transistors 307, the intermediate frequency zero generating unit 105 and the second-stage amplifying unit 111, the gate of the fourteenth NMOS transistor 307 are connected to the power output module 103, the fourteenth PMOS transistor 308, the fifteenth PMOS transistor 309,
  • the source of the sixteenth PMOS transistor 319 is connected to the power supply voltage VDD, and the sources of the tenth NMOS transistor 303 , the eleven
  • the second-stage amplifying unit 111 includes a fifteenth NMOS transistor 310 and a seventeenth PMOS transistor 311, the gate of the fifteenth NMOS transistor 310 is connected to the gate of the eleventh NMOS transistor 304, and the fifteenth The drain of the NMOS transistor 310 is connected to the drain of the seventeenth PMOS transistor 311 and the power output module 103, the gate of the seventeenth PMOS transistor 311 is connected to the drain of the fourteenth NMOS transistor 307 and the intermediate frequency zero-point generation unit 105, the tenth The source of the seventh PMOS transistor 311 is connected to the power supply voltage VDD, and the source of the fifteenth NMOS transistor 310 is grounded.
  • the first-stage amplifying unit 110, the second-stage amplifying unit 111, the power transistor 312, the eighth resistor Rf1 and the ninth resistor Rf2 form a negative feedback loop, so that the output voltage VOUT of the LDO circuit is affected by changes in the power supply voltage and load resistance Small.
  • the enable signal EN passes through the inverter 301 to obtain the enable signal ENB, and the enable signals EN and ENB control the ninth NMOS transistor 302, the twelfth NMOS transistor 305, the sixteenth PMOS transistor 319 and the The turn-on and turn-off of the sixteen NMOS transistors 320 is used to control the turn-on and turn-off of the first-stage amplifying unit 110 and the second-stage amplifying unit 111 .
  • the bandgap reference module 101 provides a bias current for the first stage amplifying unit 110 .
  • the tenth NMOS transistor 303 and the eleventh NMOS transistor 304, the tenth NMOS transistor 303 and the fifteenth NMOS transistor 310 respectively constitute a current mirror for copying the reference current IBIAS to the first-stage amplifying unit 110 and the second-stage amplifying unit 111 provides bias current.
  • the bandgap reference module 101 provides a reference voltage for the first stage amplifying unit 110 .
  • the first-stage amplifying unit 110 is a typical five-tube amplifier, wherein the thirteenth NMOS transistor 306 and the fourteenth NMOS transistor 307 are the input amplifier pair of the first-stage amplifying unit 110, and the fourteenth PMOS transistor 308, the fifteenth The PMOS transistor 309 is the current mirror load of the first-stage amplifying unit 110 .
  • the second-stage amplifying unit 111 is a common source amplifier, wherein the seventeenth PMOS transistor 311 is an amplifying transistor of the second-stage amplifying unit 111 .
  • the third capacitor 315 and the seventh resistor 316 form Miller compensation.
  • the eighth resistor Rf1 and the ninth resistor Rf2 form the feedback resistor network 33, and determine the output voltage of the LDO circuit together with the reference voltage VREF.
  • the tenth resistor 317 and the fourth capacitor 318 are connected in series to the ground to form the intermediate frequency zero generating unit 105. Its function is to generate a zero at the intermediate frequency. This zero can change the frequency response of the amplifying module 102 at the intermediate frequency to improve the LDO The power supply rejection performance of the circuit intermediate frequency.
  • the product of the tenth resistor 317 and the fourth capacitor 318 determines the frequency of the zero point, and the frequency of the zero point is specifically expressed as
  • the frequency of the zero point is specifically expressed as
  • Figure 4 is a comparison of the power supply rejection (PSR) simulation results of the Bandgap voltage output terminal of the bandgap reference module, where curve 1 is the power supply suppression simulation result before the bandgap reference module is added to the intermediate frequency zero adjustment unit, and curve 2 is the bandgap reference module adding the intermediate frequency zero adjustment
  • PSR power supply rejection
  • Fig. 5 is the comparison of the power supply suppression (PSR) simulation results of the voltage output terminal VOUT of the LDO circuit provided by the present invention, wherein curve 3 is the power supply suppression simulation result before the LDO circuit is added to the intermediate frequency zero generating unit, and curve 4 is the LDO circuit adding the intermediate frequency zero
  • PSR power supply suppression
  • the LDO circuit with power supply suppression function provided by the present invention can be used in integrated circuit chips.
  • the specific structure of the LDO circuit with power supply suppression function in the integrated circuit chip will not be described in detail here.
  • the above-mentioned LDO circuit with power supply suppression function can also be used in a communication terminal as an important part of a radio frequency integrated circuit.
  • the communication terminals mentioned here refer to devices that can be used in a mobile environment and support multiple communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, including mobile phones, notebook computers, tablet computers, and Internet of Vehicles terminals.
  • the technical solutions provided by the present invention are also applicable to other applications of radio frequency integrated circuits, such as communication base stations, intelligent networked vehicles, and the like.
  • the communication terminal includes at least a processor and a memory, and may further include a communication component, a sensor component, a power supply component, a multimedia component, and an input/output interface according to actual needs.
  • memory, communication components, sensor components, power supply components, multimedia components and input/output interfaces are all connected with the processor.
  • the memory can be Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic memory, flash memory, etc.
  • the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable logic gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing ( DSP) chips, etc.
  • CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable logic gate array
  • ASIC application-specific integrated circuit
  • DSP digital signal processing
  • the LDO circuit with power supply suppression function provided by the present invention is aimed at the power supply suppression at the intermediate frequency, cooperates to adjust the intermediate frequency zero point adjustment unit in the bandgap reference module and the intermediate frequency zero point generation unit in the LDO circuit, so that the intermediate frequency Power supply rejection performance is better optimized.
  • Using the LDO circuit suppressing the intermediate frequency power supply as the voltage bias circuit of the radio frequency chip can enhance the ability of the radio frequency chip power supply to suppress the intermediate frequency signal, thereby improving the working performance of the radio frequency chip.

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Abstract

一种具有电源抑制功能的LDO电路、芯片及通信终端。LDO电路包括设置有中频零点调整单元(109)的带隙基准模块(101)、设置有中频零点产生单元(105)的放大模块(102)和功率输出模块(103)，带隙基准模块(101)连接放大模块(102)，放大模块(102)连接功率输出模块(103)。针对中频处的电源抑制，配合调整带隙基准模块(101)中的中频零点调整单元(109)和LDO电路中的中频零点产生单元(105)，使中频电源抑制性能得到更好的优化。将中频电源抑制的LDO电路作为射频芯片的电压偏置电路，可增强射频芯片电源对中频信号的抑制能力，进而提升射频芯片的工作性能。

Description

一种具有电源抑制功能的LDO电路、芯片及通信终端 技术领域
本发明涉及一种具有电源抑制功能的LDO电路，同时也涉及包括该LDO电路的集成电路芯片及相应的通信终端，属于集成电路技术领域。
背景技术
随着通信技术的发展，通信终端中芯片的应用环境越来越复杂。通常，一个通信终端中包括有CPU、电源管理芯片、存储芯片、时钟芯片、外围电路和射频芯片等部分，且各部分由同一个电源供电。其中，CPU、电源管理芯片、存储芯片、时钟芯片和外围电路等会产生一些中频信号(100KHz～10MHz)，这些中频信号会通过电源进入射频芯片的电压偏置电路，进而干扰恶化射频芯片调制谱、开关谱和噪声等性能，严重限制了射频通信技术的发展。
低压差线性稳压器(low dropout regulator，简称为LDO)是一种射频芯片常用的电压偏置电路，它的主要作用是为射频芯片提供直流电压工作点。为了减小通信终端内部中频信号对射频芯片的干扰，增强电源对中频信号的抑制能力，提供一种高性能中频电源抑制(Power Supply Rejection，简称为PSR)的LDO电路是必要的。
发明内容
本发明所要解决的首要技术问题在于提供一种具有电源抑制功能的LDO电路。
本发明所要解决的另一技术问题在于提供一种包括具有电源抑制功能的LDO电路的芯片及通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种具有电源抑制功能的LDO电路，包括设置有中频零点调整单元的带隙基准模块、设置有中频零点产生单元的放大模块和功率输出模块，所述带隙基准模块连接所述放大模块，所述放大模块连接所述功率输出模块；
所述带隙基准模块利用所述中频零点调整单元调整的中频零点的 频率，生成带有预设温度系数的基准电压，输出到所述放大模块；其中，所述基准电压作为所述LDO电路的参考电压，配合所述中频零点产生单元生成的零点，所述零点的频率为中频，调节所述LDO电路在中频处的电源抑制。
其中较优地，所述带隙基准模块包括启动单元、PTAT电流产生单元、输出单元和中频零点调整单元；所述启动单元和所述中频零点调整单元的输出端连接所述PTAT电流产生单元的输入端，所述PTAT电流产生单元的输出端连接所述输出单元的输入端，所述输出单元的输出端连接所述放大模块的输入端。
其中较优地，所述启动单元包括第一PMOS管、第二PMOS管、第一电阻、第二电阻、第一NMOS管、第二NMOS管、第三PMOS管、第四PMOS管、第三NMOS管和第四NMOS管；所述第一PMOS管和所述第二PMOS管的源极连接电源电压，所述第二PMOS管的漏极连接所述第一电阻的一端，所述第一电阻的另一端连接所述第一PMOS管的漏极、所述第四PMOS管的栅极和所述第二电阻的一端，所述第二电阻的另一端连接所述第一NMOS管的栅极和漏极，所述第四PMOS管的漏极连接所述第三NMOS管的栅极和漏极、所述第四NMOS管的栅极，所述第四NMOS管的漏极、所述第四PMOS管的源极和所述第三PMOS管的漏极相互连接，并与所述第二PMOS管的栅极连接到所述PTAT电流产生单元，所述第一PMOS管、所述第二NMOS管和所述第三PMOS管的栅极连接外部的使能信号，所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的源极连接电源电压，所述第二NMOS管、所述第三NMOS管和所述第四NMOS管的源极接地。
其中较优地，所述PTAT电流产生单元包括第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第九PMOS管、第三电阻、第四电阻、第五NMOS管、第六NMOS管、第七NMOS管、第八NMOS管、第五电阻、第一双极型晶体管和第二双极型晶体管；所述第五PMOS管的栅极连接外部的使能信号，所述第五PMOS管的漏极、所述第六PMOS管、所述第七PMOS管与所述第二PMOS管的栅极、所述第九PMOS管的漏极、所述第三电阻的一端和所述输出单元之间相互连接，所述第六PMOS管的漏极连接所述第八PMOS管的源极，所述第七PMOS管的漏极连接所述 第九PMOS管的源极，所述第八PMOS管与所述第九PMOS管的栅极、所述第三PMOS管的漏极、所述第四PMOS管的源极、所述第三电阻的另一端、所述第七NMOS管的漏极和所述输出单元之间相互连接，所述第八PMOS管的漏极连接所述第四电阻的一端、所述第五NMOS管与所述第七NMOS管的栅极，所述第四电阻的另一端连接所述第五NMOS管的漏极、所述第六NMOS管与所述第八NMOS管的栅极，所述第五NMOS管的源极连接所述第六NMOS管的漏极，所述第七NMOS管的源极连接所述第八NMOS管的漏极，所述第六NMOS管的源极连接所述第一双极型晶体管的发射极，所述第八NMOS管的源极通过所述第五电阻连接所述第二双极型晶体管的发射极，所述第五PMOS管、所述第六PMOS管、所述第七PMOS管的源极连接电源电压,所述第一双极型晶体管和所述第二双极型晶体管的基极和集电极均接地。
其中较优地，所述输出单元包括第十PMOS管、第十一PMOS管、第六电阻、第三双极型晶体管、第十二PMOS管和第十三PMOS管；所述第十PMOS管与所述第十二PMOS管的栅极连接所述第九PMOS管的漏极和所述中频零点调整单元，所述第十PMOS管的漏极连接所述第十一PMOS管的源极，所述第十二PMOS管的漏极连接所述第十三PMOS管的源极，所述第十一PMOS管与所述第十三PMOS管的栅极连接所述第三电阻的另一端和所述中频零点调整单元，所述第十一PMOS管的漏极与所述第六电阻的一端连接所述放大模块，所述第六电阻的另一端连接所述第三双极型晶体管的发射极，所述第十三PMOS管的漏极连接所述放大模块，所述第十PMOS管与所述第十二PMOS管的源极连接所述电源电压，所述第三双极型晶体管的基极和集电极接地。
其中较优地，所述中频零点调整单元包括第一电容和第二电容,所述第一电容与所述第二电容的一端连接所述电源电压，所述第一电容的另一端连接所述第六PMOS管、所述第七PMOS管、所述第十PMOS管和所述第十二PMOS管的栅极，所述第二电容的另一端连接所述第八PMOS管、所述第九PMOS管、所述第十一PMOS管和所述第十三PMOS管的栅极。
其中较优地，所述放大模块包括第一级放大单元、第二级放大单元和设置在所述第一级放大单元与所述第二级放大单元之间的所述中 频零点产生单元，所述第一级放大单元连接所述第二级放大单元和所述功率输出模块。
其中较优地，所述中频零点产生单元由第十电阻和第四电容串联到地组成。
根据本发明实施例的第二方面，提供一种集成电路芯片，所述集成电路芯片包括上述具有电源抑制功能的LDO电路。
根据本发明实施例的第三方面，提供一种通信终端，所述通信终端中包括上述具有电源抑制功能的LDO电路。
本发明所提供的具有电源抑制功能的LDO电路，针对中频处的电源抑制，配合调整带隙基准模块中的中频零点调整单元和LDO电路中的中频零点产生单元，使中频电源抑制性能得到更好的优化。将该中频电源抑制的LDO电路作为射频芯片的电压偏置电路，可增强射频芯片电源对中频信号的抑制能力，进而提升射频芯片的工作性能。
附图说明
图1为本发明实施例提供的具有电源抑制功能的LDO电路的原理图；
图2为本发明实施例提供的具有电源抑制功能的LDO电路中，带隙基准模块的电路原理图；
图3为本发明实施例提供的具有电源抑制功能的LDO电路中，放大模块和功率输出模块的电路原理图；
图4为带隙基准模块的基准电压输出端的电源抑制仿真结果对比图；
图5为LDO电路的电压输出端VOUT的电源抑制仿真结果对比图；
图6为采用该具有电源抑制功能的LDO电路的通信终端的示例图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
为了提高射频芯片在复杂应用环境中对中频信号的抗干扰能力，进而提升射频芯片的工作性能，如图1所示，本发明实施例提供了具有电源抑制功能的LDO电路，包括设置有中频零点调整单元109的带隙基准模块101、设置有中频零点产生单元105的放大模块102和功 率输出模块103，带隙基准模块101连接放大模块102，放大模块102连接功率输出模块103。
带隙基准模块101利用中频零点调整单元109调整中频零点的频率，生成带有预设温度系数、并具有中频电源抑制的基准电压，输出到放大模块102，作为LDO电路的参考电压，配合中频零点产生单元105生成的用于改变放大模块102在中频处频率响应的频率为中频的零点，以提高LDO电路的中频电源抑制性能。
如图1所示，带隙基准模块101包括启动单元106、PTAT(Proportional To Absolute Temperature,与绝对温度成正比)电流产生单元107、输出单元108和中频零点调整单元109；启动单元106和中频零点调整单元109的输出端连接PTAT电流产生单元107的输入端，PTAT电流产生单元107的输出端连接输出单元108的输入端，输出单元108的输出端连接放大模块102。
需要强调的是，本发明中，主要对带隙基准模块101为放大模块102提供预设温度系数(一般为零温度系数)、并具有中频电源抑制的基准电压VREF的实现过程进行详细说明，而带隙基准模块101还会为放大模块102提供偏置电流为现有公知技术，在此不再详述。
具体的说，启动单元106，用于使PTAT电流产生单元107避开电流为0的简并点，确保该PTAT电流产生单元107正常启动并稳定。如图2所示，启动单元106包括第一PMOS管201、第二PMOS管202、第一电阻203、第二电阻204、第一NMOS管205、第二NMOS管206、第三PMOS管207、第四PMOS管208、第三NMOS管209和第四NMOS管210。启动单元106各部分连接关系如下：第一PMOS管201和第二PMOS管202的源极连接电源电压VDD，第二PMOS管202的漏极连接第一电阻203的一端，第一电阻203的另一端连接第一PMOS管201的漏极、第四PMOS管208的栅极和第二电阻204的一端，第二电阻204的另一端连接第一NMOS管205的栅极和漏极，第四PMOS管208的漏极连接第三NMOS管209的栅极和漏极、第四NMOS管210的栅极，第四NMOS管210的漏极、第四PMOS管208的源极和第三PMOS管207的漏极相互连接，并与第二PMOS管202的栅极连接到PTAT电流产生单元107的相应位置，第一PMOS管201、第二NMOS管206和第三PMOS管207 的栅极连接外部的使能信号EN，第一PMOS管201、第二PMOS管202和第三PMOS管207的源极连接电源电压VDD，第二NMOS管206、第三NMOS管209和第四NMOS管210的源极接地。
PTAT电流产生单元107，利用
Figure PCTCN2022107152-appb-000001
原理产生与温度成正比的电流。如图2所示，PTAT电流产生单元107包括第五PMOS管211、第六PMOS管212、第七PMOS管213、第八PMOS管214、第九PMOS管215、第三电阻216、第四电阻217、第五NMOS管218、第六NMOS管219、第七NMOS管220、第八NMOS管221、第五电阻222、第一双极型晶体管223和第二双极型晶体管224。PTAT电流产生单元107各部分连接关系如下：第五PMOS管211的栅极连接外部的使能信号，第五PMOS管211的漏极、第六PMOS管212、第七PMOS管213与第二PMOS管202的栅极、第九PMOS管215的漏极、第三电阻216的一端和输出单元108相应位置之间相互连接，第六PMOS管212的漏极连接第八PMOS管214的源极，第七PMOS管213的漏极连接第九PMOS管215的源极，第八PMOS管214与第九PMOS管215的栅极、第三PMOS管207的漏极、第四PMOS管208的源极、第三电阻216的另一端、第七NMOS管220的漏极和输出单元108相应位置之间相互连接，第八PMOS管214的漏极连接第四电阻217的一端、第五NMOS管218与第七NMOS管220的栅极，第四电阻217的另一端连接第五NMOS管218的漏极、第六NMOS管219与第八NMOS管221的栅极，第五NMOS管218的源极连接第六NMOS管219的漏极，第七NMOS管220的源极连接第八NMOS管221的漏极，第六NMOS管219的源极连接第一双极型晶体管223的发射极，第八NMOS管221的源极通过第五电阻222连接第二双极型晶体管224的发射极，第五PMOS管211、第六PMOS管212、第七PMOS管213的源极连接电源电压VDD,第一双极型晶体管223和第二双极型晶体管224的基极和集电极均接地。
其中，第一PMOS管201、第二NMOS管206、第三PMOS管207和第五PMOS管211作为使能控制管，控制带隙基准模块101的开启与关闭。当使能信号EN为低电平时，第一PMOS管201、第三PMOS管207和第五PMOS管211导通，第二NMOS管206截止，带隙基准模块101 关闭。当使能信号EN从低电平变成高电平，第一PMOS管201、第三PMOS管207和第五PMOS管211截止，第二NMOS管206导通。由第二PMOS管202、第一电阻203、第二电阻204、第一NMOS管205、第二NMOS管206组成的支路导通，节点A处的电压VA被拉低，第四PMOS管208导通，产生电流，第三NMOS管209和第四NMOS管210构成电流镜，第四NMOS管210导通，节点B处的电压VB被拉低，第八PMOS管214和第九PMOS管215开始导通，使PTAT电流产生单元107避开电流为0的简并点，开始启动，等其建立稳定，节点A处的电压VA大于节点B处的电压VB，第四PMOS管208截止，PTAT电流产生单元107启动完成。第五PMOS管211、第六PMOS管212、第七PMOS管213、第八PMOS管214、第九PMOS管215、第三电阻216、第四电阻217、第五NMOS管218、第六NMOS管219、第七NMOS管220、第八NMOS管221组成共源共栅电流镜自举电路，左右两支路的电流相等，实现节点C和节点D的钳位，使节点C处的电压VC和节点D处的电压VD近似相等，即VC＝VD，且VC＝V BE_223(第一双极型晶体管223的基极-发射极电压)，VD＝V BE_224+V 222((第二双极型晶体管224的基极-发射极电压与第五电阻222两端的压降之和)，第一双极型晶体管223和第二双极型晶体管224的基极-发射极电压的差值ΔV BE＝InN*V T，其中N为第一双极型晶体管223和第二双极型晶体管224并联个数的比值，V T为双极型晶体管的热电压，V T的表达式为
Figure PCTCN2022107152-appb-000002
其中k为玻尔兹曼常数，q为电子电荷，T为绝对温度，即
Figure PCTCN2022107152-appb-000003
其中
Figure PCTCN2022107152-appb-000004
是常数，因此第一双极型晶体管223和第二双极型晶体管224的基极-发射极电压的差值ΔV BE与绝对温度T成正比。第五电阻222两端的压降为V 222＝ΔV BE，共源共栅电流镜自举电路左右两支路的电流为
Figure PCTCN2022107152-appb-000005
该电流与绝对温度T成正比，即PTAT电流。
输出单元108，基于PTAT电流产生单元107产生的与温度成正比的电流，生成基准电压VREF和基准电流IBIAS。如图2所示，输出单 元108包括第十PMOS管227、第十一PMOS管228、第六电阻229、第三双极型晶体管230、第十二PMOS管231和第十三PMOS管232。输出单元108各部分连接关系如下：第十PMOS管227与第十二PMOS管231的栅极连接第九PMOS管215的漏极和中频零点调整单元109，第十PMOS管227的漏极连接第十一PMOS管228的源极，第十二PMOS管231的漏极连接第十三PMOS管232的源极，第十一PMOS管228与第十三PMOS管232的栅极连接第三电阻216的另一端和中频零点调整单元109，第十一PMOS管228的漏极与第六电阻229的一端连接放大模块102，用于为其提供基准电压VREF，第六电阻229的另一端连接第三双极型晶体管230的发射极，第十三PMOS管232的漏极连接放大模块102，用于将基准电流IBIAS传输给放大模块102，实现为其提供偏置电流，第十PMOS管227与第十二PMOS管231的源极连接电源电压VDD，第三双极型晶体管230的基极和集电极接地。
利用第十PMOS管227和第十一PMOS管228，第十二PMOS管231和第十三PMOS管232分别构成电流镜，将PTAT电流产生单元107的PTAT电流复制，得到基准电流IBIAS，用于提供给放大模块102做偏置电流。基准电压VREF可表示为
Figure PCTCN2022107152-appb-000006
其中V BE为第三双极型晶体管230基极-发射极电压，该电压是一个负温度系数的电压，因此调整第五电阻222和第六电阻229的比例，可使基准电压VREF成为一个零温度的电压，用于提供给放大模块102做参考电压。
中频零点调整单元109，用于调整带隙基准模块101中频零点的频率，以提高带隙基准模块101的中频电源抑制性能。如图2所示，中频零点调整单元109包括第一电容225和第二电容226,第一电容225与第二电容226的一端连接电源电压VDD，第一电容225的另一端连接第六PMOS管212、第七PMOS管213、第十PMOS管227和第十二PMOS管231的栅极，第二电容226的另一端连接第八PMOS管214、第九PMOS管215、第十一PMOS管228和第十三PMOS管232的栅极。
带隙基准模块101中，电源电压VDD通过与第一电容225和第二 电容226另一端连接的各个PMOS管，其栅极的寄生电容Cgs，Cgd存在支路到基准电压输出端，支路上会产生一个零点。此零点的频率由该支路上电阻(PMOS管的电阻)和电容的乘积决定，通过改变其电容，进而改变零点频率，使带隙基准模块101在中频处的电源抑制得到优化。其中，第一电容225和第二电容226的容值大小及两者的比例大小共同决定该中频零点的频率，针对中频处的电源抑制调整第一电容225和第二电容226的容值大小和比例大小，可以达到更好的优化效果，具体通过如下公式实现。
Figure PCTCN2022107152-appb-000007
其中，R bg为带隙基准模块101中频零点支路上的电阻，C bg为带隙基准模块101中频零点支路上的电容，r ds_227为第十PMOS管227漏源之间的等效交流电阻，r ds_228为第十一PMOS管228漏源之间的等效交流电阻，C gs1_227为第十PMOS管227栅源之间的寄生电容，C 225为第一电容225的容值，C gd1_227为第十PMOS管227栅漏之间的寄生电容，C gs2_228为第十一PMOS管228栅源之间的寄生电容，C 226为第二电容226的容值，C gd2_228为第十一PMOS管228栅漏之间的寄生电容，//为电路中的并联符号。
如图3所示，放大模块102包括第一级放大单元110、第二级放大单元111和设置在第一级放大单元110与第二级放大单元111之间的中频零点产生单元105，第一级放大单元110连接第二级放大单元111和功率输出模块103。功率输出模块103包括功率管312、第十六NMOS管320、第三电容315、第七电阻316和由第八电阻Rf1和第九电阻Rf2组成的反馈电阻网络112，功率管312的栅极连接第十六NMOS管320的漏极、第三电容315的一端和第二级放大单元111，第三电容315的另一端连接第七电阻316的一端，第七电阻316的另一端连接功率管312漏极、第八电阻Rf1的一端，第八电阻Rf1的另一端连接第九电阻Rf2的一端、第一级放大单元110，第九电阻Rf2的另一 端接地，功率管312和第十六NMOS管320的源极连接电源电压VDD，第十六NMOS管320的栅极连接外部的使能信号。
如图3所示，第一级放大单元110包括反相器301、第九NMOS管302、第十NMOS管303、第十一NMOS管304、第十二NMOS管305、第十三NMOS管306、第十四NMOS管307、第十四PMOS管308、第十五PMOS管309、第十六PMOS管319。第一级放大单元110各部分连接关系如下：反相器301的输入端连接外部的使能信号，反相器301的输出端连接第十二NMOS管305的栅极，第九NMOS管302和第十六PMOS管319的栅极连接外部的使能信号，第九NMOS管302的漏极连接输出单元108的第十三PMOS管232的漏极，第九NMOS管302的源极连接第十NMOS管303的栅极和漏极、第十一NMOS管304的栅极、第二级放大单元111、第十二NMOS管305的漏极，第十一NMOS管304的漏极连接第十三NMOS管306和第十四NMOS管307的源极，第十三NMOS管306的栅极连接输出单元108的第十一PMOS管228的漏极与第六电阻229的一端，第十三NMOS管306的漏极连接第十四PMOS管308的栅极和漏极、第十五PMOS管309的栅极、第十六PMOS管319的漏极，第十五PMOS管309的漏极连接第十四NMOS管307的漏极、中频零点产生单元105和第二级放大单元111，第十四NMOS管307的栅极连接功率输出模块103，第十四PMOS管308、第十五PMOS管309、第十六PMOS管319的源极连接电源电压VDD，第十NMOS管303、第十一NMOS管304、第十二NMOS管305的源极均接地。
如图3所示，第二级放大单元111包括第十五NMOS管310和第十七PMOS管311，第十五NMOS管310的栅极连接第十一NMOS管304的栅极，第十五NMOS管310的漏极连接第十七PMOS管311的漏极和功率输出模块103，第十七PMOS管311的栅极连接第十四NMOS管307的漏极和中频零点产生单元105，第十七PMOS管311的源极连接电源电压VDD，第十五NMOS管310的源极接地。
如图3所示，中频零点产生单元105包括第十电阻317和第四电容318，第十电阻317的一端连接第十五PMOS管309的漏极和第十七PMOS管311的栅极，第十电阻317的另一端连接第四电容318的一端，第四电容318的另一端接地。
其中，第一级放大单元110与第二级放大单元111、功率管312、第八电阻Rf1和第九电阻Rf2构成负反馈环路，使得LDO电路的输出电压VOUT受电源电压和负载电阻变化影响小。
具体的说，使能信号EN经过反相器301得到使能信号ENB，使能信号EN和ENB通过控制使能管第九NMOS管302、第十二NMOS管305、第十六PMOS管319和第十六NMOS管320的导通和截止，实现控制第一级放大单元110与第二级放大单元111的开启和关闭。带隙基准模块101为第一级放大单元110提供偏置电流。第十NMOS管303和第十一NMOS管304，第十NMOS管303和第十五NMOS管310分别构成电流镜，用于将基准电流IBIAS复制给第一级放大单元110和第二级放大单元111提供偏置电流。带隙基准模块101为第一级放大单元110提供参考电压。第一级放大单元110是典型的五管放大器，其中第十三NMOS管306和第十四NMOS管307是第一级放大单元110的输入放大对管，第十四PMOS管308、第十五PMOS管309是第一级放大单元110的电流镜负载。第二级放大单元111是共源放大器，其中第十七PMOS管311是第二级放大单元111的放大管。第三电容315和第七电阻316组成密勒补偿。第八电阻Rf1和第九电阻Rf2组成反馈电阻网络33，和基准电压VREF一起决定LDO电路输出电压的大小，该输出电压
Figure PCTCN2022107152-appb-000008
第十电阻317和第四电容318串联到地组成中频零点产生单元105，它的作用是生成一个频率为中频的零点，这一零点可以改变放大模块102在中频处的频率响应，以提高LDO电路中频的电源抑制性能。其中，第十电阻317和第四电容318的乘积决定该零点的频率，该零点的频率具体表示为
Figure PCTCN2022107152-appb-000009
针对中频处的电源抑制，配合调整带隙基准模块101中频零点的频率和中频零点产生单元生成的中频零点的频率，可以达到更好的优化效果。
图4为带隙基准模块Bandgap电压输出端的电源抑制(PSR)仿真结果对比，其中曲线1是带隙基准模块加入中频零点调整单元之前电源抑制仿真结果，曲线2是带隙基准模块加入中频零点调整单元之后电源抑制仿真结果，图中标注的是频率300KHz处的电源抑制，根据仿真结果可以看出带隙基准模块在加入中频零点调整单元之后，在 300KHz频率处的电源抑制优化了11.2dB。
图5为本发明所提供的LDO电路的电压输出端VOUT的电源抑制(PSR)仿真结果对比，其中曲线3是LDO电路加入中频零点产生单元之前电源抑制仿真结果，曲线4是LDO电路加入中频零点产生单元之后电源抑制仿真结果，图中标注的是频率300KHz处的电源抑制，根据仿真结果可以看出LDO电路在加入中频零点单元之后，在300KHz频率处的电源抑制优化11.1dB。
另外，本发明所提供的具有电源抑制功能的LDO电路可以被用在集成电路芯片中。对于该集成电路芯片中具有电源抑制功能的LDO电路的具体结构，在此不再一一详述。
上述具有电源抑制功能的LDO电路还可以被用在通信终端中，作为射频集成电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的设备，包括移动电话、笔记本电脑、平板电脑、车联网终端等。此外，本发明所提供的技术方案也适用于其他射频集成电路应用的场合，例如通信基站、智能网联汽车等。
如图6所示，该通信终端至少包括处理器和存储器，还可以根据实际需要进一步包括通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口。其中，存储器、通信组件、传感器组件、电源组件、多媒体组件及输入/输出接口均与该处理器连接。存储器可以是静态随机存取存储器(SRAM)、电可擦除可编程只读存储器(EEPROM)、可擦除可编程只读存储器(EPROM)、可编程只读存储器(PROM)、只读存储器(ROM)、磁存储器、快闪存储器等，处理器可以是中央处理器(CPU)、图形处理器(GPU)、现场可编程逻辑门阵列(FPGA)、专用集成电路(ASIC)、数字信号处理(DSP)芯片等。其它通信组件、传感器组件、电源组件、多媒体组件等均可以采用通用部件实现，在此就不具体说明了。
与现有技术相比较，本发明所提供的具有电源抑制功能的LDO电路针对中频处的电源抑制，配合调整带隙基准模块中的中频零点调整单元和LDO电路中的中频零点产生单元，使中频电源抑制性能得到更好的优化。将该中频电源抑制的LDO电路作为射频芯片的电压偏置电 路，可增强射频芯片电源对中频信号的抑制能力，进而提升射频芯片的工作性能。
以上对本发明所提供的具有电源抑制功能的LDO电路、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (10)

  1. 一种具有电源抑制功能的LDO电路，其特征在于包括设置有中频零点调整单元的带隙基准模块、设置有中频零点产生单元的放大模块和功率输出模块，所述带隙基准模块连接所述放大模块，所述放大模块连接所述功率输出模块；
    所述带隙基准模块利用所述中频零点调整单元调整的中频零点的频率，生成预设温度系数的基准电压，输出到所述放大模块；其中，所述基准电压作为所述LDO电路的参考电压，配合所述中频零点产生单元生成的零点，所述零点的频率为中频，调节所述LDO电路在中频处的电源抑制。
  2. 如权利要求1所述的具有电源抑制功能的LDO电路，其特征在于：
    所述带隙基准模块包括启动单元、PTAT电流产生单元、输出单元和中频零点调整单元；所述启动单元和所述中频零点调整单元的输出端连接所述PTAT电流产生单元的输入端，所述PTAT电流产生单元的输出端连接所述输出单元的输入端，所述输出单元的输出端连接所述放大模块的输入端。
  3. 如权利要求2所述的具有电源抑制功能的LDO电路，其特征在于：
    所述启动单元包括第一PMOS管、第二PMOS管、第一电阻、第二电阻、第一NMOS管、第二NMOS管、第三PMOS管、第四PMOS管、第三NMOS管和第四NMOS管；所述第一PMOS管和所述第二PMOS管的源极连接电源电压，所述第二PMOS管的漏极连接所述第一电阻的一端，所述第一电阻的另一端连接所述第一PMOS管的漏极、所述第四PMOS管的栅极和所述第二电阻的一端，所述第二电阻的另一端连接所述第一NMOS管的栅极和漏极，所述第四PMOS管的漏极连接所述第三NMOS管的栅极和漏极、所述第四NMOS管的栅极，所述第四NMOS管的漏极、所述第四PMOS管的源极和所述第三PMOS管的漏极相互连接，并与所述第二PMOS管的栅极连接到所述PTAT电流产生单元，所述第一PMOS管、所述第二NMOS管和所述第三PMOS管的栅极连接外部的使能信号， 所述第一PMOS管、所述第二PMOS管和所述第三PMOS管的源极连接电源电压，所述第二NMOS管、所述第三NMOS管和所述第四NMOS管的源极接地。
  4. 如权利要求3所述的具有电源抑制功能的LDO电路，其特征在于：
    所述PTAT电流产生单元包括第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第九PMOS管、第三电阻、第四电阻、第五NMOS管、第六NMOS管、第七NMOS管、第八NMOS管、第五电阻、第一双极型晶体管和第二双极型晶体管；所述第五PMOS管的栅极连接外部的使能信号，所述第五PMOS管的漏极、所述第六PMOS管、所述第七PMOS管与所述第二PMOS管的栅极、所述第九PMOS管的漏极、所述第三电阻的一端和所述输出单元之间相互连接，所述第六PMOS管的漏极连接所述第八PMOS管的源极，所述第七PMOS管的漏极连接所述第九PMOS管的源极，所述第八PMOS管与所述第九PMOS管的栅极、所述第三PMOS管的漏极、所述第四PMOS管的源极、所述第三电阻的另一端、所述第七NMOS管的漏极和所述输出单元之间相互连接，所述第八PMOS管的漏极连接所述第四电阻的一端、所述第五NMOS管与所述第七NMOS管的栅极，所述第四电阻的另一端连接所述第五NMOS管的漏极、所述第六NMOS管与所述第八NMOS管的栅极，所述第五NMOS管的源极连接所述第六NMOS管的漏极，所述第七NMOS管的源极连接所述第八NMOS管的漏极，所述第六NMOS管的源极连接所述第一双极型晶体管的发射极，所述第八NMOS管的源极通过所述第五电阻连接所述第二双极型晶体管的发射极，所述第五PMOS管、所述第六PMOS管、所述第七PMOS管的源极连接电源电压,所述第一双极型晶体管和所述第二双极型晶体管的基极和集电极均接地。
  5. 如权利要求4所述的具有电源抑制功能的LDO电路，其特征在于：
    所述输出单元包括第十PMOS管、第十一PMOS管、第六电阻、第三双极型晶体管、第十二PMOS管和第十三PMOS管；所述第十PMOS管与所述第十二PMOS管的栅极连接所述第九PMOS管的漏极和所述中频零点调整单元，所述第十PMOS管的漏极连接所述第十一PMOS管的源 极，所述第十二PMOS管的漏极连接所述第十三PMOS管的源极，所述第十一PMOS管与所述第十三PMOS管的栅极连接所述第三电阻的另一端和所述中频零点调整单元，所述第十一PMOS管的漏极与所述第六电阻的一端连接所述放大模块，所述第六电阻的另一端连接所述第三双极型晶体管的发射极，所述第十三PMOS管的漏极连接所述放大模块，所述第十PMOS管与所述第十二PMOS管的源极连接所述电源电压，所述第三双极型晶体管的基极和集电极接地。
  6. 如权利要求5所述的具有电源抑制功能的LDO电路，其特征在于：
    所述中频零点调整单元包括第一电容和第二电容,所述第一电容与所述第二电容的一端连接所述电源电压，所述第一电容的另一端连接所述第六PMOS管、所述第七PMOS管、所述第十PMOS管和所述第十二PMOS管的栅极，所述第二电容的另一端连接所述第八PMOS管、所述第九PMOS管、所述第十一PMOS管和所述第十三PMOS管的栅极。
  7. 如权利要求1所述的具有电源抑制功能的LDO电路，其特征在于：
    所述放大模块包括第一级放大单元、第二级放大单元和设置在所述第一级放大单元与所述第二级放大单元之间的所述中频零点产生单元，所述第一级放大单元连接所述第二级放大单元和所述功率输出模块。
  8. 如权利要求1所述的具有电源抑制功能的LDO电路，其特征在于：
    所述中频零点产生单元由第十电阻和第四电容串联到地组成。
  9. 一种集成电路芯片，其特征在于包括权利要求1～8中任意一项所述的具有电源抑制功能的LDO电路。
  10. 一种通信终端，其特征在于包括权利要求1～8中任意一项所述的具有电源抑制功能的LDO电路。
PCT/CN2022/107152 2021-07-30 2022-07-21 一种具有电源抑制功能的ldo电路、芯片及通信终端 WO2023005806A1 (zh)

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