WO2023005545A1 - Mémoire non volatile et son procédé de fabrication - Google Patents

Mémoire non volatile et son procédé de fabrication Download PDF

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Publication number
WO2023005545A1
WO2023005545A1 PCT/CN2022/101507 CN2022101507W WO2023005545A1 WO 2023005545 A1 WO2023005545 A1 WO 2023005545A1 CN 2022101507 W CN2022101507 W CN 2022101507W WO 2023005545 A1 WO2023005545 A1 WO 2023005545A1
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WO
WIPO (PCT)
Prior art keywords
barrier layer
silicide
floating gate
layer
substrate
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PCT/CN2022/101507
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English (en)
Chinese (zh)
Inventor
徐顺强
王浩
郭术明
张楠
龚才
黄勇
李侠
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无锡华润上华科技有限公司
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Publication of WO2023005545A1 publication Critical patent/WO2023005545A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuits, and relates to a nonvolatile memory and a manufacturing method thereof.
  • Non-volatile memory based on single-layer polycrystalline (Poly) is divided into one-time programmable (OTP), limited-time programmable (FTP) and multiple-time programmable (MTP) memories according to the number of programmable times.
  • OTP one-time programmable
  • FTP limited-time programmable
  • MTP multiple-time programmable
  • FIG. 1 is a schematic diagram of a non-volatile memory based on single-layer polycrystalline, including a bit line terminal 101, a selection terminal 102, a control terminal 103, a tunneling terminal 104, a floating gate (Floating Gate) 105, and a control transistor capacitance 106 , selection transistor 107 and floating gate transistor 108, the substrate end of floating gate transistor 108, the source end and the substrate end of selection transistor 107 are connected to tunnel end 104, the drain end of floating gate transistor 108 is connected to the source of selection transistor 107 Connected to each other, it can be programmed by hot electron (HCI) or F-N tunneling, and erased by F-N tunneling.
  • HCI hot electron
  • F-N tunneling F-N tunneling
  • the non-volatile memory based on single-layer polysilicon adopts the mechanism of floating gate to store charges, only one layer of polysilicon is required, and the production process of the non-volatile memory based on single-layer polysilicon is compatible with the standard CMOS process.
  • the charge stored on the floating gate may leak through the dielectric around the floating gate.
  • the floating Leakage on the top and sidewalls of the gate especially on the top of the floating gate.
  • the charge on the floating gate can affect the charge distribution of the hole etch stop layer (CESL) through capacitive coupling, which will affect the retention of charge on the floating gate, especially when reverse encoding, the reverse encoding effect will aggravate the floating gate charge leakage .
  • the dielectric leakage around the floating gate will affect the data retention time of the non-volatile memory, so that the non-volatile memory cannot meet the data retention time requirement.
  • the object of the present invention is to provide a nonvolatile memory and its manufacturing method, which is used to solve the problem of storing on the floating gate in the nonvolatile memory based on single-layer polycrystalline
  • the charge is easy to leak through the dielectric around the floating gate, thereby affecting the data retention time of the non-volatile memory.
  • non-volatile memory including:
  • the floating gate structure located on the substrate, the floating gate structure comprising a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;
  • a silicide barrier layer located on the substrate and covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;
  • a hole etch barrier layer is located on the substrate and covers the silicide barrier layer.
  • the thickness of the silicide barrier layer is greater than 100 nm.
  • the non-volatile memory includes a silicide region, the silicide barrier layer surrounds the silicide region, the hole etching barrier layer is provided with a contact hole located in the silicide region, and the contact The spacing between the boundary of the hole and the boundary of the silicide barrier layer around the silicide region is greater than 0.15 ⁇ m.
  • the material of the silicide barrier layer includes silicon oxide
  • the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.
  • the present invention also provides a method for manufacturing a non-volatile memory, comprising the following steps:
  • a substrate is provided, and a floating gate structure is formed on the substrate, and the floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;
  • the silicide barrier layer covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;
  • a hole etch stop layer is formed on the substrate, and the hole etch stop layer covers the silicide stop layer.
  • the thickness of the silicide barrier layer is greater than 100 nm.
  • the distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region is greater than 0.15 ⁇ m.
  • the material of the silicide barrier layer includes silicon oxide
  • the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.
  • the nonvolatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer, Therefore, the data retention time of the non-volatile memory is improved, and the data retention time can be maintained at 85°C for 10 years.
  • the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes The etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes.
  • FIG. 1 is a schematic diagram of a single-layer polycrystalline non-volatile memory in the prior art.
  • Figure 2 shows a structure of a floating gate and its surrounding dielectric layer fabricated by a CMOS process.
  • Figure 3 shows another floating gate and its surrounding dielectric layer structure.
  • FIG. 4 shows a structure of a floating gate and its surrounding dielectric layer of a non-volatile memory in an embodiment.
  • FIG. 5 is a schematic layout diagram of an active region, a floating gate and a silicide barrier layer of a memory cell of a nonvolatile memory in an embodiment.
  • FIG. 6 is a schematic layout diagram of an active region, a silicide barrier layer and a contact hole of a memory cell of a nonvolatile memory in an embodiment.
  • FIG. 7 is a process flow chart of a manufacturing method of a non-volatile memory in an embodiment.
  • FIGS. 1 to 7 are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than according to the present invention.
  • the number, shape and size of the components in the actual implementation can be changed arbitrarily in the type, quantity and proportion of the components in the actual implementation, and the layout of the components may also be more complicated.
  • FIG. 2 it is a floating gate and its surrounding dielectric layer structure made by CMOS technology, wherein the sidewall 204 is usually a sandwich structure of oxide layer, silicon nitride and oxide layer, and the hole etching stops
  • the material of layer 206 is silicon nitride.
  • Polycrystalline is surrounded by an insulating medium to form a floating gate. Due to defects in the dielectric layer around the floating gate, the charges stored in the floating gate may leak through the surrounding dielectric layer. As for the non-volatile memory, even a relatively weak electric leakage will affect the data retention time of the non-volatile memory.
  • the thermally grown gate oxide 202 at the bottom of the floating gate is generally of high quality, but the defect density of the dielectric layer at the top of the floating gate is relatively high, especially the hole etching stopper layer 206, which is made of silicon nitride. With a high defect density, the floating gate charge may leak through the top dielectric.
  • FIG. 3 it shows another floating gate and its surrounding dielectric layer structure, including silicon substrate 301, gate oxide 302, polysilicon 303, sidewall 304, oxide layer 305 and hole etching stopper layer 306, wherein,
  • the thickness of the oxide layer 305 is relatively thin, only tens of nanometers, a typical value is 35 nanometers, and the hole etching stopper layer 306 is silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride.
  • the material of the hole etch stop layer 306 is adjusted from silicon nitride to silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride, so that the hole etch stop layer 306 can be reduced.
  • the defect density reduces the leakage of floating gate charge.
  • it is necessary to effectively control the defect density Only when the defect density is lower than a certain level can the charge leakage stored in the floating gate be controlled within a satisfactory range.
  • the process of controlling defects by adjusting the composition of the hole etching barrier layer is relatively complicated, which increases the process cost; and adjusting the composition of the hole etching barrier layer has an impact on the etching ratio of the hole etching barrier layer and the oxide layer. , which further affects the etching of the holes.
  • the present invention also provides a new solution to reduce the charge leakage stored in the floating gate, so as to improve the data retention time of the non-volatile memory.
  • the technical solutions of the present invention are illustrated below through specific examples.
  • FIG. 4 shows the floating gate of the non-volatile memory and its surrounding dielectric layer structure, including a substrate 401, a floating gate structure, a silicide barrier layer 405 and Hole etching barrier layer 406, wherein the floating gate structure is located on the substrate 401, and the floating gate structure includes a gate dielectric layer 402 and a polysilicon layer 403 stacked sequentially from bottom to top; the silicide barrier layer 405 Located on the substrate 401 and covering the floating gate structure, the thickness of the silicide barrier layer 405 is greater than 35 nm; the hole etching barrier layer 406 is located on the substrate 401 and covers the silicide barrier layer 405 .
  • the floating gate structure further includes sidewalls 404 located on sides of the gate dielectric layer 402 and the polysilicon layer 403 .
  • FIG. 5 is a schematic diagram of the layout of the active region 407, the floating gate 408 and the silicide barrier layer 405 of the memory cell of the nonvolatile memory, wherein the floating gate of the nonvolatile memory 408 is covered by the silicide barrier layer 405 .
  • the substrate 401 includes but is not limited to common semiconductor substrates such as silicon, germanium, silicon germanium, III-V compounds, SOI (silicon-on-insulator);
  • the material of the silicide barrier layer 405 is silicon oxide;
  • the material of the hole etching barrier layer 406 is silicon nitride;
  • the sidewall 404 is an ONO composite structure, that is, a silicon oxide-silicon nitride-silicon oxide composite structure.
  • the thickness of the usual silicide barrier layer 405 is in the thickness range of tens of nanometers, with a typical value of 35 nm, while in the present invention, the silicide between the floating gate structure and the hole etch barrier layer 406
  • the thickness of the barrier layer 405 is thicker, the thickness of the silicide barrier layer 405 is significantly increased, and the thickness can be greater than 100nm, for example, the thickness of the silicide barrier layer 405 can be selected from 105nm, 110nm, 115nm, 120nm, 125nm and 130nm One, preferably 120nm.
  • the significantly increased silicide barrier layer 405 can effectively suppress the leakage of floating gate charges through the top dielectric, thereby improving the data retention time of the non-volatile memory, and the data retention time can be maintained at 85° C. for 10 years.
  • the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes The etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes.
  • the material of the hole etching stopper layer 406 may also be silicon oxynitride, or a composite structure of silicon oxynitride and silicon nitride. Since the floating gate charge leakage has been improved by the thickened silicide barrier layer, the requirement for defect density control of the hole etch barrier layer can be reduced. Compared with the scheme of reducing the charge leakage stored in the floating gate only by changing the composition of the hole etching barrier layer, the present invention will increase the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. The scheme of adjusting the composition of the hole etching stopper layer still has relatively low process difficulty.
  • the data retention performance of the device is improved by increasing the thickness of the silicide barrier layer, although it does not involve changing the composition of the hole etching barrier layer, and then does not affect the etching ratio of the hole etching barrier layer layer to the oxide layer; also reduces The process is difficult, but it brings a new technical problem, that is, the increase in the thickness of the silicide barrier layer makes it difficult to control the hole etching accurately, and it is prone to insufficient hole etching, which can directly lead to device failure.
  • the increase in the thickness of the silicide barrier layer makes it difficult to control the hole etching accurately, and it is prone to insufficient hole etching, which can directly lead to device failure.
  • FIG. 6 which is a schematic layout diagram of an active region 407, a silicide barrier layer 405, and a contact hole 409 of a memory cell of the nonvolatile memory, wherein the nonvolatile memory includes In the silicided region, the silicide barrier layer 405 surrounds the silicided region, and the contact hole 409 is located in the hole etching barrier layer 406 and located in the silicided region.
  • the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 is set to 0.15 ⁇ m.
  • the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 around the silicide region may be further set to be greater than 0.15 ⁇ m.
  • Fig. 6 shows the transverse distance D 1 and the longitudinal distance D 2
  • the transverse distance D 1 and the longitudinal distance D 2 can be set to the same value, or can be set to different values, but they are all greater than 0.15 ⁇ m.
  • the increased distance can be adjusted according to the specific etching process, as long as the increased distance is satisfied so that the holes can be etched sufficiently without over-etching.
  • the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 around the silicide region can be selected from among 0.18 ⁇ m, 0.19 ⁇ m, 0.2 ⁇ m, 0.21 ⁇ m and 0.22 ⁇ m. One, preferably 0.2 ⁇ m. Therefore, it is ensured that the data retention performance of the device is effectively improved under the premise of avoiding insufficient hole etching.
  • FIG. 7 is a process flow diagram of the method, including the following steps:
  • S1 Provide a substrate, and form a floating gate structure on the substrate, the floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;
  • forming the floating gate structure includes the following steps: using chemical vapor deposition, physical vapor deposition or other suitable methods to sequentially deposit a gate dielectric layer and a polysilicon layer, and using dry etching and /or wet etching and patterning the polysilicon layer and the gate dielectric layer to obtain a gate structure of a desired shape.
  • the deposition and etching of the sidewall dielectric are further performed to obtain sidewalls located on both sides of the gate dielectric layer and the polysilicon layer.
  • the etching menu for the silicide barrier layer also needs to be adjusted accordingly, and the etching amount corresponding to the thickness is increased to expose the substrate.
  • the thickness of the silicide barrier layer is greater than 100 nm, for example, the thickness of the silicide barrier layer may be selected from one of 105 nm, 110 nm, 115 nm, 120 nm, 125 nm and 130 nm.
  • the contact hole etching does not meet the requirements, and can be further
  • the distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region is greater than a conventional distance, for example greater than 0.15 ⁇ m. It should be pointed out that the increased distance can be adjusted according to the specific etching process, as long as the increased distance is satisfied so that the holes can be etched sufficiently without over-etching.
  • the distance between the contact hole and the silicide barrier layer around the silicide region can be selected from one of 0.18 ⁇ m, 0.19 ⁇ m, 0.2 ⁇ m, 0.21 ⁇ m and 0.22 ⁇ m. Therefore, on the premise of avoiding insufficient hole etching, the data retention performance of the device is effectively improved.
  • the material of the silicide barrier layer includes silicon oxide
  • the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.
  • the manufacturing method of the non-volatile memory in this embodiment suppresses the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. Specifically, it only needs to increase the deposition It only needs to increase the thickness of the silicide barrier layer and increase the etching amount of the silicide barrier layer when defining the silicide region, which has the advantages of low process complexity and low process cost.
  • the scheme of increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer can also be used at the same time as the scheme of adjusting the composition of the hole etching barrier layer to achieve better suppression of floating gate charges passing through the top The effect of dielectric leakage.
  • the nonvolatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. , thereby improving the data retention time of the non-volatile memory, the data retention time of the non-volatile memory of the present invention can be maintained at 85° C. for 10 years.
  • the solution of the present invention compared with the solution of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching barrier layer, the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes
  • the etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention concerne une mémoire non volatile et son procédé de fabrication. La mémoire non volatile comprend un substrat, une structure de grille flottante, une couche d'arrêt de silicification et une couche d'arrêt de gravure de trous, la structure de grille flottante étant située sur le substrat, et la structure de grille flottante comprend une couche diélectrique de grille et une couche de polysilicium, qui sont empilées de manière séquentielle de bas en haut, et comprend une paroi latérale, qui est située sur des faces latérales de la couche diélectrique de grille et de la couche de polysilicium ; la couche d'arrêt de silicification est située sur le substrat et recouvre la structure de grille flottante, et l'épaisseur de la couche d'arrêt de silicification est supérieure à 35 nm ; et la couche d'arrêt de gravure de trous est située sur le substrat et recouvre une couche d'arrêt de siliciure. Dans la présente invention, l'épaisseur d'une couche d'arrêt de silicification entre une grille flottante polycristalline et une couche d'arrêt de gravure de trous est augmentée, de telle sorte que la fuite électrique de charges de grille flottante à travers un diélectrique supérieur peut être efficacement supprimée, ce qui permet de prolonger le temps de conservation de données d'une mémoire non volatile, le temps de conservation de données pouvant être de dix ans à 85 °C. De plus, la solution de la présente invention présente les avantages d'une complexité de traitement relativement faible et d'un coût de traitement relativement faible.
PCT/CN2022/101507 2021-07-27 2022-06-27 Mémoire non volatile et son procédé de fabrication WO2023005545A1 (fr)

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CN202110860442.3A CN115701219A (zh) 2021-07-27 2021-07-27 一种非易失性存储器及其制造方法
CN202110860442.3 2021-07-27

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170115A (zh) * 2007-11-21 2008-04-30 上海宏力半导体制造有限公司 一种非挥发性存储器结构及其制造方法
US20080283974A1 (en) * 2007-05-17 2008-11-20 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
CN102427066A (zh) * 2011-12-05 2012-04-25 上海先进半导体制造股份有限公司 Cmos一次性可编程只读存储器及其制造方法
CN111180448A (zh) * 2018-11-13 2020-05-19 合肥晶合集成电路有限公司 一种非易失性存储器及其制作方法
WO2021020082A1 (fr) * 2019-08-01 2021-02-04 ローム株式会社 Dispositif de stockage non volatil à semi-conducteurs

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080283974A1 (en) * 2007-05-17 2008-11-20 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
CN101170115A (zh) * 2007-11-21 2008-04-30 上海宏力半导体制造有限公司 一种非挥发性存储器结构及其制造方法
CN102427066A (zh) * 2011-12-05 2012-04-25 上海先进半导体制造股份有限公司 Cmos一次性可编程只读存储器及其制造方法
CN111180448A (zh) * 2018-11-13 2020-05-19 合肥晶合集成电路有限公司 一种非易失性存储器及其制作方法
WO2021020082A1 (fr) * 2019-08-01 2021-02-04 ローム株式会社 Dispositif de stockage non volatil à semi-conducteurs

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