WO2023005545A1 - Non-volatile memory and method for manufacturing same - Google Patents

Abstract

Provided in the present invention are a non-volatile memory and a method for manufacturing same. The non-volatile memory comprises a substrate, a floating gate structure, a silicification stop layer and a hole etching stop layer, wherein the floating gate structure is located on the substrate, and the floating gate structure comprises a gate dielectric layer and a polysilicon layer, which are sequentially stacked from bottom to top, and comprises a side wall, which is located on side faces of the gate dielectric layer and the polysilicon layer; the silicification stop layer is located on the substrate and covers the floating gate structure, and the thickness of the silicification stop layer is greater than 35 nm; and the hole etching stop layer is located on the substrate and covers a silicide stop layer. In the present invention, the thickness of a silicification stop layer between a polycrystalline floating gate and a hole etching stop layer is increased, such that the electric leakage of floating gate charges through a top dielectric can be effectively suppressed, thereby prolonging the data hold time of a non-volatile memory, wherein the data hold time can be ten years at 85℃. In addition, the solution of the present invention has the advantages of a relatively low process complexity and a relatively low process cost.

Description

A kind of non-volatile memory and its manufacturing method

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202110860442.3 and the invention title "a non-volatile memory and its manufacturing method" filed with the China Patent Office on July 27, 2021, the entire contents of which are incorporated by reference in this application.

technical field

The invention belongs to the technical field of semiconductor integrated circuits, and relates to a nonvolatile memory and a manufacturing method thereof.

Background technique

Non-volatile memory (NVM) based on single-layer polycrystalline (Poly) is divided into one-time programmable (OTP), limited-time programmable (FTP) and multiple-time programmable (MTP) memories according to the number of programmable times. Gate (Floating Gate) mechanism for storing charges. As shown in Figure 1 is a schematic diagram of a non-volatile memory based on single-layer polycrystalline, including a bit line terminal 101, a selection terminal 102, a control terminal 103, a tunneling terminal 104, a floating gate (Floating Gate) 105, and a control transistor capacitance 106 , selection transistor 107 and floating gate transistor 108, the substrate end of floating gate transistor 108, the source end and the substrate end of selection transistor 107 are connected to tunnel end 104, the drain end of floating gate transistor 108 is connected to the source of selection transistor 107 Connected to each other, it can be programmed by hot electron (HCI) or F-N tunneling, and erased by F-N tunneling.

The non-volatile memory based on single-layer polysilicon adopts the mechanism of floating gate to store charges, only one layer of polysilicon is required, and the production process of the non-volatile memory based on single-layer polysilicon is compatible with the standard CMOS process. However, in the non-volatile memory manufactured by the general single-layer polycrystalline CMOS process, the charge stored on the floating gate may leak through the dielectric around the floating gate. In addition to the leakage of the bottom gate oxide of the floating gate, the floating Leakage on the top and sidewalls of the gate, especially on the top of the floating gate. The charge on the floating gate can affect the charge distribution of the hole etch stop layer (CESL) through capacitive coupling, which will affect the retention of charge on the floating gate, especially when reverse encoding, the reverse encoding effect will aggravate the floating gate charge leakage . The dielectric leakage around the floating gate will affect the data retention time of the non-volatile memory, so that the non-volatile memory cannot meet the data retention time requirement.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a nonvolatile memory and its manufacturing method, which is used to solve the problem of storing on the floating gate in the nonvolatile memory based on single-layer polycrystalline The charge is easy to leak through the dielectric around the floating gate, thereby affecting the data retention time of the non-volatile memory.

In order to achieve the above purpose and other related purposes, the present invention provides a non-volatile memory, including:

Substrate;

a floating gate structure located on the substrate, the floating gate structure comprising a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;

a silicide barrier layer located on the substrate and covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;

A hole etch barrier layer is located on the substrate and covers the silicide barrier layer.

Optionally, the thickness of the silicide barrier layer is greater than 100 nm.

Optionally, the non-volatile memory includes a silicide region, the silicide barrier layer surrounds the silicide region, the hole etching barrier layer is provided with a contact hole located in the silicide region, and the contact The spacing between the boundary of the hole and the boundary of the silicide barrier layer around the silicide region is greater than 0.15 μm.

Optionally, the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.

The present invention also provides a method for manufacturing a non-volatile memory, comprising the following steps:

A substrate is provided, and a floating gate structure is formed on the substrate, and the floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;

performing ion implantation on the substrate to form a source region and a drain region located on both sides of the floating gate structure;

forming a silicide barrier layer on the substrate, the silicide barrier layer covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;

etching the silicide barrier layer to expose silicide regions of the substrate;

forming a metal silicide layer on the silicide region;

A hole etch stop layer is formed on the substrate, and the hole etch stop layer covers the silicide stop layer.

Optionally, the thickness of the silicide barrier layer is greater than 100 nm.

Optionally, further comprising forming a contact hole in the hole etching barrier layer, the distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region is greater than 0.15 μm.

Optionally, the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.

As mentioned above, the nonvolatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer, Therefore, the data retention time of the non-volatile memory is improved, and the data retention time can be maintained at 85°C for 10 years. In addition, compared with the solution of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching barrier layer, the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes The etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes.

Description of drawings

FIG. 1 is a schematic diagram of a single-layer polycrystalline non-volatile memory in the prior art.

Figure 2 shows a structure of a floating gate and its surrounding dielectric layer fabricated by a CMOS process.

Figure 3 shows another floating gate and its surrounding dielectric layer structure.

FIG. 4 shows a structure of a floating gate and its surrounding dielectric layer of a non-volatile memory in an embodiment.

FIG. 5 is a schematic layout diagram of an active region, a floating gate and a silicide barrier layer of a memory cell of a nonvolatile memory in an embodiment.

FIG. 6 is a schematic layout diagram of an active region, a silicide barrier layer and a contact hole of a memory cell of a nonvolatile memory in an embodiment.

FIG. 7 is a process flow chart of a manufacturing method of a non-volatile memory in an embodiment.

Component designation description

201, 301 Silicon substrate

202, 302 Gate oxide

203, 303 polysilicon

204, 304 side wall

205, 305 oxide layer

206, 306 Pore etch stop layer

401 Substrate

402 Gate Dielectric Layer

403 polysilicon layer

404 side wall

405 Silicide barrier layer

406 Hole Etch Stop Layer

407 Active area

408 floating gate

409 Contact hole

D ₁ horizontal spacing

D ₂ longitudinal spacing

S1～S6 Steps

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the diagrams provided in this embodiment (please refer to FIGS. 1 to 7 ) are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than according to the present invention. The number, shape and size of the components in the actual implementation can be changed arbitrarily in the type, quantity and proportion of the components in the actual implementation, and the layout of the components may also be more complicated.

As shown in FIG. 2 , it is a floating gate and its surrounding dielectric layer structure made by CMOS technology, wherein the sidewall 204 is usually a sandwich structure of oxide layer, silicon nitride and oxide layer, and the hole etching stops The material of layer 206 is silicon nitride. Polycrystalline is surrounded by an insulating medium to form a floating gate. Due to defects in the dielectric layer around the floating gate, the charges stored in the floating gate may leak through the surrounding dielectric layer. As for the non-volatile memory, even a relatively weak electric leakage will affect the data retention time of the non-volatile memory. For the CMOS process, the thermally grown gate oxide 202 at the bottom of the floating gate is generally of high quality, but the defect density of the dielectric layer at the top of the floating gate is relatively high, especially the hole etching stopper layer 206, which is made of silicon nitride. With a high defect density, the floating gate charge may leak through the top dielectric.

As shown in FIG. 3, it shows another floating gate and its surrounding dielectric layer structure, including silicon substrate 301, gate oxide 302, polysilicon 303, sidewall 304, oxide layer 305 and hole etching stopper layer 306, wherein, The thickness of the oxide layer 305 is relatively thin, only tens of nanometers, a typical value is 35 nanometers, and the hole etching stopper layer 306 is silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride. By adjusting the composition of the hole etch stop layer 306, the material of the hole etch stop layer 306 is adjusted from silicon nitride to silicon oxynitride or a composite structure of silicon oxynitride and silicon nitride, so that the hole etch stop layer 306 can be reduced. The defect density reduces the leakage of floating gate charge. However, in this method, it is necessary to effectively control the defect density. Only when the defect density is lower than a certain level can the charge leakage stored in the floating gate be controlled within a satisfactory range. In addition, the process of controlling defects by adjusting the composition of the hole etching barrier layer is relatively complicated, which increases the process cost; and adjusting the composition of the hole etching barrier layer has an impact on the etching ratio of the hole etching barrier layer and the oxide layer. , which further affects the etching of the holes.

Therefore, the present invention also provides a new solution to reduce the charge leakage stored in the floating gate, so as to improve the data retention time of the non-volatile memory. The technical solutions of the present invention are illustrated below through specific examples.

Embodiment one

A non-volatile memory is provided in this embodiment, please refer to FIG. 4, which shows the floating gate of the non-volatile memory and its surrounding dielectric layer structure, including a substrate 401, a floating gate structure, a silicide barrier layer 405 and Hole etching barrier layer 406, wherein the floating gate structure is located on the substrate 401, and the floating gate structure includes a gate dielectric layer 402 and a polysilicon layer 403 stacked sequentially from bottom to top; the silicide barrier layer 405 Located on the substrate 401 and covering the floating gate structure, the thickness of the silicide barrier layer 405 is greater than 35 nm; the hole etching barrier layer 406 is located on the substrate 401 and covers the silicide barrier layer 405 .

As an example, the floating gate structure further includes sidewalls 404 located on sides of the gate dielectric layer 402 and the polysilicon layer 403 .

As an example, please refer to FIG. 5 , which is a schematic diagram of the layout of the active region 407, the floating gate 408 and the silicide barrier layer 405 of the memory cell of the nonvolatile memory, wherein the floating gate of the nonvolatile memory 408 is covered by the silicide barrier layer 405 .

As an example, the substrate 401 includes but is not limited to common semiconductor substrates such as silicon, germanium, silicon germanium, III-V compounds, SOI (silicon-on-insulator); the material of the silicide barrier layer 405 is silicon oxide; The material of the hole etching barrier layer 406 is silicon nitride; the sidewall 404 is an ONO composite structure, that is, a silicon oxide-silicon nitride-silicon oxide composite structure.

Specifically, the thickness of the usual silicide barrier layer 405 is in the thickness range of tens of nanometers, with a typical value of 35 nm, while in the present invention, the silicide between the floating gate structure and the hole etch barrier layer 406 The thickness of the barrier layer 405 is thicker, the thickness of the silicide barrier layer 405 is significantly increased, and the thickness can be greater than 100nm, for example, the thickness of the silicide barrier layer 405 can be selected from 105nm, 110nm, 115nm, 120nm, 125nm and 130nm One, preferably 120nm. The significantly increased silicide barrier layer 405 can effectively suppress the leakage of floating gate charges through the top dielectric, thereby improving the data retention time of the non-volatile memory, and the data retention time can be maintained at 85° C. for 10 years. In addition, compared with the solution of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching barrier layer, the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes The etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes.

Certainly, in another embodiment, the material of the hole etching stopper layer 406 may also be silicon oxynitride, or a composite structure of silicon oxynitride and silicon nitride. Since the floating gate charge leakage has been improved by the thickened silicide barrier layer, the requirement for defect density control of the hole etch barrier layer can be reduced. Compared with the scheme of reducing the charge leakage stored in the floating gate only by changing the composition of the hole etching barrier layer, the present invention will increase the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. The scheme of adjusting the composition of the hole etching stopper layer still has relatively low process difficulty.

However, the data retention performance of the device is improved by increasing the thickness of the silicide barrier layer, although it does not involve changing the composition of the hole etching barrier layer, and then does not affect the etching ratio of the hole etching barrier layer layer to the oxide layer; also reduces The process is difficult, but it brings a new technical problem, that is, the increase in the thickness of the silicide barrier layer makes it difficult to control the hole etching accurately, and it is prone to insufficient hole etching, which can directly lead to device failure. As an example, please refer to FIG. 6 , which is a schematic layout diagram of an active region 407, a silicide barrier layer 405, and a contact hole 409 of a memory cell of the nonvolatile memory, wherein the nonvolatile memory includes In the silicided region, the silicide barrier layer 405 surrounds the silicided region, and the contact hole 409 is located in the hole etching barrier layer 406 and located in the silicided region. Usually, the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 is set to 0.15 μm. , the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 around the silicide region may be further set to be greater than 0.15 μm. Wherein, Fig. 6 shows the transverse distance D ₁ and the longitudinal distance D ₂ , the transverse distance D ₁ and the longitudinal distance D ₂ can be set to the same value, or can be set to different values, but they are all greater than 0.15 μm. It should be pointed out that the increased distance can be adjusted according to the specific etching process, as long as the increased distance is satisfied so that the holes can be etched sufficiently without over-etching. In this embodiment, the distance between the boundary of the contact hole 409 and the boundary of the silicide barrier layer 405 around the silicide region can be selected from among 0.18 μm, 0.19 μm, 0.2 μm, 0.21 μm and 0.22 μm. One, preferably 0.2 μm. Therefore, it is ensured that the data retention performance of the device is effectively improved under the premise of avoiding insufficient hole etching.

Embodiment two

A method for manufacturing a non-volatile memory is provided in this embodiment, please refer to FIG. 7 , which is a process flow diagram of the method, including the following steps:

S1: Provide a substrate, and form a floating gate structure on the substrate, the floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;

S2: performing ion implantation on the substrate to form a source region and a drain region located on both sides of the floating gate structure;

S3: forming a silicide barrier layer on the substrate, the silicide barrier layer covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;

S4: Etching the silicide barrier layer to expose the substrate of the silicide region;

S5: forming a metal silicide layer in the silicide region;

S6: forming a hole etching stopper layer on the substrate, the hole etch stopper layer covering the silicide stopper layer.

Specifically, in the step S1, forming the floating gate structure includes the following steps: using chemical vapor deposition, physical vapor deposition or other suitable methods to sequentially deposit a gate dielectric layer and a polysilicon layer, and using dry etching and /or wet etching and patterning the polysilicon layer and the gate dielectric layer to obtain a gate structure of a desired shape. In this embodiment, the deposition and etching of the sidewall dielectric are further performed to obtain sidewalls located on both sides of the gate dielectric layer and the polysilicon layer.

In the step S4, due to the thickness variation of the silicide barrier layer, the etching menu for the silicide barrier layer also needs to be adjusted accordingly, and the etching amount corresponding to the thickness is increased to expose the substrate.

As an example, the thickness of the silicide barrier layer is greater than 100 nm, for example, the thickness of the silicide barrier layer may be selected from one of 105 nm, 110 nm, 115 nm, 120 nm, 125 nm and 130 nm.

As an example, it also includes the step of forming a contact hole in the hole etching barrier layer. In the present invention, in order to avoid the hole contact problem caused by the increase in the thickness of the silicide barrier layer, the contact hole etching does not meet the requirements, and can be further The distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region is greater than a conventional distance, for example greater than 0.15 μm. It should be pointed out that the increased distance can be adjusted according to the specific etching process, as long as the increased distance is satisfied so that the holes can be etched sufficiently without over-etching. In this embodiment, the distance between the contact hole and the silicide barrier layer around the silicide region can be selected from one of 0.18 μm, 0.19 μm, 0.2 μm, 0.21 μm and 0.22 μm. Therefore, on the premise of avoiding insufficient hole etching, the data retention performance of the device is effectively improved.

As an example, the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride.

The manufacturing method of the non-volatile memory in this embodiment suppresses the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. Specifically, it only needs to increase the deposition It only needs to increase the thickness of the silicide barrier layer and increase the etching amount of the silicide barrier layer when defining the silicide region, which has the advantages of low process complexity and low process cost. In addition, the scheme of increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer can also be used at the same time as the scheme of adjusting the composition of the hole etching barrier layer to achieve better suppression of floating gate charges passing through the top The effect of dielectric leakage.

In summary, the nonvolatile memory and its manufacturing method of the present invention can effectively suppress the leakage of floating gate charges through the top dielectric by increasing the thickness of the silicide barrier layer between the polycrystalline floating gate and the hole etching barrier layer. , thereby improving the data retention time of the non-volatile memory, the data retention time of the non-volatile memory of the present invention can be maintained at 85° C. for 10 years. In addition, compared with the solution of reducing the charge leakage stored in the floating gate by changing the composition of the hole etching barrier layer, the solution of the present invention has the advantages of lower process complexity and lower process cost, and does not cause holes The etch selectivity ratio of the etch barrier layer and the silicide barrier layer is reduced, so as to avoid affecting the etching of the holes. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (14)

1. A kind of non-volatile memory, is characterized in that, comprises:

   Substrate;

   a floating gate structure located on the substrate, the floating gate structure comprising a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;

   a silicide barrier layer located on the substrate and covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;

   A hole etch barrier layer is located on the substrate and covers the silicide barrier layer.
2. The nonvolatile memory according to claim 1, wherein the thickness of the silicide barrier layer is greater than 100 nm.
3. The nonvolatile memory according to claim 2, wherein the thickness of the silicide barrier layer is selected from one of 105nm, 110nm, 115nm, 120nm, 125nm and 130nm.
4. The nonvolatile memory according to claim 3, wherein the thickness of the silicide barrier layer is 120nm.
5. The non-volatile memory according to claim 1, wherein the non-volatile memory comprises a silicide region, the silicide barrier layer surrounds the silicide region, and the hole etching barrier layer is provided with There is a contact hole located in the silicide region, and the distance between the boundary of the contact hole and the boundary of the silicide barrier layer around the silicide region is greater than 0.15 μm.
6. The nonvolatile memory according to claim 5, wherein the distance between the contact hole and the silicide barrier layer around the silicide region is selected from 0.18 μm, 0.19 μm, 0.2 μm, and 0.21 μm And one of 0.22μm.
7. The nonvolatile memory according to claim 6, wherein the distance between the contact hole and the silicide barrier layer around the silicide region is 0.2 μm.
8. The nonvolatile memory according to claim 1, wherein the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes at least one of silicon nitride and silicon oxynitride .
9. The nonvolatile memory according to claim 1, wherein the floating gate structure further comprises sidewalls located on sides of the gate dielectric layer and the polysilicon layer.
10. The nonvolatile memory according to claim 9, characterized in that: the sidewall adopts a silicon oxide-silicon nitride-silicon oxide composite structure.
11. A method of manufacturing a non-volatile memory, comprising the following steps:

    A substrate is provided, and a floating gate structure is formed on the substrate, and the floating gate structure includes a gate dielectric layer and a polysilicon layer stacked sequentially from bottom to top;

    performing ion implantation on the substrate to form a source region and a drain region located on both sides of the floating gate structure;

    forming a silicide barrier layer on the substrate, the silicide barrier layer covering the floating gate structure, the thickness of the silicide barrier layer is greater than 35 nm;

    etching the silicide barrier layer to expose silicide regions of the substrate;

    forming a metal silicide layer on the silicide region;

    A hole etch stop layer is formed on the substrate, and the hole etch stop layer covers the silicide stop layer.
12. The manufacturing method of the non-volatile memory according to claim 11, characterized in that: the thickness of the silicide barrier layer is greater than 100 nm.
13. The method of manufacturing a non-volatile memory according to claim 11, further comprising forming a contact hole in the hole etching barrier layer, the boundary of the contact hole is in contact with the surrounding areas of the silicided region. The spacing between the boundaries of the silicide barrier layer is greater than 0.15 μm.
14. The method for manufacturing a nonvolatile memory according to claim 11, wherein the material of the silicide barrier layer includes silicon oxide, and the material of the hole etching barrier layer includes silicon nitride and silicon oxynitride. at least one.

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