CN101170115A

CN101170115A - A non volatile memory structure and its making method

Info

Publication number: CN101170115A
Application number: CNA2007101707518A
Authority: CN
Inventors: 肖海波
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-11-21
Filing date: 2007-11-21
Publication date: 2008-04-30

Abstract

The invention provides a non-volatile memory structure and a manufacture method thereof. The device includes an underlay with a surface area, which is provided thereon with a plurality of grid dielectric medium layers, wherein, at least two grid dielectric medium layers are provided thereon with a control grid and a floating grid respectively. The control grid and the floating grid are covered by a silicon dioxide barrier layer and a silicon nitride shield layer in turn. The barrier layer and the shield layer co-form a self alignment barrier layer (SAB). The invention has the advantages of good data retentivity, logic process compatibility, simpler process control and efficiency improvement.

Description

A kind of non-volatile memory structure and manufacture method thereof

Technical field

The present invention relates to a kind of semiconductor device structure and manufacture method thereof, particularly a kind of programmable non-volatile device architecture and manufacture method thereof.

Background technology

Logical circuit can obtain good data processing performance, and memory device can obtain good data retention characteristics, if this two kinds of devices design is on a kind of circuit, can obtain good data processing and memory property simultaneously, but correspondingly, its technological process meeting relative complex that becomes, cost also can be very high.For the device of some specific functions, as the drive circuit (Driver) of high tension apparatus, the data that require storage are not a lot, and memory device shared ratio in entire circuit is less, therefore can produce sort memory spare with logic process.

The performance of weighing the good and bad most critical of sort memory spare quality is data retentivity (Data Retention).Because the autoregistration barrier layer in the conventional logic process (Salicide block, SAB) thinner, therefore, and the memory device that adopts conventional logic process to produce, its data retentivity is relatively poor.Learn by experiment, the data retentivity that thicker SAB layer can obtain, still, and when the SAB oxide skin(coating) reaches certain thickness, when for example thousand  are above, the removal of the SAB layer difficulty relatively that becomes, it is very complicated that technology controlling and process also becomes.

Therefore, how to provide a kind of data retentivity good, and the simple relatively memory device of technology controlling and process has become the technical problem that industry needs to be resolved hurrily.

Summary of the invention

The object of the present invention is to provide a kind of non-volatile memory structure and manufacture method thereof, it can reach the good data retentivity, and is compatible with logic process, makes processing procedure control more easy, raises the efficiency.

In order to reach described purpose, the invention provides a kind of non-volatile memory structure, it comprises the substrate with surf zone, be formed on a plurality of gate dielectric layers on the described substrate surface area, wherein be formed with a control grid and a floating grid respectively at least two gate dielectric layers, be coated with a barrier layer and a shielding layer of unlike material on the described floating grid respectively in regular turn, described barrier layer and shielding layer have constituted the autoregistration barrier layer jointly.

In above-mentioned non-volatile memory structure, described barrier layer is a silicon dioxide layer.

In above-mentioned non-volatile memory structure, described shielding layer is a silicon nitride layer.

Another program of the present invention provides a kind of manufacture method of above-mentioned non-volatile memory structure, and it comprises the following steps: to provide the substrate with surf zone, and forms a plurality of gate dielectric layers on the surf zone of substrate; On described a plurality of gate dielectric layers, form an at least one control grid and a floating grid; On described control grid and floating grid, form the barrier layer and the shielding layer of unlike material in regular turn; Open the control area of grid by exposure imaging; The material characteristic different with shielding layer according to the barrier layer, the method that adopts terminal point to catch etch away and are formed on the outer shielding layer of control grid; Adopt the etch process in the conventional pure logic process to remove the barrier layer that covers on the control grid.

Non-volatile memory structure of the present invention adopts the double-layer structure of barrier layer and shielding layer to constitute the SAB layer, because this SAB layer is thicker, therefore can effectively solves data and keep problem; In addition,, can etch away shielding layer, adopt the etch process in the conventional pure logic process to remove the barrier layer again, thereby can control manufacturing process more easily, enhance productivity by the method that terminal point is caught because the material on shielding layer and barrier layer is different.

Description of drawings

To the description of one embodiment of the invention, can further understand purpose, specific structural features and the advantage of its invention by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:

Fig. 1 is the structural profile schematic diagram of non-volatility memorizer of the present invention before etching SAB layer;

Fig. 2 is the structural profile schematic diagram of non-volatility memorizer of the present invention after etching SAB layer;

Fig. 3 is the manufacture method flow chart of non-volatile memory structure of the present invention.

Embodiment

Below with reference to a specific embodiment non-volatile memory structure of the present invention and manufacture method thereof are described in further detail.

See also Fig. 1, be the structural profile schematic diagram of the non-volatility memorizer spare before the etching SAB layer of the present invention.As shown in the figure, non-volatile memory structure of the present invention comprises the substrate 1 with surf zone, on the surf zone of this substrate 1, form a plurality of gate dielectric layers 20 (only drawing among the figure two), an at least one control grid 10 and a floating grid 11 are set on each gate dielectric layer 20, on control grid 10 and floating grid 11, cover a barrier layer 40 and a shielding layer 50 in regular turn then.

More specifically, this barrier layer 40 is a silicon dioxide, and this shielding layer 50 is a silicon nitride layer, this two-layer common autoregistration barrier layer (Salicide Block, SAB layer) that constituted.

Then see also Fig. 3, be the flow chart of the manufacture method of non-volatility memorizer spare of the present invention, and contrast Fig. 1 and Fig. 2 simultaneously.At first execution in step S10 provides the substrate 1 with surf zone; In step S20, form a plurality of gate dielectric layers 20 at the surf zone of aforesaid substrate 1; Then execution in step S30 is provided with an at least one control grid 10 and a floating grid 11 on aforementioned a plurality of gate dielectric layers 20; Execution in step S40 forms barrier layer 40 on

aforementioned grid

10,11 subsequently, covers aforementioned grid; Step S50 forms shielding layer 50 on aforementioned barrier layer 40, cover aforementioned barrier layer 40; Carry out S60 then, exposure imaging is opened control grid 10 zones, forms the pattern that needs on silicon chip; Execution in step S70 then, the shielding layer 50 above the method etching control grid 10 of catching with terminal point (end point); Last execution in step S80 removes following barrier layer 40 with the etch process in the conventional pure logic process.

Fig. 2 is the structural profile schematic diagram of finishing the non-volatility memorizer spare after the etching of SAB layer.

In sum, non-volatile memory structure of the present invention and manufacture method thereof adopt barrier layer and shielding layer to form the SAB layer jointly, because this SAB layer has certain thickness, therefore can effectively solve data and keep problem; Simultaneously in the etching shielding layer, because shielding layer is different with following barrier layer material, the method etching shielding layer that can catch by terminal point, remove the barrier layer with the etch process in the conventional pure logic process again, make that processing procedure control is more easy, improved production efficiency, and from the pure logic process of routine be easy to change into can compatible this non-volatility memorizer technology, have good application advantage.

Of particular note, the structure of non-volatility memorizer spare of the present invention is not limited to the mode defined in the foregoing description, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the present invention, and not breaking away from the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims

1. non-volatile memory structure, it comprises the substrate with surf zone, be formed on a plurality of gate dielectric layers on the described substrate surface area, wherein be formed with a control grid and a floating grid respectively at least two gate dielectric layers, it is characterized in that: be coated with a barrier layer and a shielding layer of unlike material on the described floating grid respectively in regular turn, described barrier layer and shielding layer have constituted the autoregistration barrier layer jointly.

2. non-volatile memory structure according to claim 1 is characterized in that: described barrier layer is a silicon dioxide layer.

3. non-volatile memory structure according to claim 1 is characterized in that: described shielding layer is a silicon nitride layer.

4. the manufacture method of a non-volatile memory structure as claimed in claim 1 is characterized in that, comprises the following steps:

Substrate with surf zone is provided, and on the surf zone of substrate, forms a plurality of gate dielectric layers;

On described a plurality of gate dielectric layers, form an at least one control grid and a floating grid;

On described control grid and floating grid, form the barrier layer and the shielding layer of unlike material in regular turn;

Open the control area of grid by exposure imaging;

The material characteristic different with shielding layer according to the barrier layer, the method that adopts terminal point to catch etch away and are formed on the outer shielding layer of control grid;

Adopt the etch process in the conventional pure logic process to remove the barrier layer that covers on the control grid.