TWI694593B - Method for forming semiconductor memory device - Google Patents

Abstract

A method for fabricating a semiconductor memory device: firstly, providing a substrate having an cell region and a logic region defined thereon, a plurality of shallow trench isolations are formed in the substrate, and forming a floating gate material layer on the substrate. A planarization step is then performed, and then a photoresist layer is formed to cover the logic region, a first etching step is performed to remove portions of the shallow trench isolation and part of the floating gate material layer in the cell region. Afterwards, removing the photoresist layer, and performing a second etching step, to remove portions of the shallow trench isolation and portions of the floating gate material layer in the cell region and in the logic region.

Description

Manufacturing method of semiconductor memory element

The present invention relates to the field of semiconductor manufacturing processes, in particular to a method for improving the flexibility of semiconductor memory device manufacturing processes.

The semiconductor memory system is a semiconductor component used for storing data or data in computers or electronic products, which can be roughly divided into volatile memory (volatile) and non-volatile memory, in which non-volatile memory has no power supply The feature of interruption and loss of stored data is widely used.

However, as the functions of computer microprocessors become more powerful, the demand for large-capacity and low-cost memory is also increasing. In order to meet this trend and the continuous challenges of semiconductor technology for high accumulation, the memory structure is becoming smaller and the manufacturing process of the memory structure is becoming more complicated. For example, in different areas of the memory device (such as the device area and the peripheral area), because different devices are included, the size and other parameters of each device are not the same, which makes it more difficult to manufacture the memory device.

The invention provides a method for manufacturing a semiconductor memory device, including: first, providing a substrate, a device region and a logic region are defined on the substrate, and then forming a plurality of shallow trenches to isolate in the substrate, and forming a floating gate material layer in On the substrate, a planarization step is performed. After the planarization step, a top surface of each shallow trench isolation and a top surface of the floating gate material layer are higher than a top surface of the substrate, and then a light is formed The resist layer covers the logic area, and then a first etching step is performed to remove a portion of the shallow trench isolation and a portion of the floating gate material layer in the device area, then remove the photoresist layer, and perform a second In the etching step, a portion of the shallow trench isolation and a portion of the floating gate material layer in the device area and the logic area are removed.

The present invention is characterized by using a photoresist layer to cover some areas (such as the logic area), and then adjusting the etching process parameters to control the height difference between the shallow trench isolation and the polysilicon layer in the device area and the logic area, and further Forming elements of various heights. In this way, the method of the present invention can increase the flexibility of the manufacturing process. In addition, the present invention should pay attention to increase the deposition thickness (more than 400 angstroms) when depositing the polysilicon layer to avoid the polysilicon layer being etched through during the planarization step and affecting the quality of the subsequent memory stack structure.

100: base

100S: top surface

102: component area

103: liner layer

104: logical area

106: Shallow trench isolation

106A: Shallow trench isolation

106B: Shallow trench isolation

106S: top surface

108: polysilicon layer

108A: polysilicon layer

108B: polysilicon layer

108C: polysilicon layer

110: photoresist layer

112: silicon oxide layer

114: silicon nitride layer

116: Silicon oxide layer

118: polysilicon layer

A: area

P1: Back etching step

P2: etching step

P3: etching step

H1: height

H2: height

H3: height

H4: height

H5: height

Figures 1 and 2 provide schematic cross-sectional flow diagrams for manufacturing the semiconductor memory device of the present invention.

FIG. 3A is a schematic structural view of continuing the subsequent manufacturing process from the semiconductor memory structure shown in FIG. 2 according to one embodiment of the present invention.

FIG. 3B illustrates another embodiment of the present invention, which is based on the semiconductor memory shown in FIG. 2 Schematic diagram of the memory structure to continue the subsequent process.

FIG. 4A and FIG. 4B respectively illustrate the structural schematic diagrams of continuing the subsequent manufacturing process according to the semiconductor memory structure shown in FIGS. 3A and 3B.

FIG. 5 provides a schematic cross-sectional flow diagram of manufacturing the semiconductor memory device of the present invention.

In order to enable those of ordinary skill in the art of the present invention to further understand the present invention, the preferred embodiments of the present invention are specifically enumerated below, and in conjunction with the accompanying drawings, the composition of the present invention and the desired effects are described in detail .

For the convenience of description, the drawings of the present invention are only schematic diagrams to make it easier to understand the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As described in the text, the relative relationship of the relative elements in the figure should be understood by those skilled in the art as it refers to the relative position of the objects, so they can be turned over to present the same components, which should belong to the The scope of disclosure is described here first.

Please refer to FIG. 1 and FIG. 2, which provide cross-sectional flow charts for manufacturing the semiconductor memory device of the present invention. As shown in FIG. 1, a substrate 100 is provided, and a device area 102 and a logic area 104 are defined on the substrate 100. The element area 102 usually contains elements such as bit lines and word lines that are formed later, and the logic area 104 usually contains transistors for read/write circuits and/or other circuits to support the memory element. run. Generally speaking, the elements in the element area 102 have a larger element density, that is, the elements are arranged closer, and the element arrangement in the logic area 104 is looser and the element density is smaller.

In addition, a plurality of shallow trench isolations 106 and a polysilicon layer 108 are formed on the substrate 100, and are located in the device region 102 and the logic region 104. The shallow trench isolation 106 is generally linear and arranged in parallel. In this embodiment, the upper surface 106S of the shallow trench isolation 106 is higher than the surface 100S of the substrate 100. The material of the shallow trench isolation 106 is, for example, silicon oxide, but it is not limited thereto.

As for the polysilicon layer 108, for example, after each shallow trench isolation 106 is completed, a polysilicon material layer (not shown) is formed in the device region 102 and the logic region 104 in an all-round way, and then a planarization step is performed. The excess polysilicon material layer is removed until at least a portion of the top of the shallow trench isolation 106 is exposed. It is worth noting that the above-mentioned elements in the logic area 104 are arranged loosely, so there may be some areas where no elements are formed, such as shallow trench isolation 106. If these areas are large, they are etched or flat The etching process will be etched faster than other areas. For example, in Figure 1, a large area A is defined. During the planarization step, the etching rate of area A will be faster than other areas with higher density of devices (such as any area in device area 102), so when After the planarization step is completed, the polysilicon layer 108 in the area A will be etched more, causing the top surface of the polysilicon layer 108 in the area A to be lower than the top surface of the polysilicon layer 108 in other areas. In addition, the surface of the shallow trench isolation 106 adjacent to the area A may also be recessed, causing part of the polysilicon layer 108 to remain on the shallow trench isolation (such as the polysilicon layer 108C in FIG. 1). However, in other regions (such as the device region 102), after the planarization step, the top surface of the shallow trench isolation 106 and the top surface of the polysilicon layer 108 are still the same height. In addition, a liner layer 103 is also included between the substrate 100 and each polysilicon layer 108. The liner layer material is, for example, silicon oxide or a composite layer composed of silicon oxide and silicon nitride.

Next, as shown in Figure 2, perform an etching step P1, in the unmasked In this case, part of the shallow trench isolation 106 and part of the polysilicon layer 108 are simultaneously removed. It is worth noting that, in the present invention, after the polysilicon layer 108 in the above-mentioned area A, after the etching back step P1, a certain thickness of the polysilicon layer 108 needs to be reserved in the area A to avoid the excessively thin thickness in the subsequent etching step The substrate 100 is exposed. Taking this embodiment as an example, after the etch back step P1, the thickness of the polysilicon layer 108 in the region A (the height from the top surface of the substrate 100) is preferably greater than 400 angstroms. Taking this embodiment as an example, the height H1 is, for example, 500 Egypt. As for the device region 102, the height of the polysilicon layer 108 in the device region 102 is aligned with the shallow trench isolation 106, and the height H2 of the polysilicon layer 108 in the device region 102 should not be affected by the depression caused by the planarization step. The height H1 of the polysilicon layer 108 in the region A is higher than the height H1 of the embodiment, for example, 600 angstroms, but not limited to this.

After the planarization step and the etch-back step P1 are performed, next, as shown in FIGS. 3A and 3B, FIG. 3A illustrates a semiconductor memory shown in FIG. 2 according to one embodiment of the present invention. FIG. 3B is a structural schematic diagram of the body structure to continue the subsequent process. FIG. 3B is a schematic structural diagram of the semiconductor memory structure shown in FIG. 2 to continue the subsequent process according to another embodiment of the present invention. Referring to FIGS. 3A and 3B, a photoresist layer 110 is covered in the logic region 104, and then an etching step P2 is performed on the shallow trench isolation 106 and the polysilicon layer 108 exposed in the device region 102, and partially removed The shallow trench isolation 106 and the polysilicon layer 108 in the device region 102. The difference between the embodiment shown in FIG. 3A and FIG. 3B is that the etching step P2 can be controlled by adjusting the parameters of the etching step P2, or selecting different types of etchants, adjusting the mixing ratio of the etchant, etc. The etching rate of the shallow trench isolation 106 and the polysilicon layer 108. In the embodiment shown in FIG. 3A, the parameters of the etching step P2 are adjusted so that the etching rates of the shallow trench isolation 106 and the polysilicon layer 108 are nearly the same. After the etching step P2 is performed, the shallow trench isolation 106 in the element region 102 With polycrystalline The height of the silicon layer 108 is reduced to H3, which means that the shallow trench isolation 106 in the device region 102 and the polysilicon layer 108 are approximately the same height. In this embodiment, H3 is about 450 angstroms, but it is not limited thereto.

As for the embodiment shown in FIG. 3B, the parameters of the etching step P2 are adjusted so that the rate of etching the polysilicon layer 108 is less than the rate of etching the shallow trench isolation 106, for example, the polysilicon layer etching rate: shallow trench isolation=3:5, so After the etching step P2 is performed, the height of the shallow trench isolation 106 in the device region 102 is H4, and the height of the polysilicon layer 108 is H5. In this embodiment, H4 is about 350 angstroms and H5 is about 450 angstroms, but not limited to this .

Please refer to FIG. 4A and FIG. 4B, which respectively show schematic structural diagrams of continuing the subsequent manufacturing process according to the semiconductor memory structure shown in FIG. 3A and FIG. 3B. After the photoresist layer 110 is removed, an etching step P3 is continued. Similarly, the height of the shallow trench isolation 106 and the polysilicon layer 108 can be controlled by adjusting the etching parameters of the etching step P3. In this embodiment shown in FIGS. 4A and 4B, since there is no protection of the photoresist layer 110, all the shallow trench isolations 106 and the polysilicon layer 108 in the device region 102 and the logic region 104 will be in the etching step P3. It was partially removed during the process. However, the etching step P3 does not completely remove the polysilicon layer 108 in the device region 102. The difference between the embodiment shown in FIG. 4A and FIG. 4B is that the etching selection ratio of the etching step P3 is different. That is, the etching step P3 is adjusted so that the rate of etching the shallow trench isolation 106 and the rate of etching the polysilicon layer 108 are different. In the embodiment shown in FIG. 4A, the etching step P3 causes the top surface height of each polysilicon layer 108 in the device region 102 and the logic region 104 to decrease by about 50 angstroms, and the shallow trench isolation 106 in the device region 102 and the logic region 104 The height of the top surface drops by about 200 angstroms. In the embodiment shown in FIG. 4B, the etching step P3 causes the top surface of each polysilicon layer 108 in the device region 102 and the logic region 104 The height decreases by about 50 angstroms, and the top surface of each shallow trench isolation 106 in the device region 102 and the logic region 104 decreases by about 100 angstroms. Of course, it is understandable that the present invention is not limited thereto, and the above etching parameters can be adjusted according to actual needs.

After the etching step P3 is performed, referring to FIG. 4A or FIG. 4B, the top surface height of the shallow trench isolation 106 and the polysilicon layer 108 in the device region 102, and the top of the shallow trench isolation 106 and the polysilicon layer 108 in the logic region 104 The surface heights are different. It is also worth noting that, taking FIG. 4A as an example, the shallow trench isolation 106 in the device region 102 (eg, shallow trench isolation 106A in FIG. 4A) and the shallow trench isolation 106 in the logic region 104 (eg, FIG. 4A) (The shallow trench isolation 106B) The bottom surfaces of the two are on the same horizontal plane, but the top surface of the shallow trench isolation 106A is lower than the top surface of the shallow trench isolation 106B. Similarly, the bottom surfaces of the polysilicon layer 108A in the device region 102 and the polysilicon layer 108B in the logic region 104 are on the same horizontal plane, while the top surface of the polysilicon layer 108A is higher than the top surface of the polysilicon layer 108B.

In the present invention, the photoresist layer 110 is used to cover part of the region (such as the logic region 104), and then the parameters of the etching process are adjusted to control the shallow trench isolation 106 and the polysilicon layer 108 in the device region 102 and the logic region 104 The height difference, and further form a variety of different height components. In a specific semiconductor manufacturing process, the devices located in the device region 102 and the devices located in the logic region 104 have different sizes, sizes, and distributions. Therefore, it is necessary to more easily adjust the parameters of the process to meet the requirements of different device sizes. The method of the present invention can increase the flexibility of the manufacturing process.

The method of forming the gate structure of the memory will be described later. As shown in FIG. 5, a patterned multilayer structure is sequentially formed on the polysilicon layer 108, wherein the patterned multilayer structure may include It includes a silicon oxide layer 112, a silicon nitride layer 114, a silicon oxide layer 116 (the above three may be collectively referred to as ONO stack layers in some embodiments), and a polysilicon layer 118. The polysilicon layer 108 is used as a material layer for the floating gate (FG) of the subsequent memory, and the polysilicon layer 118 is used as a material layer for the control gate (CG) of the subsequent memory. It is worth noting that the paragraphs and related drawings in FIG. 5 focus on describing the structure formation of the memory, so the fabrication of some elements will be omitted, such as doping P-type wells or N-type wells in the substrate. These technical features belong to the relevant knowledge known to those skilled in the art, and will not be repeated here.

In the subsequent steps, the above ONO stack layer (including the silicon oxide layer 112, the silicon nitride layer 114, and the silicon oxide layer 116) and the polysilicon layer 118 are patterned to form a plurality of memory gate structures in the device region 102 and select Side walls (not shown) are formed by the patterned memory gate. In addition, some elements (such as resistors) will also be formed in the logic area 104 in subsequent steps. The steps described herein also belong to known technologies in the art, and will not be described here.

In summary, the present invention is characterized by using a photoresist layer to cover some areas (such as the logic area), and then adjusting the etching process parameters to control the shallow trench isolation in the device area and the logic area and the polysilicon layer. The height difference, and further form a variety of different height components. In this way, the method of the present invention can increase the flexibility of the manufacturing process. In addition, when depositing a polysilicon layer in the present invention, the thickness of the polysilicon layer is increased (greater than 400 angstroms) to avoid the erosion of the polysilicon layer during the planarization step, which affects the quality of the subsequent memory stack structure.

The above are only the preferred embodiments of the present invention. Equal changes and modifications shall fall within the scope of the present invention.

100: base

100S: top surface

102: component area

103: liner layer

104: logical area

106: Shallow trench isolation

108: polysilicon layer (floating gate)

110: photoresist layer

P2: etching step

H1: height

H3: height

Claims (15)

A method for manufacturing a semiconductor memory device includes: providing a substrate with a device area and a logic area defined on the substrate; forming a plurality of shallow trenches isolated in the substrate, and forming a floating gate material layer on the substrate; performing a flattening After the planarization step, a top surface of each shallow trench isolation and a top surface of the floating gate material layer are higher than a top surface of the substrate; in the floating gate material layer and the shallow After trench isolation is formed, a photoresist layer is formed to cover the logic region; a first etching step is performed to remove a portion of the shallow trench isolation and a portion of the floating gate material layer in the device area; and remove the photoresist layer And performing a second etching step to remove portions of the shallow trench isolation and a portion of the floating gate material layer in the device area and the logic area. The method as described in item 1 of the patent application scope, wherein after the planarization step, an etching step is further performed to remove a portion of the shallow trench isolation and a portion of the part in the device region and the logic region Floating gate material layer. The method as described in item 2 of the patent application scope, wherein a large area area is further defined in the logic area, and after the planarization step, one of the floating gate material layers in the large area area has a low top surface The top surfaces are isolated by the shallow trenches in the logic area. The method as described in item 3 of the patent application scope, in which the step of etching back After the row, a vertical distance from the top surface of the substrate in the large area area to the top surface of the floating gate material layer is greater than 400 angstroms. The method according to item 1 of the patent application scope, wherein after the planarization step, the top surface of the floating gate material layer in the device region is isolated from the top surface of each shallow trench in the device region Cut it all. The method as described in item 1 of the patent application scope, wherein after the first etching step, the top surface of each shallow trench isolation in the element region is aligned with the top surface of the floating gate material layer. The method according to item 1 of the patent application scope, wherein after the first etching step, the top surface of each shallow trench isolation in the element region is lower than the top surface of the floating gate material layer. The method as described in item 1 of the patent application scope, wherein after the second etching step, a part of the floating gate material layer is still located in the device region. The method as described in item 1 of the patent application scope, wherein after the second etching step, the top surface of the floating gate material layer in the logic region is higher than that of the floating gate material layer in the device region Top surface. The method according to item 1 of the patent application scope, wherein after the second etching step, the top surface of the shallow trench isolation in the logic region is higher than the shallow surface in the device region Top surface of trench isolation. According to the method described in item 1 of the patent application scope, after the second etching step, a method of covering a stacked structure in the device area and the logic area is further included. The method described in item 11 of the patent application scope further includes performing a patterning step to remove a part of the stacked structure to form at least one memory gate structure in the logic area. The method as described in item 12 of the patent application range, wherein the memory gate structure includes at least a portion of the floating gate material layer, a stack layer of silicon oxide-silicon nitride-silicon oxide, and a control Gate material layer. The method as recited in item 12 of the patent application scope, further comprising forming at least one sidewall on the sidewall of the memory gate structure. The method as described in item 12 of the patent application scope, wherein after the formation of the memory gate structure, a third etching step is further performed to completely remove the floating gate material layer located in the device area.

Images