CN103681308A - Preparation method for multi-type silicide mask layer - Google Patents
Preparation method for multi-type silicide mask layer Download PDFInfo
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- CN103681308A CN103681308A CN201310505099.6A CN201310505099A CN103681308A CN 103681308 A CN103681308 A CN 103681308A CN 201310505099 A CN201310505099 A CN 201310505099A CN 103681308 A CN103681308 A CN 103681308A
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- mask layer
- silicide
- area
- formation method
- etching
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 54
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000012010 growth Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000243 solution Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000034655 secondary growth Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to the field of semiconductor manufacture, especially to a preparation method for a multi-type silicide mask layer. The method comprises the following steps that a semiconductor substrate is provided, and a first silicide mask layer is grown at a grid structure and the exposed upper surface of the semiconductor substrate; part of the first mask layer is removed in a first etching technology by means of a first mask, thereby forming a first mask layer residual structure; a second mask layer is grown while the first mask layer residual structure, the surface of the grid, and the exposed upper surface of the substrate are covered; and part of the second mask layer and the first mask layer residual structure are removed in a second etching technology by means of a second mask. The preparation method provided by the invention can form a pure silicon oxide mask layer in an area which requires growth of the pure silicon oxide mask layer in the semiconductor, and improves the production technology.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to the formation method of one kind of multiple class silicide mask layers.
Background technology
Along with the development of semiconductor technology, more and more higher to the requirement of device performance, in some semi-conductive manufacturing process, need to form silicide mask layer to retain the electronics writing at semiconductor device surface, and then device performance is provided.
Silicide mask layer is to be mainly used as silicide autoregistration growth, if and by pure silica as silicide mask layer, the etching technics of mask layer is proposed to high requirement, be even difficult to reach, and adopt the combination of silica/silicon nitride, can greatly reduce the difficulty of etching technics.Some particular device techniques but, as disposable programmable (OTP) device, can retain the electronics writing by silicide mask layer, and silicon nitride is unfavorable for writing the reservation of electronics, easily cause electron loss, have no alternative but to be used as its silicide mask layer by silica, existing technique is all to take the silicide mask layer of single thickness and structure as main, and is forced to the silicide mask layer of whole chip internal to adjust to unanimously in order to take into account some special applications (as OTP).Although this method has been simplified technological process, lack flexibility, increased technology difficulty, sacrificed process window, especially SRAM yield is had to impact.
Chinese patent (application number: 201110266445.0) disclose a kind of method of preparing the semiconductor device with multi-thickness silicide mask layer, specifically comprise the following steps: on semiconductor device, determine and need retain by silicide mask layer two regions of the ion writing, and according to the required time of keeping injection ion here, determine the different-thickness requirement in described two regions; On semiconductor device, form ground floor silicide mask layer, second layer silicide mask layer; By etching, remove the second layer silicide mask layer of subregion, make the combination of remaining ground floor silicide mask layer and ground floor silicide mask layer and second layer silicide mask layer meet the different-thickness requirement in described two regions.
But this invention is only to provide a kind of method of preparing the silicide mask layer of different-thickness, second layer silicide mask layer is covered in the top of ground floor silicide mask layer, and the increase of mask layer thickness also can be with simultaneously and be served adverse effect, there is in actual applications certain limitation, therefore those skilled in the art endeavour to study a kind of method that multiple types silicide mask layer coexists of preparing, with continuous boost device performance.
Summary of the invention
The present invention provides a kind of kind silicide mask layer and has deposited technique according to the deficiencies in the prior art, by growing twice mask layer carry out three step etching technics, finally in the pure silica compound mask layer region of needs growth, form the mask layer of pure silica, do not needing the region of silicide mask layer of growth by its removal, make different types of silicide mask layer be able to coexist on semiconductor device, greatly reduce the difficulty of etching technics, be conducive to writing the reservation of electronics simultaneously, and then improve device performance.
The technical solution used in the present invention is:
A formation method for silicide mask layer, is applied to, in silicide autoregistration growth technique, wherein, comprise the following steps:
One semiconductor structure with substrate is provided, on described semiconductor structure, comprises first area and second area;
Deposit after the upper surface that the first mask layer covers described Semiconductor substrate, adopt the first etching technics to remove the first mask layer that is arranged in described first area;
Deposit the second mask layer and cover described semiconductor structure upper surface and remain after the upper surface of the first mask layer, adopt the second etching technics to remove and be arranged in described second area the second mask layer and part the first mask layer, to form multiple types silicide mask layer;
Wherein, the material of described the second mask layer is silica.
The formation method of above-mentioned a kind of silicide mask layer, wherein, described the first mask layer material is silica and silicon nitride.
The formation method of above-mentioned a kind of silicide mask layer, wherein, described the first etching technics is dry etch process.
The formation method of above-mentioned a kind of silicide mask layer, wherein, adopts the first mask plate to carry out dry etching and removes the first mask layer that is arranged in described first area.
The formation method of above-mentioned a kind of silicide mask layer, wherein, described the second etching technics comprises wet-etching technology and dry etch process.
The formation method of above-mentioned a kind of silicide mask layer, wherein, by the second mask plate, adopt dry etch process to remove after the second mask layer of second area, then use wet etching to remove the part first mask layer remaining structure in this region by described the second mask plate.
The formation method of above-mentioned a kind of silicide mask layer, wherein, described first area is for being formed with the region of silicon oxide masking film layer, and described second area is the region of semiconductor structure except first area.
The formation method of above-mentioned a kind of silicide mask layer, wherein, the thickness of described the second mask layer is
Because the present invention has adopted above technical scheme, by the different types of mask layer of two secondary growths, and carry out different etching technics by different mask plates, finally on semiconductor structure, form different types of nitride mask layer, be conducive to writing the reservation of electronics and then having improved device performance.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the schematic diagram of semiconductor structure provided by the invention;
Fig. 2 is the structural representation that the present invention grows after the first mask layer;
Fig. 3 is that the present invention adopts the structural representation after the first etching technics;
Fig. 4 is the structural representation that the present invention grows after the second mask layer;
Fig. 5-6 adopt the structural representation after the second etching technics for the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The flow chart of the formation method that Fig. 1-6 are one kind of multiple class silicide mask layers of the present invention, specifically comprises the following steps:
Step S1, provide semiconductor structure, this semiconductor structure comprises a substrate 1, on this substrate 1, be formed with a well region 2, well region upper surface is formed with a plurality of grid structures, the side wall of grid structure is coated with a sidewall oxide, and the sidewall oxide lower surface of grid structure is positioned at well region and is formed with ion doped region, simultaneously, well region between neighboring gates structure oxide layer is formed with the ion doped region different from sidewall oxide lower surface, as shown in Figure 1 structure.
Step S2, in the upper surface of semiconductor structure first mask layer 3 of growing, preferred, this first mask layer 3 be the silicide mask layer of silica and silicon nitride composition, as shown in Figure 2 structure.
Step S3, by the first mask plate, the pure silica compound mask layer region A1(Ji first area A1 that adopts dry etch process removal to grow) the first mask layer 3, due to by the first mask plate carry out dry etching, can guarantee in etching technics, only remove the first mask layer of first area A1, A2 region beyond in semiconductor structure A1 region form the first mask layer remaining structure 3 ', structure as shown in Figure 3.
Step S4, in semiconductor structure upper surface second mask layer 4 of growing, preferred, this second mask layer growth thickness is
to meet process requirements; Simultaneously this second mask layer 4 cover A1 region and the first mask layer remaining structure 3 ' surface, structure as shown in Figure 4.
Step S5, by the second mask plate, adopt wet-etching technology to remove second mask layer 4 in A2 region; Due to by the second mask plate carry out wet etching; in etching process, can guarantee second mask layer 4 in etching removal A2 region; avoid the mask layer of first area A1 to cause damage; simultaneously due at second area A2, be formed with the first mask layer remaining structure 3 '; semiconductor structure that also can fine protection first mask layer remaining structure 4 ' lower surface when wet etching; avoid etching it to be caused to damage; after this step completes, in A1 region, form the second mask layer remaining structure 4 ', structure as shown in Figure 5.
Step S6, again by the second mask plate, the part first mask layer remaining structure 3 in employing dry etching removal A2 region ', and retain according to technological requirement the first mask layer remaining structure 3 ' (not the marking in figure) that A2 region need to be formed with the position of silicide mask layer, and the mask layer 4 of the pure silica of A1 region formation the most finally compound formation ', in A2 region, be formed with the region (not marking in figure) that mask layer that partial oxygen SiClx and silicon nitride form covers simultaneously, structure as shown in Figure 6, make different types of silicide mask layer be able to coexist on semiconductor device, be conducive to writing the reservation of electronics and then improving device performance.
In sum, because the present invention has adopted above technical scheme, by the different mask layer of two secondary growths and adopt etching technics three times, finally in the pure silica compound mask layer region of needs growth, form the mask layer of pure silica, do not needing the region of silicide mask layer of growth by its removal, make different types of silicide mask layer be able to coexist on semiconductor device, greatly reduce the difficulty of etching technics, be conducive to writing the reservation of electronics simultaneously, and then improve device performance.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (8)
1. a formation method for silicide mask layer, is applied to, in silicide autoregistration growth technique, it is characterized in that, comprises the following steps:
One semiconductor structure with substrate is provided, on described semiconductor structure, comprises first area and second area;
Deposit after the upper surface that the first mask layer covers described substrate, adopt the first etching technics to remove the first mask layer that is arranged in described first area;
Deposit the second mask layer and cover described semiconductor structure upper surface and remain after the upper surface of the first mask layer, adopt the second etching technics to remove and be arranged in described second area the second mask layer and part the first mask layer, to form multiple types silicide mask layer;
Wherein, the material of described the second mask layer is silica.
2. the formation method of a kind of silicide mask layer according to claim 1, is characterized in that, described the first mask layer material is silica and silicon nitride.
3. the formation method of a kind of silicide mask layer according to claim 1, is characterized in that, described the first etching technics is dry etch process.
4. the formation method of a kind of silicide mask layer according to claim 3, is characterized in that, adopts the first mask plate to carry out dry etching and removes the first mask layer that is arranged in described first area.
5. the formation method of a kind of silicide mask layer according to claim 1, is characterized in that, described the second etching technics comprises wet-etching technology and dry etch process.
6. the formation method of a kind of silicide mask layer according to claim 5, it is characterized in that, by the second mask plate, adopt dry etch process to remove after the second mask layer of second area, then use wet etching to remove the part first mask layer remaining structure in this region by described the second mask plate.
7. the formation method of a kind of silicide mask layer according to claim 1, is characterized in that, described first area is for being formed with the region of silicon oxide masking film layer, and described second area is the region of semiconductor structure except first area.
8. the formation method of a kind of silicide mask layer according to claim 1, is characterized in that, the thickness of described the second mask layer is
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310505099.6A CN103681308B (en) | 2013-10-23 | 2013-10-23 | The formation method of multiple types silicide mask layer |
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| CN201310505099.6A CN103681308B (en) | 2013-10-23 | 2013-10-23 | The formation method of multiple types silicide mask layer |
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| CN103681308B CN103681308B (en) | 2016-04-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105565252A (en) * | 2014-10-10 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | MEMS (Micro-Electro-Mechanical System) device, manufacturing method thereof and electronic device |
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| US6977408B1 (en) * | 2003-06-30 | 2005-12-20 | Lattice Semiconductor Corp. | High-performance non-volatile memory device and fabrication process |
| US7033957B1 (en) * | 2003-02-05 | 2006-04-25 | Fasl, Llc | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices |
| CN1819144A (en) * | 2004-12-10 | 2006-08-16 | 国际商业机器公司 | Device having dual etch stop liner and reformed silicide layer and related methods |
| CN1819145A (en) * | 2004-12-10 | 2006-08-16 | 国际商业机器公司 | Device having dual etch stop liner and protective layer and related methods |
| CN101170115A (en) * | 2007-11-21 | 2008-04-30 | 上海宏力半导体制造有限公司 | A non volatile memory structure and its making method |
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2013
- 2013-10-23 CN CN201310505099.6A patent/CN103681308B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7033957B1 (en) * | 2003-02-05 | 2006-04-25 | Fasl, Llc | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices |
| US6977408B1 (en) * | 2003-06-30 | 2005-12-20 | Lattice Semiconductor Corp. | High-performance non-volatile memory device and fabrication process |
| CN1819144A (en) * | 2004-12-10 | 2006-08-16 | 国际商业机器公司 | Device having dual etch stop liner and reformed silicide layer and related methods |
| CN1819145A (en) * | 2004-12-10 | 2006-08-16 | 国际商业机器公司 | Device having dual etch stop liner and protective layer and related methods |
| CN101170115A (en) * | 2007-11-21 | 2008-04-30 | 上海宏力半导体制造有限公司 | A non volatile memory structure and its making method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105565252A (en) * | 2014-10-10 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | MEMS (Micro-Electro-Mechanical System) device, manufacturing method thereof and electronic device |
| CN105565252B (en) * | 2014-10-10 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
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