CN108054091B - A method of promoting MOS device grid-control ability - Google Patents
A method of promoting MOS device grid-control ability Download PDFInfo
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- CN108054091B CN108054091B CN201711376700.0A CN201711376700A CN108054091B CN 108054091 B CN108054091 B CN 108054091B CN 201711376700 A CN201711376700 A CN 201711376700A CN 108054091 B CN108054091 B CN 108054091B
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000001737 promoting effect Effects 0.000 title claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 65
- 229920005591 polysilicon Polymers 0.000 claims abstract description 65
- 230000001413 cellular effect Effects 0.000 claims abstract description 36
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 33
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000004408 titanium dioxide Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of method for promoting MOS device grid-control ability, belongs to technical field of manufacturing semiconductors, comprising: the upper surface for providing the substrate that a substrate is located at cellular region is equipped with FGS floating gate structure, deposits one first polysilicon layer；Deposit a silicon dioxide layer；Etching removal is located at the silicon dioxide layer of cellular region；Deposit the silicon dioxide layer that the covering of one second polysilicon layer is located at external zones；Etching is located at the first polysilicon layer and FGS floating gate structure layer of cellular region, to form multiple control gates and the floating gate under control gate in cellular region, and removes the second polysilicon layer and silicon dioxide layer for being located at external zones；Etching removal is located at the first polysilicon layer of external zones, and to form multiple polysilicon gates in external zones, the height of polysilicon gate is less than the height of control gate.Beneficial effects of the present invention: under conditions of not changing control gate height, reducing the height of polysilicon gate, promotes the grid-control ability of MOS device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of methods for promoting MOS device grid-control ability.
Background technique
The height of the area edge (Periphery) polysilicon gate directly affects the grid-control ability of MOS device, and existing way is
It reduces the deposition of substrate polysilicon grid directly to reduce the height of polysilicon gate, promotes the grid-control ability of MOS device.
The advantage of existing way is that technical process is simple, and disadvantage is the control gate that can also reduce the area cellular (cell) accordingly
Height also can be reduced accordingly, to influence the performance of the area cell device, and the ion implanting in the area cell easily propagate through it is too low
Control gate damages oxide layer-nitride layer-oxide layer (OXIDE NITRIDE OXIDE, ONO) and tunnel oxide (tunnel
OX)。
Summary of the invention
Aiming at the problems existing in the prior art, the present invention relates to a kind of methods for promoting MOS device grid-control ability.
The present invention adopts the following technical scheme:
A method of promoting MOS device grid-control ability, comprising:
Step S1, a substrate is provided, the substrate includes external zones and cellular region, the substrate positioned at the cellular region
Upper surface be equipped with FGS floating gate structure, deposit one first polysilicon layer, first polysilicon layer covering is located at the external zones
The substrate and the FGS floating gate structure layer positioned at the cellular region；
Step S2, a silicon dioxide layer is deposited, the silicon dioxide layer covers first polysilicon layer；
Step S3, etching removal is located at the silicon dioxide layer of the cellular region；
Step S4, one second polysilicon layer is deposited, the second polysilicon layer covering is located at described the two of the external zones
Silicon oxide layer；
Step S5, etching is located at first polysilicon layer and the FGS floating gate structure layer of the cellular region, described
Cellular region formed multiple control gates being made of first polysilicon layer and under the control gate by the floating gate knot
The floating gate that structure layer is constituted, and remove second polysilicon layer for being located at the external zones and the silicon dioxide layer；
Step S6, etching removal is located at first polysilicon layer of the external zones, more to be formed in the external zones
A polysilicon gate being made of first polysilicon layer, the height of the polysilicon gate are less than the height of the control gate.
Preferably, the FGS floating gate structure layer includes being successively set on the substrate of the cellular region from the bottom to top
The first insulating layer, floating gate polysilicon layer and second insulating layer.
Preferably, in the step S3, using the silicon dioxide layer as exposure mask, in the dioxy for being located at the cellular region
The first etching window is formed on SiClx layer, and is located at described the two of the cellular region according to first etching window etching removal
Silicon oxide layer.
Preferably, the first etching window is formed in the silicon dioxide layer for being located at the cellular region by photoetching
Mouthful.
Preferably, in the step S3, the silicon dioxide layer of the cellular region is located at using dry etching removal.
Preferably, in the step S5, the control gate is formed using dry etching.
Preferably, in the step S6, the polysilicon gate is formed using dry etching.
Beneficial effects of the present invention: under conditions of not changing control gate height, reducing the height of polysilicon gate, is promoted
The grid-control ability of MOS device.
Detailed description of the invention
Fig. 1 is the flow chart that the method for MOS device grid-control ability is promoted in a preferred embodiment of the present invention；
Fig. 2-7 is the process signal for the method that MOS device grid-control ability is promoted in a preferred embodiment of the present invention
Figure.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in figs. 1-7, a method of promoting MOS device grid-control ability, comprising:
Step S1, a substrate 1 is provided, above-mentioned substrate 1 includes external zones and cellular region, the above-mentioned lining positioned at above-mentioned cellular region
The upper surface at bottom 1 is equipped with FGS floating gate structure, deposits one first polysilicon layer 3, and the above-mentioned covering of first polysilicon layer 3 is located at above-mentioned periphery
The above-mentioned substrate 1 in area and above-mentioned FGS floating gate structure floor 2 positioned at above-mentioned cellular region；
Step S2, a silicon dioxide layer 4 is deposited, above-mentioned silicon dioxide layer 4 covers above-mentioned first polysilicon layer 3；
Step S3, etching removal is located at the above-mentioned silicon dioxide layer 4 of above-mentioned cellular region；
Step S4, one second polysilicon layer 6 is deposited, the above-mentioned covering of second polysilicon layer 6 is located at the above-mentioned of above-mentioned external zones
Silicon dioxide layer 4；
Step S5, etching is located at above-mentioned first polysilicon layer 3 and above-mentioned FGS floating gate structure layer 2 of above-mentioned cellular region, upper
State cellular region formed multiple control gates being made of above-mentioned first polysilicon layer 3 and under above-mentioned control gate by above-mentioned floating gate
The floating gate that structure sheaf 2 is constituted, and remove above-mentioned second polysilicon layer 6 and above-mentioned silicon dioxide layer 4 for being located at above-mentioned external zones；
Step S6, etching removal is located at above-mentioned first polysilicon layer 3 of above-mentioned external zones, more to be formed in above-mentioned external zones
A polysilicon gate being made of above-mentioned first polysilicon layer 3, the height of above-mentioned polysilicon gate are less than the height of above-mentioned control gate.
In the present embodiment, in view of in the prior art, enough grid-control energy are obtained by reducing the deposition of polysilicon
Power will greatly affect the device performance in the area cell.The present invention passes through stepped depositions the first polysilicon layer 3 and the second polysilicon layer
6, and silica is realized as hard mask layer under conditions of control gate height in the area cell is constant, reduce periphery
Area's polysilicon gate height.
The present invention is considered from the angle of process integration, and process sequence is optimized, and is guaranteeing that control gate height in the area cell is constant
Under the premise of, exhausting for polysilicon is reduced by reducing the height of the area periphery polysilicon gate, promotes the area periphery
Grid-control ability.
In preferred embodiment, above-mentioned grid structure layer includes being successively set on from the bottom to top positioned at the above-mentioned of above-mentioned cellular region
The first insulating layer 21, floating gate polysilicon layer 22 and second insulating layer 23 on substrate 1, the first insulating layer 21, floating gate polysilicon layer
22 and second insulating layer 23 can be modified according to actual fabrication technique additions and deletions.
It is exposure mask (hard exposure mask) with above-mentioned silicon dioxide layer 4 in above-mentioned steps S3 in preferred embodiment, it is upper being located at
It states and forms the first etching window in the above-mentioned silicon dioxide layer 4 of cellular region, and removal position is etched according to above-mentioned first etching window
Above-mentioned silicon dioxide layer 4 in above-mentioned cellular region.
In the present embodiment, using the silica in photoetching plus dry etching removal the first polysilicon layer of the area cell 3, such as
Shown in attached drawing 4, the silica on etching removal the first polysilicon layer of the area cell 3 is realized using the first photoresist layer (PR1) 5.
In preferred embodiment, in above-mentioned steps S3, in above-mentioned steps S3, above-mentioned cellular is located at using dry etching removal
The above-mentioned silicon dioxide layer 4 in area.
In preferred embodiment, in above-mentioned steps S5, above-mentioned control gate is formed using dry etching.
In the present embodiment, control gate is formed using photoetching plus dry etching, and removes the dioxy in the area periphery simultaneously
The second polysilicon layer 6 in SiClx and silica realizes etching shape using the second photoresist layer (PR2) 7 as shown in Fig. 6
At control gate.
In preferred embodiment, in above-mentioned steps S3, in above-mentioned steps S6, above-mentioned polysilicon is formed using dry etching
Grid.
In the present embodiment, above-mentioned polysilicon gate is formed using photoetching plus dry etching.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (7)
1. a kind of method for promoting MOS device grid-control ability characterized by comprising
Step S1, a substrate is provided, the substrate includes external zones and cellular region, positioned at the cellular region the substrate it is upper
Surface is equipped with FGS floating gate structure layer, deposits one first polysilicon layer, and the first polysilicon layer covering is located at the institute of the external zones
State substrate and the FGS floating gate structure layer positioned at the cellular region；
Step S2, a silicon dioxide layer is deposited, the silicon dioxide layer covers first polysilicon layer；
Step S3, etching removal is located at the silicon dioxide layer of the cellular region；
Step S4, one second polysilicon layer is deposited, the second polysilicon layer covering is located at the titanium dioxide of the external zones
Silicon layer；
Step S5, etching is located at first polysilicon layer and the FGS floating gate structure layer of the cellular region, in the cellular
Area formed multiple control gates being made of first polysilicon layer and under the control gate by the FGS floating gate structure floor
The floating gate of composition, and remove second polysilicon layer for being located at the external zones and the silicon dioxide layer；
Step S6, etching removal be located at the external zones first polysilicon layer, with the external zones formed it is multiple by
The polysilicon gate that first polysilicon layer is constituted, the height of the polysilicon gate are less than the height of the control gate.
2. the method according to claim 1, which is characterized in that the grid structure layer includes being successively set on from the bottom to top positioned at institute
State the first insulating layer, floating gate polysilicon layer and the second insulating layer on the substrate of cellular region.
3. the method according to claim 1, which is characterized in that in the step S3, using the silicon dioxide layer as exposure mask, in place
In forming the first etching window in the silicon dioxide layer of the cellular region, and is etched and removed according to first etching window
The silicon dioxide layer positioned at the cellular region.
4. according to the method in claim 3, which is characterized in that in the step S3, be located at the cellular region by photoetching
First etching window is formed in the silicon dioxide layer.
5. the method according to claim 1, which is characterized in that in the step S3, be located at the member using dry etching removal
The silicon dioxide layer in born of the same parents area.
6. the method according to claim 1, which is characterized in that in the step S5, form the control gate using dry etching.
7. the method according to claim 1, which is characterized in that in the step S6, form the polysilicon using dry etching
Grid.
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