CN108807406A - A method of promoting device grid-control ability - Google Patents
A method of promoting device grid-control ability Download PDFInfo
- Publication number
- CN108807406A CN108807406A CN201810556671.4A CN201810556671A CN108807406A CN 108807406 A CN108807406 A CN 108807406A CN 201810556671 A CN201810556671 A CN 201810556671A CN 108807406 A CN108807406 A CN 108807406A
- Authority
- CN
- China
- Prior art keywords
- grid
- polysilicon layer
- layer
- control ability
- external zones
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
Abstract
The present invention relates to a kind of methods promoting device grid-control ability, include the following steps：Substrate is provided, the substrate is divided into device region and external zones；The first polysilicon layer is deposited over the substrate；The deposited silicon dioxide layer on the first polysilicon layer；Remove the silicon dioxide layer on the device region；The second polysilicon layer is deposited on the first polysilicon layer of the device region；Remove the silicon dioxide layer on the external zones；And the second polysilicon layer and the first polysilicon layer etched on the device region forms first grid, the first polysilicon layer etched on the external zones forms second grid.The present invention reduces the height of the external zones polysilicon to reduce exhausting for polysilicon, to promote the grid-control ability of device external zones under conditions of not influencing the device region poly height.The method provided by the invention for promoting device grid-control ability not only contributes to the grid-control ability for promoting Metal-oxide-semicondutor (MOS) class device, but also does not influence the performance of the device region.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of method promoting device grid-control ability.
Background technology
In recent years, in the memory device of semiconductor integrated circuit, the development of flash memory is particularly rapid.Flash memory has integrated level
It is high, access speed is fast, the advantages that being easy to wipe and rewrite, thus obtained extensively in the multinomial field such as microcomputer, automation control
Application.In the devices, control gate is connected with wordline, controls the reading and write-in of information；Floating boom is embedded in silicon dioxide insulating layer,
It, can long-term preservation after injection charge not with turned on outside in electric " suspensions " state.
In device fabrication, external zones deposition typically synchronous with the polysilicon of device region, but external zones polysilicon
Height directly affect the grid-control ability of device, existing mode is the direct deposition for reducing external zones polysilicon on device.
The advantage of this mode is that technical process is simple, and disadvantage, which is the height of device region, also can accordingly reduce, and causes to influence device region device
The performance of part.
Therefore, it is badly in need of providing a kind of method promoting device grid-control ability, to solve device grid-control ability in the prior art
Low, device region polysilicon thickness is not enough and the problem of influence properties of product.
Invention content
The purpose of the present invention is to provide a kind of methods promoting device grid-control ability, to solve device gate in the prior art
The problem of control ability is low, and device region polysilicon thickness not enough influences properties of product.
In order to solve the problems in the existing technology, the present invention provides it is a kind of promoted device grid-control ability method,
It is characterized by comprising the following steps：
Substrate is provided, the substrate is divided into device region and external zones；
The first polysilicon layer is deposited over the substrate；
The deposited silicon dioxide layer on the first polysilicon layer；
Remove the silicon dioxide layer on the device region；
The second polysilicon layer is deposited on the first polysilicon layer of the device region；
Remove the silicon dioxide layer on the external zones；And
The second polysilicon layer and the first polysilicon layer etched on the device region forms first grid, etches the periphery
The first polysilicon layer in area forms second grid.
Optionally, in the method for promoting device grid-control ability, the thickness of the first polysilicon layer and the second polysilicon layer
It is 95 nanometers~105 nanometers to spend range.
Optionally, in the method for promoting device grid-control ability, the titanium dioxide is removed using wet-etching technology
Silicon layer.
Optionally, in the method for promoting device grid-control ability, the wet-etching technology includes using hydrofluoric acid
Remove the silicon dioxide layer.
Optionally, it in the method for promoting device grid-control ability, sinks on the first polysilicon layer of the device region
While the second polysilicon layer of product, second polysilicon layer is also formed in the silicon dioxide layer of the external zones, is being removed
Before silicon dioxide layer on the external zones, the second polycrystalline on the external zones is removed using the method for chemical mechanical grinding
Silicon layer.
Optionally, it in the method for promoting device grid-control ability, is set gradually on the substrate described in the device region
There are tunnel oxidation layer, floating gate layer and grid oxic horizon.
Optionally, include setting gradually in the method for promoting device grid-control ability, on the device region substrate
Tunnel oxidation layer, floating gate layer and grid oxic horizon.
Optionally, in the method for promoting device grid-control ability, the second polysilicon layer on the device region is etched
Include with the step of the first polysilicon layer formation first grid：Resist coating and pattern is carried out on second polysilicon layer
Change, then forms the first grid by the second polysilicon layer described in mask etching and first polysilicon layer of patterned photoresist
Pole.
Optionally, in the method for promoting device grid-control ability, the first polysilicon layer on the external zones is etched
Formed second grid the step of include：It resist coating and is patterned on first polysilicon layer, then with patterning
Photoresist be mask etching described in the first polysilicon layer formed second grid.
Optionally, it is described promoted device grid-control ability method in, after etching forms second grid, further include with
Lower step：Carry out wet-cleaning.
In the method provided by the present invention for promoting device grid-control ability, include the following steps：It deposits over the substrate
First polysilicon layer；The deposited silicon dioxide layer on the first polysilicon layer；Remove the silicon dioxide layer on the device region；Institute
It states and deposits the second polysilicon layer on the first polysilicon layer of device region；Remove the silicon dioxide layer on the external zones；And it carves
The second polysilicon layer and the first polysilicon layer lost on the device region forms first grid, etches first on the external zones
Polysilicon layer forms second grid.The height of external zones polysilicon gate directly affects Metal-oxide-semicondutor (MOS) class device
The grid-control ability of part can make the poly height of the device region also corresponding if directly reducing the deposition of external zones polysilicon
It reduces, the device region device performance is caused to reduce.The present invention is not under conditions of influencing the device region poly height, drop
The height of external zones polysilicon reduces exhausting for polysilicon on low substrate, to promote the grid-control ability of device external zones.
Further, the method provided by the invention for promoting device grid-control ability both contributes to the grid for promoting MOS class devices
Control ability, and the performance of the device region is not influenced.
Description of the drawings
Fig. 1 is the flow chart provided in an embodiment of the present invention for promoting device grid-control ability；
Fig. 2-Fig. 9 is the structural schematic diagram provided in an embodiment of the present invention for promoting device grid-control ability；
Wherein, 1- substrates；11- device regions；12- external zones；2- tunnel oxidation layers；3- floating gate layers；4- oxide skin(coating)s；5- nitrogen
Compound layer；The first polysilicon layers of 6-；7- silicon dioxide layers；The second polysilicon layers of 8-.
Specific implementation mode
The specific implementation mode of the present invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In the following description, it should be appreciated that when layer (or film), region, pattern or structure be referred to as substrate, layer (or
Film), region and/or when pattern "upper", it can be on another layer or substrate, and/or there may also be insert layers.
In addition, it is to be appreciated that when layer is referred to as another layer of "lower", it can be under another layer, and/or can be with
There are one or more insert layers.Furthermore it is possible to be carried out about the reference in each layer "up" and "down" based on attached drawing.
It please refers to Fig.1 to the flow chart that Fig. 9, Fig. 1 are the method provided in an embodiment of the present invention for promoting device grid-control ability；
Fig. 2-Fig. 9 is the structural schematic diagram provided in an embodiment of the present invention for promoting device grid-control ability.
As shown in Figures 1 to 9, the present invention provides a kind of method promoting device grid-control ability, include the following steps：
Step S1：Substrate 1 is provided, the substrate 1 divides for device region 11 and external zones 12；
Step S2：The first polysilicon layer 6 is deposited on the substrate 1；
Step S3：The deposited silicon dioxide layer 7 on the first polysilicon layer 6；
Step S4：Remove the silicon dioxide layer 7 on the device region 11；
Step S5：The second polysilicon layer 8 is deposited on the first polysilicon layer 6 of the device region 11；
Step S6：Remove the silicon dioxide layer 7 on the external zones 12；And
Step S7：The second polysilicon layer 8 and the first polysilicon layer 6 etched on the device region 11 forms first grid,
The first polysilicon layer 6 etched on the external zones 12 forms second grid.
The present invention reduces by 12 polysilicon of the external zones under conditions of not influencing 11 poly height of device region
Height reduces exhausting for polysilicon, to promote the grid-control ability of the external zones 12.Further, provided by the present invention to carry
In the method for rising device grid-control ability, not only contribute to the grid-control ability for promoting Metal-oxide-semicondutor (MOS) class device, but also
The performance of 11 device of the device region is not influenced.
Referring to FIG. 2, in step sl, the constituent material of the substrate 1 may be used undoped monocrystalline silicon, doped with
Monocrystalline silicon, silicon-on-insulator (SOI) of impurity etc..As an example, in the present embodiment, substrate 1 selects single crystal silicon material to constitute.
Buried layer (not shown) etc. can also be formed in the substrate 1.In addition, for example for PMOS, in the substrate 1
N trap (not shown)s can also be formed with.
The substrate 1 divides for device region 11 and external zones 12, in one embodiment, in the lining of the device region 11
Tunnel oxidation layer 2, floating gate layer 3 and grid oxic horizon are disposed on bottom 1.For example, the grid oxic horizon includes layer successively
Oxide skin(coating) 4, nitride layer 5 and the oxide skin(coating) 4 of folded setting, i.e. ONO structure.The oxide skin(coating) 4 for example can be oxidation
Silicon, the nitride layer 5 for example can with silicon nitride.
Further, the device region 11 and the external zones 12 can cover each film layer formed later, and not only
It is only limitted to substrate 1.
It follows that being of virtually different height on the device region 11 and the external zones 12, i.e., due to periphery
In area 12 and it is not provided with tunnel oxidation layer 2, floating gate layer 3 and grid oxic horizon, therefore relatively low.
With continued reference to FIG. 2, for step S2, carry out when depositing operation the device region 11 and external zones 12 simultaneously into
Row.Specifically, when the first polysilicon layer 6 of deposition, it is identical that the device region 11 with external zones 12 can increase a layer thickness simultaneously
First polysilicon layer 6.It is understood that after first polysilicon layer 6 formation, it is located at described on the device region 11
The top surface of first polysilicon layer 6 is higher than the top surface for first polysilicon layer 6 being located on the external zones 12.
In one embodiment, the thickness range of first polysilicon layer 6 can be 95 nanometers~105 nanometers, such as
98nm, 100nm, 103nm etc..
It is understood that according to practical devices structure and performance requirement, the thickness of first polysilicon layer 6 is not special
Above range is not limited to it, the first polysilicon layer 6 of other thickness also may be used.
Then, can also be 11 He of the device region for the deposition of silicon dioxide layer 7 referring to FIG. 3, for step S3
External zones 12 is carried out at the same time, i.e., the described device region 11 and the external zones 12 can all increase by one layer of silicon dioxide layer 7 simultaneously.
The silicon dioxide layer 7 is by the mask layer as external zones 12, in order to subsequently be continuously formed on device region 11
Second polysilicon layer 8.
Then, referring to FIG. 4, for step S4, wet-etching technology may be used and remove institute on the device region 11
State silicon dioxide layer 7.Further, the wet-etching technology includes removing the silica 7 using hydrofluoric acid.The hydrogen
Two kinds of forms of liquid and gaseous state may be used in fluoric acid, preferably, hydrofluoric acid solution is used in an embodiment of the present invention, in order to
The position for removing the silica 7 is controlled by controlling the amount of the hydrofluoric acid.
After this step removes the silicon dioxide layer 7 on device region 11, the first polysilicon layer 6 is exposed.
Later, referring to FIG. 5, for step S5, the second polycrystalline is deposited on the first polysilicon layer 6 of the device region 11
While silicon layer 8, second polysilicon layer 8 is also formed in the silicon dioxide layer 7 of the external zones 12.
In one embodiment, the thickness range of second polysilicon layer 8 can be 95nm~105nm, such as 98nm,
100nm, 103nm etc..
It is understood that according to practical devices structure and performance requirement, the thickness of second polysilicon layer 8 is not special
Above range is not limited to it, the second polysilicon layer 8 of other thickness also may be used.
Later, referring to FIG. 6, the method that chemical mechanical grinding may be used removes the second polycrystalline on the external zones 12
Silicon layer 8.Specifically, mill grinds second polysilicon layer 8, and receive the signal of grinding charge.When the mill is ground
When being milled to the silicon dioxide layer 7, the signal for being ground to the silicon dioxide layer 7 can be received, and judges that grinding charge is not
Only polysilicon, also other substances then control the mill and stop grinding.
In the second polysilicon layer 8 on removing the external zones 12, can also remove on the device region 11 of segment thickness
The second polysilicon layer 8, thus come adjust the final polysilicon layer on the device region 11 (i.e. combine 6 He of the first polysilicon layer
Second polysilicon layer 8) thickness.
In one embodiment, before depositing second polysilicon layer 8, in the silicon dioxide layer 7 of the external zones 12
One mask of upper setting, the mask can be that mask layer is deposited in the silicon dioxide layer 7, or mask plate is set to
In the silicon dioxide layer 7.It is preferred that being set in the silicon dioxide layer 7 using mask plate, to deposit second polycrystalline
After silicon layer 8, second polysilicon layer 8 of external zones 12 can be directly removed, it is not necessary to carry out other complicated removal techniques.
Then, referring to FIG. 7, removing remaining silicon dioxide layer 7, i.e. the silicon dioxide layer 7 of external zones 12 exposes outer
Enclose the first polysilicon layer 6 in area 12.
In the method provided by the present invention for promoting device grid-control ability, using the silicon dioxide layer 7 as periphery
The hard mask of first polysilicon layer 6 in area 12, the polysilicon for making the external zones 12 deposit twice separate, and keep outer
The thickness of 12 first polysilicon layer 6 of area is enclosed, while convenient for removing 12 second polysilicon layers 8 on the external zones, and ensured
The polysilicon layer thicknesses meet demand of device region 11, improves the grid-control ability of MOS class devices, and does not influence the device region 11
Performance.
Finally, Fig. 8 and Fig. 9 are please referred to, 6 shape of the second polysilicon 8 and the first polysilicon layer on the device region 11 is etched
Include at the step of first grid：It resist coating and is patterned on second polysilicon layer 8, then with patterned
Photoresist is that the second polysilicon layer 8 and first polysilicon layer 6 described in mask etching form first grid.
Etching the step of the first polysilicon layer 6 on the external zones 12 forms second grid includes：More than described first
It resist coating and is patterned on crystal silicon layer 6, then using patterned photoresist as the first polysilicon layer 6 described in mask etching
Form second grid.
Preferably, the etching technics includes dry etching.The dry etching is to carry out film etching with plasma
Technology.
In the method for the promotion device grid-control ability that the embodiment of the present invention is provided, first grid and the are formed in etching
It is further comprising the steps of after two grids：Carry out wet-cleaning.Wet-cleaning can be in the etching of first grid and second grid
It carries out respectively afterwards.
Further, wet-cleaning includes being cleaned using hydrofluoric acid, SC-1 solution and SC-2 solution.The SC-1 is molten
Liquid is the mixed liquor of ammonium hydroxide and hydrogen peroxide, and the SC-2 solution is the mixed liquor of hydrochloric acid and hydrogen peroxide.Mainly use hydrogen fluorine
The oxide of acid cleaning post-etch residue；Successively using described in the mixed liquor of SC-1 and SC-2 cleaning solutions and sulfuric acid solution cleaning
Other residues of device surface etc..
To sum up, in the method provided by the present invention for promoting device grid-control ability, include the following steps：Include on substrate
Device region and external zones deposit the first polysilicon layer over the substrate；The deposited silicon dioxide layer on the first polysilicon layer；It goes
Except the silicon dioxide layer on the device region；Then the second polysilicon layer is deposited on the device region and external zones；Removal institute
State the second polysilicon layer and the silicon dioxide layer on external zones；And the second polysilicon layer and first on the etching device region
Polysilicon layer forms first grid, and the first polysilicon layer etched on the external zones forms second grid.External zones polysilicon
The height of grid directly affects the grid-control ability of Metal-oxide-semicondutor (MOS) class device, if directly reducing external zones polycrystalline
The deposition of silicon can be such that the poly height of the device region also accordingly reduces, and the device region device performance is caused to reduce.This
Under conditions of not influencing the device region poly height, the height for reducing external zones polysilicon on substrate is more to reduce for invention
Crystal silicon exhausts, to promote the grid-control ability of device external zones.
Further, the method provided by the invention for promoting device grid-control ability both contributes to the grid for promoting MOS class devices
Control ability, and the performance of the device region is not influenced.
The preferred embodiment of the present invention is above are only, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical scheme of the present invention, to the invention discloses technical solution and
Technology contents make the variations such as any type of equivalent replacement or modification, belong to the content without departing from technical scheme of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. a kind of method promoting device grid-control ability, which is characterized in that include the following steps：
Substrate is provided, the substrate is divided into device region and external zones；
The first polysilicon layer is deposited over the substrate；
The deposited silicon dioxide layer on the first polysilicon layer；
Remove the silicon dioxide layer on the device region；
The second polysilicon layer is deposited on the first polysilicon layer of the device region；
Remove the silicon dioxide layer on the external zones；And
The second polysilicon layer and the first polysilicon layer etched on the device region forms first grid, etches on the external zones
The first polysilicon layer formed second grid.
2. the method for promoting device grid-control ability as described in claim 1, which is characterized in that the first polysilicon layer and more than second
The thickness range of crystal silicon layer is 95 nanometers~105 nanometers.
3. the method for promoting device grid-control ability as described in claim 1, which is characterized in that removed using wet-etching technology
The silicon dioxide layer.
4. the method for promoting device grid-control ability as claimed in claim 3, which is characterized in that the wet-etching technology includes
The silicon dioxide layer is removed using hydrofluoric acid.
5. the method for promoting device grid-control ability as described in claim 1, which is characterized in that more than the first of the device region
While depositing the second polysilicon layer on crystal silicon layer, second polysilicon layer is also formed in the silicon dioxide layer of the external zones
On, before the silicon dioxide layer on removing the external zones, removed on the external zones using the method for chemical mechanical grinding
The second polysilicon layer.
6. the method for promoting device grid-control ability as described in claim 1, which is characterized in that include on the device region substrate
Tunnel oxidation layer, floating gate layer and the grid oxic horizon set gradually.
7. as claimed in claim 6 promoted device grid-control ability method, which is characterized in that the grid oxic horizon include according to
The secondary oxide skin(coating) being stacked, nitride layer and oxide skin(coating).
8. the method for promoting device grid-control ability as described in claim 1, which is characterized in that etch the on the device region
Two polysilicon layers and the first polysilicon layer form the step of first grid and include：Resist coating is simultaneously on second polysilicon layer
It is patterned, then using patterned photoresist as the second polysilicon layer described in mask etching and the first polysilicon layer shape
At first grid.
9. the method for promoting device grid-control ability as described in claim 1, which is characterized in that etch the on the external zones
One polysilicon layer formed second grid the step of include：It resist coating and is patterned, is connect on first polysilicon layer
It and forms second grid by the first polysilicon layer described in mask etching of patterned photoresist.
10. the method for promoting device grid-control ability as claimed in claim 9, which is characterized in that form second grid in etching
Later, further comprising the steps of：Carry out wet-cleaning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810556671.4A CN108807406A (en) | 2018-05-31 | 2018-05-31 | A method of promoting device grid-control ability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810556671.4A CN108807406A (en) | 2018-05-31 | 2018-05-31 | A method of promoting device grid-control ability |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108807406A true CN108807406A (en) | 2018-11-13 |
Family
ID=64090046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810556671.4A Pending CN108807406A (en) | 2018-05-31 | 2018-05-31 | A method of promoting device grid-control ability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108807406A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050185446A1 (en) * | 2004-02-24 | 2005-08-25 | Luca Pividori | Method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices |
| CN102956554A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Separate gate type flash memory of embedded logic circuit and fabricating method thereof |
| CN105990368A (en) * | 2015-03-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN108054091A (en) * | 2017-12-19 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of method for promoting MOS device grid-control ability |
-
2018
- 2018-05-31 CN CN201810556671.4A patent/CN108807406A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050185446A1 (en) * | 2004-02-24 | 2005-08-25 | Luca Pividori | Method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices |
| CN102956554A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Separate gate type flash memory of embedded logic circuit and fabricating method thereof |
| CN105990368A (en) * | 2015-03-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN108054091A (en) * | 2017-12-19 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of method for promoting MOS device grid-control ability |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106206451B (en) | Gate-division type flash memory device making method | |
| US6159823A (en) | Trench isolation method of semiconductor device | |
| WO2005122281A2 (en) | Gate stack of nanocrystal memory and method for forming same | |
| CN106206597B (en) | Avoid the remaining method of etching polysilicon and Split-gate flash memory manufacturing method | |
| US20050190598A1 (en) | Non-volatile memory technology compatible with 1T-RAM process | |
| CN109545790A (en) | The forming method in the channel hole of three-dimensional storage | |
| CN106206598B (en) | Gate-division type flash memory device making method | |
| JP2003197789A (en) | Method of forming self-aligned floating gate in flash memory cell | |
| CN100517655C (en) | SONOS flash memory and production method thereof | |
| CN101807577A (en) | Split gate flash memory and manufacture method thereof | |
| CN102945832B (en) | The forming method of flush memory device | |
| CN106340520B (en) | The forming method of semiconductor devices | |
| JP2006313901A (en) | Semiconductor device and fabrication method | |
| CN108321087B (en) | A kind of forming method of floating gate | |
| CN105762114B (en) | The forming method of semiconductor structure | |
| KR19980055746A (en) | Electrode Formation Method of Semiconductor Device | |
| US7425486B2 (en) | Method for forming a trench capacitor | |
| CN108807406A (en) | A method of promoting device grid-control ability | |
| CN105513954A (en) | Forming method of semiconductor device | |
| US6544855B1 (en) | Process flow for sacrificial collar with polysilicon void | |
| CN105140176B (en) | A kind of semiconductor devices and its manufacture method and electronic device | |
| CN109841626B (en) | Semiconductor structure and forming method thereof | |
| US11605641B2 (en) | Flash device and manufacturing method thereof | |
| CN111933567B (en) | Manufacturing method of shallow trench isolation structure | |
| KR100384859B1 (en) | Method of fabricating capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181113 |