CN107464758A - A kind of forming method of semiconductor devices - Google Patents
A kind of forming method of semiconductor devices Download PDFInfo
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- CN107464758A CN107464758A CN201710802501.5A CN201710802501A CN107464758A CN 107464758 A CN107464758 A CN 107464758A CN 201710802501 A CN201710802501 A CN 201710802501A CN 107464758 A CN107464758 A CN 107464758A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 177
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 238000005530 etching Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 15
- 238000000576 coating method Methods 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000002131 composite material Substances 0.000 claims abstract description 8
- 238000010276 construction Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 6
- 238000011049 filling Methods 0.000 claims abstract description 4
- 230000000717 retained effect Effects 0.000 claims description 13
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of forming method of semiconductor devices, suitable for rear grid technique, wherein, comprise the following steps：The dummy grid in composite construction is removed to form the bottom-exposed substrate of metal gates groove and groove；Boundary layer is formed in the bottom of metal gates groove, and sequentially forms a high k dielectric layer, coating and the second etching stop layer；Forming workfunction layers makes workfunction layers covering metal gates channel bottom and the second etching stop layer of partial sidewall；The surface of second etching stop layer exposure and workfunction metal layer surface form diffusion impervious layer；Diffusion barrier layer surface forms gate material layers, and makes to be recessed corresponding to the full metal gates groove of gate material layers filling；The surface of interlayer dielectric layer side wall exposure and remaining gate material layers are flushed by grinding technics.The beneficial effect of its technical scheme is, the etch step to workfunction layers is increase only in existing technique, and existing process is changed less, implements simple.
Description
Technical field
The present invention relates to field of semiconductor device preparation, more particularly to a kind of forming method of semiconductor devices.
Background technology
With semiconductor integrated circuit integration density more and more higher, semiconductor devices is also less and less, corresponding semiconductor
Device channel can also shorten, and the ratio for the total electrical charge that source lining, leakage lining PN junction share raceway groove depletion region electric charge and raceway groove will increase,
So as to cause grid-control ability to decline, short-channel effect is formed.As drain induced barrier reduces (DIBL), with the increase of drain-source voltage,
Leakage lining reverse biased pn junction space-charge region broadening, then under the effective length of raceway groove subtracts, this is particularly evident in short channel, can seriously lead
Cause Punchthrough component failure.How to reduce or prevent short-channel effect from having become asking for semiconductor industry general relationship
Topic.The scheme that a kind of grid material by original single work function changes into the grid structure with variable levels work function is carried
Go out, to improve short channel effect, but how to carry out being integrated into difficult point by this scheme and existing technique in process.It is existing
In technology is that kind of solution method is that come in and gone out in the substrate of the semiconductor work function regulation ion of doses realizes level
The grid structure of variable work function, but not only control is complicated in the manufacturing process of reality but also effect is unsatisfactory.
The content of the invention
For the above mentioned problem of short-channel effect in semiconductor devices being in the prior art present, one kind being now provided and is intended to reality
Technique is simple, realizes the forming method of the semiconductor devices of the grid structure of variable levels work function.
Concrete technical scheme is as follows：
A kind of forming method of semiconductor devices, suitable for rear grid technique, wherein, comprise the following steps：
Step S1, a composite construction is provided, the composite construction includes substrate, is provided with dummy grid on the substrate, institute
Stating dummy grid both sides has side wall, and one first etching stop layer covers the region of the substrate exposure and the side wall both sides,
One interlayer dielectric layer covers the etching stop layer, and is flushed with the dummy grid；
Step S2, the dummy grid is removed, to form a metal gates groove, the bottom-exposed of the metal gates groove
The substrate；
Step S3, form a boundary layer in the bottom of the metal gates groove to cover the substrate, and further in
The interlayer dielectric layer surface, the surface of the first etching stop layer exposure and inwall and the bottom of the metal gates groove
Sequentially form high K (dielectric coefficient) dielectric layer, coating and second etching stop layer；
Step S4, a workfunction layers are formed, the workfunction layers is covered the metal gates channel bottom
And second etching stop layer of partial sidewall；
Step S5, a diffusion is formed in the surface of second etching stop layer exposure and the workfunction metal layer surface
Barrier layer；
Step S6, a gate material layers are formed in the diffusion barrier layer surface, and fills out the gate material layers
Full of depression corresponding to the metal gates groove；
Step S7, by a grinding technics, removal is covered in the inter-level dielectric layer surface, the surface of the side wall exposure
The gate material layers, the diffusion impervious layer, second etching stop layer, the coating and the high k dielectric
Layer, and make the interlayer dielectric layer, the surface of the side wall exposure and the remaining gate material layers flush.
Preferably, the step S4 specifically includes following steps：
Step S41, the workfunction layers are deposited, the workfunction layers is covered second etching stop layer
Surface；
Step S42, the workfunction layers are etched, to remove outside being recessed corresponding to the metal gates groove
The workfunction layers, and part remove the work content of the two side in being recessed corresponding to the metal gates groove
Number metal level, makes concave bottom corresponding to the metal gates groove, and two side close to the work content in the region of bottom
Number metal level is retained.
Preferably, in the step S41, the workfunction layers have in being recessed corresponding to the metal gates groove
There is opening.
Preferably, the width of the opening is more than 5nm, and less than the width of the metal gates groove.
Preferably, in the step S42, depression two side is described corresponding to the retained metal gates groove
The height of workfunction layers is more than or equal to 5 angstroms, and less than the depth of the metal gates groove.
Preferably, in the step S42, depression two side is described corresponding to the retained metal gates groove
The width of workfunction layers is respectively less than the 25% of the metal gates width.
Preferably, in the step S42, be each recessed two side corresponding to the retained metal gates groove
The workfunction layers towards the one side in the depression be plane.
Preferably, in the step S42, be each recessed two side corresponding to the retained metal gates groove
The workfunction layers towards the one side in the depression be curved surface.
Preferably, the gate material layers are aluminium lamination.
Preferably, the coating is titanium oxide, and/or second etching stop layer is tantalum nitride.
Above-mentioned technical proposal has the following advantages that or beneficial effect：It is increase only in existing technique to workfunction metal
The etch step of layer, realizes the grid structure of variable levels work function and the integration of existing production technology, and to existing work
Skill changes less, implements simple.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is a kind of flow chart of the embodiment of the forming method of semiconductor devices of the present invention；
Fig. 2 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, on forming workfunction layers
Schematic flow sheet；
Fig. 3 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, the formation on removing dummy grid is golden
Belong to the structural representation of gate trench；
Fig. 4 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, on the shape in metal gates groove
Into the structural representation of boundary layer, high k dielectric layer, coating and etching stop layer；
Fig. 5 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, and power function gold is formed on deposition
Belong to the structural representation of layer；
Fig. 6 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, on power function metal level
Form the structural representation of depression；
Fig. 7 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, is exposed on the second etching stop layer
Surface and workfunction metal layer surface formed a diffusion impervious layer structural representation
Fig. 8 is in a kind of embodiment of the forming method of semiconductor devices of the present invention, and inter-level dielectric is covered on removing
Layer surface, gate material layers, diffusion impervious layer, the second etching stop layer, coating and the high k dielectric on the surface of side wall exposure
Structural representation after layer.
Reference represents：
1st, substrate；11st, the first etching stop layer；12nd, interlayer dielectric layer；13rd, side wall；
2nd, metal gates groove；3rd, boundary layer；4th, high k dielectric layer, 5, coating；6th, the second etching stop layer；7 work functions
Metal level；8th, it is recessed；9th, diffusion impervious layer；10th, gate material layers；
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as limiting to the invention.
Technical scheme includes a kind of forming method of semiconductor devices.
As shown in figure 1, a kind of embodiment of the forming method of semiconductor devices, suitable for rear grid technique, wherein, including
Following steps：
Step S1, a composite construction is provided, composite construction includes substrate, dummy grid, dummy grid both sides are provided with substrate
With side wall 13, the region and the both sides of side wall 13 of the covering substrate exposure of one first etching stop layer 11, an interlayer dielectric layer 12
Etching stop layer is covered, and is flushed with dummy grid；
Step S2, dummy grid is removed, to form a metal gates groove 2, the bottom-exposed substrate of metal gates groove 2；
Step S3, a boundary layer 3 is formed in the bottom of metal gates groove 2 to cover substrate, and is further situated between in interlayer
The surface of electric layer 12, the surface of the first etching stop layer 11 exposure and the inwall of metal gates groove 2 and bottom sequentially form a high K
Dielectric layer 4, the etching stop layer 6 of coating 5 and second；
Step S4, a workfunction layers 7 are formed, workfunction layers 7 is covered the bottom of metal gates groove 2 and portion
Divide the second etching stop layer 6 of side wall；
Step S5, a diffusion impervious layer is formed in the surface of the second etching stop layer 6 exposure and the surface of workfunction layers 7
9；
Step S6, a gate material layers 10 are formed in the surface of diffusion impervious layer 9, and makes the full metal of the filling of gate material layers 10
Depression 8 corresponding to gate trench 2；
Step S7, by a grinding technics, removal is covered in inter-level dielectric layer surface, the grid on the surface that side wall 13 exposes
Material layer 10, diffusion impervious layer 9, the second etching stop layer 6, coating 5 and high k dielectric layer 4, and make interlayer dielectric layer, side
The surface and remaining gate material layers 10 that wall 13 exposes flush.
For preparing short-channel effect existing for semiconductor devices in the prior art, above-mentioned technical proposal is realizing level
On the basis of the grid structure of variable work function, existing production work is integrated in a manner of only increasing workfunction layers etching
In skill, in simple process method, the grid structure of variable levels work function is realized.
In the present invention, by making workfunction layers 7 cover the second quarter of the bottom of metal gates groove 2 and partial sidewall
Lose stop-layer 6 so that metal gates form adjustable workfunction layers 7 in the horizontal direction, can effectively improve short channel
Effect.
Above-mentioned grinding technics can be CMP (chemical mechanical polish, CMP, cmp) work
Skill.
Above-mentioned deposit diffusion barriers 9 can also be net profit layer, the wherein side of deposit diffusion barriers 9 or wetting layer
Method can use the methods of low temperature chemical vapor deposition, low-pressure chemical vapor deposition.
In a kind of preferably embodiment, as shown in Fig. 2 step S4 specifically includes following steps：
Step S41, workfunction layers 7 are deposited, workfunction layers 7 is covered the surface of the second etching stop layer 6；
Step S42, workfunction layers 7 are etched, to remove positioned at the work content corresponding to metal gates groove 2 outside depression 8
Number metal level 7, and part remove the workfunction layers 7 of the two side in the corresponding depression 8 of metal gates groove 2, make
8 bottoms of depression corresponding to metal gates groove 2, and workfunction layers 7 of the two side close to the region of bottom are retained
In above-mentioned technical proposal, the method for deposition workfunction layers 7 can use physical vaporous deposition or chemical gas
Phase deposition process, and the method for etching workfunction layers 7 can use dry etching or wet etching.
In a kind of preferably embodiment, in step S41, workfunction layers 7 are in recessed corresponding to metal gates groove 2
Falling into 8 has opening.
In a kind of preferably embodiment, the width of opening is more than 5nm, and less than the width of metal gates groove 2.
In a kind of preferably embodiment, in step S42,8 liang of depression corresponding to retained metal gates groove 2
The height of the workfunction layers 7 of side wall is more than or equal to 5 angstroms, and less than the depth of metal gates groove 2.
In a kind of preferably embodiment, in step S42,8 liang of depression corresponding to retained metal gates groove 2
The width of the workfunction layers 7 of side wall is respectively less than the 25% of metal gates width.
It is each recessed corresponding to retained metal gates groove 2 in step S42 in a kind of preferably embodiment
Fall into 8 two sides workfunction layers 7 towards depression 8 in one side be plane.
It is each recessed corresponding to retained metal gates groove 2 in step S42 in a kind of preferably embodiment
Fall into 8 two sides workfunction layers 7 towards depression 8 in one side be curved surface.
In a kind of preferably embodiment, gate material layers 10 are aluminium lamination.
In above-mentioned technical proposal, gate material layers 10 are also to select as copper, tungsten etc..
In a kind of preferably embodiment, coating 5 is titanium nitride.
In a kind of preferably embodiment, the second etching stop layer 6 is tantalum nitride.
Specifically illustrated below in conjunction with accompanying drawing：
As shown in figure 3, after being removed to the dummy grid in composite construction, metal gates groove 2, metal gates groove 2 are formed
Bottom-exposed substrate；
As shown in figure 4, boundary layer 3 is formed in the bottom of metal gates groove 2 to cover substrate, in the table of interlayer dielectric layer 12
Face, the surface and the inwall of metal gates groove 2 and bottom of the exposure of the first etching stop layer 11 sequentially form a high k dielectric layer 4,
The etching stop layer 6 of coating 5 and second；
As shown in figure 5, deposition forms workfunction layers 7；
As shown in fig. 6, being performed etching to the function metal of deposition, workfunction layers 7 are made to cover metal gates groove 2
Bottom and the second etching stop layer 6 of partial sidewall；
As shown in fig. 7, a diffusion resistance is formed on the surface of the second etching stop layer 6 exposure and the surface of workfunction layers 7
Barrier 9；
A gate material layers 10 are formed on the surface of diffusion impervious layer 9, and make the full metal gates ditch of the filling of gate material layers 10
Depression 8 corresponding to groove 2；
As shown in figure 8, by a grinding technics, removal is covered in inter-level dielectric layer surface, the surface that side wall 13 exposes
Gate material layers 10, diffusion impervious layer 9, the second etching stop layer 6, coating 5 and high k dielectric layer 4, and make inter-level dielectric
Layer, the surface and remaining gate material layers 10 that side wall 13 exposes flush.
In above-mentioned technical proposal, the etch step to workfunction layers is increase only in existing technique, is realized
The grid structure of variable levels work function and the integration of existing production technology, and existing process is changed less, implement simple.
Preferred embodiments of the present invention are the foregoing is only, not thereby limit embodiments of the present invention and protection model
Enclose, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Scheme obtained by equivalent substitution and obvious change, should be included in protection scope of the present invention.
Claims (10)
- A kind of 1. forming method of semiconductor devices, suitable for rear grid technique, it is characterised in that comprise the following steps：Step S1, a composite construction is provided, the composite construction includes substrate, dummy grid, the puppet are provided with the substrate Grid both sides have side wall, the region and the side wall both sides that the one first etching stop layer covering substrate exposes, one layer Between dielectric layer cover the etching stop layer, and flushed with the dummy grid；Step S2, the dummy grid is removed, to form a metal gates groove, described in the bottom-exposed of the metal gates groove Substrate；Step S3, a boundary layer is formed in the bottom of the metal gates groove to cover the substrate, and further in described Interlayer dielectric layer surface, the surface of the first etching stop layer exposure and the inwall of the metal gates groove and bottom are successively Form a high k dielectric layer, coating and the second etching stop layer；Step S4, a workfunction layers are formed, make the workfunction layers cover the metal gates channel bottom and Second etching stop layer of partial sidewall；Step S5, a diffusion barrier is formed in the surface of second etching stop layer exposure and the workfunction metal layer surface Layer；Step S6, a gate material layers are formed in the diffusion barrier layer surface, and makes the gate material layers filling full It is recessed corresponding to the metal gates groove；Step S7, by a grinding technics, removal is covered in the inter-level dielectric layer surface, the institute on the surface of the side wall exposure Gate material layers, the diffusion impervious layer, second etching stop layer, the coating and the high k dielectric layer are stated, and Make the interlayer dielectric layer, the surface of the side wall exposure and the remaining gate material layers flush.
- 2. the forming method of semiconductor devices according to claim 1, it is characterised in that the step S4 specifically include with Lower step：Step S41, the workfunction layers are deposited, the workfunction layers is covered the second etching stop layer table Face；Step S42, the workfunction layers are etched, described in removing outside being recessed corresponding to the metal gates groove Workfunction layers, and part remove the work function gold of the two side in being recessed corresponding to the metal gates groove Belong to layer, make concave bottom corresponding to the metal gates groove, and two side close to the work function gold in the region of bottom Category layer is retained.
- 3. the forming method of semiconductor devices according to claim 2, it is characterised in that in the step S41, the work( Function metal has opening in being recessed corresponding to the metal gates groove.
- 4. the forming method of semiconductor devices according to claim 3, it is characterised in that the width of the opening is more than 5nm, and less than the width of the metal gates groove.
- 5. the forming method of semiconductor devices according to claim 2, it is characterised in that in the step S42, protected The height of the workfunction layers of depression two side is more than or equal to 5 angstroms corresponding to the metal gates groove stayed, and small In the depth of the metal gates groove.
- 6. the forming method of semiconductor devices according to claim 2, it is characterised in that in the step S42, protected The width of the workfunction layers of depression two side is respectively less than the metal gate corresponding to the metal gates groove stayed The 25% of pole width.
- 7. the forming method of semiconductor devices according to claim 2, it is characterised in that in the step S42, each The workfunction layers of depression two side corresponding to the retained metal gates groove are towards one in the depression Face is plane.
- 8. the forming method of semiconductor devices according to claim 2, it is characterised in that in the step S42, each The workfunction layers of depression two side corresponding to the retained metal gates groove are towards one in the depression Face is curved surface.
- 9. the forming method of semiconductor devices according to claim 1, it is characterised in that the gate material layers are aluminium Layer.
- 10. the forming method of semiconductor devices according to claim 1, it is characterised in that the coating is titanium oxide, And/or second etching stop layer is tantalum nitride.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828377A (en) * | 2018-08-08 | 2020-02-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
| CN111816609A (en) * | 2020-07-15 | 2020-10-23 | 浙江驰拓科技有限公司 | Method for processing interconnection structure in semiconductor device |
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| CN104299897A (en) * | 2013-07-17 | 2015-01-21 | 格罗方德半导体公司 | Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same |
| CN105470200A (en) * | 2014-09-09 | 2016-04-06 | 联华电子股份有限公司 | Semiconductor element with metal gate electrodes and manufacturing method thereof |
| CN107968054A (en) * | 2016-10-19 | 2018-04-27 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110828377A (en) * | 2018-08-08 | 2020-02-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
| CN110828377B (en) * | 2018-08-08 | 2022-06-21 | 联华电子股份有限公司 | Semiconductor element with asymmetric work function metal layer |
| CN111816609A (en) * | 2020-07-15 | 2020-10-23 | 浙江驰拓科技有限公司 | Method for processing interconnection structure in semiconductor device |
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