CN107749413B - A method of it improving memory cell areas and control circuit area side wall thicknesses is poor - Google Patents
A method of it improving memory cell areas and control circuit area side wall thicknesses is poor Download PDFInfo
- Publication number
- CN107749413B CN107749413B CN201710978316.1A CN201710978316A CN107749413B CN 107749413 B CN107749413 B CN 107749413B CN 201710978316 A CN201710978316 A CN 201710978316A CN 107749413 B CN107749413 B CN 107749413B
- Authority
- CN
- China
- Prior art keywords
- layer
- side wall
- substrate
- reaction pressure
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of method for improving memory cell areas and control circuit area side wall thicknesses difference, is suitable for non-volatile flash memory, comprising: provides a composite construction；The first S is sequentially depositing using the first reaction pressure on substrate in a reaction chamberiO2Layer andLayer, deposits the 2nd S using the second reaction pressure on substrateiO2Layer, the first SiO2Layer,Layer and the 2nd SiO2Layer constitutes the first side wall of covering gate structure sidewall and the second side wall of covering spacer structure side wall, and the first reaction pressure is greater than the second reaction pressure, the 2nd S in the first side walliO2Thickness degree is less than the 2nd S in the second side walliO2Thickness degree.Beneficial effects of the present invention: can be improved non-volatile flash memory memory cell areas and control circuit area side wall thicknesses are poor, under the premise of guaranteeing memory cell areas performance, the high temperature breakdown voltage for improving control circuit area, increases the adjusting space of ion implanting, improves the performance of metal-oxide-semiconductor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of raising memory cell areas and control circuit area side
The method of wall thickness difference.
Background technique
The thickness of side wall directly affects the ion implanting of the source-drain electrode S/D of metal-oxide-semiconductor, and then decides the electricity of metal-oxide-semiconductor
Performance, while the performance win-win in memory cell areas (area CELL) and control circuit area (area PERI) depends on the thickness of the two side wall
Difference.In existing processing procedure, the side wall in the area CELL and the area PERI is with oxidenitride oxide (Oxide-Nitride-
Oxide, ONO) structure is completed at the same time, and the thickness difference of the two is in 4nm or so.
The thickness difference of the area CELL and the area PERI side wall decides whether the two electrical property being capable of win-win.In the existing processing procedure of flash memory
Under, up to expection, the area CELL is almost filled up by side wall in the area PERI；Otherwise the area PERI leads to metal-oxide-semiconductor then since the thickness of side wall is excessively thin
Source-drain electrode S/D and lightly doped drain (Low doped drain, LDD) Distance Shortened, there is high temperature breakdown voltage in metal-oxide-semiconductor
The problems such as (Breakdown Voltage, BV) is too small.So improving the side wall relative thickness difference in the area CELL and the area PERI for increasing
The adjustable extent of big metal-oxide-semiconductor electrical property is most important.
Existing way is finished in control gate (Control Gate, CG) and polysilicon gate (Gate Poly, GP), note
After entering LDD, the side wall of the SiO2 and SIN of layer are first deposited, then redeposited one layer thicker of SiO2 side wall.It carries out again
Side wall etches to form isolation (Spacer), finally carries out the ion implanting of source-drain electrode S/D again.Under comparable size and area ratio,
The reaction pressure of reaction cavity is larger in side wall deposition, and it is little in the area CELL and the area PERI difference to directly result in formed side wall.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provides a kind of raising memory cell areas and control circuit area side
The method of wall thickness difference.
The present invention adopts the following technical scheme:
A method of it improving memory cell areas and control circuit area side wall thicknesses is poor, be suitable for non-volatile flash memory, packet
It includes:
Step S1, a composite construction is provided, the composite construction has memory cell areas and control circuit area, described compound
Structure includes substrate, the gate structure on the substrate of memory cell areas and on the substrate in control circuit area
Spacer structure；The method also includes:
Step S2, first thickness is sequentially depositing using preset first reaction pressure over the substrate in a reaction chamber
The first SiO2Layer and second thicknessLayer, using preset second reaction pressure in the lining in the reaction chamber
The 2nd S of third thickness is deposited on bottomiO2Layer, the first SiO2Layer, it is describedLayer and the 2nd SiO2Layer constitutes covering
First side wall of the gate structure sidewall and the second side wall for covering the spacer structure side wall, first reaction pressure are big
The 2nd S in second reaction pressure, first side walliO2Thickness degree is less than described in second side wall
2nd SiO2Thickness degree and have a preset thickness difference.
Preferably, the step S1 includes:
Step S11, a substrate is provided, carries out shallow grooved-isolation technique over the substrate to form element isolation junction
Structure, the substrate and the component isolation structure constitute the composite construction, and the composite construction includes the memory cell areas
With the control circuit area, the composite construction further include be located at the memory cell areas in the adjacent component isolation structure it
Between well region；
Step S12, the gate structure is formed above the substrate of the well region, the gate structure includes under
The supreme floating gate set gradually, dielectric layer and control gate carry out ion implanting to the well region, the phase in the control circuit area
The spacer structure is formed above substrate between the adjacent component isolation structure.
Preferably, the step S12 includes:
Step S121, over the substrate surface deposit polycrystalline silicon to form the first polysilicon layer；
Step S122, planarization process is carried out to first polysilicon layer and removes the institute positioned at the control circuit area
It states the first polysilicon layer and retains first polysilicon layer for being located at the memory cell areas；
Step S123, isolating oxide layer is formed on first polysilicon layer for being located at the memory cell areas, used
Preset first exposure mask is exposed and etches to the isolating oxide layer and first polysilicon layer, with formed by it is described every
The dielectric layer constituted from oxide layer and the floating gate being made of first polysilicon；
Step S124, ion implanting is carried out to the well region；
Step S125, deposit polycrystalline silicon is continued to form the second polysilicon layer in surface over the substrate；
Step S126, second polysilicon layer is exposed and is etched using preset second exposure mask, described
The top of dielectric layer forms the control gate being made of the second polysilicon layer, and the adjacent element in the control circuit area every
The spacer structure being made of from formation above the substrate between structure second polysilicon layer；
Step S127, low concentration doping object is injected in the well region to form the low concentration doping area LDD.
Preferably, the step S2 includes:
Step S21, it is sequentially depositing over the substrate in the reaction chamber using preset first reaction pressure
First S of first thicknessiO2Layer and second thicknessLayer；
Step S22, third is deposited using preset second reaction pressure over the substrate in the reaction chamber
2nd S of thicknessiO2Layer；
Step S23, in the reaction chamber using preset etch period to the first SiO2Layer, it is describedLayer
And the 2nd SiO2Layer is performed etching to remove the first S that part covers the upper surface of substrateiO2Layer, it is described
Layer and the 2nd SiO2Layer simultaneously forms first side wall for covering the gate structure sidewall and covers the spacer structure side
Second side wall of wall.
Preferably, in the step S2, first reaction pressure and second reaction pressure have a reaction pressure
Difference, the reaction pressure difference and the thickness difference are proportional.
Preferably, in the step S23, the etch period and second reaction pressure are proportional.
Preferably, the thickness difference is 13nm.
Preferably, the second pressure is 0.2tor.
Beneficial effects of the present invention: the present invention can be improved non-volatile flash memory memory cell areas and control circuit area side wall
Thickness difference improves the high temperature breakdown voltage in control circuit area under the premise of guaranteeing memory cell areas performance, increases ion implanting
Adjusting space, improve the performance of metal-oxide-semiconductor.
Detailed description of the invention
Fig. 1 is to improve memory cell areas and control circuit area side wall thicknesses difference in a preferred embodiment of the present invention
The flow chart of method；
Fig. 2 is the flow chart of step S1 in a preferred embodiment of the present invention；
Fig. 3 is the flow chart of step S12 in a preferred embodiment of the present invention；
Fig. 4 is the flow chart of step S2 in a preferred embodiment of the present invention；
Fig. 5-8 is to improve memory cell areas in a preferred embodiment of the present invention and control circuit area side wall thicknesses are poor
Method schematic diagram；
Fig. 9 is the corresponding relationship of thickness difference and pressure difference in a preferred embodiment of the present invention；
Figure 10 is the schematic diagram that the first side wall and the second side wall of the prior art and the technology of the present invention preparation is respectively adopted.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in Figure 1, a kind of method for improving memory cell areas and control circuit area side wall thicknesses difference, is suitable for non-volatile
Property flash memory, comprising:
Step S1, a composite construction is provided, above-mentioned composite construction has memory cell areas and control circuit area, above-mentioned compound
Structure includes substrate, the gate structure 5 on the above-mentioned substrate of memory cell areas and the above-mentioned substrate positioned at control circuit area
On spacer structure 6；The above method further include:
Step S2, first thickness is sequentially depositing on above-mentioned substrate using preset first reaction pressure in a reaction chamber
The first SiO2Layer 7 and second thicknessLayer 8, using preset second reaction pressure above-mentioned in above-mentioned reaction chamber
The 2nd S of third thickness is deposited on substrateiO2Layer 9, above-mentioned first SiO2Layer 7, it is above-mentioned8 and above-mentioned 2nd S of layeriO2Layer 9
The first side wall 10 for covering above-mentioned 5 side wall of gate structure and the second side wall 11 for covering above-mentioned 6 side wall of spacer structure are constituted, it is above-mentioned
First reaction pressure is greater than above-mentioned second reaction pressure, above-mentioned 2nd S in above-mentioned first side wall 10iO29 thickness of layer are less than above-mentioned
Above-mentioned 2nd S in second side wall 11iO2Layer 9 thickness and have a preset thickness difference.
In the present embodiment, Process ba- sis of the above-mentioned technical proposal based on 50nm non-volatile flash memory, due to being located at storage
The depth-to-width ratio between the gate structure 5 being made of 2/ dielectric layer of floating gate, 3/ control gate 4 in cellular zone (area CELL) is much larger than position
Depth-to-width ratio between the spacer structure 6 (GP) in control circuit area (area PERI), in outermost 2nd SiO2The deposition of layer 9
Cheng Zhong, by suitably reducing the second intracavitary reaction pressure of deposition reaction, so that the gas molecule for participating in reaction is difficult storing
It is sufficiently reacted in cellular zone, the step coverage for reducing memory cell areas reduces the 2nd S in the first side wall 10iO2Layer 9
Thickness, while the 2nd S in second side wall 11 in control circuit areaiO2The thickness change of layer 9 is unobvious, to realize the two
Between thickness difference raising.
By Optimizing Technical, brought by the deposition process conditions and sedimentary condition variation of exploring and optimize side wall
Etching process improve the thickness difference of the first side wall 10 and the second side wall 11, when 10 thickness of the first side wall being avoided to reach expected
Two side walls, 11 thickness is too small, and 10 thickness of the first side wall excessive problem when 11 thickness of the second side wall being avoided to reach expected, leads to
It crosses and improves the 2nd S in the first side wall 10iO22nd S in the thickness and the second side wall 11 of layer 9iO2Thickness difference between 9 thickness of layer,
And then guarantee the thickness difference of the first side wall 10 and the second side wall 11 simultaneously, to guarantee that the first side wall 10 and the second side wall 11 reach
To expection, the present invention improves the high temperature breakdown voltage in control circuit area under the premise of guaranteeing memory cell areas performance, increase from
The adjusting space of son injection, improves the performance of metal-oxide-semiconductor, realizes the two-win of electric property.
As shown in Fig. 2, in preferred embodiment, above-mentioned steps S1 includes:
Step S11, an above-mentioned substrate is provided, carries out shallow grooved-isolation technique on above-mentioned substrate to form component isolation structure
1, above-mentioned substrate and said elements isolation structure 1 constitute above-mentioned composite construction, and above-mentioned composite construction includes said memory cells area
With above-mentioned control circuit area, above-mentioned composite construction further includes being located at adjacent said elements isolation structure 1 in said memory cells area
Between well region；
Step S12, form above-mentioned gate structure 5 above the above-mentioned substrate of above-mentioned well region, above-mentioned gate structure 5 include by
Under the supreme floating gate 2 set gradually, dielectric layer 3 and control gate 4, to above-mentioned well region carry out ion implanting, in above-mentioned control circuit
Above-mentioned spacer structure 6 is formed above substrate between the adjacent said elements isolation structure 1 in area.
As shown in figure 3, in preferred embodiment, above-mentioned steps S12 includes:
Step S121, in above-mentioned upper surface of substrate deposit polycrystalline silicon to form the first polysilicon layer；
Step S122, above-mentioned first polysilicon layer is carried out planarization process and removed to be located at the upper of above-mentioned control circuit area
It states the first polysilicon layer and retains above-mentioned first polysilicon layer for being located at said memory cells area；
Step S123, isolating oxide layer is formed on above-mentioned first polysilicon layer for being located at said memory cells area, used
Preset first exposure mask is exposed and etches to above-mentioned isolating oxide layer and above-mentioned first polysilicon layer, with formed by it is above-mentioned every
The dielectric layer 3 constituted from oxide layer and the floating gate 2 being made of above-mentioned first polysilicon；
Step S124, ion implanting is carried out to above-mentioned well region；
Step S125, continue deposit polycrystalline silicon in above-mentioned upper surface of substrate to form the second polysilicon layer；
Step S126, above-mentioned second polysilicon layer is exposed and is etched using preset second exposure mask, above-mentioned
The top of dielectric layer 3 forms the control gate 4 being made of the second polysilicon layer, and the adjacent said elements in above-mentioned control circuit area
The spacer structure 6 being made of above-mentioned second polysilicon layer is formed above substrate between isolation structure 1；
Step S127, low concentration doping object is injected in above-mentioned well region to form above-mentioned low concentration doping area.
In the present embodiment, it is prior art that step S1, which forms the technique of composite construction,.
As shown in figure 4, in preferred embodiment, above-mentioned steps S2 includes:
Step S21, it is sequentially depositing on above-mentioned substrate in above-mentioned reaction chamber using preset above-mentioned first reaction pressure
First S of first thicknessiO2Layer 7 and second thicknessLayer 8；
Step S22, third is deposited on above-mentioned substrate using preset above-mentioned second reaction pressure in above-mentioned reaction chamber
2nd S of thicknessiO2Layer 9；
Step S23, in above-mentioned reaction chamber using preset etch period to above-mentioned first SiO2Layer 7, it is above-mentionedLayer
8 and above-mentioned 2nd SiO2Layer 9 is performed etching to remove above-mentioned first S that part covers above-mentioned upper surface of substrateiO2Layer 7, it is above-mentioned8 and above-mentioned 2nd S of layeriO2Layer 9 is simultaneously formed on above-mentioned first side wall 10 for covering above-mentioned 5 side wall of gate structure and covering
State above-mentioned second side wall 11 of 6 side wall of spacer structure.
In the present embodiment, only retain above-mentioned first S of the side wall of covering gate structure 5 and spacer structure 6iO2Layer 7,
It is above-mentioned8 and above-mentioned 2nd S of layeriO2Layer 9, extra above-mentioned first S above substrateiO2Layer 7, it is above-mentionedLayer
8 and above-mentioned 2nd SiO2Layer 9 removes.
In preferred embodiment, in above-mentioned steps S2, above-mentioned first reaction pressure and above-mentioned second reaction pressure have one
Reaction pressure is poor, and above-mentioned reaction pressure difference and above-mentioned thickness difference are proportional.
In the present embodiment, the etching characteristic of the SiO2 deposited under different pressures is obtained by research, optimizes etching technics,
The second reaction pressure is reduced when making the first side wall 10 and the second side wall 11, reducing pressure can be obtained biggish thickness difference, make to deposit
2nd S in storage unit areaiO29 thickness of floor is less than the 2nd S in control circuit areaiO29 thickness of layer.
In preferred embodiment, in above-mentioned steps S23, above-mentioned etch period and above-mentioned second reaction pressure are proportional.
In the present embodiment, the time of etching will reduce as the reduction of deposition pressure is opposite.
In preferred embodiment, above-mentioned thickness difference is 13nm.
In preferred embodiment, above-mentioned second reaction pressure is 0.2tor.
It is in the present embodiment, optimal in the requirement that thickness difference floats in reasonable monolithic wafer to can reach 13nm or so,
Corresponding peak optimization reaction pressure is 0.2tor or so.
It as viewed in figures 5-8, is the schematic diagram that the first side wall 10 and the second side wall 11 are prepared by the way of of the invention, first
Component isolation structure 1 (as shown in Figure 1) is prepared in the substrate, and then in memory cell areas, preparation is subsequently used for preparing floating gate 2
Polysilicon layer and the isolating oxide layer (as shown in Figure 6) for being subsequently used for preparation node layer 3, then obtain 2 He of floating gate by etching
Dielectric layer 3 continues deposit polycrystalline silicon to form control gate 4 and spacer structure 6, and floating gate 2, dielectric layer 3 and control gate 4 constitute grid
Structure 5 (as shown in Figure 7) deposits a S using different reaction pressuresiO2Layer 7,Layer 8 and the 2nd SiO2Layer 9 constitutes first
Side wall 10 and the second side wall 11.
As shown in figure 9, being the corresponding relationship of thickness difference and pressure difference, the second reaction pressure is bigger, in the first side wall 10
The 2nd SiO2The 2nd S in bigger closer second side wall 11 of thickness of layer 9iO2The thickness of layer 9.
As shown in Figure 10, the figure in the upper left corner is the 2nd S in the second side wall 11 using prior art preparationiO2The thickness of layer 9
Degree is 48.5mm, and the figure in the upper right corner is the 2nd S in the first side wall 10 using prior art preparationiO2Layer 9 with a thickness of
47.35nm, the lower left corner are the 2nd S in the second side wall 11 prepared using the technology of the present inventioniO2Layer 9 with a thickness of 43.5nm, it is right
Inferior horn is the 2nd S in the first side wall 10 prepared using the technology of the present inventioniO2Layer 9 with a thickness of 39.91nm.Obviously, using this
After the method for invention, 11 thickness change of the second side wall in control circuit area is smaller, and the first side wall 10 of memory cell areas is thick
Degree changes greatly, this, which allows for the first side wall 10 and the second side wall 11, has biggish thickness difference, to realize electric property
Two-win.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (8)
1. a kind of method for improving memory cell areas and control circuit area side wall thicknesses difference, is suitable for non-volatile flash memory, comprising:
Step S1, a composite construction is provided, composite construction has memory cell areas and control circuit area, and composite construction includes lining
Bottom, the gate structure on the substrate of memory cell areas and the spacer structure on the substrate in control circuit area；Its feature
It is, method further include:
Step S2, it is sequentially depositing the first of first thickness on substrate using preset first reaction pressure in a reaction chamber
SiO2The Si of layer and second thickness3O4Layer deposits third thickness using preset second reaction pressure in reaction chamber on substrate
The 2nd SiO2Layer, the first SiO2Layer, Si3O4Layer and the 2nd SiO2Layer constitutes the first side wall and the covering of covering gate structure sidewall
Second side wall of spacer structure side wall, the first reaction pressure are greater than the second reaction pressure, the 2nd SiO in the first side wall2Thickness
Degree is less than the 2nd SiO in the second side wall2Thickness degree and have a preset thickness difference.
2. the method according to claim 1, which is characterized in that step S1 includes:
Step S11, a substrate is provided, carries out shallow grooved-isolation technique on substrate to form component isolation structure, the composite junction
Structure includes the substrate and the component isolation structure, and composite construction includes memory cell areas and control circuit area, composite construction
It further include the well region between adjacent elements isolation structure in memory cell areas；
Step S12, form gate structure above the substrate of well region, gate structure include the floating gate set gradually from the bottom to top,
Dielectric layer and control gate, to well region progress ion implanting, on the substrate between the adjacent elements isolation structure in control circuit area
Rectangular structure at interval.
3. method according to claim 2, which is characterized in that step S12 includes:
Step S121, on substrate surface deposit polycrystalline silicon to form the first polysilicon layer；
Step S122, planarization process is carried out to the first polysilicon layer and removal is located at first polysilicon layer in control circuit area simultaneously
Retain the first polysilicon layer for being located at memory cell areas；
Step S123, isolating oxide layer is formed on the first polysilicon layer for being located at memory cell areas, is covered using preset first
Film is exposed and etches to isolating oxide layer and the first polysilicon layer, with formed the dielectric layer that is made of isolating oxide layer and by
The floating gate that first polysilicon is constituted；
Step S124, ion implanting is carried out to well region；
Step S125, deposit polycrystalline silicon is continued to form the second polysilicon layer in surface on substrate；
Step S126, the second polysilicon layer is exposed and is etched using preset second exposure mask, in the top of dielectric layer
The control gate being made of the second polysilicon layer is formed, and above the substrate between the adjacent elements isolation structure in control circuit area
Form the spacer structure being made of the second polysilicon layer；
Step S127, low concentration doping object is injected in well region to form low concentration doping area.
4. the method according to claim 1, which is characterized in that step S2 includes:
Step S21, it is sequentially depositing the first SiO of first thickness on substrate using preset first reaction pressure in reaction chamber2
The Si of layer and second thickness3O4Layer；
Step S22, the 2nd SiO of third thickness is deposited on substrate using preset second reaction pressure in reaction chamber2Layer；
Step S23, in reaction chamber using preset etch period to the first SiO2Layer, Si3O4Layer and the 2nd SiO2Layer is carved
Erosion is to remove the first SiO that part covers upper surface of substrate2Layer, Si3O4Layer and the 2nd SiO2Layer simultaneously forms covering grid structure side
First side wall of wall and the second side wall of covering spacer structure side wall.
5. the method according to claim 1, which is characterized in that in step S2, the first reaction pressure has with the second reaction pressure
One reaction pressure is poor, and reaction pressure difference and thickness difference are proportional.
6. method according to claim 4, which is characterized in that in step S23, etch period and the second reaction pressure are proportional.
7. the method according to claim 1, which is characterized in that thickness difference 13nm.
8. the method according to claim 1, which is characterized in that the second reaction pressure is 0.2tor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710978316.1A CN107749413B (en) | 2017-10-18 | 2017-10-18 | A method of it improving memory cell areas and control circuit area side wall thicknesses is poor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710978316.1A CN107749413B (en) | 2017-10-18 | 2017-10-18 | A method of it improving memory cell areas and control circuit area side wall thicknesses is poor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107749413A CN107749413A (en) | 2018-03-02 |
| CN107749413B true CN107749413B (en) | 2019-02-19 |
Family
ID=61253938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710978316.1A Active CN107749413B (en) | 2017-10-18 | 2017-10-18 | A method of it improving memory cell areas and control circuit area side wall thicknesses is poor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107749413B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080047663A (en) * | 2006-11-27 | 2008-05-30 | 동부일렉트로닉스 주식회사 | Method of forming flash memory device |
| CN101325173A (en) * | 2007-06-12 | 2008-12-17 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN101673662A (en) * | 2008-09-09 | 2010-03-17 | 中芯国际集成电路制造(北京)有限公司 | Method for stabilizing electrical thickness of gate oxide |
| JP2010161301A (en) * | 2009-01-09 | 2010-07-22 | Toshiba Corp | Semiconductor memory device and method of manufacturing the same |
| CN102768953A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Process for eliminating side wall width load effect |
| CN103646864A (en) * | 2013-11-22 | 2014-03-19 | 上海华力微电子有限公司 | Method for improving thickness uniformity of grid side wall spacing layer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418091B1 (en) * | 2001-06-29 | 2004-02-11 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR20050069437A (en) * | 2003-12-31 | 2005-07-05 | 동부아남반도체 주식회사 | Method for fabricating static random access memory device |
-
2017
- 2017-10-18 CN CN201710978316.1A patent/CN107749413B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080047663A (en) * | 2006-11-27 | 2008-05-30 | 동부일렉트로닉스 주식회사 | Method of forming flash memory device |
| CN101325173A (en) * | 2007-06-12 | 2008-12-17 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN101673662A (en) * | 2008-09-09 | 2010-03-17 | 中芯国际集成电路制造(北京)有限公司 | Method for stabilizing electrical thickness of gate oxide |
| JP2010161301A (en) * | 2009-01-09 | 2010-07-22 | Toshiba Corp | Semiconductor memory device and method of manufacturing the same |
| CN102768953A (en) * | 2012-07-25 | 2012-11-07 | 上海华力微电子有限公司 | Process for eliminating side wall width load effect |
| CN103646864A (en) * | 2013-11-22 | 2014-03-19 | 上海华力微电子有限公司 | Method for improving thickness uniformity of grid side wall spacing layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107749413A (en) | 2018-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9356095B2 (en) | Vertical devices and methods of forming | |
| US7316955B2 (en) | Method of manufacturing semiconductor device | |
| US8609492B2 (en) | Vertical memory cell | |
| TWI409854B (en) | Split gate storage device including a horizontal first gate and a vertical second gate in a trench | |
| US20150011063A1 (en) | Methods of fabricating semiconductor structures | |
| CN106206598B (en) | Gate-division type flash memory device making method | |
| US10242880B2 (en) | Method of wet etching and method of fabricating semiconductor device using the same | |
| CN101777520B (en) | Production method of split-gate type nonvolatile storage of embedded floating gate | |
| US20080283897A1 (en) | Flash memory device and fabrication method thereof | |
| CN109904162A (en) | A kind of ferroelectric storage unit and its manufacturing method | |
| JP2000091520A (en) | Manufacture of trench capacitor in two-step ion layout | |
| CN104681494A (en) | Semiconductor memory device and preparation method thereof | |
| CN107749413B (en) | A method of it improving memory cell areas and control circuit area side wall thicknesses is poor | |
| CN115810546A (en) | Manufacturing method of shielded gate trench MOSFET with high-k dielectric | |
| US20020102808A1 (en) | Method for raising capacitance of a trench capacitor and reducing leakage current | |
| CN110289260A (en) | Manufacturing method, flash memory and the light shield mask plate of flash memory | |
| CN111508841A (en) | Semiconductor structure and manufacturing method thereof | |
| US10608006B2 (en) | Semiconductor memory device and fabrication method thereof | |
| US11024645B2 (en) | Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same | |
| KR20010059517A (en) | Method for forming cylinder type bottom electrode intergrated memory device | |
| CN105789277A (en) | Floating gate structure of flash memory and fabrication method | |
| KR20070000603A (en) | Method of manufacturing a floating gate in non-volatile memory device | |
| TWI555065B (en) | Method of manufacturing non-volatile memory | |
| CN102201452A (en) | Nonvolatile memory and manufacturing method thereof | |
| KR100877002B1 (en) | Non volatile memory device having a silicon oxide nitride oxide silicon structure and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |