WO2023005008A1 - 一种低介电常数高熵薄膜及其制备方法 - Google Patents

一种低介电常数高熵薄膜及其制备方法 Download PDF

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WO2023005008A1
WO2023005008A1 PCT/CN2021/125075 CN2021125075W WO2023005008A1 WO 2023005008 A1 WO2023005008 A1 WO 2023005008A1 CN 2021125075 W CN2021125075 W CN 2021125075W WO 2023005008 A1 WO2023005008 A1 WO 2023005008A1
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dielectric constant
thin film
low dielectric
buffer layer
constant high
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French (fr)
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娄晓杰
乔文婧
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西安交通大学
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/025—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3457—Sputtering using other particles than noble gas ions
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • C30B29/22—Complex oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of ultra-large-scale integrated circuit manufacturing, in short, relates to a low dielectric constant high-entropy thin film and a preparation method thereof.
  • interlayer dielectrics In microelectronic circuits, in order to realize the chip interconnection of VLSI devices with high speed, low dynamic power consumption and low crosstalk noise, materials with low dielectric constant are required as interlayer dielectrics.
  • the smaller the dielectric constant of the interlayer dielectric the higher the interconnectivity of the circuit and the smaller the switching delay.
  • the threshold voltage shift caused by the moving charge is small, and the leakage current is small, thereby reducing the power consumption of the integrated circuit.
  • scientists use compounds with extremely low polarizability and introduce pores to reduce the dielectric constant. However, such porous materials are often difficult to meet the stringent requirements for low-permittivity mechanical properties of microelectronic circuits.
  • SiO2 which has excellent thermal stability, has been the insulating material used between metal interconnection lines, while metal aluminum is the main material of interconnection lines.
  • the wires in the chip become denser, and the spacing and width become smaller and smaller, resulting in an increasing parasitic resistance-capacitance effect between the resistance (R) and the capacitance (C). more obvious.
  • RC delay causes power dissipation, device heating, line-to-line interference and signal delay.
  • the dielectric constant of a material there are two ways to reduce the dielectric constant of a material.
  • One is to reduce the number of polarized molecules per unit volume by reducing the material density, which is mainly achieved by introducing pores into the material. When nanometer-sized pores are introduced into the material, the dielectric constant of the material decreases rapidly. However, with the increase of pores in the material, the mechanical properties and corrosion resistance of the material will be poor, and the pore-forming agent is not easy to completely remove.
  • Another approach is to reduce the dielectric constant by reducing the polarization of the material. This method generally selects materials with low polarizability, such as some organic polymer materials. Although their dielectric constants are low, most of their mechanical properties are not stable, and the stability of integrated circuits in high-temperature environments cannot be guaranteed.
  • MOCVD chemical vapor deposition
  • the dielectric constant of low dielectric constant films prepared by chemical vapor deposition (MOCVD) is usually difficult to achieve very low, and organic polymers are difficult to integrate into existing integrated circuit processes due to their poor thermal stability.
  • the thin film material prepared by magnetron sputtering deposition technology has better temperature stability and excellent mechanical properties. Moreover, its preparation process is relatively simple, and its preparation cost is relatively low, so it has great advantages. Therefore, this project chooses to use magnetron sputtering technology to prepare thin film materials with low dielectric constant.
  • the present invention provides an interlayer dielectric material with low dielectric constant and low dielectric loss, which is applied in the semiconductor and large-scale integrated circuit industry, and its dielectric constant is comparable to that of current commercial materials (k ⁇ 2.7).
  • the object of the present invention is to overcome the problems existing in the prior art, and to provide a low dielectric constant high-entropy film and a preparation method thereof.
  • the low-permittivity high-entropy film involved in the present invention has a relatively dense structure and has a Characterized by permittivity and low dielectric loss.
  • a low dielectric constant high entropy thin film comprising: SrTiO 3 substrate , La 0.7 Sr 0.3 MnO 3 buffer layer placed on the surface of SrTiO 3 substrate and Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 film, Me is a transition metal element ion.
  • the La 0.7 Sr 0.3 MnO 3 buffer layer has a thickness in the range of 50-60 nm
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film has a thickness in the range of 100-400 nm.
  • Me uses Y, Nb, Ta, V, Mo or W.
  • the SrTiO 3 substrate is a single crystal SrTiO 3 substrate grown in (001) orientation.
  • the present invention also provides a method for preparing a low dielectric constant high-entropy thin film, comprising the following process:
  • both the La 0.7 Sr 0.3 MnO 3 buffer layer and the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 film are prepared by magnetron sputtering, Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 film is then annealed to obtain the low dielectric constant high entropy film.
  • BaCO 3 powder, ZrO 2 powder, TiO 2 powder, SnO 2 powder, HfO 2 powder and Me The oxide powder is prepared by ball milling, calcining, granulation, molding and sintering, and the sintering temperature is 100-200°C lower than the phase formation temperature of the system; the La 0.7 Sr 0.3 MnO target is made of ceramics purchased from Hefei Kejing target.
  • the La 0.7 Sr 0.3 MnO 3 buffer layer has a thickness in the range of 50-60 nm
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film has a thickness in the range of 100-400 nm.
  • Me uses Y, Nb, Ta, V, Mo or W.
  • the SrTiO 3 substrate is a single crystal SrTiO 3 substrate grown in (001) orientation.
  • FIG. 1 is a schematic structural diagram of an interrow capacitor with two parallel lines.
  • Fig. 2 is a ⁇ 2 ⁇ scanning diagram of the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film of the present invention.
  • Fig. 3 is a schematic diagram of the dielectric constant and dielectric loss of the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film of the present invention.
  • the low dielectric constant high - entropy film of the present invention comprises a SrTiO3 substrate and a La0.7Sr0.3MnO3 buffer layer placed on the surface of the SrTiO3 substrate and a film on the buffer layer , the film comprising Ba ( Zr0.2Sn0.2Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film, Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film is placed on top of La 0.7 Sr 0.3 MnO 3 buffer layer, and the buffer layer is placed on the surface of SrTiO 3 substrate.
  • Me adopts Y, Nb, Ta, V, Mo or W, and the corresponding valences are Y 3+ , Nb 5+ , Ta 5+ , V 5+ , Mo 6+ and W 6+ .
  • the La 0.7 Sr 0.3 MnO 3 buffer layer has a thickness ranging from 50 to 60 nm
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 ) O 3 film has a thickness ranging from 10 to 500 nm.
  • the SrTiO 3 substrate is a single crystal SrTiO 3 substrate grown in (001) orientation.
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 single crystal epitaxial film has the characteristics of low dielectric constant and low dielectric loss.
  • the preparation process of the low dielectric constant high-entropy thin film of the present invention comprises the following steps:
  • the sample is annealed for 10 minutes under an air pressure of 1.0 to 1.2 Pa; after the annealing is over, the temperature is lowered to room temperature, and the sample is taken out to obtain the high-entropy compound with low dielectric constant and low dielectric loss of the present invention.
  • Single crystal epitaxial thin film Single crystal epitaxial thin film.
  • the low dielectric constant high-entropy thin film obtained in this example is a single crystal epitaxial thin film with a perovskite structure, its dielectric constant value can reach 1.102, and its dielectric loss is 0.044. better stability.
  • the sample is annealed for 15 minutes under an air pressure of 1.0 to 1.2 Pa; after the annealing is over, the temperature is lowered to room temperature, and the sample is taken out to obtain the high-entropy compound with low dielectric constant and low dielectric loss of the present invention.
  • Single crystal epitaxial thin film Single crystal epitaxial thin film.
  • the low dielectric constant high-entropy thin film obtained in this example is a single crystal epitaxial thin film with a perovskite structure, its dielectric constant value can reach 1.963, and its dielectric loss is 0.048. better stability.
  • the sample is annealed for 13 minutes under an air pressure of 1.0 to 1.2 Pa; after the annealing is over, the temperature is lowered to room temperature, and the sample is taken out to obtain the high-entropy compound with low dielectric constant and low dielectric loss of the present invention.
  • Single crystal epitaxial thin film
  • the low dielectric constant high-entropy thin film obtained in this example is a single crystal epitaxial thin film with a perovskite structure, its dielectric constant value can reach 3.307, and its dielectric loss is 0.213. better stability.
  • a multi-stage pumping system composed of a mechanical pump and a molecular pump to pump the air pressure in the deposition chamber to a higher vacuum degree.
  • the vacuum degree is not less than 10-5 Pa;
  • the mixed gas of argon and oxygen required for the film, the volume ratio of argon and oxygen in the mixed gas is (3.9 ⁇ 4.1):1, and the pressure in the chamber is 1.0 ⁇ 1.2Pa; then the STO substrate is heated at 600°C , 1.0-1.2Pa under the pressure of baking for 12min, remove STO 3 substrate surface attachments; slowly introduce the mixed gas of argon and oxygen and adjust the mass flow meter to the required growth pressure of 1.0-1.2Pa.
  • the sample is annealed for 12 minutes under an air pressure of 1.0 to 1.2 Pa; after the annealing is over, the temperature is lowered to room temperature, and the sample is taken out to obtain the high-entropy compound with low dielectric constant and low dielectric loss of the present invention.
  • Single crystal epitaxial thin film
  • the low-dielectric constant high-entropy film obtained in this example is a single-crystal epitaxial film with a perovskite structure, its dielectric constant value can reach 3.932, and its dielectric loss is 0.094. better stability.
  • the present invention adopts radio frequency magnetron sputtering technology, and obtains La 0.7 Sr 0.3 MnO 3 buffer layer and Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 thin film on the substrate by bombarding the target with plasma. Depending on the sputtering time of the target, films with different thicknesses are obtained, and the films produced have both low dielectric constant and low dielectric loss.
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 system single crystal epitaxial thin film involved in the present invention can prepare a low dielectric constant single crystal epitaxial film by adjusting different thicknesses while maintaining the same composition. Thin films can be widely used in various integrated circuits or large-scale integrated circuits (such as chips).
  • the thin film with low dielectric constant of the present invention After the thin film with low dielectric constant of the present invention is obtained, its structure and dielectric properties are tested. When carrying out the dielectric property test, select the 200-mesh square copper mesh to plate the platinum electrode, and carry out the dielectric property test on it.
  • Figure 1 is a schematic diagram of the structure of two parallel line capacitors. As shown in Figure 1, it can be seen that two parallel wire structures are embedded in the dielectric layer, and these wires are insulated from the substrate (or the metal plane on top of the substrate) by the bottom dielectric layer. Line-to-line capacitors are more realistic structures than parallel-plate capacitors because they represent the capacitance between interconnect lines caused by technical constraints (minimum size, dielectric layer type, process conditions). Therefore, the performance of the low dielectric constant material has a particularly obvious impact on the performance of the entire capacitor.
  • the orientations of the prepared films are (001), (002), (003), all of which are c-axis oriented single crystal epitaxial films, and the orientations of the prepared films are (001), (002 ), (003), both are c-axis oriented single crystal epitaxial films. All films in Examples 1, 2, 3, and 4 have no second phase present.
  • Fig. 3 is the dielectric constant and dielectric loss measured at room temperature for samples of different preparation schemes involved in the present invention. It can be seen that the film prepared by the present invention has the lowest dielectric constant of 1.102, and the minimum dielectric loss can reach 0.056, indicating that the high-entropy film involved in the present invention has extremely low dielectric constant and dielectric loss.
  • the high-entropy thin film involved in the present invention has the characteristics of low dielectric constant and low dielectric loss at the same time, can effectively improve the interconnection type of the circuit, reduce the switching delay of the circuit, and reduce the leakage current and power consumption at the same time.
  • the high-entropy thin film of the invention belongs to the single crystal lead-free thin film, avoids the harm of the traditional Pb-based thin film to the environment and the human body, and meets the requirements for environmental protection in current and future industrial production.
  • the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 system high-entropy single-crystal epitaxial film provided by the present invention adopts radio frequency magnetron sputtering technology, and obtains La on the substrate by bombarding the ceramic target with plasma. 0.7 Sr 0.3 MnO 3 buffer layer, and then prepared Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 film on the buffer layer.
  • Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 ceramic target was synthesized by using high-purity powder and the traditional solid-phase preparation process of ceramics, and then using radio frequency magnetron sputtering technology, at high temperature and high oxygen pressure
  • the growth of the epitaxial thin film on the substrate buffer layer is achieved by bombarding the target with plasma under certain conditions; at the same time, the control of the thickness of the thin film can be realized by adjusting the sputtering time of the target.
  • By adjusting the chemical composition and film thickness of the film its dielectric properties have reached a new minimum value, which is comparable to that of Si-based low dielectric constant materials.
  • the invention realizes films with different thicknesses by adjusting the sputtering time of the target.
  • the dielectric constant of Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 samples varies with different examples, but generally remains between 1 and 5 , to meet the requirements for low dielectric constant in integrated circuits.
  • the advantages of the Ba(Zr 0.2 Sn 0.2 Ti 0.2 Hf 0.2 Me 0.2 )O 3 single crystal epitaxial thin film of the present invention are at least the following aspects:
  • An advantage of the present invention is that the preparation method is simple to operate, the performance of the equipment is stable, the preparation efficiency and product qualification rate are high, and it has good application and popularization.
  • a low dielectric constant high-entropy film provided by the present invention has a dense structure.
  • the low dielectric constant high-entropy thin film provided by the present invention has no volatile and harmful elements, stable performance and environmental friendliness.
  • the principle of reducing the dielectric constant of thin film materials in the present invention has the possibility of being extended to other substrates and substrate materials. Based on this principle, it is possible to find A lossy high-entropy thin film material, which can meet various performance requirements for low dielectric constant in the field of microelectronics.
  • the low dielectric constant high-entropy film provided by the invention has a relatively dense structure and excellent mechanical properties, and has the characteristics of low dielectric constant and low dielectric loss at the same time, which can effectively improve the interconnection type of the circuit and reduce the size of the circuit. Transition delay, while reducing leakage current and reducing power consumption.
  • the low dielectric constant high-entropy film provided by the invention has no volatile and harmful elements, avoids the harm of the traditional Pb-based film to the environment and human body, and meets the requirements for environmental protection in current and future industrial production.
  • the film provided by the present invention has the advantages of low dielectric constant and low dielectric loss.

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Abstract

一种低介电常数高熵薄膜及其制备方法，低介电常数高熵薄膜包括：SrTiO 3基片、置于SrTiO 3基片表面的La 0.7Sr 0.3MnO 3缓冲层以及设置于La 0.7Sr 0.3MnO 3缓冲层表面的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，Me为过渡族金属元素离子。低介电常数高熵薄膜具有比较致密的结构，并具有低介电常数和低介电损耗的特征。

Description

一种低介电常数高熵薄膜及其制备方法 技术领域
本发明涉及超大规模集成电路制造领域，简而言之，涉及一种低介电常数高熵薄膜及其制备方法。
背景技术
微电子电路中，为了实现高速、低动态功耗和低串扰噪声的超大规模集成器件芯片互连，需要低介电常数的材料作为层间介质。对于集成电路来说，层间介质的介电常数越小，电路的互连性越高，转换延迟越小。同时，移动电荷引起的阈值电压位移小，漏电流小，从而降低集成电路的功耗。一般情况下，科学家们采用具有极低极化率的化合物并引入孔隙等手段来降低介电常数。但是，这种多孔材料往往难以满足微电子电路对低介电常数机械性能的严格要求。大多数电子系统(如计算机，芯片等)是由集成电路(Integrated Circuits,ICs，比如芯片)和为ICs供电并传输数据的导电路径组成。集成电路越先进，对介电或绝缘材料的某些特征要求就越严格。此外，在嵌入器件和后续处理过程中，层间介质保持其特定的电、物理和化学性质是至关重要的。由于使用温度范围的限制，以及特征尺寸在0.25μm以下会加速缩小，故不能再依靠传统的选择。因此，在微电子器件小型化和摩尔定律的共同驱动下，科学家们必须寻找新的低介电常数和低介电损耗材料来代替当前使用的材料。
目前，有着优异热稳定性的SiO 2一直是金属互连线之间使用的绝缘材料，而金属铝则是互连导线的主要材料。但是，随着集成电路的集成度越来越高，芯片中的导线越来越密，间距和宽度越来越小，导致电阻(R)和电容(C)之间的寄生阻容效应越来越明显。当器件尺寸小于0.25微米时，阻容延迟(RC delay)造成功率耗散、器件发热、线间干扰和信号延迟。因此，除了用铜线(电阻率只有铝的60％)替代铝线之外，研发具有更低介电常数(k)的材料来取 代SiO 2(k＝4)来降低阻容延迟(RC delay)已成为当前半导体集成电路领域研究的一个重要课题。
一般情况下，降低材料的介电常数有两种办法。一种是通过降低材料密度来减少单位体积内的极化分子数，该种方法主要通过向材料中引入孔隙来实现。当向材料中引入具有纳米尺寸的孔隙的时候，材料的介电常数会较快降低。但随着材料中孔隙的增多，材料的机械性能和耐腐蚀性能都会较差，而且其中的成孔剂也不容易完全去除。另外一种方法是通过降低材料的极化强度来降低介电常数。该方法一般会选择低极化能力的材料，如一些有机聚合物材料，虽然其介电常数较低，但是大多数机械性能都不太稳定，无法保证集成电路在高温环境下的稳定性。
现有的低k材料主要为SiO 2(k＝4)及其衍生物(k＝2.8～3.7)，比如：无定形的等离子体增强化学气相沉积的掺碳氧化硅，有机聚合物，有机硅酸盐等。其中，化学气相沉积法(MOCVD)制备的低介电常数薄膜的介电常数通常很难达到很低，而有机聚合物由于较差的热稳定性使其难以集成到现有的集成电路工艺中。而磁控溅射沉积技术所制备的薄膜材料具有较好的温度稳定性和优异的机械特性。而且其制备工艺相对简单，制备成本相对较低，因此具有巨大的优势。因此，本项目选择利用磁控溅射技术制备低介电常数的薄膜材料。
因此，本发明提供的一种应用于半导体和大规模集成电路产业的具有低介电常数和低介电损耗的层间介质材料，其介电常数可媲美目前商用的材料(k≈2.7)。
发明内容
本发明的目的在于克服现有技术中存在的问题，提供一种低介电常数高熵薄膜及其制备方法，本发明涉及的低介电常数高熵薄膜具有比较致密的结构，并具有低介电常数和低介电损耗的特征。
本发明采用的技术方案如下：
一种低介电常数高熵薄膜，包括：SrTiO 3基片、置于SrTiO 3基片表面的La 0.7Sr 0.3MnO 3缓 冲层以及设置于La 0.7Sr 0.3MnO 3缓冲层表面的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，Me为过渡族金属元素离子。
优选的，La 0.7Sr 0.3MnO 3缓冲层的厚度范围为50～60nm，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的厚度范围为100～400nm。
优选的，Me采用Y、Nb、Ta、V、Mo或W。
优选的，SrTiO 3基片采用(001)取向生长的单晶SrTiO 3基片。
本发明还提供了一种低介电常数高熵薄膜的制备方法，包括如下过程：
在SrTiO 3基片的表面制备La 0.7Sr 0.3MnO 3缓冲层，在缓冲层表面制备Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，得到所述低介电常数高熵薄膜，Me为过渡族金属元素离子。
优选的，La 0.7Sr 0.3MnO 3缓冲层和Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜均通过磁控溅射的方法制备而成，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜后进行退火，得到所述低介电常数高熵薄膜。
优选的，磁控溅射Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜时的陶瓷靶材采用BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Me的氧化物粉经球磨、预烧、造粒、成型和烧结制备而成，其中烧结温度均低于体系成相温度100～200℃；La 0.7Sr 0.3MnO靶材采用购于合肥科晶的陶瓷靶材。
磁控溅射Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜以及La 0.7Sr 0.3MnO 3缓冲层过程中：将La 0.7Sr 0.3MnO 3缓冲层的陶瓷靶材和Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的陶瓷靶材安装完成后，在氩气和氧气的以体积比为(3.9～4.1):1的混合气体氛围中，进行预溅射1～2h，除去靶材表面杂质；然后将磁控溅射系统的沉积腔抽真空，真空度不小于10 -5Pa；再向沉积腔内通入所述氩气和氧气的混合气体，使沉积腔内气压为1.0～1.2Pa；然后将SrTiO 3基片在600～650℃、1.0～1.2Pa的气压下进行烘烤10～15min，除去SrTiO 3基片表面附着物；再向沉积腔缓慢通入所述氩气和氧气的混合气体并调节气压为1.0～1.2Pa；再在SrTiO 3基片上生长La 0.7Sr 0.3MnO 3缓冲层，然后在La 0.7Sr 0.3MnO 3缓冲层上生长Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜； Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜生长结束后，在1.0～1.2Pa的气压下进行退火10～15min；退火结束后待温度降至室温，将样品取出，得到所述低介电常数高熵薄膜。
优选的，La 0.7Sr 0.3MnO 3缓冲层的厚度范围为50～60nm，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的厚度范围为100～400nm。
优选的，Me采用Y、Nb、Ta、V、Mo或W。
优选的，SrTiO 3基片采用(001)取向生长的单晶SrTiO 3基片。
本发明具有以下有益的技术效果：
本发明涉及的低介电常数高熵薄膜介电常数最低可达到1.102，其介电常数可媲美目前商用的材料(k＝2.7)，且无孔洞，具有致密的结构，使得机械强度高，不易吸水，能够极大的提高集成电路的寿命。
附图说明
图1是两平行线结构的行间电容器的结构示意图。
图2是本发明Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的θ～2θ扫描图。
图3是本发明Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的介电常数和介电损耗示意图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
本发明的低介电常数高熵薄膜包括SrTiO 3基片和置于SrTiO 3基片表面的La 0.7Sr 0.3MnO 3缓冲层以及缓冲层上面的薄膜，所述薄膜包括Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜设置于La 0.7Sr 0.3MnO 3缓冲层上面，缓冲层则置于SrTiO 3基片表面。其中，Me采用Y、Nb、Ta、V、Mo或W，对应的化合价分别为Y 3+、Nb 5+、Ta 5+、V 5+、Mo 6+和W 6+。La 0.7Sr 0.3MnO 3缓冲层的厚度范围为50～60nm，所述Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的厚度范围为10～500nm。SrTiO 3基片为(001)取向生长的 单晶SrTiO 3基片。该Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3单晶外延薄膜具有低介电常数和低介电损耗的特点。
本发明的低介电常数高熵薄膜制备过程包括如下步骤：
(1)首先根据化学式Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3分别称取适量的4～5N级别BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Me的氧化物的高纯粉，对上述高纯粉的混合物进行球磨、预烧、造粒、成型和烧结工艺，采用传统固相陶瓷制备工艺制备成Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材。在制备陶瓷靶材的过程中，烧结温度均低于体系成相温度100～200℃。
(2)将所制备出的陶瓷靶材先用砂纸打磨再用气枪清净表面后，安装到磁控溅射系统中，在体积比为(3.9～4.1)：1的氩气和氧气的混合气体以及室温溅射环境下，首先进行预溅射1～2h，除去陶瓷靶材表面杂质。
(3)选用(001)取向生长的单晶SrTiO 3基片进行薄膜的沉积，将SrTiO 3基片浸入酒精中，用超声清洗设备进行震荡清洗3～10min，将清洗后的SrTiO 3基片用氮气吹干后立即放入磁控溅射系统的沉积腔中。
(4)利用机械泵和分子泵组合构成的多级抽气系统将沉积腔内气压抽至一个较高的真空度，此时真空度不小于10 -5Pa；再向沉积腔内通入生长薄膜所需的氩气和氧气的混合气体，混合气体中氩气和氧气的体积比为(3.9～4.1):1，此时腔内气压为1.0～1.2Pa；然后将STO基片在600～650℃、1.0～1.2Pa的气压下进行烘烤10～15min，除去STO基片(即SrTiO 3基片)表面附着物；缓慢通入所述氩气和氧气的混合气体并调节质量流量计至所需生长气压1.0～1.2Pa。
(5)待气压稳定后，调节生长时间，在STO基片上生长La 0.7Sr 0.3MnO 3缓冲层，然后在缓冲层上实现高熵单晶外延薄膜的生长，利用磁控溅射能够生长处致密的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜。
(6)生长结束后，在1.0～1.2Pa气压下对样品进行退火10～15min；退火结束后待温度降至室温，将样品取出，得到本发明的具有低介电常数与低介电损耗的高熵单晶外延薄膜。
实施例1
本实施例的低介电常数高熵薄膜制备过程包括如下步骤：
(1)首先根据化学式Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3分别称取适量的4N级别BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Nb 2O 5粉的高纯粉，对上述高纯粉的混合物进行球磨、预烧、造粒、成型和烧结的艺，采用传统固相陶瓷制备工艺制备成Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材。在制备陶瓷靶材的过程中，烧结温度均低于体系成相温度200℃。
(2)将所制备出的陶瓷靶材先用砂纸打磨再用气枪清净表面后，安装到磁控溅射系统中，在体积比为(3.9～4.1)：1的氩气和氧气的混合气体以及室温溅射环境下，首先进行预溅射2h，除去陶瓷靶材表面杂质。
(3)选用(001)取向生长的单晶SrTiO 3基片进行薄膜的沉积，将SrTiO 3基片浸入酒精中，用超声清洗设备进行震荡清洗5min，将清洗后的SrTiO 3基片用氮气吹干后立即放入磁控溅射系统的沉积腔中。
(4)利用机械泵和分子泵组合构成的多级抽气系统将沉积腔内气压抽至一个较高的真空度，此时真空度不小于10 -5Pa；再向沉积腔内通入生长薄膜所需的氩气和氧气的混合气体，混合气体中氩气和氧气的体积比为(3.9～4.1):1，此时腔内气压为1.0～1.2Pa；然后将STO基片在650℃、1.01.2Pa的气压下进行烘烤10min，除去STO 3基片表面附着物；缓慢通入所述氩气和氧气的混合气体并调节质量流量计至所需生长气压1.0～1.2Pa。
(5)待气压稳定后，调节生长时间，在STO 3基片上生长50～60nm的La 0.7Sr 0.3MnO 3缓冲层，然后在缓冲层上实现100nm的高熵单晶外延薄膜的生长。
(6)生长结束后，在1.0～1.2Pa气压下对样品进行退火10min；退火结束后待温度降至室 温，将样品取出，得到本发明的具有低介电常数与低介电损耗的高熵单晶外延薄膜。
本实施例制得的低介电常数高熵薄膜为钙钛矿结构的单晶外延薄膜，其介电常数值能达到1.102，介电损耗为0.044，同时在5kHz～1000kHz的频率范围内都具有较好的稳定性。
实施例2
本实施例的低介电常数高熵薄膜制备过程包括如下步骤：
(1)首先根据化学式Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3分别称取适量的4N级别BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Nb 2O 5粉的高纯粉，对上述高纯粉的混合物进行球磨、预烧、造粒、成型和烧结的艺，采用传统固相陶瓷制备工艺制备成Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材。在制备陶瓷靶材的过程中，烧结温度均低于体系成相温度150℃。
(2)将所制备出的陶瓷靶材先用砂纸打磨再用气枪清净表面后，安装到磁控溅射系统中，在体积比为(3.9～4.1)：1的氩气和氧气的混合气体以及室温溅射环境下，首先进行预溅射2h，除去陶瓷靶材表面杂质。
(3)选用(001)取向生长的单晶SrTiO 3基片进行薄膜的沉积，将SrTiO 3基片浸入酒精中，用超声清洗设备进行震荡清洗10min，将清洗后的SrTiO 3基片用氮气吹干后立即放入磁控溅射系统的沉积腔中。
(4)利用机械泵和分子泵组合构成的多级抽气系统将沉积腔内气压抽至一个较高的真空度，此时真空度不小于10 -5Pa；再向沉积腔内通入生长薄膜所需的氩气和氧气的混合气体，混合气体中氩气和氧气的体积比为(3.9～4.1):1，此时腔内气压为1.0～1.2Pa；然后将STO基片在630℃、1.0～1.2Pa的气压下进行烘烤15min，除去STO 3基片表面附着物；缓慢通入所述氩气和氧气的混合气体并调节质量流量计至所需生长气压1.0～1.2Pa。
(5)待气压稳定后，调节生长时间，在STO 3基片上生长50～60nm的La 0.7Sr 0.3MnO 3缓冲层，然后在缓冲层上实现200nm高熵单晶外延薄膜的生长。
(6)生长结束后，在1.0～1.2Pa气压下对样品进行退火15min；退火结束后待温度降至室温，将样品取出，得到本发明的具有低介电常数与低介电损耗的高熵单晶外延薄膜。
本实施例制得的低介电常数高熵薄膜为钙钛矿结构的单晶外延薄膜，其介电常数值能达到1.963，介电损耗为0.048，同时在5kHz～1000kHz的频率范围内都具有较好的稳定性。
实施例3
本实施例的低介电常数高熵薄膜制备过程包括如下步骤：
(1)首先根据化学式Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3分别称取适量的4N级别BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Nb 2O 5粉的高纯粉，对上述高纯粉的混合物进行球磨、预烧、造粒、成型和烧结的艺，采用传统固相陶瓷制备工艺制备成Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材。在制备陶瓷靶材的过程中，烧结温度均低于体系成相温度200℃。
(2)将所制备出的陶瓷靶材先用砂纸打磨再用气枪清净表面后，安装到磁控溅射系统中，在体积比为(3.9～4.1)：1的氩气和氧气的混合气体以及室温溅射环境下，首先进行预溅射1.5h，除去陶瓷靶材表面杂质。
(3)选用(001)取向生长的单晶SrTiO 3基片进行薄膜的沉积，将SrTiO 3基片浸入酒精中，用超声清洗设备进行震荡清洗3min，将清洗后的SrTiO 3基片用氮气吹干后立即放入磁控溅射系统的沉积腔中。
(4)利用机械泵和分子泵组合构成的多级抽气系统将沉积腔内气压抽至一个较高的真空度，此时真空度不小于10 -5Pa；再向沉积腔内通入生长薄膜所需的氩气和氧气的混合气体，混合气体中氩气和氧气的体积比为(3.9～4.1):1，此时腔内气压为1.0～1.2Pa；然后将STO基片在620℃、1.0～1.2Pa的气压下进行烘烤13min，除去STO 3基片表面附着物；缓慢通入所述氩气和氧气的混合气体并调节质量流量计至所需生长气压1.0～1.2Pa。
(5)待气压稳定后，调节生长时间，在STO 3基片上生长50～60nm的La 0.7Sr 0.3MnO 3缓冲 层，然后在缓冲层上实现300nm高熵单晶外延薄膜的生长。
(6)生长结束后，在1.0～1.2Pa气压下对样品进行退火13min；退火结束后待温度降至室温，将样品取出，得到本发明的具有低介电常数与低介电损耗的高熵单晶外延薄膜。
本实施例制得的低介电常数高熵薄膜为钙钛矿结构的单晶外延薄膜，其介电常数值能达到3.307，介电损耗为0.213，同时在5kHz～1000kHz的频率范围内都具有较好的稳定性。
实施例4
本实施例的低介电常数高熵薄膜制备过程包括如下步骤：
(1)首先根据化学式Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3分别称取适量的5N级别BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Nb 2O 5粉的高纯粉，对上述高纯粉的混合物进行球磨、预烧、造粒、成型和烧结的艺，采用传统固相陶瓷制备工艺制备成Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材。在制备陶瓷靶材的过程中，烧结温度均低于体系成相温度200℃。
(2)将所制备出的陶瓷靶材先用砂纸打磨再用气枪清净表面后，安装到磁控溅射系统中，在体积比为(3.9～4.1)：1的氩气和氧气的混合气体以及室温溅射环境下，首先进行预溅射1h，除去陶瓷靶材表面杂质。
(3)选用(001)取向生长的单晶SrTiO 3基片进行薄膜的沉积，将SrTiO 3基片浸入酒精中，用超声清洗设备进行震荡清洗5min，将清洗后的SrTiO 3基片用氮气吹干后立即放入磁控溅射系统的沉积腔中。
(4)利用机械泵和分子泵组合构成的多级抽气系统将沉积腔内气压抽至一个较高的真空度，此时真空度不小于10 ～5Pa；再向沉积腔内通入生长薄膜所需的氩气和氧气的混合气体，混合气体中氩气和氧气的体积比为(3.9～4.1):1，此时腔内气压为1.0～1.2Pa；然后将STO基片在600℃、1.0～1.2Pa的气压下进行烘烤12min，除去STO 3基片表面附着物；缓慢通入所述氩气和氧气的混合气体并调节质量流量计至所需生长气压1.0～1.2Pa。
(5)待气压稳定后，调节生长时间，在STO 3基片上生长50～60nm的La 0.7Sr 0.3MnO 3缓冲层，然后在缓冲层上实现400nm高熵单晶外延薄膜的生长。
(6)生长结束后，在1.0～1.2Pa气压下对样品进行退火12min；退火结束后待温度降至室温，将样品取出，得到本发明的具有低介电常数与低介电损耗的高熵单晶外延薄膜。
本实施例制得的低介电常数高熵薄膜为钙钛矿结构的单晶外延薄膜，其介电常数值能达到3.932，介电损耗为0.094，同时在5kHz～1000kHz的频率范围内都具有较好的稳定性。
本发明采用射频磁控溅射技术，通过等离子体对靶材的轰击在基片上得到La 0.7Sr 0.3MnO 3缓冲层和Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，通过调节靶材的溅射时间，得到了不同厚度的薄膜，制得的薄膜既较低的介电常数，又有较低的介电损耗。本发明涉及的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3体系单晶外延薄膜，在保持相同组分的情况下通过调整不同的厚度，制备出低介电常数的单晶外延的薄膜，可广泛地应用在各种集成电路中或大规模集成电路(比如芯片)。
得到本发明的具有低介电常数的薄膜后，对其进行结构和介电性能测试。进行介电性能测试时，选用200目的方形铜网镀上铂电极，对其进行介电性能测试。
所得到的材料性能：
图1为两平行线电容器的结构示意图。如图1，可以看出两条平行线结构嵌入在电介质层中，这些线通过底部介电层与衬底(或衬底顶部的金属平面)绝缘。与平行板电容器相比，线间电容器是更现实的结构，因为它们代表了由技术限制(最小尺寸、介质层类型、工艺条件)造成的互连线之间的电容。因此，低介电常数材料的性能对整个电容器的性能影响尤为明显。
由图2可以看出，所制备的薄膜的取向为(001)，(002)，(003)，均为c轴取向的单晶外延薄膜，所制备的薄膜的取向为(001)，(002)，(003)，均为c轴取向的单晶外延薄膜。实施例1,2,3,4 中的所有薄膜都没有第二相出现。
图3为本发明所涉及的不同制备方案的样品在室温下所测得的介电常数与介电损耗，可以看出，本发明所制备的薄膜在10 6时，具有最低的介电常数为1.102，介电损耗最低能达到0.056，说明本发明所涉及的高熵薄膜具有极低的介电常数与介电损耗。
本发明所涉及的高熵薄膜，同时具有低介电常数和低介电损耗的特征，能够有效地提高电路的互连型，减小电路的转换延迟，同时减小漏电流，降低功耗。本发明的高熵薄膜属于单晶无铅薄膜，避免了传统Pb基薄膜对环境以及人体的危害，符合当今和未来工业生产中对环保的要求。
本发明提供的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3体系高熵单晶外延薄膜是采用射频磁控溅射技术，通过等离子体对陶瓷靶材的轰击，在基片上得到La 0.7Sr 0.3MnO 3缓冲层，进而在缓冲层上制备得到Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜。首先采用高纯粉、通过陶瓷的传统固相制备工艺合成出Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3陶瓷靶材，再利用射频磁控溅射技术，在高温、高氧压条件下通过等离子体对靶材的轰击实现在基片缓冲层上外延薄膜的生长；同时，可以通过调节靶材的溅射时间来实现对薄膜厚度的控制。通过对该薄膜的化学成分和薄膜厚度进行调控，使其介电特性达到了新的最低值，可与Si基低介电常数的材料相媲美。
本发明通过调节靶材的溅射时间，实现了不同厚度的薄膜。通过对样品介电性能的测试，发现Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3样品的介电常数随着不同实施例的不同而变化，但总体都保持在1～5之间，满足集成电路中对于低介电常数的要求。本发明的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3单晶外延薄膜的优点至少还有以下几个方面：
(1)工艺简单。只是通过对制备时间的控制生长了不同厚度的薄膜，具有结构简单，工艺简洁的优点。
(2)频率稳定性好。可以看到，随着频率的增加，样品的介电常数和介电损耗都保持在 一个比较平稳的水平。
如上所述，在不偏离本发明精神和范围的情况下。还可以构成许多有很大差别的实施实例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。
(1)本发明的一个优势在于制备方法操作简单，设备性能稳定，制备效率和产品合格率高，具有很好的应用推广性。
(2)本发明的试剂和原料均市售可得，
(3)现有的低介电常数材料大多具有孔隙，孔隙的存在使得低介电常数材料的机械性能较差，本发明提供的一种低介电常数高熵薄膜具有致密的结构。
(4)本发明提供的一种低介电常数高熵薄膜，无挥发性和有害元素，性能稳定，环境友好。
(5)本发明提供的一种低介电常数高熵薄膜，具有较好的频率稳定性，
(6)本发明提供的一种低介电常数高熵薄膜，，由于高熵材料的稳定性，从而其具有较好的温度稳定性，
(7)更重要的是，本发明降低薄膜材料介电常数的原理具有可扩大至其他基体和衬底材料的可能性，基于此原理，能够发现同时具有极低介电常数和极低介电损耗的高熵薄膜材料，该薄膜材料可满足微电子领域对低介电常数的各项性能要求。
本发明提供的低介电常数高熵薄膜，具有比较致密的结构和优异的机械性能，同时具有低介电常数和低介电损耗的特征，能够有效地提高电路的互连型，减小电路的转换延迟，同时减小泄露电流，降低功耗。本发明提供的低介电常数高熵薄膜，无挥发性以及有害元素，避免了传统Pb基薄膜对环境以及人体的危害，符合当今和未来工业生产中对环保的要求。
由本发明所述薄膜的有益效果可知，本发明提供的薄膜同时具有低介电常数和低介电损耗等优点。

Claims (10)

  1. 一种低介电常数高熵薄膜，其特征在于，包括：SrTiO 3基片、置于SrTiO 3基片表面的La 0.7Sr 0.3MnO 3缓冲层以及设置于La 0.7Sr 0.3MnO 3缓冲层表面的Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，Me为过渡族金属元素离子。
  2. 根据权利要求1所述的一种低介电常数高熵薄膜，其特征在于，La 0.7Sr 0.3MnO 3缓冲层的厚度范围为50～60nm，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的厚度范围为100～400nm。
  3. 根据权利要求1所述的一种低介电常数高熵薄膜，其特征在于，Me采用Y、Nb、Ta、V、Mo或W。
  4. 根据权利要求1所述的一种低介电常数高熵薄膜，其特征在于，SrTiO 3基片采用(001)取向生长的单晶SrTiO 3基片。
  5. 一种低介电常数高熵薄膜的制备方法，其特征在于，包括如下过程：
    在SrTiO 3基片的表面制备La 0.7Sr 0.3MnO 3缓冲层，在缓冲层表面制备Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜，得到所述低介电常数高熵薄膜，Me为过渡族金属元素离子。
  6. 根据权利要求5所述的一种低介电常数高熵薄膜的制备方法，其特征在于，La 0.7Sr 0.3MnO 3缓冲层和Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜均通过磁控溅射的方法制备而成，然后退火15min，得到所述低介电常数高熵薄膜。
  7. 根据权利要求5所述的一种低介电常数高熵薄膜的制备方法，其特征在于，磁控溅射制备Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜时所用的陶瓷靶材采用BaCO 3粉、ZrO 2粉、TiO 2粉、SnO 2粉、HfO 2粉和Me的氧化物粉经球磨、预烧、造粒、成型和烧结制备而成，其烧结温度均低于体系成相温度100～200℃；
    用磁控溅射制备Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜以及La 0.7Sr 0.3MnO 3缓冲层过程中：将La 0.7Sr 0.3MnO 3缓冲层的陶瓷靶材和Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的陶瓷靶材安装完成后，在氩气和氧气的以体积比为(3.9～4.1):1的混合气体氛围中，进行预溅射1～2h，除去靶材表 面杂质；然后将磁控溅射系统的沉积腔抽真空，真空度不小于10 -5Pa；再向沉积腔内通入所述氩气和氧气的混合气体，使沉积腔内气压为1.0～1.2Pa；然后将SrTiO 3基片在600～650℃、1.0～1.2Pa的气压下进行烘烤10～15min，除去SrTiO 3基片表面附着物；再向沉积腔内缓慢通入所述氩气和氧气的混合气体并调节气压为1.0～1.2Pa；再在SrTiO 3基片上生长La 0.7Sr 0.3MnO 3缓冲层，然后在La 0.7Sr 0.3MnO 3缓冲层上生长Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜；Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜生长结束后，在1.0～1.2Pa气压下进行退火10～15min；退火结束后待温度降至室温，将样品取出，得到所述低介电常数高熵薄膜。
  8. 根据权利要求5所述的一种低介电常数高熵薄膜的制备方法，其特征在于，La 0.7Sr 0.3MnO 3缓冲层的厚度范围为50～60nm，Ba(Zr 0.2Sn 0.2Ti 0.2Hf 0.2Me 0.2)O 3薄膜的厚度范围为100～400nm。
  9. 根据权利要求5所述的一种低介电常数高熵薄膜的制备方法，其特征在于，Me采用Y、Nb、T、V、Mo或W。
  10. 根据权利要求5所述的一种低介电常数高熵薄膜的制备方法，其特征在于，SrTiO 3基片采用(001)取向生长的单晶SrTiO 3基片。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116924796A (zh) * 2023-08-14 2023-10-24 昆明理工大学 一种abo3型低介电损耗陶瓷及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020189533A1 (en) * 2001-06-01 2002-12-19 Jun Ho Kim Superconductor incorporating therein superconductivity epitaxial thin film and manufacturing method thereof
CN1725444A (zh) * 2004-07-20 2006-01-25 中国科学院物理研究所 在硅衬底上外延生长铝酸镧薄膜材料及制备方法
CN101230450A (zh) * 2007-08-28 2008-07-30 北京有色金属研究总院 一种射频溅射制备织构化钛酸锶钡介电陶瓷薄膜的方法
CN101510556A (zh) * 2008-11-28 2009-08-19 湖北大学 一种双层高介电常数栅介质薄膜及其制备方法
CN108796444A (zh) * 2018-06-01 2018-11-13 西安交通大学 一种高硬度四元难熔高熵合金薄膜的制备方法
CN111118464A (zh) * 2019-12-30 2020-05-08 四川大学 一种纳米晶高熵氧化物薄膜的制备方法及应用
CN112670086A (zh) * 2020-10-27 2021-04-16 西安交通大学 一种硅集成具有高储能密度的薄膜电容器及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4120589B2 (ja) * 2004-01-13 2008-07-16 セイコーエプソン株式会社 磁気抵抗効果素子及び磁気メモリ装置
US9255347B2 (en) * 2013-11-22 2016-02-09 Sandia Corporation Voltage tunability of thermal conductivity in ferroelectric materials
CN110257788B (zh) * 2019-06-25 2020-08-18 西安交通大学 一种BaZr0.35Ti0.65O3外延薄膜及其制备方法
CN112582173A (zh) * 2020-11-25 2021-03-30 西安潜龙环保科技有限公司 一种高能量密度的钛酸锶钡基介电薄膜电容器及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020189533A1 (en) * 2001-06-01 2002-12-19 Jun Ho Kim Superconductor incorporating therein superconductivity epitaxial thin film and manufacturing method thereof
CN1725444A (zh) * 2004-07-20 2006-01-25 中国科学院物理研究所 在硅衬底上外延生长铝酸镧薄膜材料及制备方法
CN101230450A (zh) * 2007-08-28 2008-07-30 北京有色金属研究总院 一种射频溅射制备织构化钛酸锶钡介电陶瓷薄膜的方法
CN101510556A (zh) * 2008-11-28 2009-08-19 湖北大学 一种双层高介电常数栅介质薄膜及其制备方法
CN108796444A (zh) * 2018-06-01 2018-11-13 西安交通大学 一种高硬度四元难熔高熵合金薄膜的制备方法
CN111118464A (zh) * 2019-12-30 2020-05-08 四川大学 一种纳米晶高熵氧化物薄膜的制备方法及应用
CN112670086A (zh) * 2020-10-27 2021-04-16 西安交通大学 一种硅集成具有高储能密度的薄膜电容器及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116924796A (zh) * 2023-08-14 2023-10-24 昆明理工大学 一种abo3型低介电损耗陶瓷及其制备方法
CN116924796B (zh) * 2023-08-14 2024-05-14 昆明理工大学 一种abo3型低介电损耗陶瓷及其制备方法

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