WO2023000647A1 - 耗材芯片、具有其的耗材盒以及耗材芯片的制作方法 - Google Patents

耗材芯片、具有其的耗材盒以及耗材芯片的制作方法 Download PDF

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Publication number
WO2023000647A1
WO2023000647A1 PCT/CN2022/075041 CN2022075041W WO2023000647A1 WO 2023000647 A1 WO2023000647 A1 WO 2023000647A1 CN 2022075041 W CN2022075041 W CN 2022075041W WO 2023000647 A1 WO2023000647 A1 WO 2023000647A1
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Prior art keywords
terminal
voltage
terminals
detection
voltage terminal
Prior art date
Application number
PCT/CN2022/075041
Other languages
English (en)
French (fr)
Inventor
周祎
Original Assignee
杭州旗捷科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杭州旗捷科技有限公司 filed Critical 杭州旗捷科技有限公司
Priority to JP2022581634A priority Critical patent/JP2023537663A/ja
Priority to EP22844821.3A priority patent/EP4180235A4/en
Priority to US18/098,715 priority patent/US20230150268A1/en
Publication of WO2023000647A1 publication Critical patent/WO2023000647A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17526—Electrical contacts to the cartridge
    • B41J2/1753—Details of contacts on the cartridge, e.g. protection of contacts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically

Definitions

  • the present application relates to the technical field of printing equipment, and in particular to a consumable chip, a consumable box with the same, and a method for manufacturing the consumable chip.
  • Printing equipment needs to be used with consumable boxes.
  • Common consumable boxes include ink cartridges.
  • Ink cartridge chips are installed in the ink cartridges.
  • the ink cartridge chips are used to store brand information, ink type information, ink color information, and ink dosage information.
  • the ink cartridges are installed behind the printing equipment. , it needs to be certified before it can be used normally. Therefore, the ink cartridge chip plays a vital role in whether the printing device can use the ink cartridge normally.
  • the printing device end is provided with a plurality of contact pins.
  • the ink cartridge chip is correspondingly provided with a plurality of terminals which cooperate with the plurality of contact pins;
  • Contact pins and detection pins the terminals of the ink cartridge chip include high-voltage terminals, detection terminals, and signal transmission terminals, and the signal transmission terminals include multiple conductive terminals, such as power terminals, grounding terminals, and data terminals; in order to verify whether the ink cartridge is installed in place , the printing device performs installation inspection by verifying the contact between the high-voltage terminal and the high-voltage contact pin, the detection contact pin and the detection terminal.
  • the signal transmission terminal of the ink cartridge chip is also in good contact with the contact pin of the printing device.
  • the ink cartridge chip is short-circuited due to ink dripping or contact pin deformation between the high-voltage terminal and its adjacent detection terminal, which may cause damage to the ink cartridge chip and printer equipment, and bring unnecessary economic losses to consumers. and time loss.
  • a short circuit detection circuit is provided at the printing device end, and the voltage change of the contact pin at the printing device end is detected by the short circuit detection circuit, so as to determine whether a short circuit occurs between terminals on the ink cartridge chip.
  • the above-mentioned short-circuit detection scheme is performed after the ink cartridge chip is installed on the printing device, and although the short-circuit phenomenon is detected at this time, the storage element on the ink cartridge chip may have been short-circuited and damaged.
  • there are printing devices on the market that are not provided with a short-circuit detection circuit and there is a relatively large potential safety hazard for such printing devices.
  • the related art also discloses a scheme of setting a short-circuit detection mechanism at the ink cartridge chip. Although this scheme can independently complete the detection of the short-circuit phenomenon at the ink cartridge chip, it is necessary to additionally set detection terminals and corresponding hardware circuits on the ink cartridge chip substrate. , higher cost, more complicated, and may cause potential interference to the normal communication between the ink cartridge chip and the printing device.
  • a consumable chip including a memory, a substrate, at least one low-voltage terminal electrically connected to the memory, at least one high-voltage terminal, and at least one detection terminal arranged on the substrate, the high-voltage terminal and the detection terminal are arranged at intervals
  • the consumable chip further includes a conductive structure, one end of the conductive structure is electrically connected to the low-voltage terminal, and the other end of the conductive structure extends between the high-voltage terminal and the detection terminal.
  • the number of the high-voltage terminals and the detection terminals is two groups and arranged at intervals, at least one of the low-voltage terminals is connected to at least one conductive structure, and one end of the conductive structure is electrically connected to the low-voltage terminal. , and the other end extends between at least one set of the high-voltage terminals and the detection terminals.
  • the conductive structure is a metal lead.
  • the conductive structure is T-shaped or L-shaped.
  • a first notch is opened on the side wall of the substrate, and a conductive layer is provided in the first notch to form the low-voltage terminal;
  • a second notch is opened on the side wall of the substrate, and a conductive layer is provided in the second notch to form the high-voltage terminal;
  • the side wall of the substrate is provided with a third notch and a fourth notch, the fourth notch is formed along the length direction of the substrate, and the third notch is arranged on the side of the fourth notch On the wall, a conductive layer is provided in the third notch to form the detection terminal.
  • the second notch is a right-angled slot having a long side wall and a short side wall, and the long side wall is provided with a conductive layer and forms the high voltage terminal.
  • the conductive structure includes a connecting section and a blocking section, one end of the connecting section is electrically connected to the low-voltage terminal, the other end of the connecting section is electrically connected to the blocking section, and the blocking section A segment extends between the high voltage terminal and the detection terminal.
  • a consumable material box comprising a consumable material box body and the above-mentioned consumable material chip, the consumable material chip being arranged on the consumable material box body.
  • a method for manufacturing a consumable chip which is used to prepare the above-mentioned consumable chip.
  • the consumable chip is provided with a conductive structure, and the end of the conductive structure away from the low-voltage terminal extends to between the high-voltage terminal and the detection terminal, so that if the high-voltage terminal and the detection terminal are short-circuited by ink, etc., the high-voltage terminal
  • the high voltage on the high voltage will be guided to the corresponding low voltage terminal through the conductive structure, so as to divide and reduce the high voltage through the low voltage terminal, preventing the high voltage on the high voltage terminal from being added to the detection terminal; that is, the detection terminal does not receive high voltage signals , to play the role of short-circuit detection and short-circuit protection, to prevent consumable chips and printing equipment from being burned out and damaged due to high voltage.
  • Fig. 1 is a structural schematic diagram 1 of the consumable chip provided by the present application.
  • Fig. 2 is the structural schematic diagram II of the consumable chip provided by the present application.
  • Fig. 3 is a schematic diagram of the third structure of the consumable chip provided by the present application.
  • Fig. 4 is a schematic structural diagram of the consumable chip in Example 1 provided by the present application.
  • Fig. 5 is a schematic diagram of the terminal of the consumable chip provided by the present application in contact with the contact pin of the printing device;
  • FIG. 6 is a schematic diagram of ink droplets on the consumable chip in Example 1 provided by the present application.
  • Fig. 7 is a schematic diagram II of the structure of the consumable chip in Example 1 provided by the present application.
  • Fig. 8 is a schematic diagram of the third structure of the consumable chip in Example 1 provided by the present application.
  • FIG. 9 is a schematic diagram of the electrical connection between the two detection terminals and the memory provided by the present application.
  • FIG. 10 is a schematic structural diagram of Embodiment 2 of the consumable chip provided by the present application.
  • Fig. 11 is a schematic structural diagram of Embodiment 3 of the consumable chip provided by the present application.
  • Fig. 12 is a schematic structural diagram of Embodiment 4 of the consumable chip provided by the present application.
  • FIG. 13 is a schematic structural diagram of Embodiment 5 of the consumable chip provided by the present application.
  • Figure 14 is a schematic structural diagram of Embodiment 6 of the consumable chip provided by the present application.
  • Fig. 15 is a schematic structural diagram of Embodiment 7 of the consumable chip provided by the present application.
  • Fig. 16 is a schematic structural diagram of Embodiment 8 of the consumable chip provided by the present application.
  • Fig. 17 is a schematic structural diagram of Embodiment 9 of the consumable chip provided by the present application.
  • Fig. 18 is a schematic structural diagram of Embodiment 10 of the consumable chip provided by the present application.
  • Fig. 19 is a schematic structural diagram of Embodiment 11 of the consumable chip provided by the present application.
  • Fig. 20 is a schematic structural diagram of Embodiment 12 of the consumable chip provided by the present application.
  • Fig. 21 is the second structural diagram of Embodiment 12 of the consumable chip provided by the present application.
  • Fig. 22 is a schematic flow chart of the method for making a consumable chip provided by the present application.
  • a component when a component is said to be “mounted on” another component, it may be directly mounted on another component or there may be an intervening component.
  • a component When a component is said to be “set on” another component, it can be set directly on the other component or there may be an intervening component at the same time.
  • a component When a component is said to be “fixed” to another component, it may be directly fixed to the other component or there may be an intervening component at the same time.
  • the present application provides a consumable chip 100 installed on a consumable box for recording/recording relevant information of the consumable box and realizing connection between the consumable box and a printing device.
  • the consumable chip 100 includes a memory 104, a substrate 10, at least one low-voltage terminal 100a arranged on the substrate 10 and electrically connected to the memory 104, at least one high-voltage terminal 21, and at least one detection terminal 22.
  • the high-voltage terminal 21 and the detection terminal 22 are arranged at intervals.
  • the consumable chip 100 also includes a conductive structure 3 , one end of the conductive structure 3 is electrically connected to the low-voltage terminal, and the other end of the conductive structure 3 extends between the high-voltage terminal 21 and the detection terminal 22 .
  • the detection terminal 22 does not Receive the high voltage signal to play the role of short circuit detection and short circuit protection, so as to avoid the consumable chips and printing equipment from being burned out and damaged due to high voltage.
  • the number of high-voltage terminals 21 and detection terminals 22 is two groups and arranged at intervals, at least one low-voltage terminal 100a is connected to at least one conductive structure 3, one end of the conductive structure 3 is electrically connected to the low-voltage terminal 100a, and the other end extends to at least one group Between the high voltage terminal 21 and the detection terminal 22 .
  • one low-voltage terminal 100a can be connected to multiple conductive structures 3
  • one conductive structure 3 can be connected to multiple low-voltage terminals
  • the other end of the conductive structure 3 can extend between a group of high-voltage terminals 21 and detection terminals 22. They can respectively extend between two sets of high-voltage terminals 21 and detection terminals 22 .
  • the conductive structure 3 includes a connecting section 301 and a blocking section 302, one end of the connecting section 301 is electrically connected to the low-voltage terminal 100a, the other end of the connecting section 301 is electrically connected to the blocking section 302, and the blocking section 302 extends to the high-voltage terminal 21 and detection terminal 22.
  • barrier section 302 can extend between any set of high voltage terminals 21 and detection terminals 22 , or between two groups of high voltage terminals 21 and detection terminals 22 respectively.
  • the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the two groups of terminals are arranged on the substrate 10 at intervals;
  • the conductive structure 3 includes a conductive lead 30, and the conductive lead 30 includes a connecting section 301 and a blocking section 302; one end of the connecting section 301 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the blocking section 302; the two ends of the blocking section 302 correspond to a group terminals, and the two ends of the blocking section 302 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • both groups of high-voltage terminals 21 and detection terminals 22 can be connected to the same low-voltage terminal 100a through the blocking section 302 and the connecting section 301 of the conductive lead 30 .
  • the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the two groups of terminals are arranged on the substrate 10 at intervals;
  • the conductive structure 3 includes a plurality of conductive leads 30, one end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end extends between a group of high-voltage terminals 21 and detection terminals 22; one end of at least one conductive lead 30 is electrically connected to The other end of at least one low-voltage terminal 100 a extends between another group of high-voltage terminals 21 and detection terminals 22 .
  • the conductive structure includes a plurality of conductive leads 30, at least one conductive lead 30 is connected to at least one low-voltage terminal 100a between any set of high-voltage terminals 21 and detection terminals 22, and between two groups of high-voltage terminals 21 and detection terminals 22
  • the wire leads 30 between them may be connected to the same low-voltage terminal 100a, or to different low-voltage terminals 100a.
  • the other end extends to the conductive lead 30 between a group of high-voltage terminals 21 and the detection terminal 22, including a first connecting section 303 and a first blocking section 304; one end of the first connecting section 303 is electrically connected to At least one low-voltage terminal 100a, the other end of which is connected to the first barrier segment 304; the two ends of the first barrier segment 304 respectively correspond to a group of terminals, and the two ends of the first barrier segment 304 respectively extend to the high-voltage terminals 21 and 21 in the corresponding group. Between detection terminals 22;
  • the other end extends to the conductive lead 30 between another set of high-voltage terminals 21 and the detection terminal 22, including a second connection section 305 and a second barrier section 306; one end of the second connection section 305 is electrically connected to at least one low-voltage terminal 100a, and the other end It is connected with the second blocking section 306; the two ends of the second blocking section 306 respectively correspond to a group of terminals, and the two ends of the second blocking section 306 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • any conductive lead 30 can extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group at the same time.
  • the low-voltage terminal 100a includes a first low-voltage terminal 101 and a second low-voltage terminal 102 arranged at intervals
  • the conductive structure 3 includes a first conductive lead 31 and a second conductive lead 32, and the first conductive lead 31
  • One end is electrically connected to the first low-voltage terminal 101, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22.
  • One end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends to correspond to the first conductive lead 31.
  • the installation detection part inside the printing device will apply a high voltage (about 40V) to the high voltage terminal 21 to detect the voltage or current value transmitted to the output terminal of the installation detection part. Detect whether the high-voltage terminal 21 is in electrical contact with the corresponding contact pin on the printing device, and then determine whether the consumable cartridge is correctly installed on the printing device.
  • conductive substances such as ink are sometimes sputtered onto the substrate 10 and cover the high-voltage terminal 21 and the detection terminal 22, causing the high-voltage terminal 21 to communicate with the detection terminal 22 to cause a short circuit, resulting in a consumable chip 100 and/or damage to the printing device.
  • the printing device uses the internal circuit to detect the state of the consumable chip 100, such as the installation status and ink level status; the printing device usually inputs a voltage of about 40V to one of the high-voltage terminals 21, and through The other high-voltage terminal 21 outputs, wherein the voltage output by the other high-voltage terminal 21 is usually greater than 3.2V and less than 40V.
  • the printing device usually sends a voltage not higher than 3.2V or not higher than 5V to one of the two detection terminals 22, and the other detection terminal 22 outputs a voltage not higher than 3.2V or not higher than 5V. Therefore,
  • the voltage received by the two high-voltage terminals 21 is higher than the voltage received by the detection terminal 22, and because the voltage difference between the two is too large, if a short circuit occurs between the two, the high voltage is mistakenly applied to the low-voltage detection terminal 22 , it may cause damage to the consumable chip 100 before the detection terminal 22 triggers the short circuit protection function.
  • this application provides a new type of consumable chip 100, which is provided with a first conductive lead 31 and a second conductive lead 32, and the first conductive lead 31 and the second conductive lead 32 are respectively far away from the first conductive lead 31 and the second conductive lead 32.
  • One end of a low-voltage terminal 101 and a second low-voltage terminal 102 respectively extend between the high-voltage terminal 21 and the detection terminal 22 .
  • the high voltage on the high voltage terminal 21 will be guided to the corresponding first low voltage terminal 101 and the second conductive lead 32 through the first conductive lead 31 and the second conductive lead 32.
  • the high voltage is divided and reduced by the first low-voltage terminal 101 and the second low-voltage terminal 102, preventing the high voltage on the high-voltage terminal 21 from being added to the detection terminal 22; that is, the detection terminal 22 does not receive High voltage signal is used to detect short circuit and protect against short circuit, so as to prevent consumable chips 100 and printing equipment from being burnt out or damaged due to high voltage.
  • the ink cartridge chip When the high voltage is guided to the low-voltage terminal 100a through the conductive lead, the ink cartridge chip will trigger the printing device to give an error message such as "required to turn off the power" or "the ink cartridge is installed abnormally", so that the printing device cannot print, prompting the user to check or check the ink cartridge. replace.
  • the high-voltage output terminal When the high-voltage output terminal is short-circuited with the data terminal and the ground terminal, the voltage of the high-voltage output terminal will be pulled down, and at the same time, the high-voltage input terminal will still normally send an installation detection signal to the high-voltage output terminal. Normal installation detection signal, at this time, the printing device will prompt an error message such as "Ink cartridge installation is abnormal".
  • the substrate 10 includes a first surface 10a and a second surface (not shown) opposite to each other, and the first low-voltage terminal 101, the second low-voltage terminal 102, the conductive lead 30, the high-voltage terminal 21 and the detection terminal 22 are all Arranged on the first side 10a, the memory 104 is arranged on the second side.
  • the high voltage may be greater than the working voltage of the consumable chip 100 , that is, the voltage applied to the chip terminals.
  • the operating voltage of the consumable chip 100 is mostly 3.3V or 5V.
  • the high voltage may be higher than 3.3V or higher than 5V, and the low voltage may be lower than 3.3V or lower than 5V.
  • a first notch 11 is opened on the side wall of the substrate 10, and a conductive layer is disposed in the first notch 11 to form a low-voltage terminal 100a;
  • a second notch 12 is opened on the side wall of the substrate 10, and a conductive layer is provided in the second notch 12 to form a high-voltage terminal 21; and/or
  • the side wall of the substrate 10 is provided with a third notch 13 and a fourth notch 14, the fourth notch 14 is formed along the length direction of the substrate 10 (i.e. the x-axis direction in Figure 8), and the third notch 13 is located at On the sidewall of the fourth notch 14 , a conductive layer is disposed inside the third notch 13 and a detection terminal 22 is formed.
  • the first low-voltage terminal 101 may be any one of an enable terminal 101a, a clock terminal 101b, a ground terminal 101c, a data terminal 101d, and a power terminal 101e.
  • the second low voltage terminal 102 may also be any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e.
  • the first low-voltage terminal 101 is a power supply terminal 101e
  • the second low-voltage terminal 102 is an enabling terminal 101a.
  • first low voltage terminal 101 and/or the second low voltage terminal 102 may be formed by disposing a conductive layer on the substrate 10 .
  • the first low-voltage terminal 101 and/or the second low-voltage terminal 102 are solid terminals, and the shape can be set to any shape such as a waist-shaped hole, an ellipse, a semicircle, or a rectangle.
  • the conductive layer is made of conductive material, such as silver layer, copper layer, copper alloy layer and so on.
  • the first low-voltage terminal 101 and/or the second low-voltage terminal 102 can be formed by directly plating a conductive layer on the substrate 10, or by opening a first notch 11 on the substrate 10 (as shown in FIG. 7 ), And a conductive layer is formed in the first notch 11 .
  • the notch of the first notch 11 is arranged flush with the lower side of the substrate 10 .
  • the shape of the first notch 11 is set to be a rectangle, an ellipse, or a semicircle. In this embodiment, the shape of the first notch 11 may be a rectangle.
  • the selected terminals between the first low-voltage terminal 101 and the second low-voltage terminal 102 do not overlap.
  • the first low-voltage terminal 101 is the enable terminal 101a
  • the second low-voltage terminal 102 is a terminal other than the enable terminal 101a, such as the clock terminal 101b, the ground terminal 101c, the data terminal 101d or the power supply terminal 101e
  • the first low-voltage terminal 101 is a data terminal 101d
  • the second low-voltage terminal 102 is a terminal other than the data terminal 101d, such as an enable terminal 101a, a clock terminal 101b, a ground terminal 101c, or a power supply terminal 101e, and so on Assume.
  • the first conductive lead 31 and the second conductive lead 32 can be respectively connected to different terminals, thereby improving the effect of reducing/dividing voltage.
  • the substrate 10 is respectively provided with an enable terminal 101a, a clock terminal 101b, a ground terminal 101c, a data terminal 101d and a power supply terminal 101e, and the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and The power terminals 101e are arranged in an array.
  • the detection terminal 22 is connected to the ground terminal 101c after connecting a resistor, so that the detection terminal 22 is grounded through the ground terminal 101c, so as to release some abnormally large currents on the detection terminal 22 through the ground terminal 101c, thereby protecting the consumable chip 100 Burned due to high current.
  • the data terminal 101d is used for data transmission with an external printing device, and the power terminal 101e is used for supplying power to the consumable chip 100 .
  • the enable terminal 101 a and the clock terminal 101 b are arranged side by side; the ground terminal 101 c , the data terminal 101 d and the power terminal 101 e are arranged side by side.
  • the arrangement of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e can be arranged according to the overall design of the actual consumable chip 100, and will not be repeated here. , the same or similar layout manners belong to the limited combination of this embodiment.
  • the enable terminal 101 a , the clock terminal 101 b , the ground terminal 101 c , the data terminal 101 d and the power terminal 101 e can all be formed by a conductive layer coated on the substrate 10 .
  • the shapes of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e are not limited, and may be waist-shaped holes, circles, semicircles, ovals or rectangles.
  • the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e are all arranged in the shape of a waist-shaped hole.
  • the enable terminal 101a and the clock terminal 101b are arranged in the shape of a waist-shaped hole, and at least one of the ground terminal 101c, the data terminal 101d or the power terminal 101e can be formed on the substrate 10 A first notch 11 is opened, and a conductive layer is formed in the first notch 11 opened on the substrate 10 .
  • the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the two groups of terminals are arranged on the substrate 10 at intervals, and the high-voltage terminals 21 in the two groups of terminals are electrically connected, Therefore, the two high-voltage terminals 21 respectively abut against the high-voltage contact pins corresponding to the printing device side to form a detection circuit, so that the printing device can realize the installation detection of the high-voltage terminals 21 .
  • the detection terminals 22 in the two groups of terminals are electrically connected, so that the two detection terminals 22 abut against the detection pins corresponding to the printing device side respectively to form a detection circuit, so that the printing device can realize the installation detection of the detection terminals 22 .
  • a resistor R1 or a sensor is set between the two high-voltage terminals 21, and the resistor R1 is used for installation detection, that is, the installation detection part on the printing device judges the high voltage by detecting the corresponding current value or voltage value flowing through the resistor R1
  • the terminal 21 corresponds to the installation state of the contact pin of the printing device.
  • the sensor is set to detect the ink level of the consumable cartridge.
  • the substrate 10 is provided with a second notch 12 , and the second notch 12 has a plurality of sidewalls, at least one of which is plated with a conductive layer to form a high-voltage terminal on the substrate 10 twenty one.
  • the high voltage terminal 21 can also be directly formed by plating a conductive layer on the substrate 10 .
  • the second notch 12 is a right-angle slot, that is, it is arranged in a rectangular shape, and the high-voltage contact pin is in contact with the long side wall of the right-angle slot to realize the communication between the printing device and the consumable chip 100; wherein, the right-angle slot has a long side wall and the short side wall, the long side wall is provided with a conductive layer and forms a high voltage terminal 21, the right angle groove can be copper-plated on the long side wall, the short side wall is not copper-plated, and the short side wall only acts as a limiter.
  • the movement of the high-voltage contact pin is effectively limited, and the high-voltage contact pin is prevented from being in poor contact with the corresponding high-voltage terminal 21 or from being short-circuited with other low-voltage terminals 100a to cause damage to the consumable chip 100 .
  • the consumables chip 100 also includes a memory 104, which can be arranged on the second surface of the substrate 10 for storing relevant information of the ink cartridge, and two detection terminals 22 are connected in series.
  • the resistor R2 and the resistor R3 are connected in parallel to the ground terminal 101c, and the memory 104 is electrically connected to the ground terminal 101c, thereby realizing the electrical connection between the detection terminal 22 and the memory 104.
  • a third notch 13 is provided on the substrate 10, and a conductive layer is arranged in the third notch 13, and the detection contact pin is in contact with the conductive layer in the third notch 13 to realize data communication/electrical communication. connect.
  • the conductive layer is plated on the groove wall of the third notch 13 by means of plating, so that the above-mentioned detection terminal 22 is formed on the substrate 10 .
  • the third notch 13 may be a semicircular groove, a rectangular groove or be arranged in other forms.
  • the groove bottom of the 3rd notch 13 can be plane, also can be curved surface, no matter which kind of form as long as can fix detection contact pin and get final product.
  • the third notch 13 is provided with a conductive layer, and the third notch 13 is used to make electrical contact with the detection contact pin and fix the detection contact pin to prevent the signal detection contact pin from shaking.
  • the substrate 10 is provided with a fourth notch 14, and the third notch 13 is located on the second notch.
  • the notch of the third notch 13 is flush with the side walls of the fourth notch 14 . It can be understood that the arrangement of the fourth notch 14 is beneficial to the drainage of ink, thereby providing further protection against the short circuit between the high voltage terminal 21 and the detection terminal 22 .
  • the first conductive lead 31 includes a third connecting section 311 and a third blocking section 312 , one end of the third connecting section 311 is electrically connected to the first low-voltage terminal 101 , and the third blocking section 312 and the third connecting section 311 connected, and the other end of the third blocking section 312 extends between the high voltage terminal 21 and the detection terminal 22 in the corresponding group, thereby forming the first layer of protection.
  • the second conductive lead 32 includes a fourth connecting segment 321 and a fourth blocking segment 322, one end of the fourth connecting segment 321 is electrically connected to the second low-voltage terminal 102, the fourth blocking segment 322 is connected to the fourth connecting segment 321, and the fourth blocking segment
  • the other end of the section 322 extends to between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group, and is spaced apart from the third blocking section 312, thereby forming a second layer of protection, and the setting of double protection can effectively ensure the high-voltage
  • the division and step-down of the high voltage on the terminal 21 side can better protect the detection terminal 22 .
  • first conductive lead 31 and the second conductive lead 32 located between the high voltage terminal 21 and the detection terminal 22 are arranged at intervals; wherein, the first conductive lead 31 is arranged closer to the detection terminal 22 relative to the second conductive lead 32; or, the second The second conductive lead 32 is arranged closer to the detection terminal 22 relative to the first conductive lead 31 .
  • the third blocking section 312 and the fourth blocking section 322 are arranged at intervals, wherein the third blocking section 312 is arranged closer to the detection terminal 22 relative to the fourth blocking section 322; or, the fourth blocking section 322 Relative to the third barrier section 312, it is arranged close to the detection terminal 22. That is, the third blocking section 312 and the fourth blocking section 322 are arranged in a stacked manner, so that the high voltage on the side of the high voltage terminal 21 can be fully divided and reduced.
  • the number of first conductive leads 31 is at least two; and/or the number of second conductive leads 32 is at least two; wherein, at least two first conductive leads 31 are connected to The same first low voltage terminal 101 is connected to different first low voltage terminals 101 respectively; at least two second conductive leads 32 are connected to the same second low voltage terminal 102 or are connected to different second low voltage terminals 102 respectively.
  • the number of the first conductive lead 31 may also be one, and the number of the second conductive lead 32 may also be one.
  • the quantity of the first conductive lead 31 is two, and the quantity of the second conductive lead 32 can also be one; Two etc. It can be understood that the number of the first conductive wires 31 and the number of the second conductive wires 32 can be selected according to the specific design, and the descriptions in Embodiments 1-12 can be referred to.
  • the high-voltage terminal 21 and the detection terminal 22 are arranged in two groups, and the first conductive lead 31 includes a third connecting section 311 and a third blocking section 312, wherein one end of the third connecting section 311 Electrically connected to the first low-voltage terminal 101, the third barrier segment 312 is connected to the third connection segment 311, and the two ends of the third barrier segment 312 respectively correspond to a group of terminals, and the two ends of the third barrier segment 312 respectively extend to the corresponding group Between the high voltage terminal 21 and the detection terminal 22.
  • the second conductive lead 32 includes a fourth connecting segment 321 and a fourth blocking segment 322, one end of the fourth connecting segment 321 is electrically connected to the second low-voltage terminal 102, the fourth blocking segment 322 is connected to the fourth connecting segment 321, and the fourth blocking segment Both ends of the segment 322 respectively correspond to a group of terminals, and both ends of the fourth blocking segment 322 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • the first low voltage terminal 101 is a data terminal 101d or a power supply terminal 101e
  • the second low voltage terminal 102 is an enable terminal 101a or a clock terminal 101b.
  • the third barrier segment 312 and the fourth barrier segment 322 located between the high-voltage terminal 21 and the detection terminal 22 are arranged at intervals to effectively form a double barrier, and then when the consumable chip 100 is short-circuited , the voltage on the high-voltage terminal 21 is guided to the data terminal 101d or the power terminal 101e by the third blocking section 312, and is respectively guided to the enable terminal 101a or the clock terminal 101b by the fourth blocking section 322 for voltage division, so as to reduce the voltage of the detection terminal 22
  • the accepted voltage signal realizes its protection.
  • the first low-voltage terminal 101 is a power supply terminal 101e
  • the second low-voltage terminal 102 is an enabling terminal 101a.
  • the power terminal 101 e and the enable terminal 101 a are disposed on different regions of the substrate 10 . This can facilitate the wiring of the first conductive lead 31 and the second conductive lead 32, and make the layout of the entire consumable chip 100 compact and reasonable; at the same time, it can effectively reduce the length of the first conductive lead 31 and the second conductive lead 32, saving costs .
  • the third barrier segment 312 and the fourth barrier segment 322 are arranged in parallel and are arranged in a straight line, that is, formed by plating a linear conductive layer on the substrate 10 .
  • the formation shapes of the third barrier section 312 and the fourth barrier section 322 may not be set as a straight line, but may also be set as any shape such as a curve or a broken line according to requirements.
  • the fourth barrier segment 322 and the third barrier segment 312 are stacked in the y direction; wherein, x and y is arranged vertically, and the fourth blocking section 322 is arranged closer to the detection terminal 22 relative to the third blocking section 312 .
  • a T-shape is formed between the third connecting section 311 and the third blocking section 312
  • a T-shape is formed between the fourth connecting section 321 and the fourth blocking section 322 . That is, the first conductive lead 31 is arranged in a T shape, and the second conductive lead 32 is arranged in a T shape. Certainly, in other embodiments, the first conductive lead 31 and the second conductive lead 32 may also be arranged in other shapes, which are not limited here.
  • the number of the first conductive lead 31 is set to one, and the number of the second conductive lead 32 is also set to one.
  • the structure of embodiment 2 is basically the same as that of embodiment 1, and the same parts will not be repeated here.
  • the difference is that the number of first conductive leads 31 is two, and one of the first conductive leads 31 One end of the lead wire 31 is connected to the power terminal 101e, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other first conductive lead 31 is also connected to the power terminal 101e, and the other end extends to Between the high voltage terminal 21 and the detection terminal 22 in another group of terminals.
  • the two first conductive leads 31 are arranged in an L shape, and the number of the second conductive lead 32 is one, and is arranged in a T shape.
  • the structure of embodiment 3 is basically the same as that of embodiment 1, and the same parts will not be repeated here.
  • the difference is that there are two second conductive leads 32, one of which is the second conductive lead
  • One end of the lead wire 32 is connected to the enable terminal 101a, and the other end extends between the high voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other second conductive lead 32 is also connected to the enable terminal 101a, and the other end It extends between the high voltage terminal 21 and the detection terminal 22 in another group of terminals.
  • first conductive lead 31 arranged in a T-shaped structure
  • second conductive lead 32 is arranged in an L-shaped structure.
  • the structure of embodiment 4 is basically the same as that of embodiment 3, and the same parts will not be repeated here.
  • the difference is that the number of second conductive leads 32 is two, and one of the second conductive leads 32 One end of the lead wire 32 is connected to the enable terminal 101a, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other second conductive lead 32 is connected to the clock terminal 101b, and the other end extends to Between the high voltage terminal 21 and the detection terminal 22 in another group of terminals.
  • first conductive lead 31 arranged in a T-shaped structure
  • second conductive lead 32 is arranged in an L-shaped structure.
  • the structure of Embodiment 5 is basically the same as that of Embodiment 1, and the same parts will not be repeated here.
  • the consumable chip 100 also includes a third low-voltage terminal 103
  • the conductive lead 30 also includes a third conductive lead 33; wherein, the first conductive lead 31 includes a third connection segment 311 and a third barrier segment 312, one end of the third connection segment 311 is electrically connected to the first low-voltage terminal 101, and the third barrier segment 312 is connected to the third connection section 311, and the two ends of the third blocking section 312 respectively correspond to a group of terminals, and the two ends of the third blocking section 312 respectively extend to between the high voltage terminal 21 and the detection terminal 22 in each group
  • One end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the third conductive lead 33 is electrically connected to the
  • the third low-voltage terminal 103 includes any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e.
  • the selected terminals among the first low-voltage terminal 101 , the second low-voltage terminal 102 and the third low-voltage terminal 103 do not overlap.
  • the first low voltage terminal 101 , the second low voltage terminal 102 , and the third low voltage terminal 103 are different terminals on the substrate 10 .
  • the first low-voltage terminal 101 is the enable terminal 101a
  • the second low-voltage terminal 102 is the clock terminal 101b
  • the third low-voltage terminal 103 is a terminal other than the enable terminal 101a and the clock terminal 101b, such as the ground terminal 101c, data terminal 101d or power supply terminal 101e.
  • the first low-voltage terminal 101 is a ground terminal 101c
  • the second low-voltage terminal 102 is a power supply terminal 101e
  • the third low-voltage terminal 103 is a terminal other than the ground terminal 101c and the power supply terminal 101e, such as enabling terminal 101a, clock Terminal 101b or data terminal 101d.
  • the third low voltage terminal 103 is a data terminal 101d
  • the first low voltage terminal 101 is a ground terminal 101c
  • the second low voltage terminal 102 is a power terminal 101e. That is, the third connecting section 311 is connected to the ground terminal 101c, and the end of the third blocking section 312 away from the third connecting section 311 respectively extends between the high voltage terminal 21 and the detecting terminal 22 in each group, and the second conductive lead 32
  • One end is electrically connected to the power supply terminal 101e, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one group of terminals.
  • One end of the third conductive lead 33 is electrically connected to the data terminal 101d, and the other end extends to the other group of terminals. Between the high voltage terminal 21 and the detection terminal 22.
  • the fourth barrier segment 322 and the third barrier segment 312 are stacked in the y direction (as shown in FIG. 13 ), where x and y are vertically arranged, and the third barrier segment 312 is opposite to the third barrier segment 312
  • the four blocking sections 322 are disposed close to the detection terminal 22 .
  • the first conductive lead 31 is also arranged close to the detection terminal 22 relative to the third conductive wire 33 .
  • the high voltage on the side of the high-voltage terminal 21 is first divided through the second conductive lead 32 or the third conductive wire 33, and then grounded and lowered through the first conductive lead 31, so that the detection terminal 22 no longer accepts high voltage, that is, the protection of detection terminal 22 is realized.
  • the third connecting section 311 and the third blocking section 312 form a T-shaped structure, that is, the first conductive lead 31 is arranged in a T-shaped structure.
  • the second conductive lead 32 is L-shaped
  • the third conductive lead 33 is also L-shaped
  • the third conductive lead 33 and the second conductive lead 32 are arranged symmetrically with the ground terminal 101c as a symmetrical point.
  • the number of the first conductive lead 31 , the second conductive lead 32 and the third conductive lead 33 is set to one.
  • the number of first conductive leads 31 is two, one end of one first conductive lead 31 is connected to the ground terminal 101c, and the other end extends between the high voltage terminal 21 and the detection terminal 22 in one group of terminals; One end of the first conductive lead 31 is also connected to the ground terminal 101c, and the other end extends between the high voltage terminal 21 and the detection terminal 22 in another group of terminals.
  • the first conductive lead 31 is arranged in an L shape
  • the second conductive lead 32 is arranged in an L shape
  • the third conductive lead 33 is also arranged in an L shape.
  • the structure of embodiment 7 is basically the same as that of embodiment 2, and the same parts will not be repeated here.
  • Both ends of the blocking section 312 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • One end of the third blocking section 312 is connected to the third connecting section 311 , and the third connecting section 311 is connected to the first low-voltage terminal 101 .
  • the fourth blocking section 322 corresponds to a group of terminals.
  • One end of the fourth blocking section 322 is connected to the fourth connecting section 321 , and the other end extends between the high voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals.
  • One end of the fourth blocking section 322 is connected to the fourth connecting section 321 , and the fourth connecting section 321 is connected to the second low voltage terminal 102 . That is, it can be understood that the first conductive lead 31 and the second conductive lead 32 are arranged between one group of terminals, and the first conductive lead 31 is arranged between the other group of terminals.
  • the first low voltage terminal 101 and the second low voltage terminal 102 may be any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, the power supply terminal 101e or the ground terminal 101c.
  • one end of the third connection section 311 is electrically connected to the ground terminal 101c, that is, the first conductive lead 31 is connected to the ground terminal 101c, and the second conductive lead 32 is connected to other terminals except the ground terminal 101c, such as the enabling terminal 101a , clock terminal 101b, data terminal 101d and power supply terminal 101e.
  • the third blocking section 312 is closer to the detection terminal 22 than the fourth blocking section 322 . In this way, in a group of terminals with the first conductive lead 31 and the second conductive lead 32, when a short circuit occurs between the high-voltage terminal 21 and the detection terminal 22, the voltage can be divided first through the first blocking section 322, and then through the blocking section 322.
  • the segment 312 is used to reduce the voltage, so as to achieve double protection; while in the other group of terminals, the blocking segment 312 is used to directly reduce the voltage.
  • the first conductive lead 31 is arranged in a T-shaped structure
  • the second conductive lead 32 is arranged in an L-shaped structure.
  • the structure of embodiment 8 is basically the same as that of embodiment 2, and the same parts will not be repeated here.
  • Both ends of the blocking section 322 respectively extend between the high-voltage terminal 21 and the detection terminal 22 in the corresponding group of terminals, that is, one end of the fourth blocking section 322 is connected to the fourth connecting section 321, and the other end extends to the corresponding terminal in the group of terminals.
  • the fourth connection section 321 is connected to the fifth low voltage terminal 102 .
  • the third blocking section 312 corresponds to a group of terminals, one end of the third blocking section 312 is connected to the third connecting section 311, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one group of terminals, the third connecting section 311 and The first low voltage terminal 101 is connected. That is, it can be understood that the first conductive lead 31 and the second conductive lead 32 are arranged between one group of terminals, and the second conductive lead 32 is arranged in the other group of terminals.
  • the first low voltage terminal 101 and the second low voltage terminal 102 may be any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, the power supply terminal 101e or the ground terminal 101c.
  • the first low-voltage terminal 101 is a power supply terminal 101e; the second low-voltage terminal 102 is an enabling terminal 101a.
  • the first conductive lead 31 is arranged in an L-shaped structure, and the second conductive lead 32 is arranged in a T-shaped structure.
  • the structure of Embodiment 9 is basically the same as that of Embodiment 1, and the same parts will not be repeated here.
  • the consumable chip 100 also includes a third low-voltage terminal 103 and The fourth low-voltage terminal 105
  • the conductive lead 30 also includes a third conductive lead 33 and a fourth conductive lead 34; here, in order to facilitate the description of the relationship between each conductive lead and each low-voltage terminal, the two groups of terminals are respectively defined as the first one group and the second group.
  • one end of the first conductive lead 31 is electrically connected to the first low-voltage terminal 101, and the other end extends between the high-voltage terminal 21 and the detection terminal 22 in the first group; one end of the second conductive lead 32 is electrically connected to the second low-voltage terminal.
  • one end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end extends to the high-voltage terminal 21 and detection terminal 22 in the second group
  • one end of the fourth conductive lead 34 is electrically connected to the fourth low-voltage terminal 105 , and the other end extends to between the high-voltage terminal 21 and the detection terminal 22 in the second group. In this way, double protection is formed between the two groups of terminals respectively.
  • the third low-voltage terminal 103 includes any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power supply terminal 101e;
  • the fourth low-voltage terminal 105 includes the enable terminal 101a, the clock terminal 101b , any one of the ground terminal 101c, the data terminal 101d and the power terminal 101e.
  • the selected terminals among the first low voltage terminal 101 , the second low voltage terminal 102 , the third low voltage terminal 103 and the fourth low voltage terminal 105 do not overlap.
  • the first low voltage terminal 101 , the second low voltage terminal 102 , the third low voltage terminal 103 , and the fourth low voltage terminal 105 are different terminals on the substrate 10 .
  • the first low-voltage terminal 101 is the enabling terminal 101a
  • the second low-voltage terminal 102 is the clock terminal 101b
  • the third low-voltage terminal 103 is the data terminal 101d
  • the fourth low-voltage terminal 105 removes the enabling terminal 101a, the clock terminal 101b and the data terminal 101b.
  • Terminals other than the terminal 101d such as the ground terminal 101c, or the power supply terminal 101e. It can be understood that the selection of the above-mentioned terminals can be selected according to the actual situation, and its simple and reasonable layouts are all included in this application.
  • the first low-voltage terminal 101 is a power supply terminal 101e
  • the second low-voltage terminal 102 is an enable terminal 101a
  • the third low-voltage terminal 103 is a data
  • the fourth low-voltage terminal 105 is the clock terminal 101b.
  • the enable terminal 101a and the clock terminal 101b are located in the same area of the substrate
  • the power supply terminal 101e and the data terminal 101d are also located in the same area of the substrate
  • the first conductive leads 31 and the second conductive leads 32 correspond to the first group
  • the third conductive lead 33 and the fourth conductive lead 34 correspond to the second group.
  • the first conductive lead 31 , the second conductive lead 32 , the third conductive lead 33 and the fourth conductive lead 34 have the same shape, and are all arranged in an L-shaped structure.
  • Embodiment 10 is basically the same as that of Embodiment 7, and the same parts will not be repeated here.
  • the two ends of the consumable chip include a third barrier section 312 respectively corresponding to a group of terminals, And the two ends of the third blocking section 312 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • One end of the third blocking section 312 is connected to the third connecting section 311 , and the third connecting section 311 is connected to the first low-voltage terminal 101 .
  • the fourth blocking section 322 and the fourth connecting section 321 are not provided.
  • the first conductive lead 31 is provided between one group of terminals, and the first conductive lead 31 is also provided between the other group of terminals.
  • the first low-voltage terminal 101 may be any one of the enable terminal 101a, the clock terminal 101b, the data terminal 101d, and the power terminal 101e or the ground terminal 101c.
  • connection section 311 is electrically connected to the ground terminal 101c, that is, the first conductive lead 31 is connected to the ground terminal 101c.
  • the blocking section 312 can be used to reduce the voltage, thereby realizing short circuit protection.
  • the first conductive lead 31 is configured as a T-shaped structure.
  • Embodiment 11 is basically the same as that of Embodiment 10, and the same parts will not be repeated here.
  • the difference is that there are two first conductive leads 31, one of which is the first conductive lead One end of the lead wire 31 is connected to the ground terminal 101c, and the other end extends to between the high voltage terminal 21 and the detection terminal 22 in one group of terminals; one end of the other first conductive lead wire 31 is also connected to the ground terminal 101c, and the other end extends to Between the high voltage terminal 21 and the detection terminal 22 in another group of terminals.
  • the first conductive lead 31 is arranged in an L shape.
  • Embodiment 12 As shown in Figure 20 and Figure 21, the structure of Embodiment 12 is similar to that of Embodiment 10 and Embodiment 11, and the same parts will not be repeated here. The difference lies in the ratio of the area occupied by each terminal on the substrate 10 The terminal area in Embodiment 10 and Embodiment 11 is large, which is beneficial to improve the connection stability between the contact pin on the printer side and the chip terminal.
  • the conductive leads 30 are used in each of the above-mentioned embodiments, the present application is not limited to the specific composition of the conductive structure 3, such as metal leads, and lead structures composed of other materials with conductive functions can be used instead of the conductive leads. 30, such as alloys, conductive rubber, conductive plastics, polymer conductive materials, etc.
  • the present application also provides a method for manufacturing a consumable chip, which is used to prepare the above-mentioned consumable chip.
  • the manufacturing method of the consumable chip includes the following steps: arranging a memory 104 on the substrate 10, at least one low-voltage terminal 100a electrically connected to the memory 104, at least one high-voltage terminal 21, and at least one detection terminal 22, The high-voltage terminal 21 and the detection terminal 22 are arranged at intervals;
  • the conductive structure 3 is arranged on the substrate 10 , one end of the conductive structure 3 is electrically connected to the low-voltage terminal 100 a , and the other end of the conductive structure 3 is extended to between the high-voltage terminal 21 and the detection terminal 22 .
  • the number of high-voltage terminals 21 and detection terminals 22 is two groups, and the method further includes:
  • At least one low-voltage terminal 100a is connected to at least one conductive structure 3 , one end of the conductive structure 3 is electrically connected to the low-voltage terminal 100a , and the other end is extended to between at least one set of high-voltage terminals 21 and detection terminals 22 .
  • the method also includes:
  • At least two conductive structures 3 are arranged between each group of high-voltage terminals 21 and detection terminals 22; or
  • One conductive structure 3 is arranged between one group of high voltage terminals 21 and the detection terminal 22 , and at least two conductive structures 3 are arranged between another group of high voltage terminals 21 and the detection terminal 22 .
  • the method further includes: using metal leads as the conductive structure 3 .
  • the method further includes: setting the conductive structure 3 in a T-shape or an L-shape.
  • the method also includes:
  • a first notch 11 is opened on the side wall of the substrate 10, a conductive layer is arranged in the first notch 11 and a low-voltage terminal 100a is formed; and/or
  • a second notch 12 is opened on the side wall of the substrate 10, a conductive layer is arranged in the second notch 12 and a high voltage terminal 21 is formed; and/or
  • the method also includes:
  • the second slot 12 is set as a right-angle slot, which has a long side wall and a short side wall, and a conductive layer is provided on the long side wall to form a high voltage terminal 21 .
  • the conductive structure 3 includes a connecting section 301 and a blocking section 302, and the method further includes: electrically connecting one end of the connecting section 301 to the low-voltage terminal 100a, and electrically connecting the other end of the connecting section 301 to the blocking section 302 , extending the blocking section 302 to between the high voltage terminal 21 and the detection terminal 22 .
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups;
  • the conductive structure 3 includes a conductive lead 30, and the conductive lead 30 includes a connecting segment 301 and a blocking segment 302; the method further includes:
  • One end of the connecting section 301 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the barrier section 302; the two ends of the barrier section 302 correspond to a group of terminals respectively, and the two ends of the barrier section 302 terminals respectively extend between the high voltage terminals 21 and the detection terminals 22 in the corresponding group.
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups;
  • the conductive structure 3 includes a plurality of conductive leads 30, and the method further includes:
  • One end of at least one conductive lead 30 is electrically connected to at least one low-voltage terminal 100a, and the other end is extended to between a set of high-voltage terminals 21 and the detection terminals 22; one end of at least one conductive lead 30 is connected to at least one low-voltage terminal 100a.
  • the terminal 100 a is electrically connected, and the other end is extended to another group of the high voltage terminal 21 and the detection terminal 22 .
  • the other end extends to a set of conductive leads 30 between the high-voltage terminal 21 and the detection terminal 22, including a first connecting section 303 and a first blocking section 304; the method further includes:
  • One end of the first connecting section 303 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the first blocking section 304; the two ends of the first blocking section 304 correspond to a group of terminals respectively, and the Both ends of the first blocking section 304 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group;
  • the other end extends to another set of conductive leads 30 between the high-voltage terminal 21 and the detection terminal 22, including a second connecting section 305 and a second blocking section 306; the method further includes:
  • One end of the second connecting section 305 is electrically connected to at least one low-voltage terminal 100a, and the other end is connected to the second blocking section 306; the two ends of the second blocking section 306 correspond to a group of terminals respectively, and the Two ends of the second blocking section 306 respectively extend between the high voltage terminal 21 and the detection terminal 22 in the corresponding group.
  • the at least one low-voltage terminal 100a includes a first low-voltage terminal 101 and a second low-voltage terminal 102 arranged at intervals, and the conductive structure 3 includes a first conductive lead 31 and a second conductive lead 32; the method Also includes:
  • first conductive lead 31 is electrically connected to the first low-voltage terminal 101, the other end is extended between the high-voltage terminal 21 and the detection terminal 22, and one end of the second conductive lead 32 is It is electrically connected with the second low-voltage terminal 102 , and the other end is extended to between the high-voltage terminal 21 corresponding to the first conductive lead 31 and the detection terminal 22 .
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups
  • the first conductive lead 31 includes a third connecting section 311 and a third blocking section 312
  • the second conductive lead 32 Including the fourth connecting section 321 and the fourth blocking section 322, the method further includes:
  • Two sets of terminals are arranged on the substrate 10 at intervals, one end of the third connection section 311 is electrically connected to the first low-voltage terminal 101, and the third barrier section 312 is connected to the third connection section 311 connection, electrically connecting one end of the fourth connecting section 321 to the second low-voltage terminal 102, and connecting the fourth blocking section 322 to the fourth connecting section 321;
  • the two ends of the third blocking section 312 respectively correspond to a group of terminals, and the two ends of the third blocking section 312 are respectively extended between the high voltage terminal 21 and the detection terminal 22 in the corresponding group; or,
  • the third blocking section 312 corresponds to a group of terminals, one end of the third blocking section 312 is connected to the third connecting section 311, and the other end is extended to the high voltage terminal 21 and the detection terminal in the corresponding group. Between terminals 22;
  • the two ends of the fourth blocking section 322 respectively correspond to a group of terminals, and the two ends of the fourth blocking section 322 are respectively extended to between the high voltage terminal 21 and the detection terminal 22 in the corresponding group; or,
  • the fourth blocking section 322 corresponds to a group of terminals, one end of the fourth blocking section 322 is connected to the fourth connecting section 321, and the other end is extended to the high voltage terminal 21 and the detection terminal in the corresponding group. between terminals 22.
  • the number of the first conductive leads 31 is at least two; and/or the number of the second conductive leads 32 is at least two; the method further includes:
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups; the consumable chip also includes a third low-voltage terminal 103, and the conductive lead 30 also includes a third conductive lead 33;
  • the first conductive lead 31 includes a third connecting section 311 and a third blocking section 312, and the method further includes:
  • Two sets of terminals are arranged on the substrate 10 at intervals; one end of the third connection section 311 is electrically connected to the first low-voltage terminal 101, and the third barrier section 312 is connected to the third connection section 311 connection, the two ends of the third blocking section 312 are respectively corresponding to a group of terminals, and the two ends of the third blocking section 312 are respectively extended to correspond to the high voltage terminal 21 and the detection terminal in each group Between 22;
  • One end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end is extended to between one group of the high-voltage terminals 21 and the detection terminal 22;
  • One end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103 , and the other end is extended between another group of the high-voltage terminals 21 and the detection terminal 22 .
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups, the consumable chip also includes a third low-voltage terminal 103, the conductive lead 30 also includes a third conductive lead 33, the The quantity of the first conductive lead 31 is two;
  • the method also includes:
  • the two first conductive leads 31 are respectively corresponding to a group of terminals, one end of one of the first conductive leads 31 is connected to the first low-voltage terminal 101, and the other end is extended to one of the corresponding group of terminals. Between the high-voltage terminal 21 and the detection terminal 22; one end of the other first conductive lead 31 is connected to the first low-voltage terminal 101, and the other end is extended to the high-voltage terminal 21 and the detection terminal in a group of terminals corresponding to it. Between terminals 22;
  • One end of the second conductive lead 32 is electrically connected to the second low-voltage terminal 102, and the other end is extended to between one group of the high-voltage terminals 21 and the detection terminal 22;
  • One end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103 , and the other end is extended between another group of the high-voltage terminals 21 and the detection terminal 22 .
  • the number of the high-voltage terminals 21 and the detection terminals 22 is two groups, the consumable chip also includes a third low-voltage terminal 103 and a fourth low-voltage terminal 105, and the conductive lead 30 also includes a third Conductive lead 33 and fourth conductive lead 34;
  • the method also includes:
  • first conductive lead 31 is electrically connected to the first low-voltage terminal 101, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22 in one group of terminals, and the first One end of the two conductive leads 32 is electrically connected to the second low-voltage terminal 102, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22 in the group of terminals corresponding to the first conductive lead 31 between;
  • One end of the third conductive lead 33 is electrically connected to the third low-voltage terminal 103, and the other end is extended to between the high-voltage terminal 21 and the detection terminal 22 in another group of terminals, and the first One end of the four conductive leads 34 is electrically connected to the fourth low-voltage terminal 105, and the other end is extended to the high-voltage terminal 21 and the detection terminal 22 in another group of terminals corresponding to the third conductive lead 33 between.
  • the method further includes: arranging the first conductive lead 31 in a T-shaped structure or an L-shaped structure; and/or, arranging the second conductive lead 32 in a T-shaped structure or an L-shaped structure set up.
  • the method further includes: arranging the first conductive lead 31 and the second conductive lead 32 between the high voltage terminal 21 and the detection terminal 22 at intervals;
  • the first conductive lead 31 is arranged closer to the detection terminal 22 relative to the second conductive lead 32 ; or, the second conductive lead 32 is arranged closer to the detection terminal 22 relative to the first conductive lead 31 .
  • the first low-voltage terminal 101 is any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d, and the power terminal 101e;
  • the second low voltage terminal 102 is any one of the enable terminal 101a, the clock terminal 101b, the ground terminal 101c, the data terminal 101d and the power terminal 101e.
  • the first low voltage terminal 101 is a ground terminal 101c
  • the second low voltage terminal 102 is any one of an enable terminal 101a, a clock terminal 101b, a data terminal 101d and a power terminal 101e.
  • the method further includes: opening a first notch 11 on the substrate 10, and disposing a conductive layer in the first notch 11 to form the ground terminal 101c, the data terminal 101d . At least one of the power terminals 101e;
  • the ground terminal 101c, the data terminal 101d or the power terminal 101e are arranged side by side.
  • the method further includes: opening a second slot 12 on the side wall of the substrate 10, the second slot 12 has a plurality of second slot walls, and placing at least one of the second slots A conductive layer is provided on the groove wall to form the high voltage terminal 21;
  • a third notch 13 is opened on the side wall of the substrate 10 , and a conductive layer is disposed inside the third notch 13 to form the detection terminal 22 .
  • the manufacturing method of the consumable chip in the embodiment of the present application corresponds to the above-mentioned consumable chip, and the technical features and beneficial effects described in the above embodiment of the consumable chip are applicable to the embodiment of the manufacturing method of the consumable chip.
  • the steps of the manufacturing method of the consumable chip can be combined arbitrarily, and there is no sequence.

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Abstract

一种耗材芯片、具有其的耗材盒以及耗材芯片的制作方法。该耗材芯片(100)包括存储器(104)、基板(10)、布设于基板(10)上的至少一与存储器(104)电连接的低压端子(100a)、至少一高压端子(21)以及至少一检测端子(22)，高压端子(21)与检测端子(22)间隔设置，耗材芯片(100)还包括导电结构(3)，导电结构(3)的一端电连接于低压端子(100a)，导电结构(3)的另一端延伸至高压端子(21)与检测端子(22)之间。此耗材芯片通过设置导电结构，实现了短路检测和短路保护，避免耗材芯片、打印设备因高压而损坏。

Description

耗材芯片、具有其的耗材盒以及耗材芯片的制作方法
相关申请
本申请要求2021年7月19日申请的，申请号为202121642369.4，发明名称为“耗材芯片以及具有其的耗材盒”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及打印设备技术领域，特别是涉及一种耗材芯片、具有其的耗材盒以及耗材芯片的制作方法。
背景技术
打印设备需配合耗材盒使用，常见的耗材盒有墨盒，墨盒中安装有墨盒芯片，墨盒芯片用于存储品牌商信息、墨水类型信息、墨水颜色信息以及墨水剂量信息等，墨盒安装于打印设备后，需要经认证后才能正常使用，因此，墨盒芯片对于打印设备是否能正常使用墨盒起着至关重要的作用。
为了与墨盒及墨盒芯片进行连接，打印设备端设置有多个触针，相应地，墨盒芯片对应设置有和多个触针配合接触的多个端子；相关技术中，打印设备端的触针包括高压触针和检测触针，墨盒芯片的端子包括高压端子、检测端子以及信号传输端子，信号传输端子包括多个导电端子，例如电源端子、接地端子以及数据端子等；为了对墨盒是否安装到位进行验证，打印设备通过验证高压端子和高压触针、检测触针和检测端子的接触情况进行安装检测，若打印设备判断到高压端子和高压触针、检测触针和检测端子的接触情况良好，则认定墨盒芯片的信号传输端子与打印设备端的触针也表现为接触良好。
然而，有时高压端子和其邻近的检测端子之间会因墨水滴漏或触针变形等原因造成墨盒芯片短路，从而有可能造成墨盒芯片和打印机设备的损坏，给消费者带来不必要的经济损失和时间损失。
在相关技术中，公开了在打印设备端设置短路检测电路的方案，通过该短路检测电路来检测打印设备端触针的电压变化情况，从而判断墨盒芯片上的端子之间是否发生短路。然而，上述短路检测方案是在墨盒芯片被安装到打印设备端之后进行的，此时尽管短路现象被检测发现，但墨盒芯片上的存储元件可能已经发生短路损坏。另外，市场上存在并未设置短路检测电路的打印设备，对于这样的打印设备而言存在较大的安全隐患。
相关技术中还公开了在墨盒芯片处设置短路检测机制的方案，该方案虽然能够在墨盒芯片处即可独立完成短路现象的检测，但需在墨盒芯片基板上额外设置检测端子及相应的硬件电路，成本较高，较为复杂，且有可能对墨盒芯片与打印设备的正常通信造成潜在可能的干扰。
发明内容
有鉴于此，有必要提供一种能够独立进行短路异常处理，且结构简单、成本较低的耗材芯片、具有其的耗材盒以及耗材芯片的制作方法。
为实现上述目的，本申请提供的技术方案如下：
一种耗材芯片，包括存储器、基板、布设于所述基板上的至少一与所述存储器电连接的低压端子、至少一高压端子以及至少一检测端子，所述高压端子与所述检测端子间隔设置，所述耗材芯片还包括导电结构，所述导电结构的一端电连接于所述低压端子，所述导电结构的另一端延伸至所述高压端子与所述检测端子之间。
可以理解的是，在本申请中，通过设置导电结构，并且导电结构远离低压端子的一端延伸至高压端子和检测端子之间，从而，如果高压端子和检测端子因墨水等发生短路时，高压端子上的高压会通过导电结构引导至相应的低压端子上，从而通过低压端子对高压进行分压和降压，阻止高压端子上的高压加在检测端子上；即，使得检测端子不接收到高压信号，以起到短路检测并短路保护的作用，避免耗材芯片、打印设备因高压而烧坏、损坏。
在其中一个实施例中，所述高压端子与所述检测端子的数量为两组且间隔设置，至少一所述低压端 子连接至少一个导电结构，所述导电结构的一端电连接于所述低压端子，另一端延伸至至少一组所述高压端子与所述检测端子之间。
在其中一个实施例中，每组所述高压端子与所述检测端子之间存在至少两个所述导电结构；或
一组所述高压端子与所述检测端子之间存在一个所述导电结构，另一组所述高压端子与所述检测端子之间存在至少两个所述导电结构。
在其中一个实施例中，所述导电结构为金属引线。
在其中一个实施例中，所述导电结构呈T型或L型。
在其中一个实施例中，所述基板的侧壁上开设有第一槽口，所述第一槽口内设有导电层并形成所述低压端子；和/或
所述基板的侧壁上开设有第二槽口，所述第二槽口内设有导电层并形成所述高压端子；和/或
所述基板的侧壁上设有第三槽口和第四槽口，所述第四槽口沿所述基板的长度方向形成，所述第三槽口设于所述第四槽口的侧壁上，所述第三槽口内设有导电层并形成所述检测端子。
在其中一个实施例中，所述第二槽口为直角槽，其具有长边侧壁和短边侧壁，所述长边侧壁设有导电层并形成所述高压端子。
在其中一个实施例中，所述导电结构包括连接段和阻隔段，所述连接段的一端电连接于所述低压端子，所述连接段的另一端电连接于所述阻隔段，所述阻隔段延伸至所述高压端子与所述检测端子之间。本申请还提供如下技术方案：
一种耗材盒，包括耗材盒本体及如上述耗材芯片，所述耗材芯片设置于所述耗材盒本体上。
一种耗材芯片的制作方法，用于制备上述耗材芯片。
与相关技术相比，所述耗材芯片通过设置导电结构，并且导电结构远离低压端子的一端延伸至高压端子和检测端子之间，从而，如果高压端子和检测端子因墨水等发生短路时，高压端子上的高压会通过导电结构引导至相应的低压端子上，从而通过低压端子对高压进行分压和降压，阻止高压端子上的高压加在检测端子上；即，使得检测端子不接收到高压信号，以起到短路检测并短路保护的作用，避免耗材芯片、打印设备因高压而烧坏、损坏。
附图说明
图1为本申请提供的耗材芯片的结构示意图一；
图2为本申请提供的耗材芯片的结构示意图二；
图3为本申请提供的耗材芯片的结构示意图三；
图4为本申请提供的实施例1耗材芯片的结构示意图一；
图5为本申请提供的耗材芯片的端子与打印设备的触针相接触的示意图；
图6为本申请提供的实施例1耗材芯片沾上墨滴的示意图；
图7为本申请提供的实施例1耗材芯片的结构示意图二；
图8为本申请提供的实施例1耗材芯片的结构示意图三；
图9为本申请提供的两个检测端子与存储器电连接的示意图；
图10为本申请提供的耗材芯片实施例2的结构示意图；
图11为本申请提供的耗材芯片实施例3的结构示意图；
图12为本申请提供的耗材芯片实施例4的结构示意图；
图13为本申请提供的耗材芯片实施例5的结构示意图；
图14为本申请提供的耗材芯片实施例6的结构示意图；
图15为本申请提供的耗材芯片实施例7的结构示意图；
图16为本申请提供的耗材芯片实施例8的结构示意图；
图17为本申请提供的耗材芯片实施例9的结构示意图；
图18为本申请提供的耗材芯片实施例10的结构示意图；
图19为本申请提供的耗材芯片实施例11的结构示意图；
图20为本申请提供的耗材芯片实施例12的结构示意图一；
图21为本申请提供的耗材芯片实施例12的结构示意图二；
图22为本申请提供的耗材芯片的制作方法的流程示意图。
附图标记：100、耗材芯片；10、基板；10a、第一面；11、第一槽口；12、第二槽口；13、第三槽口；14、第四槽口；100a、低压端子；101、第一低压端子；101a、使能端子；101b、时钟端子；101c、接地端子；101d、数据端子；101e、电源端子；102、第二低压端子；103、第三低压端子；104、存储器；105、第四低压端子；21、高压端子；22、检测端子；3、导电结构；30、导电引线；301、连接段；302、阻隔段；303、第一连接段；304、第一阻隔段；305、第二连接段；306、第二阻隔段；31、第一导电引线；311、第三连接段；312、第三阻隔段；32、第二导电引线；321、第四连接段；322、第四阻隔段；33、第三导电引线；34、第四导电引线。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
需要说明的是，当组件被称为“装设于”另一个组件，它可以直接装设在另一个组件上或者也可以存在居中的组件。当一个组件被认为是“设置于”另一个组件，它可以是直接设置在另一个组件上或者可能同时存在居中组件。当一个组件被认为是“固定于”另一个组件，它可以是直接固定在另一个组件上或者可能同时存在居中组件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。本文所使用的术语“或/及”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1-图9所示，本申请提供一种耗材芯片100，该耗材芯片100安装于耗材盒上，用于刻录/记载耗材盒的相关信息以及实现耗材盒与打印设备之间的连接。
耗材芯片100包括存储器104、基板10、布设于基板10上的至少一与存储器104电连接的低压端子100a、至少一高压端子21以及至少一检测端子22，高压端子21与检测端子22间隔设置，耗材芯片100还包括导电结构3，导电结构3的一端电连接于低压端子，导电结构3的另一端延伸至高压端子21与检测端子22之间。
通过设置导电结构3，并且导电结构3远离低压端子100a的一端延伸至高压端子21和检测端子22之间，从而，如果高压端子21和检测端子22因墨水等发生短路时，高压端子21上的高压会通过导电结构3引导至相应的低压端子100a上，从而通过低压端子100a对高压进行分压和降压，阻止高压端子21上的高压加在检测端子22上；即，使得检测端子22不接收到高压信号，以起到短路检测并短路保护的作用，避免耗材芯片、打印设备因高压而烧坏、损坏。
进一步的，高压端子21与检测端子22的数量为两组且间隔设置，至少一低压端子100a连接至少一个导电结构3，导电结构3的一端电连接于低压端子100a，另一端延伸至至少一组高压端子21与检测端子22之间。
需要说明的是，一个低压端子100a可连接多个导电结构3，一个导电结构3可连接多个低压端子，导电结构3的另一端可延伸至一组高压端子21与检测端子22之间，也可分别延伸至两组高压端子21与检测端子22之间。
在一些实施例中，导电结构3包括连接段301和阻隔段302，连接段301的一端电连接于低压端子100a，连接段301的另一端电连接于阻隔段302，阻隔段302延伸至高压端子21与检测端子22之间。
需要说明的是，阻隔段302可延伸至任意一组高压端子21与检测端子22之间，也可分别延伸至两组高压端子21与检测端子22之间。
进一步的，如图2所示，高压端子21与检测端子22的数量为两组，且两组端子间隔地设于基板10上；
导电结构3包括导电引线30，导电引线30包括连接段301和阻隔段302；连接段301的一端电连 接至少一低压端子100a，另一端与阻隔段302连接；阻隔段302的两端分别对应一组端子，并且阻隔段302的两端分别延伸至对应组中的高压端子21和检测端子22之间。
在本实施例中，两组高压端子21与检测端子22之间，均可通过导电引线30的阻隔段302和连接段301连接到同一低压端子100a。
进一步的，如图3所示，高压端子21与检测端子22的数量为两组，且两组端子间隔地设于基板10上；
导电结构3包括多个导电引线30，至少一个导电引线30的一端电连接至少一低压端子100a，另一端延伸至一组高压端子21和检测端子22之间；至少一个导电引线30的一端电连接至少一低压端子100a，另一端延伸至另一组高压端子21和检测端子22之间。
在本实施例中，导电结构包括多个导电引线30，任意一组高压端子21和检测端子22之间有至少一个导电引线30连接至少一低压端子100a，两组高压端子21和检测端子22之间的导线引线30可连接到同一低压端子100a，或不同的低压端子100a。
在一些实施例中，每组高压端子21与检测端子22之间存在至少两个导电结构3；或
一组高压端子21与检测端子22之间存在一个导电结构3，另一组高压端子21与检测端子之间存在至少两个导电结构3。
进一步的，如图3所示，另一端延伸至一组高压端子21和检测端子22之间的导电引线30包括第一连接段303和第一阻隔段304；第一连接段303的一端电连接至少一低压端子100a，另一端与第一阻隔段304连接；第一阻隔段304的两端分别对应一组端子，并且第一阻隔段304的两端分别延伸至对应组中的高压端子21和检测端子22之间；
和/或，
另一端延伸至另一组高压端子21和检测端子22之间的导电引线30包括第二连接段305和第二阻隔段306；第二连接段305的一端电连接至少一低压端子100a，另一端与第二阻隔段306连接；第二阻隔段306的两端分别对应一组端子，并且第二阻隔段306的两端分别延伸至对应组中的高压端子21和检测端子22之间。
在本实施例中，任意一导电引线30可同时延伸至对应组中的高压端子21和检测端子22之间。
具体地，如图4所示，低压端子100a包括间隔设置的第一低压端子101和第二低压端子102，导电结构3包括第一导电引线31和第二导电引线32，第一导电引线31的一端电连接第一低压端子101，另一端延伸至高压端子21和检测端子22之间，第二导电引线32的一端电连接第二低压端子102，另一端延伸至与第一导电引线31相对应的高压端子21和检测端子22之间。
当耗材盒安装于打印设备上(如图5所示)时，打印设备内部安装检测部会向高压端子21施加高电压(约为40V)，从而检测传输至安装检测部输出端的电压或电流值来检测高压端子21是否与打印设备上对应的触针电接触，进而确定耗材盒是否正确安装在打印设备上。
需要解释的是，相关技术中，由于有时候墨水等导电物质会溅射至基板10上并覆盖高压端子21和检测端子22，造成高压端子21与检测端子22连通而发生短路，导致耗材芯片100和/或打印设备损坏。在打印设备和耗材芯片100连通后，打印设备利用内部电路对耗材芯片100的状态进行检测，例如，安装状态和墨量状态；打印设备通常向其中一个高压端子21输入约40V的电压，并经另一个高压端子21输出，其中另一个高压端子21输出的电压通常大于3.2V小于40V。同时，打印设备通常向两个检测端子22中的其中一个发送不高于3.2V或者不高于5V的电压，另一个检测端子22输出不高于3.2V或不高于5V的电压，故而，两个高压端子21接收到的电压均高于检测端子22接收到的电压，且由于二者的电压差过大，若二者之间因发生短路造成高压错误地施加在低压的检测端子22上，则有可能导致耗材芯片100在检测端子22触发短路保护功能之前发生损坏。
因此，基于上述出现的问题，本申请提供的一种新型的耗材芯片100，其通过设置第一导电引线31以及第二导电引线32，并且第一导电引线31、第二导电引线32分别远离第一低压端子101和第二低压端子102的一端分别延伸至高压端子21和检测端子22之间。从而，如果高压端子21和检测端子22因墨水等导电物质等发生短路时，高压端子21上的高压会通过第一导电引线31、第二导电引线32引导至相应的第一低压端子101和第二低压端子102上，从而通过第一低压端子101、第二低压端子102 对高压进行分压和降压，阻止高压端子21上的高压加在检测端子22上；即，使得检测端子22不接收到高压信号，以起到短路检测并短路保护的作用，避免耗材芯片100、打印设备因高压而烧坏、损坏。
具体原理如下：如图6所示，若墨滴要致使高压端子21和检测端子22之间出现短路，则墨滴一定会覆盖延伸至高压端子21和检测端子22之间的导电引线，从而引发与该导电引线电连接的低压端子100a先于检测端子22触发短路保护机制。
当高压通过导电引线被引导至低压端子100a之后，墨盒芯片会触发打印设备进行“要求关闭电源”或“墨盒安装异常”等报错提示，从而使得打印设备无法进行打印，促使用户对墨盒进行检查或更换。
具体地，当高压输入端子和使能端子发生短路时，高压输入端子和高压输出端子的电压会同时被使能端子拉低，此时打印设备会提示“要求关闭电源”等报错提示。
当高压输入端子和电源端子发生短路时，高压输入端子和高压输出端子的电压会同时被电源端子拉低，此时打印设备会提示“要求关闭电源”等报错提示。
当高压输入端子和电源端子、接地端子发生短路时，高压输入端子和高压输出端子的电压会同时被拉低，此时打印设备会提示“要求关闭电源”等报错提示。
当高压输出端子与时钟端子发生短路时，高压输出端子的电压会被时钟端子拉低，同时高压输入端子还是会正常向高压输出端子发送装机检测信号，此时打印设备无法通过高压输出端子获取正常的装机检测信号，此时打印设备会提示“墨盒安装异常”等报错提示。
当高压输出端子与数据端子发生短路时，高压输出端子的电压会被数据端子拉低，同时高压输入端子还是会正常向高压输出端子发送装机检测信号，此时打印设备无法通过高压输出端子获取正常的装机检测信号，此时打印设备会提示“墨盒安装异常”等报错提示。
当高压输出端子与数据端子、接地端子发生短路时，高压输出端子的电压会被拉低，同时高压输入端子还是会正常向高压输出端子发送装机检测信号，此时打印设备无法通过高压输出端子获取正常的装机检测信号，此时打印设备会提示“墨盒安装异常”等报错提示。
作为可选地，基板10包括相背设置的第一面10a和第二面(图未示)，第一低压端子101、第二低压端子102、导电引线30以及高压端子21和检测端子22均布设在第一面10a上，存储器104布设在第二面。
需要解释的是，高压可以大于耗材芯片100的工作电压即施加在芯片端子上的电压。通常，耗材芯片100的工作电压多为3.3V或者5V，相应的，所述高压可以是高于3.3V或者高于5V的电压，低压可以是低于3.3V或者低于5V的电压。
在一些实施例中，基板10的侧壁上开设有第一槽口11，第一槽口11内设有导电层并形成低压端子100a；和/或
基板10的侧壁上开设有第二槽口12，第二槽口12内设有导电层并形成高压端子21；和/或
基板10的侧壁上设有第三槽口13和第四槽口14，第四槽口14沿基板10的长度方向(即图8中的x轴方向)形成，第三槽口13设于第四槽口14的侧壁上，第三槽口13内设有导电层并形成检测端子22。
如图4所示，第一低压端子101可以是使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种。第二低压端子102也可以是使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种。在本实施例中，第一低压端子101为电源端子101e，第二低压端子102为使能端子101a。
进一步地，第一低压端子101和/或第二低压端子102可以通过在基板10上设置导电层形成。第一低压端子101和/或第二低压端子102为实心端子，且形状可以设置为腰型孔形状、椭圆形、半圆形或者矩形等任意形状。在这里，导电层为具有导电性能的材料制成，如银层、铜层、铜合金层等。
可选地，第一低压端子101和/或第二低压端子102可以直接在基板10上镀设导电层形成，也可以通过在基板10上开设第一槽口11(如图7所示)，并在第一槽口11内设置导电层形成。
作为可选地，第一槽口11的槽口与基板10的下侧面齐平设置。可选地，第一槽口11的形状设置为矩形、椭圆形或者半圆形等形状。在本实施例中，第一槽口11的形状可选为矩形。
进一步地，第一低压端子101和第二低压端子102之间选用的端子不重合。换而言之，若第一低压 端子101为使能端子101a，那么第二低压端子102为除去使能端子101a之外的端子，如时钟端子101b、接地端子101c、数据端子101d或者电源端子101e；若第一低压端子101为数据端子101d，那么第二低压端子102为除去数据端子101d之外的端子，如使能端子101a、时钟端子101b、接地端子101c、或者电源端子101e，以此类设。可以理解的是，通过上述设置，可以使得第一导电引线31和第二导电引线32可以分别连接不同的端子，从而提高降压/分压的效果。
作为可选地，基板10上分别设有使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e，且使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e以阵列的方式布设。其中，检测端子22通过连接电阻后与接地端子101c连接，从而检测端子22通过接地端子101c进行接地设置，以通过接地端子101c释放检测端子22上的一些异常的较大电流，从而保护耗材芯片100因大电流而被烧毁。数据端子101d用于和外部打印设备进行数据传输，电源端子101e用于为耗材芯片100供电。
在本实施例中，如图4所示，使能端子101a、时钟端子101b并排设置；接地端子101c、数据端子101d以及电源端子101e并排设置。当然，在其他实施例中，使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e的排布方式，可以根据实际耗材芯片100的设计整体进行布局，在此不再赘述，其相同或者相类似的布局方式均属于本实施例的有限组合。
如图4所示，使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e均可以由涂覆在基板10上的导电层形成。其中使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e的形状不作限制，可以是腰型孔形状、圆形、半圆形、椭圆形或者矩形等。
在一实施例中，作为举例，使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e均设置为腰型孔形状。在另一实施例中，如图7所示，使能端子101a和时钟端子101b设置为腰型孔形状，而接地端子101c、数据端子101d或者电源端子101e中的至少之一可以由基板10上开设有第一槽口11，并在基板10上开设有第一槽口11内设置导电层形成。
如图4所示，在本实施例中，高压端子21和检测端子22的数量为两组，两组端子间隔地布设于基板10上，且两组端子中的高压端子21之间电连接，从而两个高压端子21分别与对应于打印设备侧高压触针抵接形成一个检测回路，使得打印设备能够实现对高压端子21的安装检测。两组端子中的检测端子22之间电连接，从而两个检测端子22分别与对应于打印设备侧的检测触针抵接形成一个检测回路，使得打印设备能够实现检测端子22的安装检测。
作为可选地，两个高压端子21之间设置有电阻R1或者传感器，电阻R1用于安装检测，即打印设备上的安装检测部根据检测流过电阻R1的相应电流值或电压值来判定高压端子21与打印设备对应触针的安装状态。传感器的设置可以检测耗材盒的墨量。
进一步地，如图7所示，基板10上开设有第二槽口12，第二槽口12具有多个侧壁，至少其中一个侧壁上镀设有导电层以在基板10上形成高压端子21。当然，在其他实施例中，高压端子21也可以直接在基板10上镀设导电层直接形成。
作为可选地，第二槽口12为直角槽，即设置为矩形状，高压触针与直角槽的长边侧壁接触，实现打印设备与耗材芯片100连通；其中，直角槽具有长边侧壁和短边侧壁，长边侧壁设有导电层并形成高压端子21，直角槽可为长边侧壁镀铜，短边侧壁不镀铜，短边侧壁只起限位作用，有效限制了高压触针的移动，避免高压触针与对应高压端子21接触不良或避免高压触针与其他低压端子100a短接造成耗材芯片100毁坏。
作为可选地，如图9所示，耗材芯片100还包括存储器104，存储器104可以设置于基板10的第二面上，用于存储墨盒的相关信息，两个检测端子22之间串联两个电阻R2，再并联电阻R3后与接地端子101c连接，存储器104与接地端子101c电连接，进而实现检测端子22与存储器104电连接。
进一步地，如图8所示，基板10上开设有第三槽口13，第三槽口13内设有导电层，检测触针与第三槽口13内的导电层接触实现数据通信/电连接。
作为可选地，导电层通过镀设的方式镀设于第三槽口13的槽壁上，从而，在基板10上形成上述检测端子22。
可选地，第三槽口13可以为半圆形凹槽、矩形槽或者设置成其他形式。第三槽口13的槽底可以呈 平面，也可以呈曲面，不管哪种形式只要能够固定检测触针即可。第三槽口13设有导电层，第三槽口13用于和检测触针电接触并固定检测触针，防止信号检测触针晃动。
作为可选地，如图8所示，沿着所述基板10的长度方向(即如图8中的x方向)，基板10上开设有第四槽口14，第三槽口13设于第四槽口14的侧壁上，且第三槽口13的槽口与所述第四槽口14的侧壁齐平设置。可以理解的是，第四槽口14的设置，有利于墨水的引流，从而对高压端子21与检测端子22之间的短路提供进一步的保护。
如图4所示，第一导电引线31包括第三连接段311和第三阻隔段312，第三连接段311的一端电连接第一低压端子101，第三阻隔段312与第三连接段311连接，且第三阻隔段312的另一端延伸至对应组中的高压端子21和检测端子22之间，从而形成第一重防护。第二导电引线32包括第四连接段321和第四阻隔段322，第四连接段321的一端电连接第二低压端子102，第四阻隔段322与第四连接段321连接，且第四阻隔段322的另一端延伸至对应组中的高压端子21和检测端子22之间，并与第三阻隔段312之间间隔设置，从而形成第二重防护，而双重防护的设置，可以有效保证高压端子21侧的高电压的分压以及降压，能够更好地实现对检测端子22的保护。进一步地，位于高压端子21和检测端子22之间的第一导电引线31和第二导电引线32间隔设置；其中，第一导电引线31相对第二导电引线32靠近检测端子22设置；或者，第二导电引线32相对第一导电引线31靠近检测端子22设置。换而言之，作为可选地，第三阻隔段312和第四阻隔段322是间隔设置，其中第三阻隔段312相对第四阻隔段322靠近检测端子22设置；或者，第四阻隔段322相对第三阻隔段312靠近检测端子22设置。即，第三阻隔段312和第四阻隔段322以堆叠方式排布，如此可以充分实现对高压端子21侧的高电压进行分压、降压。
作为可选地，在一实施例中，第一导电引线31的数量至少为两条；和/或第二导电引线32的数量至少为两条；其中，至少两条第一导电引线31连接于同一个第一低压端子101，或者分别连接于不同的第一低压端子101；至少两条第二导电引线32连接于同一个第二低压端子102，或者分别连接于不同的第二低压端子102。当然，在另一实施例中，第一导电引线31的数量也可以为一条，第二导电引线32的数量也可以为一条。又或者，第一导电引线31的数量为两条，第二导电引线32的数量也可以为一条；还可以是，第一导电引线31的数量为一条，第二导电引线32的数量也可以为两条等。可以理解的是，第一导电引线31以及第二导电引线32的数量可以根据具体设计进行选择，并且可以参考实施例1-12中的描述。
实施例1
如图4、图7、图8所示，高压端子21和检测端子22设置为两组，第一导电引线31包括第三连接段311和第三阻隔段312，其中第三连接段311的一端电连接第一低压端子101，第三阻隔段312与第三连接段311连接，且第三阻隔段312的两端分别对应一组端子，并且第三阻隔段312的两端分别延伸至对应组中的高压端子21和检测端子22之间。第二导电引线32包括第四连接段321和第四阻隔段322，第四连接段321的一端电连接第二低压端子102，第四阻隔段322与第四连接段321连接，且第四阻隔段322的两端分别对应一组端子，并且第四阻隔段322的两端分别延伸至对应组中的高压端子21和检测端子22之间。
可选地，第一低压端子101为数据端子101d或者电源端子101e，第二低压端子102为使能端子101a或时钟端子101b。并且，在一组端子中，位于高压端子21和检测端子22之间的第三阻隔段312和第四阻隔段322之间间隔设置，以有效地形成双重阻隔，进而当耗材芯片100发生短路时，高压端子21上的电压被第三阻隔段312引导至数据端子101d或者电源端子101e，以及被第四阻隔段322分别引导至使能端子101a或时钟端子101b进行分压，以降低检测端子22所接受的电压信号，实现其保护。
作为可选地，第一低压端子101为电源端子101e，第二低压端子102为使能端子101a。可以理解的是，电源端子101e与使能端子101a设于基板10的不同区域。这样可以便于第一导电引线31和第二导电引线32的布线，并使得整个耗材芯片100的布局紧凑、合理；同时，能够有效减少第一导电引线31和第二导电引线32使用长度，节约成本。
进一步地，在本实施例中，第三阻隔段312和第四阻隔段322之间平行设置，且均呈直线段设置，即通过在基板10上镀设直线状的导电层形成。当然，第三阻隔段312和第四阻隔段322的形成形状也 可以不设置为直线形，其还可根据需求设置为曲线、折线等任意形状。
进一步地，在本实施例中，沿着基板10的宽度方向(即如图8中的y方向)，第四阻隔段322和第三阻隔段312在y方向呈堆叠方式设置；其中，x与y垂直设置，第四阻隔段322相对第三阻隔段312靠近检测端子22设置。
可选地，第三连接段311和第三阻隔段312之间形成T形，第四连接段321和第四阻隔段322之间形成T形。即，第一导电引线31设置为T形，第二导电引线32设置为T形。当然，在其他实施例中，第一导电引线31以及第二导电引线32还可以设置成其他形状，在此不作限定。
并且，在本实施例中，第一导电引线31的数量设置为一条，第二导电引线32的数量也设置为一条。
实施例2
如图10所示，实施例2与实施例1的结构基本相同，其相同部分在此不再赘述，其不同之处在于：第一导电引线31的数量为两个，其中一根第一导电引线31的一端连接电源端子101e，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；其中另一根第一导电引线31的一端也连接电源端子101e，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
作为可选地，在本实施例中，两根第一导电引线31均设置成L形，第二导电引线32的数量为一条，且设置成T型。
实施例3
如图11所示，实施例3与实施例1的结构基本相同，其相同部分在此不再赘述，其不同之处在于：第二导电引线32的数量为两根，其中一根第二导电引线32的一端连接使能端子101a，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；其中另一根第二导电引线32的一端也连接使能端子101a，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
作为可选地，在本实施例中，第一导电引线31的数量为一条，且设置成T型结构，第二导电引线32设置成L型。
实施例4
如图12所示，实施例4与实施例3的结构基本相同，其相同部分在此不再赘述，其不同之处在于：第二导电引线32的数量为两根，其中一根第二导电引线32的一端连接使能端子101a，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；其中另一根第二导电引线32的一端连接时钟端子101b，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
作为可选地，在本实施例中，第一导电引线31的数量为一条，且设置成T型结构，第二导电引线32设置成L型。
实施例5
如图13所示，实施例5与实施例1的结构基本相同，其相同部分在此不再赘述，其不同之处在于：在本实施例中，耗材芯片100还包括第三低压端子103，导电引线30还包括第三导电引线33；其中，第一导电引线31包括第三连接段311和第三阻隔段312，第三连接段311的一端电连接第一低压端子101，第三阻隔段312与第三连接段311连接，且第三阻隔段312的两端分别对应一组端子，并且第三阻隔段312的两端分别延伸至对应每组中的高压端子21和检测端子22之间；第二导电引线32的一端电连接第二低压端子102，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；第三导电引线33的一端电连接第三低压端子103，另一端延伸至其中另一组端子中的高压端子21和检测端子22之间。
可选地，第三低压端子103包括使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种。
进一步地，第一低压端子101、第二低压端子102、第三低压端子103之间选用的端子不重合。换而言之，第一低压端子101、第二低压端子102、第三低压端子103分别为基板10上的不同端子。例如，第一低压端子101为使能端子101a，第二低压端子102为时钟端子101b，那么第三低压端子103为除去使能端子101a、时钟端子101b之外的端子，如接地端子101c、数据端子101d或者电源端子101e。再如，第一低压端子101为接地端子101c，第二低压端子102为电源端子101e，那么第三低压端子103为除去接地端子101c、电源端子101e之外的端子，如使能端子101a、时钟端子101b或者数据端子101d。 以上为2种举例，其他类型情况在此就不再一一举例，其不同的变化，依然属于申请范围之中。
具体地，在一实施例中，继续参考图13，第三低压端子103为数据端子101d，第一低压端子101为接地端子101c，第二低压端子102电源端子101e。即，第三连接段311与接地端子101c连接，第三阻隔段312远离第三连接段311的一端分别延伸至对应每组中的高压端子21和检测端子22之间，第二导电引线32的一端电连接电源端子101e，另一端延伸至其中一组端子中的高压端子21和检测端子22之间，第三导电引线33的一端电连接数据端子101d，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
进一步地，在本实施例中，第四阻隔段322和第三阻隔段312在y方向(如图13所示)呈堆叠方式设置，其中，x与y垂直设置，第三阻隔段312相对第四阻隔段322靠近检测端子22设置。同时，第一导电引线31相对第三导电线33也靠近检测端子22设置。这样，当耗材芯片100出现短路时，高压端子21侧的高电压首先通过第二导电引线32或者第三导电线33进行分压，然后再通过第一导电引线31进行接地降压，使得检测端子22不再接受高电压，即实现检测端子22的保护。
作为可选地，如图13所示，第三连接段311和第三阻隔段312组成T型结构，即第一导电引线31设置为T型。第二导电引线32设置为L型，第三导电引线33也设置为L型，且第三导电引线33与第二导电引线32以接地端子101c为对称点对称设置。
在本实施例中，第一导电引线31、第二导电引线32以及第三导电引线33的数量均设置为一条。
实施例6
如图14所示，实施例6与实施例5的结构基本相同，其相同部分在此不再赘述，其不同之处在于：
第一导电引线31的数量为两根，其中一根第一导电引线31的一端连接地端子101c，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；其中另一根第一导电引线31的一端也连接地端子101c，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
其中，第一导电引线31设置为L型，第二导电引线32设置为L型，第三导电引线33也设置为L型。
实施例7
如图15所示，实施例7与实施例2的结构基本相同，其相同部分在此不再赘述，其不同之处在于：第三阻隔段312的两端分别对应一组端子，且第三阻隔段312的两端分别延伸至对应组中的高压端子21和检测端子22之间。第三阻隔段312的一端与第三连接段311连接，而第三连接段311与第一低压端子101连接。第四阻隔段322对应一组端子，第四阻隔段322的一端连接第四连接段321，另一端延伸至对应一组端子中的高压端子21和检测端子22之间。第四阻隔段322的一端与第四连接段321连接，而第四连接段321与第二低压端子102连接。即可以理解的是，其中一组端子之间设有第一导电引线31和第二导电引线32，另一组端子之间设置有第一导电引线31。在这里，第一低压端子101和第二低压端子102可以是使能端子101a、时钟端子101b、数据端子101d以及电源端子101e或者接地端子101c的任意一个。
作为可选地，第三连接段311的一端电连接接地端子101c，即第一导电引线31与接地端子101c连接，第二导电引线32连接除接地端子101c以外的其他端子，如使能端子101a、时钟端子101b、数据端子101d以及电源端子101e。同时，第三阻隔段312相对第四阻隔段322更加靠近检测端子22。这样，在一组具有第一导电引线31和第二导电引线32的端子中，当高压端子21与检测端子22之间发生短路时，首先可以通过第一阻隔段322进行分压，再经过阻隔段312进行降压，从而实现双重保护；而在另一组端子中，直接通过阻隔段312进行降压。
作为可选地，第一导电引线31设置为T型结构，第二导电引线32设置为L型结构。
实施例8
如图16所示，实施例8与实施例2的结构基本相同，其相同部分在此不再赘述，其不同之处在于：第四阻隔段322的两端分别对应一组端子，且第四阻隔段322的两端分别延伸至对应一组端子中的高压端子21和检测端子22之间，即第四阻隔段322的一端连接第四连接段321，另一端延伸至对应一组端子中的高压端子21和检测端子22之间，而第四连接段321与第五低压端子102连接。第三阻隔段312对应一组端子，第三阻隔段312的一端连接第三连接段311，另一端延伸至其中一组端子中的高压端子 21和检测端子22之间，第三连接段311与第一低压端子101连接。即可以理解的是，其中一组端子之间均设有第一导电引线31和第二导电引线32，另一组端子中设置有第二导电引线32。在这里，第一低压端子101和第二低压端子102可以是使能端子101a、时钟端子101b、数据端子101d以及电源端子101e或者接地端子101c的任意一个。
在本实施例中，第一低压端子101为电源端子101e；第二低压端子102为使能端子101a。第一导电引线31设置为L型结构，第二导电引线32设置为T型结构。
实施例9
如图17所示，实施例9与实施例1的结构基本相同，其相同部分在此不再赘述，其不同之处在于：在本实施例中，耗材芯片100还包括第三低压端子103以及第四低压端子105，导电引线30还包括第三导电引线33以及第四导电引线34；在这里为了便于阐述各条导电引线与各个低压端子之间的关系，从而将两组端子分别定义为第一组以及第二组。
具体地，第一导电引线31的一端电连接第一低压端子101，另一端延伸至第一组中的高压端子21和检测端子22之间；第二导电引线32的一端电连接第二低压端子102，另一端延伸至第一组中的高压端子21和检测端子22之间；第三导电引线33的一端电连接第三低压端子103，另一端延伸至第二组中的高压端子21和检测端子22之间；第四导电引线34的一端电连接第四低压端子105，另一端延伸至第二组中的高压端子21和检测端子22之间。这样，分别在两组端子之间形成了双重保护。
可选地，第三低压端子103包括使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种；第四低压端子105包括使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种。
进一步地，第一低压端子101、第二低压端子102、第三低压端子103以及第四低压端子105之间选用的端子不重合。换而言之，第一低压端子101、第二低压端子102、第三低压端子103、第四低压端子105分别为基板10上的不同端子。例如，第一低压端子101为使能端子101a，第二低压端子102为时钟端子101b，第三低压端子103为数据端子101d，那么第四低压端子105除去使能端子101a、时钟端子101b以及数据端子101d之外的端子，如接地端子101c、或者电源端子101e。可以理解的是，上述端子选用，可以根据实际情况进选择，其简单合理的布局均包含在本申请中。
具体地，如图17所示，为了布局的紧凑以及合理性，本实施例中，第一低压端子101为电源端子101e，第二低压端子102为使能端子101a，第三低压端子103为数据端子101d，第四低压端子105为时钟端子101b。如此，因为使能端子101a和时钟端子101b位于基板的同一区域，电源端子101e和数据端子101d也是位于基板的同一区域，并且第一导电引线31和第二导电引线32对应的是第一组，第三导电引线33和第四导电引线34对应的是第二组，通过上述的排布，不仅使得导电引线的延伸路径最短和最佳，且布局也更加紧凑和合理。
作为可选地，在本实施例中，第一导电引线31、第二导电引线32、第三导电引线33以及第四导电引线34的形状一致，均设置成L型结构。
实施例10
如图18所示，实施例10与实施例7的结构基本相同，其相同部分在此不再赘述，其不同之处在于：耗材芯片包括第三阻隔段312的两端分别对应一组端子，且第三阻隔段312的两端分别延伸至对应组中的高压端子21和检测端子22之间。第三阻隔段312的一端与第三连接段311连接，而第三连接段311与第一低压端子101连接。第四阻隔段322和第四连接段321未设置。即可以理解的是，一组端子之间设有第一导电引线31，另一组端子之间也设置有第一导电引线31。在这里，第一低压端子101可以是使能端子101a、时钟端子101b、数据端子101d以及电源端子101e或者接地端子101c的任意一个。
作为可选地，连接段311的一端电连接接地端子101c，即第一导电引线31与接地端子101c连接。这样，在一组具有第一导电引线31的端子中，当高压端子21与检测端子22之间发生短路时，可以通过阻隔段312进行降压，从而实现短路保护。
作为可选地，第一导电引线31设置为T型结构。
实施例11
如图19所示，实施例11与实施例10的结构基本相同，其相同部分在此不再赘述，其不同之处在 于：第一导电引线31的数量为两根，其中一根第一导电引线31的一端连接地端子101c，另一端延伸至其中一组端子中的高压端子21和检测端子22之间；其中另一根第一导电引线31的一端也连接地端子101c，另一端延伸至另一组端子中的高压端子21和检测端子22之间。
其中，第一导电引线31设置为L型。
实施例12
如图20和图21所示，实施例12与实施例10、实施例11的结构相似，其相同部分在此不再赘述，其不同之处在于：各个端子在基板10上所占的面积比实施例10、实施例11中的端子面积大，有利于提升打印机侧触针与芯片端子之间的连接稳定性。
需要说明的是，虽然上述各个实施例中均使用导电引线30，但本申请并不限定到导电结构3的具体构成，如金属引线，可以使用具备导电功能的其他材料组成的引线结构替代导电引线30，如合金、导电橡胶、导电塑料、高分子导电材料等。
本申请还提供一种耗材芯片的制作方法，用于制备上述耗材芯片。
如图22所示，所述耗材芯片的制作方法，包括以下步骤：在基板10上布设存储器104、至少一与存储器104电连接的低压端子100a、至少一高压端子21以及至少一检测端子22，高压端子21与检测端子22间隔设置；
在基板10上布设导电结构3，将导电结构3的一端电连接于低压端子100a，将导电结构3的另一端延伸至高压端子21与检测端子22之间。
在一个实施例中，高压端子21与检测端子22的数量为两组，所述方法还包括：
将两组端子间隔地设于基板10上；
将至少一低压端子100a连接至少一个导电结构3，将导电结构3的一端与低压端子100a与电连接，将另一端延伸至至少一组高压端子21与检测端子22之间。
在一个实施例中，所述方法还包括：
在每组高压端子21与检测端子22之间设置至少两个导电结构3；或
在一组高压端子21与检测端子22之间设置一个导电结构3，在另一组高压端子21与检测端子22之间设置至少两个导电结构3。
在一个实施例中，所述方法还包括：采用金属引线作为导电结构3。
在一个实施例中，所述方法还包括：将导电结构3设置为T型或L型。
在一个实施例中，所述方法还包括：
在基板10的侧壁上开设第一槽口11，在第一槽口11内设置导电层并形成低压端子100a；和/或
在基板10的侧壁上开设第二槽口12，在第二槽口12内设置导电层并形成高压端子21；和/或
在基板10的侧壁上开设第三槽口13和第四槽口14，沿基板10的长度方向形成第四槽口14，将第三槽口13设于第四槽口14的侧壁上，在第三槽口13内设置导电层并形成检测端子22。
在一个实施例中，所述方法还包括：
将第二槽口12设为直角槽，其具有长边侧壁和短边侧壁，在所述长边侧壁设置导电层并形成高压端子21。
在一个实施例中，导电结构3包括连接段301和阻隔段302，所述方法还包括：将连接段301的一端与低压端子100a电连接，将连接段301的另一端与阻隔段302电连接，将阻隔段302延伸至高压端子21与检测端子22之间。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组；
所述导电结构3包括导电引线30，所述导电引线30包括连接段301和阻隔段302；所述方法还包括：
将两组端子间隔地设于所述基板10上；
将所述连接段301的一端与至少一低压端子100a电连接，将另一端与所述阻隔段302连接；所述阻隔段302的两端分别对应一组端子，将所述阻隔段302的两端分别延伸至对应组中的所述高压端子21和所述检测端子22之间。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组；
所述导电结构3包括多个导电引线30，所述方法还包括：
将两组端子间隔地设于所述基板10上；
将至少一个导电引线30的一端与至少一低压端子100a电连接，将另一端延伸至一组所述高压端子21和所述检测端子22之间；将至少一个导电引线30的一端与至少一低压端子100a电连接，将另一端延伸至另一组所述高压端子21和所述检测端子22之间。
在一个实施例中，所述另一端延伸至一组所述高压端子21和所述检测端子22之间的导电引线30包括第一连接段303和第一阻隔段304；所述方法还包括：
将所述第一连接段303的一端与至少一低压端子100a电连接，将另一端与所述第一阻隔段304连接；所述第一阻隔段304的两端分别对应一组端子，将所述第一阻隔段304的两端分别延伸至对应组中的所述高压端子21和所述检测端子22之间；
和/或，
所述另一端延伸至另一组所述高压端子21和所述检测端子22之间的导电引线30包括第二连接段305和第二阻隔段306；所述方法还包括：
将所述第二连接段305的一端与至少一低压端子100a电连接，将另一端与所述第二阻隔段306连接；所述第二阻隔段306的两端分别对应一组端子，将所述第二阻隔段306的两端分别延伸至对应组中的所述高压端子21和所述检测端子22之间。
在一个实施例中，所述至少一低压端子100a包括间隔设置的第一低压端子101和第二低压端子102，所述导电结构3包括第一导电引线31和第二导电引线32；所述方法还包括：
将所述第一导电引线31的一端与所述第一低压端子101电连接，将另一端延伸至所述高压端子21和所述检测端子22之间，将所述第二导电引线32的一端与所述第二低压端子102电连接，将另一端延伸至与所述第一导电引线31相对应的所述高压端子21和所述检测端子22之间。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组，所述第一导电引线31包括第三连接段311和第三阻隔段312，所述第二导电引线32包括第四连接段321和第四阻隔段322，所述方法还包括：
将两组端子间隔地设于所述基板10上，将所述第三连接段311的一端与所述第一低压端子101电连接，将所述第三阻隔段312与所述第三连接段311连接，将所述第四连接段321的一端与所述第二低压端子102电连接，将所述第四阻隔段322与所述第四连接段321连接；
所述第三阻隔段312的两端分别对应一组端子，将所述第三阻隔段312的两端分别延伸至对应组中的所述高压端子21和所述检测端子22之间；或者，所述第三阻隔段312对应一组端子，将所述第三阻隔段312的一端与所述第三连接段311连接，将另一端延伸至对应组中的所述高压端子21和所述检测端子22之间；
所述第四阻隔段322的两端分别对应一组端子，将所述第四阻隔段322的两端分别延伸至对应组中的所述高压端子21和所述检测端子22之间；或者，所述第四阻隔段322对应一组端子，将所述第四阻隔段322的一端与所述第四连接段321连接，将另一端延伸至对应组中的所述高压端子21和所述检测端子22之间。
在一个实施例中，所述第一导电引线31的数量至少为两条；和/或所述第二导电引线32的数量至少为两条；所述方法还包括：
将至少两条所述第一导电引线31连接于所述同一个第一低压端子101，或者分别连接于不同的第一低压端子101；
将至少两条所述第二导电引线32连接于所述同一个第二低压端子102，或者分别连接于不同的第二低压端子102。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组；所述耗材芯片还包括第三低压端子103，所述导电引线30还包括第三导电引线33；所述第一导电引线31包括第三连接段311和第三阻隔段312，所述方法还包括：
将两组端子间隔地设于所述基板10上；将所述第三连接段311的一端与所述第一低压端子101电连接，将所述第三阻隔段312与所述第三连接段311连接，将所述第三阻隔段312的两端分别对应一组 端子，并且将所述第三阻隔段312的两端分别延伸至对应每组中的所述高压端子21和所述检测端子22之间；
将所述第二导电引线32的一端与所述第二低压端子102电连接，将另一端延伸至其中一组所述高压端子21和所述检测端子22之间；
将所述第三导电引线33的一端与所述第三低压端子103电连接，将另一端延伸至其中另一组所述高压端子21和所述检测端子22之间。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组，所述耗材芯片还包括第三低压端子103，所述导电引线30还包括第三导电引线33，所述第一导电引线31的数量为两根；所述方法还包括：
将两组端子间隔地设于所述基板10上；
将两根所述第一导电引线31分别对应一组端子，将一根所述第一导电引线31的一端与第一低压端子101连接，将另一端延伸至与之对应的一组端子中的高压端子21和检测端子22之间；将另一根所述第一导电引线31的一端与第一低压端子101连接，将另一端伸至与之对应的一组端子中的高压端子21和检测端子22之间；
将所述第二导电引线32的一端与所述第二低压端子102电连接，将另一端延伸至其中一组所述高压端子21和所述检测端子22之间；
将所述第三导电引线33的一端与所述第三低压端子103电连接，将另一端延伸至其中另一组所述高压端子21和所述检测端子22之间。
在一个实施例中，所述高压端子21与所述检测端子22的数量为两组，所述耗材芯片还包括第三低压端子103以及第四低压端子105，所述导电引线30还包括第三导电引线33和第四导电引线34；所述方法还包括：
将两组端子间隔地设于所述基板10上；
将所述第一导电引线31的一端与所述第一低压端子101电连接，将另一端延伸至其中一组端子中的所述高压端子21和所述检测端子22之间，将所述第二导电引线32的一端与所述第二低压端子102电连接，将另一端延伸至与所述第一导电引线31相对应的一组端子中的所述高压端子21和所述检测端子22之间；
将所述第三导电引线33的一端与所述第三低压端子103电连接，将另一端延伸至另一组端子中的所述高压端子21和所述检测端子22之间，将所述第四导电引线34的一端与所述第四低压端子105电连接，将另一端延伸至与所述第三导电引线33相对应的另一组端子中的所述高压端子21和所述检测端子22之间。
在一个实施例中，所述方法还包括：将所述第一导电引线31呈T型结构或者L型结构设置；和/或，将所述第二导电引线32呈T型结构或者L型结构设置。
在一个实施例中，所述方法还包括：将位于所述高压端子21和所述检测端子22之间的第一导电引线31和所述第二导电引线32间隔设置；
将所述第一导电引线31相对所述第二导电引线32靠近所述检测端子22设置；或者，将所述第二导电引线32相对所述第一导电引线31靠近所述检测端子22设置。
在一个实施例中，所述第一低压端子101为使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种；
和/或，第二低压端子102为使能端子101a、时钟端子101b、接地端子101c、数据端子101d以及电源端子101e中的任意一种。
在一个实施例中，所述第一低压端子101为接地端子101c，所述第二低压端子102为使能端子101a、时钟端子101b、数据端子101d以及电源端子101e中的任意一种。
在一个实施例中，所述方法还包括：在所述基板10上开设第一槽口11，在所述第一槽口11内设置导电层以形成所述接地端子101c、所述数据端子101d、所述电源端子101e中至少之一；
和/或,将所述接地端子101c、所述数据端子101d或所述电源端子101e并排设置。
在一个实施例中，所述方法还包括：在所述基板10的侧壁上开设第二槽口12，所述第二槽口12 具有多个第二槽壁，将至少一个所述第二槽壁上设置导电层以形成所述高压端子21；
和/或，在所述基板10的侧壁上开设第三槽口13，在所述第三槽口13内上设置导电层，以形成所述检测端子22。
本申请实施例的耗材芯片的制作方法与上述耗材芯片相对应，在上述耗材芯片的实施例阐述的技术特征及其有益效果均适用于耗材芯片的制作方法的实施例中。耗材芯片的制作方法的步骤可以任意组合，不存在先后顺序。
以上实施方式的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施方式中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
本技术领域的普通技术人员应当认识到，以上的实施方式仅是用来说明本申请，而并非用作为对本申请的限定，只要在本申请的实质精神范围内，对以上实施方式所作的适当改变和变化都落在本申请要求保护的范围内。

Claims (10)

  1. 一种耗材芯片，包括存储器、基板、布设于所述基板上的至少一与所述存储器电连接的低压端子、至少一高压端子以及至少一检测端子，所述高压端子与所述检测端子间隔设置，其特征在于，所述耗材芯片还包括导电结构，所述导电结构的一端电连接于所述低压端子，所述导电结构的另一端延伸至所述高压端子与所述检测端子之间。
  2. 根据权利要求1所述的耗材芯片，其特征在于，所述高压端子与所述检测端子的数量为两组且间隔设置，至少一所述低压端子连接至少一个导电结构，所述导电结构的一端电连接于所述低压端子，另一端延伸至至少一组所述高压端子与所述检测端子之间。
  3. 根据权利要求2所述的耗材芯片，其特征在于，每组所述高压端子与所述检测端子之间存在至少两个所述导电结构；或
    一组所述高压端子与所述检测端子之间存在一个所述导电结构，另一组所述高压端子与所述检测端子之间存在至少两个所述导电结构。
  4. 根据权利要求1-3中任意一项所述的耗材芯片，其特征在于，所述导电结构为金属引线。
  5. 根据权利要求1-3中任意一项所述的耗材芯片，其特征在于，所述导电结构呈T型或L型。
  6. 根据权利要求1-3中任意一项所述的耗材芯片，其特征在于，
    所述基板的侧壁上开设有第一槽口，所述第一槽口内设有导电层并形成所述低压端子；和/或
    所述基板的侧壁上开设有第二槽口，所述第二槽口内设有导电层并形成所述高压端子；和/或
    所述基板的侧壁上设有第三槽口和第四槽口，所述第四槽口沿所述基板的长度方向形成，所述第三槽口设于所述第四槽口的侧壁上，所述第三槽口内设有导电层并形成所述检测端子。
  7. 根据权利要求6所述的耗材芯片，其特征在于，所述第二槽口为直角槽，其具有长边侧壁和短边侧壁，所述长边侧壁设有导电层并形成所述高压端子。
  8. 根据权利要求1-3中任意一项所述的耗材芯片，其特征在于，所述导电结构包括连接段和阻隔段，所述连接段的一端电连接于所述低压端子，所述连接段的另一端电连接于所述阻隔段，所述阻隔段延伸至所述高压端子与所述检测端子之间。
  9. 一种耗材盒，其特征在于，包括耗材盒本体以及如权利要求1至8中任一项所述的耗材芯片，所述耗材芯片设置于所述耗材盒本体上。
  10. 一种耗材芯片的制作方法，其特征在于，所述方法包括以下步骤：
    在基板上布设存储器、至少一与存储器电连接的低压端子、至少一高压端子以及至少一检测端子，所述高压端子与所述检测端子间隔设置；
    在所述基板上布设导电结构，所述导电结构的一端电连接于所述低压端子，所述导电结构的另一端延伸至所述高压端子与所述检测端子之间。
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JP2023537663A (ja) 2023-09-05
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