WO2023000163A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023000163A1
WO2023000163A1 PCT/CN2021/107314 CN2021107314W WO2023000163A1 WO 2023000163 A1 WO2023000163 A1 WO 2023000163A1 CN 2021107314 W CN2021107314 W CN 2021107314W WO 2023000163 A1 WO2023000163 A1 WO 2023000163A1
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Prior art keywords
layer
gate
dielectric layer
forming
source
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PCT/CN2021/107314
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English (en)
French (fr)
Inventor
于海龙
荆学珍
孟晋辉
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Application filed by 中芯国际集成电路制造(上海)有限公司, 中芯国际集成电路制造(北京)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to CN202180099968.2A priority Critical patent/CN117581368A/zh
Priority to PCT/CN2021/107314 priority patent/WO2023000163A1/zh
Publication of WO2023000163A1 publication Critical patent/WO2023000163A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • the interconnection structure includes interconnection lines and contact plugs formed in the contact openings.
  • the contact plugs are connected to the semiconductor device, and the interconnection wires realize the connection between the contact plugs, thereby constituting a circuit.
  • the contact plugs in the transistor structure include gate contact plugs on the gate structure for connecting the gate structure to external circuits, and source-drain contact plugs on the source-drain doped region for Realize the connection between source and drain doped regions and external circuits.
  • the problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and its forming method, reduce the difficulty of forming gate plugs, and improve the formation quality of gate plugs.
  • an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; source and drain doped regions located in the substrate on both sides of the gate structure; a bottom a dielectric layer, located between adjacent gate structures and covering the source-drain doped region; a pad metal layer, located on the top surface of the gate structure and in contact with the gate structure, the The material of the pad metal layer is pure metal; the top dielectric layer is located on the bottom dielectric layer and covers the pad metal layer; the gate plug penetrates through the top dielectric layer and is in contact with the pad metal layer touch.
  • the material of the pad metal layer includes tungsten, ruthenium or molybdenum.
  • the thickness of the pad metal layer is 1.5 nm to 3 nm.
  • the liner metal layer contains chlorine element.
  • the material of the gate plug is the same as that of the pad metal layer.
  • the material of the gate plug includes one or both of tungsten and ruthenium.
  • the gate structure is a metal gate structure; the metal gate structure includes a work function layer, or, the metal gate structure includes a metal electrode layer and a bottom and a sidewall of the metal electrode layer work function layer.
  • the material of the work function layer includes: any one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN and TiSiN; the material of the metal electrode layer Including one or more of W, Al, Cu, Ag, Au, Pt, Ni and Ti.
  • the semiconductor structure further includes: a gate spacer located on a sidewall of the gate structure; a gate dielectric layer located between the gate structure and the substrate.
  • the top dielectric layer includes: a first dielectric layer located on the bottom dielectric layer and covering the pad metal layer; a second dielectric layer located on the first dielectric layer; the semiconductor structure It also includes: a source-drain interconnection layer, penetrating through the bottom dielectric layer on the top of the source-drain doped region and the first dielectric layer, and the source-drain interconnection layer is in contact with the source-drain doped region; The source-drain plug penetrates the second dielectric layer and is in contact with the source-drain interconnection layer.
  • the base includes a fin, the gate structure straddles the fin, and the source and drain doped regions are located in the fins on both sides of the gate structure; or, the base includes a channel A structure layer, the channel structure layer includes one or more channel layers arranged at intervals; the gate structure spans the channel structure layer and surrounds the channel layer.
  • an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, a gate structure is formed on the substrate, and source and drain doped regions are formed in the substrate on both sides of the gate structure, A bottom dielectric layer located between adjacent gate structures is formed on the source-drain doped region; a pad metal layer in contact with the gate structure is formed on the top surface of the gate structure, so The material of the pad metal layer is pure metal; a top dielectric layer is formed on the bottom dielectric layer, and the top dielectric layer covers the pad metal layer; a first selective deposition process is used to form a layer and is in contact with the pad metal layer.
  • the material of the pad metal layer includes tungsten, ruthenium or molybdenum.
  • the pad metal layer is formed by using a second selective deposition process.
  • the material of the liner metal layer is tungsten
  • the parameters of the second selective deposition process include: the reaction gas includes WCl 5 and H 2 .
  • the second selective deposition process includes an atomic layer deposition process.
  • the material of the gate plug is the same as that of the pad metal layer.
  • the material of the gate plug includes one or both of tungsten and ruthenium.
  • the step of forming a gate plug includes: forming a gate contact hole penetrating through the top dielectric layer, the gate contact hole exposing the pad metal layer; using a first selective deposition process, The gate plug in contact with the pad metal layer is formed in the gate contact hole.
  • the first selective deposition process includes a selective chemical vapor deposition process.
  • the gate structure is a metal gate structure; the metal gate structure includes a work function layer, or, the metal gate structure includes a metal electrode layer and a The work function of the bottom layer and sidewalls of the layer.
  • the step of forming the top dielectric layer includes: forming a first dielectric layer on the bottom dielectric layer to cover the pad metal layer; forming a second dielectric layer on the first dielectric layer;
  • the method for forming the semiconductor structure further includes: after forming the first dielectric layer and before forming the second dielectric layer, forming a bottom dielectric layer that penetrates the top of the source-drain doped region and the first dielectric layer.
  • the source-drain interconnection layer of the layer, the source-drain interconnection layer is in contact with the source-drain doped region; when forming the gate plug penetrating through the top dielectric layer and in contact with the liner metal layer In the step, a source-drain plug penetrating through the second dielectric layer and in contact with the source-drain interconnection layer is also formed.
  • a pad metal layer is provided on the top surface of the gate structure, and the pad metal layer
  • the material is pure metal, so that the top of the gate structure is a single metal material surface; during the formation of the semiconductor structure, the gate plug is formed by a first selective deposition process, and accordingly, the liner
  • the metal layer can provide a good formation interface and a deposition substrate for forming the gate plug by the first selective deposition process, which is conducive to the deposition and growth of the material of the gate plug on the liner metal layer, Furthermore, it is beneficial to reduce the difficulty of forming the gate plug, improve the formation quality of the gate plug, and improve the performance of the device.
  • a pad metal layer is formed on the top surface of the gate structure, and the material of the pad metal layer is pure metal, so that the top of the gate structure is A single metal material surface, correspondingly, the liner metal layer can provide a good formation interface and deposition substrate for forming the gate plug by the first selective deposition process, which is beneficial to the formation of the gate plug.
  • the deposition and growth of the material on the liner metal layer further helps to reduce the difficulty of forming the gate plug by using the first selective deposition process, improve the formation quality of the gate plug, and improve the performance of the device.
  • 1 to 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.
  • FIG. 3 is a structural schematic diagram of an embodiment of the semiconductor structure of the present invention.
  • 4 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • 1 to 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.
  • a substrate 10 is provided, on which a gate structure 11 is formed, and source and drain doped regions 12 are formed in the substrate 10 on both sides of the gate structure 11, and on the source and drain doped regions 12
  • a bottom dielectric layer 13 is formed between adjacent gate structures 11 .
  • a top dielectric layer 14 is formed on the bottom dielectric layer 13 ; a gate plug 15 penetrating through the top dielectric layer 14 and in contact with the gate structure 11 is formed by using a selective deposition process.
  • the gate structure 11 is generally a stacked structure of multi-layer film layers, for example: when the gate structure is a metal gate structure, the gate structure 11 generally includes a work function layer 17, or the gate The structure 11 includes a metal electrode layer 16 and a work function layer 17 located on the sidewall and bottom of the metal electrode layer 16, so that the top surface of the gate structure 11 is a combination of various materials, that is, the gate structure 11 The top surface is a complex combination of film layers.
  • the selective deposition process is formed on the top surface of the gate structure 11.
  • the growth rate on the surface is low and the growth is difficult, and the film quality of the formed gate plug 15 is not good.
  • the material of the work function layer 17 is generally a metal compound, and the selective deposition process is difficult to deposit on the metal compound, so that the selective deposition process is used to form the gate Pole Plug 15 presents even greater challenges.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a gate structure is formed, and active-drain doping is formed in the substrate on both sides of the gate structure.
  • a bottom dielectric layer located between adjacent gate structures is formed on the source-drain doped region;
  • a pad metal layer in contact with the gate structure is formed on the top surface of the gate structure layer, the material of the liner metal layer is pure metal;
  • a top dielectric layer is formed on the bottom dielectric layer, and the top dielectric layer covers the liner metal layer; a first selective deposition process is used to form a A gate plug on the top dielectric layer and in contact with the pad metal layer.
  • a pad metal layer is formed on the top surface of the gate structure, and the material of the pad metal layer is pure metal, so that the top of the gate structure is A single metal material surface, correspondingly, the liner metal layer can provide a good formation interface and deposition substrate for forming the gate plug by the first selective deposition process, which is beneficial to the formation of the gate plug.
  • the deposition and growth of the material on the liner metal layer further helps to reduce the difficulty of forming the gate plug by using the first selective deposition process, improve the formation quality of the gate plug, and improve the performance of the device.
  • an embodiment of the present invention also provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; source and drain doped regions located on the substrate on both sides of the gate structure Inside; a bottom dielectric layer, located between adjacent gate structures and covering the source-drain doped region; a pad metal layer, located on the top surface of the gate structure and in contact with the gate structure , the material of the liner metal layer is pure metal; the top dielectric layer is located on the bottom dielectric layer and covers the liner metal layer; the gate plug penetrates the top dielectric layer and is connected with the liner The metal layers are in contact.
  • a pad metal layer is provided on the top surface of the gate structure, and the material of the pad metal layer is pure metal, so that the top of the gate structure is a single metal material surface; during the formation of the semiconductor structure, the gate plug is formed by a first selective deposition process, and correspondingly, the pad metal layer can be formed by using the first selective deposition process to form the gate plug.
  • FIG. 3 shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.
  • the semiconductor structure includes: a substrate 100 ; a gate structure 110 located on the substrate 100 ; source and drain doped regions 140 located on both sides of the gate structure 110 .
  • the bottom dielectric layer 150 is located between the adjacent gate structures 110 and covers the source-drain doped region 140
  • the pad metal layer 120 is located on the top surface of the gate structure 110 and In contact with the gate structure 110, the material of the pad metal layer 120 is pure metal; a top dielectric layer 160, located on the bottom dielectric layer 150 and covering the pad metal layer 120; a gate plug 200 , penetrate through the top dielectric layer 160 and be in contact with the pad metal layer 120 .
  • a pad metal layer 120 is provided on the top surface of the gate structure 110, and the material of the pad metal layer 120 is pure metal, so that the top of the gate structure 110 is a single metal material surface;
  • the gate plug 200 is formed by the first selective deposition process, and accordingly, the pad metal layer 120 can provide good conditions for forming the gate plug 200 by the first selective deposition process.
  • the formation interface and deposition substrate are beneficial to the deposition and growth of the material of the gate plug 200 on the liner metal layer 120, which in turn is beneficial to reduce the difficulty of forming the gate plug 200 and improve the efficiency of the gate plug.
  • the formation quality of 200, the performance of the device has been improved.
  • the substrate 100 is used to provide a process platform for the formation of semiconductor structures.
  • the substrate 100 is used to form a Fin Field Effect Transistor (FinFET).
  • the substrate 100 is a three-dimensional substrate, including a substrate (not shown in the figure) and a fin 105 protruding from the substrate.
  • the fin 105 Used to provide the conduction channel for field effect transistors.
  • the substrate is a silicon substrate.
  • the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium.
  • the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates.
  • the material of the fin portion 105 includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.
  • the material of the fin portion 105 is single crystal silicon.
  • the fin portion 105 is an integrated structure with the substrate.
  • the substrate can also be used to form other types of transistors.
  • the base when forming an all-around gate transistor, the base includes a substrate, a raised portion protruding from the substrate, and a channel structure layer on the raised portion, and there is a gap between the channel structure layer and the raised portion.
  • the channel structure layer includes one or more channel layers arranged at intervals. The channel layer is used to provide the conduction channel of the field effect transistor.
  • an isolation layer (not shown) surrounding the fin 105 is also formed on the substrate, and the top surface of the isolation layer is lower than the top surface of the fin 105, so that the isolated Layer exposed fins 105 as effective fins (Active Fin), the effective fin is used to provide the conduction channel of the field effect transistor.
  • the isolation layer is used to isolate adjacent fins 105 , and is also used to isolate the substrate and the gate structure 110 .
  • the isolation layer is a shallow trench isolation structure (Shallow trench isolation, STI).
  • the material of the isolation layer is silicon oxide.
  • the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
  • the gate structure 110 is used to control the turn-on and turn-off of the conduction channel.
  • the gate structure 110 is located on the isolation layer, spans the fin 105 and covers part of the top and part of the sidewall of the fin 105 .
  • the gate structure when forming other types of transistors, for example, when forming an all-around gate transistor, spans the channel structure layer and surrounds the channel layer.
  • the gate structure 110 is a metal gate structure 115 .
  • the metal gate structure 115 includes a work function layer 112 , or, the metal gate structure 115 includes a metal electrode layer 111 and the work function layer 112 located at the bottom and sidewalls of the metal electrode layer 111 .
  • the gate structure may also be other types of gate structures.
  • the exposed top surface of the gate structure 110 is the top surface of the work function layer 112 , or is the top surface of the metal electrode layer 111 and the top surface of the work function layer 112 .
  • the metal gate structure 115 includes a metal electrode layer 111 and a work function layer 112 located on the bottom and sidewalls of the metal electrode layer 111, and the exposed top surface of the gate structure 110 is metal The top surface of the electrode layer 111 and the top surface of the work function layer 112 .
  • the work function layer 112 is used to adjust the work function of the metal gate structure 115 .
  • the material of the work function layer 112 includes any one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN and TiSiN.
  • the material of the metal electrode layer 111 is a conductive material.
  • a conductive material For example: one or more of W, Al, Cu, Ag, Au, Pt, Ni and Ti.
  • the semiconductor structure further includes: a gate spacer 130 located on the sidewall of the gate structure 110 .
  • the gate spacer 130 is used to define the formation region of the source-drain doped region 140 , and is also used to protect the sidewall of the gate structure 110 .
  • the gate spacer 130 can be a single layer or a stacked structure.
  • the material of the gate spacer 130 can be any one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride kind.
  • the gate spacer 130 is a laminated structure, and the gate spacer 130 includes a first sidewall 20 on the sidewall of the gate structure 110 and a first spacer 20 on the sidewall of the first sidewall 20
  • the second side wall 30 on the side wall Specifically, the materials of the first side wall 20 and the second side wall 30 are different.
  • the material of the first sidewall 20 is silicon oxide
  • the material of the second sidewall 30 is silicon nitride.
  • the semiconductor structure further includes: a gate dielectric layer 113 located between the gate structure 110 and the substrate 100 .
  • the gate dielectric layer 113 is used to realize electrical isolation between the gate structure 110 and the conductive channel.
  • the gate dielectric layer 113 is also located between the gate structure 110 and the gate spacer 130 .
  • the material of the gate dielectric layer 113 includes one of silicon oxide, nitrogen-doped silicon oxide, HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 and Al 2 O 3 or Various.
  • the source-drain doped region 140 is used as a source region and a drain region of a field effect transistor to provide a carrier source.
  • the source-drain doped regions 140 are located in the fins 105 on both sides of the gate structure 110 .
  • the source-drain doped regions are located on both sides of the gate structure and are in contact with ends of the channel structure layer along the extending direction.
  • the source-drain doped region 140 includes a stress layer doped with ions, and the source-drain doped region 150 is also used to provide stress to the channel, thereby increasing the carrier mobility of the channel.
  • the material of the source-drain doped region 140 is a stress layer doped with N-type ions, and the material of the stress layer includes Si or SiC, and the stress layer provides tension for the channel region of the NMOS transistor.
  • the effect of stress is beneficial to improve the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions.
  • the material of the source-drain doped region 140 is a stress layer doped with P-type ions
  • the material of the stress layer includes Si or SiGe
  • the stress layer provides compressive stress for the channel region of the PMOS transistor. role, thereby improving the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.
  • the bottom dielectric layer 150 is used for isolation between adjacent devices.
  • the bottom dielectric layer 150 is an interlayer dielectric layer (ILD).
  • the material of the bottom dielectric layer 150 is a dielectric material, such as silicon oxide, silicon oxynitride, and the like.
  • the bottom dielectric layer 150 exposes the top surface of the gate structure 110 .
  • the material of the pad metal layer 120 is pure metal, so that the top of the gate structure 110 is a single metal material surface, and accordingly, the pad metal layer 120 can be formed by using the first selective deposition process.
  • the gate plug 200 provides a good formation interface and a deposition substrate, which is conducive to the deposition and growth of the material of the gate plug 200 on the pad metal layer 120, thereby reducing the cost of the gate plug 200. Formation difficulty is improved, the formation quality of the gate plug 200 is improved, and the performance of the device is improved.
  • the gate plug 200 can be formed on the metal liner layer 120 by the first selective deposition process.
  • the material of the pad metal layer 120 includes tungsten (W), ruthenium (Ru) or molybdenum (Mo).
  • the material of the pad metal layer is not limited thereto, and any metal material that can facilitate the deposition and growth of the first selective deposition process for forming the gate plug is applicable.
  • the liner metal layer 120 is also located on the top surface of the gate dielectric layer 113 and the sidewall 130 part of the top surface.
  • the thickness of the pad metal layer 120 should not be too small, nor should it be too large. If the thickness of the liner metal layer 120 is too small, it will easily lead to poor film continuity of the liner metal layer 120; if the thickness of the liner metal layer 120 is too large, it will easily produce unnecessary material and waste of time, and it is easy to cause the pad metal layer 120 to extend and grow too much to both sides of the gate structure 110 , which easily increases the risk of electric leakage. Therefore, in this embodiment, the thickness of the pad metal layer 120 is 1.5nm to 3nm, for example: 2nm, 2.3nm, 2.5nm, 2.8nm and so on.
  • the pad metal layer 120 contains chlorine.
  • the material of the liner metal layer 120 is tungsten, and the liner metal layer 120 contains chlorine element, because the second selective deposition process is adopted during the formation of the liner metal layer 120, The liner metal layer 120 is formed, and the reaction gas of the second selective deposition process includes WCl 5 .
  • the second selective deposition process can selectively deposit only the metal material on the gate structure 110 Form the pad metal layer 120 on the top surface of the gate spacer 130 or the bottom dielectric layer 150 without forming the material of the pad metal layer on the top surface of the gate spacer 130 or the bottom dielectric layer 150, so that no patterning or etching process is required , which simplifies the formation process of the pad metal layer 120 .
  • the metal material includes pure metal material, metal alloy material and metal compound material.
  • WCl 5 is used as the reactant for selective deposition of tungsten, and WCl 5 gas has lower requirements on the deposition substrate of the selective deposition process, which is conducive to the deposition of tungsten on the top surface of the gate structure 110 with a complex film structure. grow.
  • the WCl 5 gas has lower requirements on the deposition substrate of the selective deposition process. It means that when WCl 5 is used as the reaction gas, a complex film structure can be used as the deposition substrate, and the deposition substrate does not need to be a single film structure.
  • tungsten fluoride gas is usually used as the reaction gas for selectively depositing tungsten.
  • tungsten fluoride is easy to damage the gate
  • the work function layer 112 in the structure 110 is corroded, resulting in damage to the gate structure 110, the structural integrity of the gate structure 110 cannot be guaranteed, and the contact performance between the tungsten and the gate structure 110 is poor.
  • the tungsten is also It is difficult to deposit on the work function layer 112 of the gate structure 110 .
  • the reaction gas of the second selective deposition process includes WCl 5 , thereby avoiding the use of tungsten fluoride as the reaction gas for the selective deposition of tungsten, and accordingly facilitating the deposition of tungsten on the top surface of the gate structure 110, In particular, the deposition of tungsten on the work function layer 112 is advantageous.
  • the top dielectric layer 160 is used for electrical isolation between adjacent gate plugs 200 .
  • the material of the top dielectric layer 160 is a dielectric material, for example: the material of the top dielectric layer 160 includes a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) , any one or more of ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, and silicon oxynitride.
  • a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9
  • ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6
  • silicon oxide silicon nitride
  • silicon oxynitride silicon oxynitride
  • the top dielectric layer 160 may be a single layer or a stacked structure.
  • the top dielectric layer 160 includes: a first dielectric layer 50 located on the bottom dielectric layer 150 and covering the pad metal layer 120; a second dielectric layer 70 located on the first dielectric layer 50 on.
  • the semiconductor structure further includes: a source-drain interconnection layer 170 , which runs through the bottom dielectric layer 150 on the top of the source-drain doped region 140 and the first dielectric layer 50 , and the source-drain interconnection The connecting layer 170 is in contact with the source-drain doped region 140 .
  • the source-drain interconnection layer 170 is used to realize the electrical connection between the source-drain doped region 140 and external circuits.
  • the material of the source-drain interconnection layer 170 is a conductive material, such as one or more of W, Co, Ru, Cu and Al. As an example, the material of the source-drain interconnection layer 170 is W.
  • an anti-diffusion barrier layer 180 is further formed on the sidewall and bottom of the source-drain interconnection layer 170 .
  • the anti-diffusion barrier layer 180 is used to prevent the material of the source-drain interconnection layer 170 from diffusing into the bottom dielectric layer 150 or the first dielectric layer 50 , thereby improving the problem of electromigration.
  • the material of the anti-diffusion barrier layer 180 includes one or more of Ta, Ti, TaN and TiN.
  • the first dielectric layer 50 is also used to realize electrical isolation between adjacent source-drain interconnection layers 170 .
  • the top dielectric layer 160 further includes: a first etch stop layer 40, located between the bottom dielectric layer 150 and the first dielectric layer 50, and the liner metal layer 120 and the first dielectric layer Between layers 50. Specifically, the first etching stop layer 40 is also located between the gate spacer 130 and the first dielectric layer 50 .
  • the first etch stop layer 40 is used to temporarily define the etching The role of the stop position, thereby reducing the probability of damage to the pad metal layer 120; the first etch stop layer 40 is also used to seal the top of the pad metal layer 120 and the gate structure 110 to prevent the pad metal layer 120 and The top surface of the gate structure 110 is affected by the external process environment.
  • the first etch stop layer 40 is selected from a material that has etch selectivity between the first dielectric layer 50 and the second dielectric layer 70 .
  • the material of the first etching stop layer 40 is silicon nitride.
  • the top dielectric layer 160 further includes: a second etch stop layer 60 located between the first dielectric layer 50 and the second dielectric layer 70 .
  • the second etching stop layer 60 is also located between the source-drain interconnection layer 170 and the second dielectric layer 70 .
  • the semiconductor structure generally further includes: a source-drain plug penetrating through the second dielectric layer 70 and in contact with the source-drain interconnection layer 170, and the second etch stop layer 60 is used for forming the source-drain plug.
  • a source-drain plug penetrating through the second dielectric layer 70 and in contact with the source-drain interconnection layer 170, and the second etch stop layer 60 is used for forming the source-drain plug.
  • the process of plugging temporarily define the position of etching stop, so as to reduce the possibility of damage to the source-drain interconnection layer 170 .
  • the gate plug 200 is used to realize the electrical connection between the gate structure 110 and an external circuit.
  • the material of the gate plug 200 is a conductive material, such as one or both of W and Ru.
  • the material of the gate plug 200 is the same as that of the pad metal layer 120, which can make the first selective deposition process easier to deposit and grow on the pad metal layer 120, further reducing the need for the first selective deposition process.
  • the difficulty of forming the gate plug 200 by a selective deposition process is not limited to a selective deposition process.
  • the semiconductor structure further includes: a source-drain plug 210 penetrating through the second dielectric layer 70 and in contact with the source-drain interconnection layer 170 .
  • the source-drain plug 210 is used to realize the electrical connection between the source-drain interconnection layer 170 and external circuits.
  • the material of the source-drain plug 210 is a conductive material, such as one or more of W, Co, Ru, Cu and Al. As an embodiment, the material of the source-drain plug 210 is the same as that of the gate plug 200 .
  • the material of the source-drain plug 210 is the same as that of the gate plug 200, because the source-drain plug 210 and the gate plug 200 are formed in the same step during the formation of the semiconductor structure.
  • the plug 200 improves process integration and simplifies process steps.
  • the present invention also provides a method for forming a semiconductor structure.
  • 4 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
  • a substrate 100 is provided, on which a gate structure 110 is formed, and source and drain doped regions 140 are formed in the substrate 100 on both sides of the gate structure 110 , and on the source and drain doped regions 140 A bottom dielectric layer 150 is formed between adjacent gate structures 110 .
  • the substrate 100 is used to provide a process platform for subsequent processes.
  • the substrate 100 is used to form a Fin Field Effect Transistor (FinFET).
  • the substrate 100 is a three-dimensional substrate, including a substrate (not shown in the figure) and a fin 105 protruding from the substrate.
  • the fin 105 Used to provide the conduction channel for field effect transistors.
  • the substrate is a silicon substrate.
  • the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium.
  • the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates.
  • the material of the fin portion 105 includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium.
  • the material of the fin portion 105 is single crystal silicon.
  • the fin portion 105 is an integrated structure with the substrate.
  • the substrate can also be used to form other types of transistors.
  • the base when forming an all-around gate transistor, the base includes a substrate, a raised portion protruding from the substrate, and a channel structure layer on the raised portion, and there is a gap between the channel structure layer and the raised portion.
  • the channel structure layer includes one or more channel layers arranged at intervals. The channel layer is used to provide the conduction channel of the field effect transistor.
  • an isolation layer (not shown) surrounding the fin 105 is also formed on the substrate, and the top surface of the isolation layer is lower than the top surface of the fin 105, so that the isolated Layer exposed fins 105 as effective fins (Active Fin), the effective fin is used to provide the conduction channel of the field effect transistor.
  • the isolation layer is used to isolate adjacent fins 105 , and is also used to isolate the substrate and the gate structure 110 .
  • the isolation layer is a shallow trench isolation structure (Shallow trench isolation, STI).
  • the material of the isolation layer is silicon oxide.
  • the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
  • the gate structure 110 is used to control the turn-on and turn-off of the conduction channel.
  • the gate structure 110 is located on the isolation layer, spans the fin 105 and covers part of the top and part of the sidewall of the fin 105 .
  • the gate structure when forming other types of transistors, for example, when forming an all-around gate transistor, spans the channel structure layer and surrounds the channel layer.
  • the gate structure 110 is a metal gate structure 115 .
  • the metal gate structure 115 includes a work function layer 112 , or, the metal gate structure 115 includes a metal electrode layer 111 and the work function layer 112 located at the bottom and sidewalls of the metal electrode layer 111 .
  • the gate structure may also be other types of gate structures.
  • the exposed top surface of the gate structure 110 is the top surface of the work function layer 112 , or is the top surface of the metal electrode layer 111 and the top surface of the work function layer 112 .
  • the metal gate structure 115 includes a metal electrode layer 111 and a work function layer 112 located on the bottom and sidewalls of the metal electrode layer 111, and the exposed top surface of the gate structure 110 is metal The top surface of the electrode layer 111 and the top surface of the work function layer 112 .
  • the work function layer 112 is used to adjust the work function of the metal gate structure 115 .
  • the material of the work function layer 112 includes any one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN and TiSiN.
  • the material of the metal electrode layer 111 is a conductive material.
  • a conductive material For example: one or more of W, Al, Cu, Ag, Au, Pt, Ni and Ti.
  • a gate spacer 130 is further formed on the sidewall of the gate structure 110 .
  • the gate spacer 130 is used to define the formation region of the source-drain doped region 140 , and is also used to protect the sidewall of the gate structure 110 .
  • the gate spacer 130 can be a single layer or a stacked structure.
  • the material of the gate spacer 130 can be any one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride kind.
  • the gate spacer 130 is a laminated structure, and the gate spacer 130 includes a first sidewall 20 on the sidewall of the gate structure 110 and a first spacer 20 on the sidewall of the first sidewall 20
  • the second side wall 30 on the side wall Specifically, the materials of the first side wall 20 and the second side wall 30 are different.
  • the material of the first sidewall 20 is silicon oxide
  • the material of the second sidewall 30 is silicon nitride.
  • a gate dielectric layer 113 is further formed between the gate structure 110 and the substrate 100 .
  • the gate dielectric layer 113 is used to realize electrical isolation between the gate structure 110 and the conductive channel.
  • the gate dielectric layer 113 is also formed between the gate structure 110 and the gate spacer 130 .
  • the material of the gate dielectric layer 113 includes one of silicon oxide, nitrogen-doped silicon oxide, HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 and Al 2 O 3 or Various.
  • the source-drain doped region 140 is used as a source region and a drain region of a field effect transistor to provide a carrier source.
  • the source-drain doped regions 140 are located in the fins 105 on both sides of the gate structure 110 .
  • the source-drain doped regions are located on both sides of the gate structure and are in contact with ends of the channel structure layer along the extending direction.
  • the source-drain doped region 140 includes a stress layer doped with ions, and the source-drain doped region 150 is also used to provide stress to the channel, thereby increasing the carrier mobility of the channel.
  • the material of the source-drain doped region 140 is a stress layer doped with N-type ions, and the material of the stress layer includes Si or SiC, and the stress layer provides tension for the channel region of the NMOS transistor.
  • the effect of stress is beneficial to improve the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions.
  • the material of the source-drain doped region 140 is a stress layer doped with P-type ions
  • the material of the stress layer includes Si or SiGe
  • the stress layer provides compressive stress for the channel region of the PMOS transistor. role, thereby improving the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.
  • the bottom dielectric layer 150 is used for isolation between adjacent devices.
  • the bottom dielectric layer 150 is an interlayer dielectric layer (ILD).
  • the material of the bottom dielectric layer 150 is a dielectric material, such as silicon oxide, silicon oxynitride, and the like.
  • the bottom dielectric layer 150 exposes the top surface of the gate structure 110 .
  • a pad metal layer 120 in contact with the gate structure 110 is formed on the top surface of the gate structure 110 , and the material of the pad metal layer 120 is pure metal.
  • a pad metal layer 120 is formed on the top surface of the gate structure 110, the material of the pad metal layer 120 is pure metal, so that the top of the gate structure 110 is a single metal material surface, correspondingly,
  • the pad metal layer 120 can provide a good formation interface and a deposition substrate for the subsequent formation of the gate plug by the first selective deposition process, which is beneficial for the material of the gate plug to be deposited on the pad metal layer 120.
  • the deposition and growth on the substrate are beneficial to reduce the difficulty of forming the gate plug by the first selective deposition process, improve the formation quality of the gate plug, and improve the performance of the device.
  • the gate plug material on a metal compound compared with using a selective deposition process to deposit the gate plug material on a metal compound, it is easier to deposit and grow on a pure metal by using a selective deposition process.
  • the The material of the metal liner layer 120 is pure metal, so as to facilitate subsequent formation of gate plugs on the metal liner layer 120 by using the first selective deposition process.
  • the material of the pad metal layer 120 includes tungsten (W), ruthenium (Ru) or molybdenum (Mo).
  • the material of the pad metal layer is not limited thereto, and any metal material that can facilitate the deposition and growth of the first selective deposition process for forming the gate plug is applicable.
  • the pad metal layer 120 in the step of forming the pad metal layer 120, as the deposition thickness of the pad metal layer 120 material on the top surface of the gate structure 110 gradually increases, the pad metal layer The material of 120 also extends around the top surface of the gate structure 110 , therefore, the pad metal layer 120 is also formed on the top surface of the gate dielectric layer 113 and part of the top surface of the spacer 130 .
  • the thickness of the pad metal layer 120 should not be too small, nor should it be too large. If the thickness of the liner metal layer 120 is too small, it will easily lead to poor film continuity of the liner metal layer 120; if the thickness of the liner metal layer 120 is too large, it will easily produce unnecessary material and waste of time, and it is easy to cause the pad metal layer 120 to extend and grow too much to both sides of the gate structure 110 , which easily increases the risk of electric leakage. Therefore, in this embodiment, the thickness of the pad metal layer 120 is 1.5nm to 3nm, for example: 2nm, 2.3nm, 2.5nm, 2.8nm and so on.
  • the pad metal layer 120 is formed by using a second selective deposition process.
  • the second selective deposition process can selectively form the pad metal layer only on the top surface of the gate structure 110 by utilizing the growth difference between the material of the pad metal layer 120 on the metal material and the non-metal material 120, without forming the material of the liner metal layer on the top surface of the gate spacer 130 or the bottom dielectric layer 150, so that no patterning or etching process is required, which simplifies the process flow.
  • the metal material includes pure metal material, metal alloy material and metal compound material.
  • the material of the liner metal layer 120 is tungsten, and the parameters of the second selective deposition process include: the reaction gas includes WCl 5 and H 2 .
  • WCl 5 is used as the reactant for selective deposition of tungsten, and WCl 5 gas has lower requirements on the deposition substrate of the selective deposition process, which is conducive to the deposition of tungsten on the top surface of the gate structure 110 with a complex film structure. grow.
  • the WCl 5 gas has lower requirements on the deposition substrate of the selective deposition process. It means that when WCl 5 is used as the reaction gas, a complex film structure can be used as the deposition substrate, and the deposition substrate does not need to be a single film structure.
  • tungsten fluoride gas is usually used as the reaction gas for selectively depositing tungsten.
  • tungsten fluoride is easy to damage the gate
  • the work function layer 112 in the structure 110 is corroded, resulting in damage to the gate structure 110, the structural integrity of the gate structure 110 cannot be guaranteed, and the contact performance between the tungsten and the gate structure 110 is poor.
  • the tungsten is also It is difficult to deposit on the work function layer 112 of the gate structure 110 .
  • the reaction gas of the second selective deposition process is WCl 5 , thereby avoiding the use of tungsten fluoride as the reaction gas for selective deposition of tungsten, which is correspondingly beneficial to the deposition of tungsten on the top surface of the gate structure 110, In particular, the deposition of tungsten on the work function layer 112 is advantageous.
  • the second selective deposition process includes an atomic layer deposition process.
  • the atomic layer deposition process is based on the self-limiting reaction process of the atomic layer deposition process.
  • the deposited film can reach the thickness of a single layer of atoms, and because the atomic layer deposition process can accurately deposit an atomic layer in each cycle, it is beneficial to the
  • the thickness of the pad metal layer 120 is precisely controlled, and the film prepared by the atomic layer deposition process also has the advantages of good bonding strength and high thickness consistency.
  • the above step of forming the pad metal layer 120 is only described as an example, and the step of forming the pad metal layer 120 is not limited thereto.
  • the step of forming a pad metal layer may further include: forming a pad metal material layer on the bottom dielectric layer and the gate structure; removing the pad metal material layer on the bottom dielectric layer, leaving the The pad metal material layer on the top surface of the gate structure is used as the pad metal layer.
  • a top dielectric layer 160 is formed on the bottom dielectric layer 150 , and the top dielectric layer 160 covers the pad metal layer 120 .
  • gate plugs are formed through the top dielectric layer 160 and in contact with the pad metal layer 120 , and the top dielectric layer 160 is used to realize electrical isolation between adjacent gate plugs.
  • the material of the top dielectric layer 160 is a dielectric material, for example: the material of the top dielectric layer 160 includes a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) , any one or more of ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, and silicon oxynitride.
  • a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9
  • ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6
  • silicon oxide silicon nitride
  • silicon oxynitride silicon oxynitride
  • the top dielectric layer 160 may be a single layer or a stacked structure.
  • the step of forming the top dielectric layer 160 includes the following steps.
  • a first dielectric layer 50 is formed on the bottom dielectric layer 150 to cover the pad metal layer 120 .
  • a first etching stop layer 40 covering the pad metal layer 120 is further formed on the bottom dielectric layer 150 .
  • the first etch stop layer 40 is used to temporarily define the etching The role of the stop position, thereby reducing the probability of damage to the pad metal layer 120; the first etch stop layer 40 is also used to seal the top of the pad metal layer 120 and the gate structure 110 to prevent the pad metal layer 120 and The top surface of the gate structure 110 is affected by the external process environment.
  • the first etch stop layer 40 is selected from a material that has etch selectivity between the first dielectric layer 50 and the second dielectric layer 70 .
  • the material of the first etching stop layer 40 is silicon nitride.
  • the method for forming the semiconductor structure further includes: after forming the first dielectric layer 50 , forming a The bottom dielectric layer 150 and the source-drain interconnection layer 170 of the first dielectric layer 50 , the source-drain interconnection layer 170 is in contact with the source-drain doped region 140 .
  • the source-drain interconnection layer 170 is used to realize the electrical connection between the source-drain doped region 140 and external circuits.
  • the material of the source-drain interconnection layer 170 is a conductive material, such as one or more of W, Co, Ru, Cu and Al. As an example, the material of the source-drain interconnection layer 170 is W.
  • the step of forming the source-drain interconnection layer 170 includes: forming a source-drain interconnection groove (not shown) penetrating through the bottom dielectric layer 150 on the top of the source-drain doped region 140 and the first dielectric layer 50 , the source-drain interconnection groove exposes the source-drain doped region 140; the source-drain interconnection layer 170 is formed in the source-drain interconnection groove.
  • the source-drain interconnection layer 170 is formed in the source-drain interconnection groove, and the forming method further includes: An anti-diffusion barrier layer 180 is formed on the bottom and sidewalls of the .
  • the anti-diffusion barrier layer 180 is used to prevent the material of the source-drain interconnection layer 170 from diffusing into the bottom dielectric layer 150 or the first dielectric layer 50 , thereby improving the problem of electromigration.
  • the material of the anti-diffusion barrier layer 180 includes one or more of Ta, Ti, TaN and TiN.
  • the forming method further includes: forming a second etch stop layer 60 on the first dielectric layer 50, the second etch stop layer 60 covers The source-drain interconnection layer 170 .
  • the second etch stop layer 60 is used to temporarily define the position of the etch stop , so as to reduce the possibility of damage to the source-drain interconnection layer 170 .
  • a second dielectric layer 70 is formed on the first dielectric layer 50 .
  • the second dielectric layer 70 is formed on the second etching stop layer 60 .
  • the top dielectric layer 160 is taken as an example for illustration. In other embodiments, the top dielectric layer may also be a single-layer structure.
  • a first selective deposition process is used to form a gate plug 200 penetrating through the top dielectric layer 160 and in contact with the pad metal layer 120 .
  • the gate plug 200 is used to realize the electrical connection between the gate structure 110 and an external circuit.
  • a pad metal layer 120 is formed on the top surface of the gate structure 110, and the material of the pad metal layer 120 is pure metal, so that the top of the gate structure 110 is a single metal material
  • the surface can provide a good formation interface and a deposition substrate for forming the gate plug 200 by the first selective deposition process, which is conducive to the material of the gate plug 200 on the liner metal layer 120
  • the deposition and growth are beneficial to reduce the difficulty of forming the gate plug 200 by using the first selective deposition process, improve the formation quality of the gate plug 200, and improve the performance of the device.
  • the material of the gate plug 200 is a conductive material, such as one or both of W and Ru.
  • the material of the gate plug 200 is the same as that of the pad metal layer 120, which can make the first selective deposition process easier to deposit and grow on the pad metal layer 120, further reducing the need for the first selective deposition process.
  • the difficulty of forming the gate plug 200 by a selective deposition process is not limited to a selective deposition process.
  • a source-drain plug 210 penetrating through the second dielectric layer 70 and in contact with the source-drain interconnection layer 170 is also formed.
  • the source-drain plug 210 is used to realize the electrical connection between the source-drain interconnection layer 170 and external circuits.
  • the material of the source-drain plug 210 is a conductive material, such as one or more of W, Co, Ru, Cu and Al. As an embodiment, the material of the source-drain plug 210 is the same as that of the gate plug 200 .
  • a gate contact hole 230 is formed through the top dielectric layer 160 , and the gate contact hole 230 exposes the pad metal layer 120 .
  • the gate contact hole 230 is used to provide a space for forming a gate plug.
  • a source-drain contact hole 220 penetrating through the second dielectric layer 70 is also formed to expose the source-drain interconnection layer 170 .
  • the source-drain contact hole 220 is used to provide a space for forming a source-drain plug.
  • the gate plug 200 in contact with the pad metal layer 120 is formed in the gate contact hole 230 by using a first selective deposition process.
  • the material of the gate plug 200 can be selectively deposited only on the pad metal layer 120 exposed by the gate contact hole 230, without removing the dielectric layer located on the top.
  • the material of the gate plug on the top surface of 160 simplifies the process flow.
  • the use of the first selective deposition process can achieve bottom-up metal-to-metal deposition, which is conducive to the maximization of the volume of the gate plug 200, and the resistivity of the gate plug 200 is obtained.
  • the lower resistivity is beneficial to increase the device density and extend the two-dimensional scaling.
  • the gate plug 200 is formed in the gate contact hole 230 and the source and drain plug is formed in the source and drain contact hole 220 by using the first selective deposition process. Plug 210.
  • the incubation (incubation) time difference between the materials of the gate plug 200 and the source-drain plug 210 on the metal material and the non-metal material is used, so that only the Conductive material is deposited in the gate contact hole 230 and in the source-drain contact hole 220 .
  • the first selective deposition process includes a selective chemical vapor deposition process.
  • the material of the gate plug 200 and the source-drain plug 210 is tungsten
  • the first selective deposition process is a selective tungsten chemical vapor deposition (Selective W CVD) process.
  • the source-drain plug 210 and the source-drain interconnection layer 170 are used to form a source-drain contact structure to realize electrical connection between the source-drain doped region and an external circuit.
  • the above step of forming the source-drain contact structure is only an example, and the step of forming the source-drain contact structure is not limited thereto.
  • the step of forming the source-drain contact structure may further include: before forming the top dielectric layer, forming a source-drain interconnection layer in the bottom dielectric layer in contact with the source-drain doped region ; After forming the top dielectric layer, forming a source-drain plug in contact with the source-drain interconnection layer in the top dielectric layer.

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Abstract

一种半导体结构及其形成方法，形成方法包括：提供基底，基底上形成有栅极结构，栅极结构两侧的基底内形成有源漏掺杂区，源漏掺杂区上形成有位于相邻栅极结构之间的底部介质层；在栅极结构的顶面上形成与栅极结构相接触衬垫金属层，衬垫金属层的材料为纯金属；在底部介质层上形成顶部介质层，顶部介质层覆盖衬垫金属层；采用第一选择性沉积工艺，形成贯穿顶部介质层且与衬垫金属层相接触的栅极插塞。衬垫金属层能够为采用第一选择性沉积工艺形成栅极插塞提供良好的形成界面和沉积衬底，有利于栅极插塞的材料在衬垫金属层上的沉积生长，进而降低采用第一选择性沉积工艺形成栅极插塞的难度、提高栅极插塞的形成质量。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
随着集成电路制造技术的不断发展，人们对集成电路的集成度和性能的要求变得越来越高。为了提高集成度、降低成本，元器件的关键尺寸不断变小，集成电路内部的电路密度越来越大，这种发展使得晶圆表面无法提供足够的面积来制作所需要的互连线。
为了满足关键尺寸缩小过后的互连线所需，目前不同金属层或者金属层与基底的导通是通过互连结构实现的。互连结构包括互连线和形成于接触开口内的接触插塞。接触插塞与半导体器件相连接，互连线实现接触插塞之间的连接，从而构成电路。晶体管结构内的接触插塞包括位于栅极结构上的栅极接触插塞，用于实现栅极结构与外部电路的连接，还包括位于源漏掺杂区上的源漏接触插塞，用于实现源漏掺杂区与外部电路的连接。
但是，目前器件的性能仍有待提高。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，降低形成栅极插塞的难度、提高栅极插塞的形成质量。
 技术解决方案
为解决上述问题，本发明实施例提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；源漏掺杂区，位于所述栅极结构两侧的所述基底内；底部介质层，位于相邻所述栅极结构之间且覆盖所述源漏掺杂区；衬垫金属层，位于所述栅极结构的顶面上且与所述栅极结构相接触，所述衬垫金属层的材料为纯金属；顶部介质层，位于所述底部介质层上且覆盖所述衬垫金属层；栅极插塞，贯穿所述顶部介质层且与所述衬垫金属层相接触。
可选的，所述衬垫金属层的材料包括钨、钌或钼。
可选的，所述衬垫金属层的厚度为1.5nm至3nm。
可选的，所述衬垫金属层中含有氯元素。
可选的，所述栅极插塞的材料与所述衬垫金属层的材料相同。
可选的，所述栅极插塞的材料包括钨和钌中的一种或两种。
可选的，所述栅极结构为金属栅极结构；所述金属栅极结构包括功函数层，或者，所述金属栅极结构包括金属电极层以及位于所述金属电极层的底部和侧壁的功函数层。
可选的，所述功函数层的材料包括：TiAl、TaAlN、TiAlN、MoN、TaCN、AlN、Ta、TiN、TaN、TaSiN和TiSiN中的任意一种或多种；所述金属电极层的材料包括W、Al、Cu、Ag、Au、Pt、Ni和Ti中的一种或多种。
可选的，所述半导体结构还包括：栅极侧墙，位于所述栅极结构的侧壁上；栅介质层，位于所述栅极结构与所述基底之间。
可选的，所述顶部介质层包括：第一介质层，位于所述底部介质层上且覆盖所述衬垫金属层；第二介质层，位于所述第一介质层上；所述半导体结构还包括：源漏互连层，贯穿所述源漏掺杂区顶部上的底部介质层以及所述第一介质层，且所述源漏互连层与所述源漏掺杂区相接触；源漏插塞，贯穿所述第二介质层且与所述源漏互连层相接触。
可选的，所述基底包括鳍部，所述栅极结构横跨所述鳍部，所述源漏掺杂区位于所述栅极结构两侧的鳍部内；或者，所述基底包括沟道结构层，所述沟道结构层包括一个或多个间隔设置的沟道层；所述栅极结构横跨所述沟道结构层且包围所述沟道层。
相应的，本发明实施例还提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极结构，所述栅极结构两侧的基底内形成有源漏掺杂区，所述源漏掺杂区上形成有位于相邻所述栅极结构之间的底部介质层；在所述栅极结构的顶面上形成与所述栅极结构相接触衬垫金属层，所述衬垫金属层的材料为纯金属；在所述底部介质层上形成顶部介质层，所述顶部介质层覆盖所述衬垫金属层；采用第一选择性沉积工艺，形成贯穿所述顶部介质层且与所述衬垫金属层相接触的栅极插塞。
可选的，所述衬垫金属层的材料包括钨、钌或钼。
可选的，采用第二选择性沉积工艺，形成所述衬垫金属层。
可选的，所述衬垫金属层的材料为钨，所述第二选择性沉积工艺的参数包括：反应气体包括WCl 5和H 2。
可选的，所述第二选择性沉积工艺包括原子层沉积工艺。
可选的，所述栅极插塞的材料与所述衬垫金属层的材料相同。
可选的，所述栅极插塞的材料包括钨和钌中的一种或两种。
可选的，形成栅极插塞的步骤包括：形成贯穿所述顶部介质层的栅极接触孔，所述栅极接触孔暴露出所述衬垫金属层；采用第一选择性沉积工艺，在所述栅极接触孔中形成与所述衬垫金属层相接触的所述栅极插塞。
可选的，所述第一选择性沉积工艺包括选择性化学气相沉积工艺。
可选的，提供基底的步骤中，所述栅极结构为金属栅极结构；所述金属栅极结构包括功函数层，或者，所述金属栅极结构包括金属电极层以及位于所述金属电极层的底部和侧壁的功函数层。
可选的，形成所述顶部介质层的步骤包括：在所述底部介质层上形成第一介质层，覆盖所述衬垫金属层；在所述第一介质层上形成第二介质层；所述半导体结构的形成方法还包括：在形成所述第一介质层之后，在形成所述第二介质层之前，形成贯穿所述源漏掺杂区顶部上的底部介质层和所述第一介质层的源漏互连层，所述源漏互连层与所述源漏掺杂区相接触；在形成贯穿所述顶部介质层且与所述衬垫金属层相接触的栅极插塞的步骤中，还形成贯穿所述第二介质层且与所述源漏互连层相接触的源漏插塞。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的半导体结构，所述栅极结构的顶面上设置有衬垫金属层，所述衬垫金属层的材料为纯金属，从而使得栅极结构的顶部上为单一的金属材料表面；在半导体结构的形成过程中，所述栅极插塞通过第一选择性沉积工艺形成，相应地，所述衬垫金属层能够为采用第一选择性沉积工艺形成所述栅极插塞提供良好的形成界面和沉积衬底，有利于所述栅极插塞的材料在所述衬垫金属层上的沉积生长，进而有利于降低栅极插塞的形成难度、提高栅极插塞的形成质量，器件的性能得到了提升。
本发明实施例提供的半导体结构的形成方法中，在所述栅极结构的顶面上形成衬垫金属层，所述衬垫金属层的材料为纯金属，从而使得栅极结构的顶部上为单一的金属材料表面，相应地，所述衬垫金属层能够为采用第一选择性沉积工艺形成所述栅极插塞提供良好的形成界面和沉积衬底，有利于所述栅极插塞的材料在所述衬垫金属层上的沉积生长，进而有利于降低采用第一选择性沉积工艺形成栅极插塞的难度、提高栅极插塞的形成质量，器件的性能得到了提升。
 附图说明
图1至图2是一种半导体结构的形成方法中各步骤对应的结构示意图。
图3是本发明半导体结构一实施例的结构示意图。
图4至图9是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，目前半导体结构的性能有待提高。现结合一种半导体结构的形成方法分析半导体结构性能有待提高的原因。图1至图2是一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，提供基底10，所述基底10上形成有栅极结构11，所述栅极结构11两侧的基底10内形成有源漏掺杂区12，所述源漏掺杂区12上形成有位于相邻所述栅极结构11之间的底部介质层13。
参考图2，在所述底部介质层13上形成顶部介质层14；采用选择性沉积工艺，形成贯穿所述顶部介质层14且与所述栅极结构11相接触的栅极插塞15。
其中，所述栅极结构11通常为多层膜层堆叠的叠层结构，例如：当所述栅极结构为金属栅极结构时，栅极结构11通常包括功函数层17，或者，栅极结构11包括金属电极层16和位于所述金属电极层16的侧壁与底部的功函数层17，从而所述栅极结构11的顶面为多种材料的组合，即所述栅极结构11的顶面为复杂的膜层组合。
在采用选择性沉积工艺形成所述栅极插塞15的过程中，由于所述栅极结构11的顶面为复杂的膜层组合，所述选择性沉积工艺在所述栅极结构11的顶面上的生长速率低、生长难度大，所形成的栅极插塞15的膜层质量不佳。尤其是，当栅极结构11为金属栅极结构时，功函数层17的材料通常为金属化合物，所述选择性沉积工艺在金属化合物上的沉积难度较大，使得采用选择性沉积工艺形成栅极插塞15具有更大的挑战。
为了解决所述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极结构，所述栅极结构两侧的基底内形成有源漏掺杂区，所述源漏掺杂区上形成有位于相邻所述栅极结构之间的底部介质层；在所述栅极结构的顶面上形成与所述栅极结构相接触衬垫金属层，所述衬垫金属层的材料为纯金属；在所述底部介质层上形成顶部介质层，所述顶部介质层覆盖所述衬垫金属层；采用第一选择性沉积工艺，形成贯穿所述顶部介质层且与所述衬垫金属层相接触的栅极插塞。
本发明实施例提供的半导体结构的形成方法中，在所述栅极结构的顶面上形成衬垫金属层，所述衬垫金属层的材料为纯金属，从而使得栅极结构的顶部上为单一的金属材料表面，相应地，所述衬垫金属层能够为采用第一选择性沉积工艺形成所述栅极插塞提供良好的形成界面和沉积衬底，有利于所述栅极插塞的材料在衬垫金属层上的沉积生长，进而有利于降低采用第一选择性沉积工艺形成栅极插塞的难度、提高栅极插塞的形成质量，器件的性能得到了提升。
为了解决所述技术问题，本发明实施例还提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；源漏掺杂区，位于所述栅极结构两侧的所述基底内；底部介质层，位于相邻所述栅极结构之间且覆盖所述源漏掺杂区；衬垫金属层，位于所述栅极结构的顶面上且与所述栅极结构相接触，所述衬垫金属层的材料为纯金属；顶部介质层，位于所述底部介质层上且覆盖所述衬垫金属层；栅极插塞，贯穿所述顶部介质层且与所述衬垫金属层相接触。
本发明实施例提供的半导体结构，所述栅极结构的顶面上设置有衬垫金属层，所述衬垫金属层的材料为纯金属，从而使得栅极结构的顶部上为单一的金属材料表面；在半导体结构的形成过程中，所述栅极插塞通过第一选择性沉积工艺形成，相应地，所述衬垫金属层能够为采用第一选择性沉积工艺形成所述栅极插塞提供良好的形成界面和沉积衬底，有利于所述栅极插塞的材料在所述衬垫金属层上的沉积生长，进而有利于降低栅极插塞的形成难度、提高栅极插塞的形成质量，器件的性能得到了提升。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面首先对本发明实施例的半导体结构进行详细说明。
参考图3，示出了本发明半导体结构一实施例的结构示意图。
如图3所示，本实施例中，所述半导体结构包括：基底100；栅极结构110，位于所述基底100上；源漏掺杂区140，位于所述栅极结构110两侧的所述基底100内；底部介质层150，位于相邻所述栅极结构110之间且覆盖所述源漏掺杂区140；衬垫金属层120，位于所述栅极结构110的顶面上且与所述栅极结构110相接触，所述衬垫金属层120的材料为纯金属；顶部介质层160，位于所述底部介质层150上且覆盖所述衬垫金属层120；栅极插塞200，贯穿所述顶部介质层160且与所述衬垫金属层120相接触。
所述栅极结构110的顶面上设置有衬垫金属层120，所述衬垫金属层120的材料为纯金属，从而使得栅极结构110的顶部上为单一的金属材料表面；在半导体结构的形成过程中，所述栅极插塞200通过第一选择性沉积工艺形成，相应地，所述衬垫金属层120能够为采用第一选择性沉积工艺形成所述栅极插塞200提供良好的形成界面和沉积衬底，有利于所述栅极插塞200的材料在所述衬垫金属层120上的沉积生长，进而有利于降低栅极插塞200的形成难度、提高栅极插塞200的形成质量，器件的性能得到了提升。
基底100用于为半导体结构的形成提供工艺平台。
本实施例中，基底100用于形成鳍式场效应晶体管（FinFET），基底100为立体型基底，包括衬底（图未示）和凸出于衬底的鳍部105，所述鳍部105用于提供场效应晶体管的导电沟道。
本实施例中，所述衬底为硅衬底。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
所述鳍部105的材料包括：单晶硅、锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。本实施例中，所述鳍部105的材料为单晶硅。
本实施例中，所述鳍部105与所述衬底为一体型结构。
在其他实施例中，所述基底还可以用于形成其他类型的晶体管。例如：当形成全包围栅极晶体管时，所述基底包括衬底、凸出于衬底的凸起部以及位于凸起部上的沟道结构层，沟道结构层与凸起部之间具有间隔，所述沟道结构层包括一个或多个间隔设置的沟道层。所述沟道层用于提供场效应晶体管的导电沟道。
本实施例中，所述衬底上还形成有围绕鳍部105的隔离层（图未示），所述隔离层的顶面低于所述鳍部105的顶面，从而使得被所述隔离层露出的所述鳍部105作为有效鳍部（Active Fin），有效鳍部用于提供场效应晶体管的导电沟道。
所述隔离层用于隔离相邻的鳍部105，还用于隔离所述衬底与所述栅极结构110。
本实施例中，所述隔离层为浅沟槽隔离结构（Shallow trench isolation，STI）。本实施例中，所述隔离层的材料为氧化硅。在其他实施例中，所述隔离层的材料还可以是氮化硅或氮氧化硅等其他绝缘材料。
在场效应晶体管工作时，栅极结构110用于控制导电沟道的开启和关断。
本实施例中，所述栅极结构110位于所述隔离层上，横跨所述鳍部105且覆盖所述鳍部105的部分顶部和部分侧壁。
在其他实施例中，当形成其他类型的晶体管时，例如：当形成全包围栅极晶体管时，所述栅极结构横跨所述沟道结构层且包围所述沟道层。
作为一实施例，所述栅极结构110为金属栅极结构115。所述金属栅极结构115包括功函数层112，或者，所述金属栅极结构115包括金属电极层111以及位于所述金属电极层111的底部和侧壁的功函数层112。在其他实施例中，栅极结构还可以为其他类型的栅极结构。
相应地，暴露出的所述栅极结构110的顶面为功函数层112的顶面，或者，为金属电极层111的顶面和功函数层112的顶面。
作为一种示例，所述金属栅极结构115包括金属电极层111以及位于所述金属电极层111的底部和侧壁的功函数层112，暴露出的所述栅极结构110的顶面为金属电极层111的顶面和功函数层112的顶面。
所述功函数层112用于调节金属栅极结构115的功函数。所述功函数层112的材料包括TiAl、TaAlN、TiAlN、MoN、TaCN、AlN、Ta、TiN、TaN、TaSiN和TiSiN中的任意一种或多种。
所述金属电极层111的材料为导电材料。例如：W、Al、Cu、Ag、Au、Pt、Ni和Ti中的一种或多种。
本实施例中，所述半导体结构还包括：栅极侧墙130，位于所述栅极结构110的侧壁上。所述栅极侧墙130用于定义所述源漏掺杂区140的形成区域，还用于在对所述栅极结构110的侧壁起到保护作用。
所述栅极侧墙130可以为单层或叠层结构。所述栅极侧墙130的材料可以为氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的任意一种或多种。
作为一实施例，所述栅极侧墙130为叠层结构，所述栅极侧墙130包括位于所述栅极结构110侧壁上的第一侧墙20以及位于所述第一侧墙20侧壁上的第二侧墙30。具体地，所述第一侧墙20和第二侧墙30的材料不同。例如：第一侧墙20的材料为氧化硅，第二侧墙30的材料为氮化硅。
本实施例中，所述半导体结构还包括：栅介质层113，位于所述栅极结构110与所述基底100之间。
所述栅介质层113用于实现栅极结构110与导电沟道之间的电隔离。
本实施例中，所述栅介质层113还位于所述栅极结构110与所述栅极侧墙130之间。
本实施例中，栅介质层113的材料包括氧化硅、掺氮氧化硅、HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2O 3和Al 2O 3中的一种或多种。
在器件工作时，所述源漏掺杂区140用于作为场效应晶体管的源区和漏区，用于提供载流子源。
本实施例中，所述源漏掺杂区140位于所述栅极结构110两侧的鳍部105内。在其他实施例中，当基底包括沟道结构层时，源漏掺杂区位于栅极结构两侧且与沟道结构层沿延伸方向的端部相接触。
本实施例中，所述源漏掺杂区140包括掺杂有离子的应力层，所述源漏掺杂区150还用于为沟道提供应力，从而提高沟道的载流子迁移率。
具体地，当形成NMOS晶体管时，源漏掺杂区140的材料为掺杂有N型离子的应力层，所述应力层的材料包括Si或SiC，应力层为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率，其中，所述N型离子为P离子、As离子或Sb离子。
当形成PMOS晶体管时，所述源漏掺杂区140的材料为掺杂有P型离子的应力层，应力层的材料包括Si或SiGe，所述应力层为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率，其中，所述P型离子为B离子、Ga离子或In离子。
所述底部介质层150用于实现相邻器件之间的隔离。本实施例中，所述底部介质层150为层间介质层（ILD）。所述底部介质层150的材料为介电材料，例如：氧化硅、氮氧化硅等。
本实施例中，所述底部介质层150暴露出所述栅极结构110的顶面。
所述衬垫金属层120的材料为纯金属，从而使得栅极结构110的顶部上为单一的金属材料表面，相应地，所述衬垫金属层120能够为采用第一选择性沉积工艺形成所述栅极插塞200提供良好的形成界面和沉积衬底，有利于所述栅极插塞200的材料在所述衬垫金属层120上的沉积生长，进而有利于降低栅极插塞200的形成难度、提高栅极插塞200的形成质量，器件的性能得到了提升。
并且，在半导体领域中，相较于采用选择性沉积工艺在金属化合物上沉积栅极插塞的材料相比，采用选择性沉积工艺在纯金属上更易于沉积生长，本实施例中，所述衬垫金属层120的材料为纯金属，从而便于采用第一选择性沉积工艺在衬垫金属层120上形成所述栅极插塞200。
作为一实施例，所述衬垫金属层120的材料包括钨（W）、钌（Ru）或钼（Mo）。所述衬垫金属层的材料不仅限于此，任何能够使得形成栅极插塞的第一选择性沉积工艺易于沉积生长的金属材料均可适用。
本实施例中，在半导体结构的形成过程中，在形成所述衬垫金属层120的步骤中，随着所述衬垫金属层120材料在所述栅极结构110的顶面的沉积厚度逐渐增加，所述衬垫金属层120的材料还会向所述栅极结构110顶面的周围延伸，因此，所述衬垫金属层120还位于所述栅介质层113的顶面和侧墙130的部分顶面上。
需要说明的是，所述衬垫金属层120的厚度不宜过小，也不宜过大。如果所述衬垫金属层120的厚度过小，则容易导致所述衬垫金属层120的薄膜连续性较差；如果所述衬垫金属层120的厚度过大，则容易产生不必要的材料和时间的浪费，而且还容易导致衬垫金属层120向所述栅极结构110的两侧延伸生长得过多，容易增加漏电的风险。为此，本实施例中，所述衬垫金属层120的厚度为1.5nm至3nm，例如：2nm、2.3nm、2.5nm、2.8nm等。
作为一实施例，所述衬垫金属层120中含有氯元素。
作为一实施例，所述衬垫金属层120的材料为钨，所述衬垫金属层120中含有氯元素，是由于在衬垫金属层120的形成过程中，采用第二选择性沉积工艺，形成所述衬垫金属层120，并且，所述第二选择性沉积工艺的反应气体包括WCl 5。
在衬垫金属层120的形成过程中，第二选择性沉积工艺，利用衬垫金属层120的材料在金属材料和非金属材料上的生长差异，能够选择性地仅在所述栅极结构110的顶面上形成所述衬垫金属层120，而不会在栅极侧墙130或底部介质层150的顶面上形成衬垫金属层的材料，从而无需进行图形化或刻蚀的工艺制程，简化了衬垫金属层120的形成工艺。其中，所述金属材料包括纯金属材料、金属合金材料以及金属化合物材料。
其中，采用WCl 5作为选择性沉积钨的反应体，WCl 5气体对选择性沉积工艺的沉积衬底要求较低，有利于钨在具有复杂的膜层结构的栅极结构110顶面上的沉积生长。WCl 5气体对选择性沉积工艺的沉积衬底要求较低指的是，采用作为WCl 5反应气体，能够以复杂的膜层结构作为沉积衬底，无需要求沉积衬底为单一的膜层结构。
具体地，在半导体领域中，通常采用氟化钨气体作为选择性沉积钨的反应气体，在采用氟化钨作为反应气体、进行选择性沉积钨的过程中，氟化钨容易对所述栅极结构110中的功函数层112进行腐蚀，导致栅极结构110受损、栅极结构110的结构完整性无法得到保障，钨与栅极结构110之间的接触性能较差，相应地，钨也难以沉积在栅极结构110的功函数层112上。
本实施例中，所述第二选择性沉积工艺的反应气体包括WCl 5，从而避免采用氟化钨作为选择性沉积钨的反应气体，相应有利于钨在栅极结构110顶面上的沉积，尤其是有利于钨在功函数层112上的沉积。
所述顶部介质层160用于实现相邻栅极插塞200之间的电隔离。
所述顶部介质层160的材料为介电材料，例如：所述顶部介质层160的材料包括低k介质材料（低k介质材料指相对介电常数大于或等于2.6且小于等于3.9的介质材料）、超低k介质材料（超低k介质材料指相对介电常数小于2.6的介质材料）、氧化硅、氮化硅和氮氧化硅中的任意一种或多种。
所述顶部介质层160可以为单层或叠层结构。
作为一种示例，所述顶部介质层160包括：第一介质层50，位于所述底部介质层150上且覆盖所述衬垫金属层120；第二介质层70，位于所述第一介质层50上。
本实施例中，所述半导体结构还包括：源漏互连层170，贯穿所述源漏掺杂区140顶部上的底部介质层150以及所述第一介质层50，且所述源漏互连层170与所述源漏掺杂区140相接触。
所述源漏互连层170用于实现源漏掺杂区140与外部电路之间的电连接。
所述源漏互连层170的材料为导电材料，例如：W、Co、Ru、Cu和Al中的一种或多种。作为一种示例，所述源漏互连层170的材料为W。
本实施例中，所述源漏互连层170的侧壁和底部还形成有防扩散阻挡层180。所述防扩散阻挡层180用于防止源漏互连层170的材料向底部介质层150或第一介质层50中扩散，从而改善电迁移的问题。
作为一种示例，所述防扩散阻挡层180的材料包括Ta、Ti、TaN和TiN中的一种或多种。
相应地，所述第一介质层50还用于实现相邻源漏互连层170之间的电隔离。
本实施例中，所述顶部介质层160还包括：第一刻蚀停止层40，位于所述底部介质层150与所述第一介质层50之间、以及衬垫金属层120与第一介质层50之间。具体地，所述第一刻蚀停止层40还位于所述栅极侧墙130与所述第一介质层50之间。
在形成贯穿第一介质层50和第二介质层70且与所述衬垫金属层120相接触的栅极插塞200的过程中，所述第一刻蚀停止层40用于暂时定义刻蚀停止位置的作用，从而降低衬垫金属层120受损的几率；所述第一刻蚀停止层40还用于密封衬垫金属层120以及栅极结构110的顶部，以免衬垫金属层120和栅极结构110的顶面受到外界工艺环境的影响。
所述第一刻蚀停止层40选用与第一介质层50和第二介质层70之间均具有刻蚀选择性的材料。作为一种示例，所述第一刻蚀停止层40的材料为氮化硅。
本实施例中，所述顶部介质层160还包括：第二刻蚀停止层60，位于所述第一介质层50和第二介质层70之间。具体地，所述第二刻蚀停止层60还位于所述源漏互连层170与第二介质层70之间。
所述半导体结构通常还包括：贯穿所述第二介质层70且与所述源漏互连层170相接触的源漏插塞，所述第二刻蚀停止层60用于在形成源漏插塞的过程中，暂时定义刻蚀停止的位置，以降低源漏互连层170受损的几率。
栅极插塞200用于实现栅极结构110与外部电路之间的电连接。
本实施例中，栅极插塞200的材料为导电材料，例如：W和Ru中的一种或两种。作为一实施例，栅极插塞200的材料与所述衬垫金属层120的材料相同，能够使得第一选择性沉积工艺更易于在所述衬垫金属层120上沉积生长，进一步降低采用第一选择性沉积工艺形成栅极插塞200的难度。
本实施例中，所述半导体结构还包括：源漏插塞210，贯穿所述第二介质层70且与所述源漏互连层170相接触。
所述源漏插塞210用于实现源漏互连层170与外部电路之间的电连接。
所述源漏插塞210的材料为导电材料，例如：W、Co、Ru、Cu和Al中的一种或多种。作为一实施例，所述源漏插塞210的材料与所述栅极插塞200的材料相同。
本实施例中，所述源漏插塞210的材料与所述栅极插塞200的材料相同，是由于在半导体结构的形成过程中，在同一步骤中，形成源漏插塞210和栅极插塞200，从而提高工艺整合度，并简化工艺步骤。
相应的，本发明还提供一种半导体结构的形成方法。图4至图9是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
以下结合附图，对本实施例半导体结构的形成方法进行详细说明。
参考图4，提供基底100，所述基底100上形成有栅极结构110，所述栅极结构110两侧的基底100内形成有源漏掺杂区140，所述源漏掺杂区140上形成有位于相邻所述栅极结构110之间的底部介质层150。
基底100用于为后续工艺制程提供工艺平台。
本实施例中，基底100用于形成鳍式场效应晶体管（FinFET），基底100为立体型基底，包括衬底（图未示）和凸出于衬底的鳍部105，所述鳍部105用于提供场效应晶体管的导电沟道。
本实施例中，所述衬底为硅衬底。在其他实施例中，衬底的材料还可以为锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
所述鳍部105的材料包括：单晶硅、锗、锗化硅、碳化硅、氮化镓、砷化镓和镓化铟中的一种或多种。本实施例中，所述鳍部105的材料为单晶硅。
本实施例中，所述鳍部105与所述衬底为一体型结构。
在其他实施例中，所述基底还可以用于形成其他类型的晶体管。例如：当形成全包围栅极晶体管时，所述基底包括衬底、凸出于衬底的凸起部以及位于凸起部上的沟道结构层，沟道结构层与凸起部之间具有间隔，所述沟道结构层包括一个或多个间隔设置的沟道层。所述沟道层用于提供场效应晶体管的导电沟道。
本实施例中，所述衬底上还形成有围绕鳍部105的隔离层（图未示），所述隔离层的顶面低于所述鳍部105的顶面，从而使得被所述隔离层露出的所述鳍部105作为有效鳍部（Active Fin），有效鳍部用于提供场效应晶体管的导电沟道。
所述隔离层用于隔离相邻的鳍部105，还用于隔离所述衬底与所述栅极结构110。
本实施例中，所述隔离层为浅沟槽隔离结构（Shallow trench isolation，STI）。本实施例中，所述隔离层的材料为氧化硅。在其他实施例中，所述隔离层的材料还可以是氮化硅或氮氧化硅等其他绝缘材料。
在场效应晶体管工作时，栅极结构110用于控制导电沟道的开启和关断。
本实施例中，所述栅极结构110位于所述隔离层上，横跨所述鳍部105且覆盖所述鳍部105的部分顶部和部分侧壁。
在其他实施例中，当形成其他类型的晶体管时，例如：当形成全包围栅极晶体管时，所述栅极结构横跨所述沟道结构层且包围所述沟道层。
作为一实施例，所述栅极结构110为金属栅极结构115。所述金属栅极结构115包括功函数层112，或者，所述金属栅极结构115包括金属电极层111以及位于所述金属电极层111的底部和侧壁的功函数层112。在其他实施例中，栅极结构还可以为其他类型的栅极结构。
相应地，暴露出的所述栅极结构110的顶面为功函数层112的顶面，或者，为金属电极层111的顶面和功函数层112的顶面。
作为一种示例，所述金属栅极结构115包括金属电极层111以及位于所述金属电极层111的底部和侧壁的功函数层112，暴露出的所述栅极结构110的顶面为金属电极层111的顶面和功函数层112的顶面。
所述功函数层112用于调节金属栅极结构115的功函数。所述功函数层112的材料包括TiAl、TaAlN、TiAlN、MoN、TaCN、AlN、Ta、TiN、TaN、TaSiN和TiSiN中的任意一种或多种。
所述金属电极层111的材料为导电材料。例如：W、Al、Cu、Ag、Au、Pt、Ni和Ti中的一种或多种。
本实施例中，所述栅极结构110的侧壁上还形成有栅极侧墙130。
所述栅极侧墙130用于定义所述源漏掺杂区140的形成区域，还用于在对所述栅极结构110的侧壁起到保护作用。
所述栅极侧墙130可以为单层或叠层结构。所述栅极侧墙130的材料可以为氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的任意一种或多种。
作为一实施例，所述栅极侧墙130为叠层结构，所述栅极侧墙130包括位于所述栅极结构110侧壁上的第一侧墙20以及位于所述第一侧墙20侧壁上的第二侧墙30。具体地，所述第一侧墙20和第二侧墙30的材料不同。例如：第一侧墙20的材料为氧化硅，第二侧墙30的材料为氮化硅。
本实施例中，所述栅极结构110与所述基底100之间还形成有栅介质层113。所述栅介质层113用于实现栅极结构110与导电沟道之间的电隔离。
本实施例中，所述栅介质层113还形成于所述栅极结构110与所述栅极侧墙130之间。
本实施例中，栅介质层113的材料包括氧化硅、掺氮氧化硅、HfO 2、ZrO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La 2O 3和Al 2O 3中的一种或多种。
在器件工作时，所述源漏掺杂区140用于作为场效应晶体管的源区和漏区，用于提供载流子源。
本实施例中，所述源漏掺杂区140位于所述栅极结构110两侧的鳍部105内。在其他实施例中，当基底包括沟道结构层时，源漏掺杂区位于栅极结构两侧且与沟道结构层沿延伸方向的端部相接触。
本实施例中，所述源漏掺杂区140包括掺杂有离子的应力层，所述源漏掺杂区150还用于为沟道提供应力，从而提高沟道的载流子迁移率。
具体地，当形成NMOS晶体管时，源漏掺杂区140的材料为掺杂有N型离子的应力层，所述应力层的材料包括Si或SiC，应力层为NMOS晶体管的沟道区提供拉应力作用，从而有利于提高NMOS晶体管的载流子迁移率，其中，所述N型离子为P离子、As离子或Sb离子。
当形成PMOS晶体管时，所述源漏掺杂区140的材料为掺杂有P型离子的应力层，应力层的材料包括Si或SiGe，所述应力层为PMOS晶体管的沟道区提供压应力作用，从而有利于提高PMOS晶体管的载流子迁移率，其中，所述P型离子为B离子、Ga离子或In离子。
所述底部介质层150用于实现相邻器件之间的隔离。本实施例中，所述底部介质层150为层间介质层（ILD）。所述底部介质层150的材料为介电材料，例如：氧化硅、氮氧化硅等。
本实施例中，所述底部介质层150暴露出所述栅极结构110的顶面。
参考图5，在所述栅极结构110的顶面上形成与所述栅极结构110相接触衬垫金属层120，所述衬垫金属层120的材料为纯金属。
在所述栅极结构110的顶面上形成衬垫金属层120，所述衬垫金属层120的材料为纯金属，从而使得栅极结构110的顶部上为单一的金属材料表面，相应地，所述衬垫金属层120能够为后续采用第一选择性沉积工艺形成栅极插塞提供良好的形成界面和沉积衬底，有利于所述栅极插塞的材料在所述衬垫金属层120上的沉积生长，进而有利于降低采用第一选择性沉积工艺形成栅极插塞的难度、提高栅极插塞的形成质量，器件的性能得到了提升。
并且，在半导体领域中，相较于采用选择性沉积工艺在金属化合物上沉积栅极插塞的材料相比，采用选择性沉积工艺在纯金属上更易于沉积生长，本实施例中，所述衬垫金属层120的材料为纯金属，从而便于后续采用第一选择性沉积工艺在衬垫金属层120上形成栅极插塞。
作为一实施例，所述衬垫金属层120的材料包括钨（W）、钌（Ru）或钼（Mo）。所述衬垫金属层的材料不仅限于此，任何能够使得形成栅极插塞的第一选择性沉积工艺易于沉积生长的金属材料均可适用。
本实施例中，在形成所述衬垫金属层120的步骤中，随着所述衬垫金属层120材料在所述栅极结构110的顶面的沉积厚度逐渐增加，所述衬垫金属层120的材料还会向所述栅极结构110顶面的周围延伸，因此，所述衬垫金属层120还形成在所述栅介质层113的顶面和侧墙130的部分顶面上。
需要说明的是，所述衬垫金属层120的厚度不宜过小，也不宜过大。如果所述衬垫金属层120的厚度过小，则容易导致所述衬垫金属层120的薄膜连续性较差；如果所述衬垫金属层120的厚度过大，则容易产生不必要的材料和时间的浪费，而且还容易导致衬垫金属层120向所述栅极结构110的两侧延伸生长得过多，容易增加漏电的风险。为此，本实施例中，所述衬垫金属层120的厚度为1.5nm至3nm，例如：2nm、2.3nm、2.5nm、2.8nm等。
作为一实施例，采用第二选择性沉积工艺，形成所述衬垫金属层120。第二选择性沉积工艺，利用衬垫金属层120的材料在金属材料和非金属材料上的生长差异，能够选择性地仅在所述栅极结构110的顶面上形成所述衬垫金属层120，而不会在栅极侧墙130或底部介质层150的顶面上形成衬垫金属层的材料，从而无需进行图形化或刻蚀的工艺制程，简化了工艺流程。其中，所述金属材料包括纯金属材料、金属合金材料以及金属化合物材料。
作为一实施例，所述衬垫金属层120的材料为钨，所述第二选择性沉积工艺的参数包括：反应气体包括WCl 5和H 2。
其中，采用WCl 5作为选择性沉积钨的反应体，WCl 5气体对选择性沉积工艺的沉积衬底要求较低，有利于钨在具有复杂的膜层结构的栅极结构110顶面上的沉积生长。WCl 5气体对选择性沉积工艺的沉积衬底要求较低指的是，采用作为WCl 5反应气体，能够以复杂的膜层结构作为沉积衬底，无需要求沉积衬底为单一的膜层结构。
具体地，在半导体领域中，通常采用氟化钨气体作为选择性沉积钨的反应气体，在采用氟化钨作为反应气体、进行选择性沉积钨的过程中，氟化钨容易对所述栅极结构110中的功函数层112进行腐蚀，导致栅极结构110受损、栅极结构110的结构完整性无法得到保障，钨与栅极结构110之间的接触性能较差，相应地，钨也难以沉积在栅极结构110的功函数层112上。
本实施例中，所述第二选择性沉积工艺的反应气体为WCl 5，从而避免采用氟化钨作为选择性沉积钨的反应气体，相应有利于钨在栅极结构110顶面上的沉积，尤其是有利于钨在功函数层112上的沉积。
作为一实施例，所述第二选择性沉积工艺包括原子层沉积工艺。原子层沉积工艺是基于原子层沉积过程的自限制反应过程，沉积所得薄膜可以达到单层原子的厚度，并且由于原子层沉积工艺在每个周期内可精确地沉积一个原子层，从而有利于对衬垫金属层120的厚度进行精确控制，并且，原子层沉积工艺制备的薄膜还具有结合强度好、厚度一致性高等优点。
需要说明的是，以上形成衬垫金属层120的步骤仅作为一种示例进行说明，形成衬垫金属层120的步骤不仅限于此。例如：形成衬垫金属层的步骤还可以包括：在所述底部介质层和所述栅极结构上形成衬垫金属材料层；去除位于所述底部介质层上的衬垫金属材料层，保留位于所述栅极结构顶面上的衬垫金属材料层用于作为所述衬垫金属层。
参考图6至图7，在所述底部介质层150上形成顶部介质层160，所述顶部介质层160覆盖所述衬垫金属层120。
后续形成贯穿所述顶部介质层160且与所述衬垫金属层120相接触的栅极插塞，所述顶部介质层160用于实现相邻栅极插塞之间的电隔离。
所述顶部介质层160的材料为介电材料，例如：所述顶部介质层160的材料包括低k介质材料（低k介质材料指相对介电常数大于或等于2.6且小于等于3.9的介质材料）、超低k介质材料（超低k介质材料指相对介电常数小于2.6的介质材料）、氧化硅、氮化硅和氮氧化硅中的任意一种或多种。
所述顶部介质层160可以为单层或叠层结构。
作为一种示例，形成所述顶部介质层160的步骤包括以下步骤。
如图6所示，在所述底部介质层150上形成第一介质层50，覆盖所述衬垫金属层120。
本实施例中，在所述底部介质层150上形成第一介质层50之前，还在所述底部介质层150上形成覆盖所述衬垫金属层120的第一刻蚀停止层40。
在后续形成贯穿第一介质层50和第二介质层70且与所述衬垫金属层120相接触的栅极插塞的过程中，所述第一刻蚀停止层40用于暂时定义刻蚀停止位置的作用，从而降低衬垫金属层120受损的几率；所述第一刻蚀停止层40还用于密封衬垫金属层120以及栅极结构110的顶部，以免衬垫金属层120和栅极结构110的顶面受到外界工艺环境的影响。
所述第一刻蚀停止层40选用与第一介质层50和第二介质层70之间均具有刻蚀选择性的材料。作为一种示例，所述第一刻蚀停止层40的材料为氮化硅。
需要说明的是，如图6所示，本实施例中，所述半导体结构的形成方法还包括：在形成所述第一介质层50之后，形成贯穿所述源漏掺杂区140顶部上的底部介质层150和所述第一介质层50的源漏互连层170，所述源漏互连层170与所述源漏掺杂区140相接触。
所述源漏互连层170用于实现源漏掺杂区140与外部电路之间的电连接。
所述源漏互连层170的材料为导电材料，例如：W、Co、Ru、Cu和Al中的一种或多种。作为一种示例，所述源漏互连层170的材料为W。
具体地，形成源漏互连层170的步骤包括：形成贯穿所述源漏掺杂区140顶部上的底部介质层150和所述第一介质层50的源漏互连槽（图未示），所述源漏互连槽暴露出所述源漏掺杂区140；在所述源漏互连槽中形成所述源漏互连层170。
其中，本实施例中，在形成源漏互连槽之后，在所述源漏互连槽中形成所述源漏互连层170，所述形成方法还包括：在所述源漏互连槽的底部和侧壁上形成防扩散阻挡层180。所述防扩散阻挡层180用于防止源漏互连层170的材料向底部介质层150或第一介质层50中扩散，从而改善电迁移的问题。
作为一种示例，所述防扩散阻挡层180的材料包括Ta、Ti、TaN和TiN中的一种或多种。
还需要说明的是，在形成所述第一介质层50之后，所述形成方法还包括：在所述第一介质层50上形成第二刻蚀停止层60，第二刻蚀停止层60覆盖所述源漏互连层170。在后续形成贯穿所述第二介质层70且与所述源漏互连层170相接触的源漏插塞的过程中，所述第二刻蚀停止层60用于暂时定义刻蚀停止的位置，以降低源漏互连层170受损的几率。
如图7所示，在所述第一介质层50上形成第二介质层70。
具体地，第二介质层70形成在所述第二刻蚀停止层60上。
需要说明的是，本实施例中，以顶部介质层160为叠层结构为示例进行说明。在其他实施例中，所述顶部介质层还可以是单层结构。
参考图8和图9，采用第一选择性沉积工艺，形成贯穿所述顶部介质层160且与所述衬垫金属层120相接触的栅极插塞200。
栅极插塞200用于实现栅极结构110与外部电路之间的电连接。
本实施例中，所述栅极结构110的顶面上形成有衬垫金属层120，所述衬垫金属层120的材料为纯金属，从而使得栅极结构110的顶部上为单一的金属材料表面，能够为采用第一选择性沉积工艺形成所述栅极插塞200提供良好的形成界面和沉积衬底，有利于所述栅极插塞200的材料在所述衬垫金属层120上的沉积生长，进而有利于降低采用第一选择性沉积工艺形成栅极插塞200的难度、提高栅极插塞200的形成质量，器件的性能得到了提升。
本实施例中，栅极插塞200的材料为导电材料，例如：W和Ru中的一种或两种。作为一实施例，栅极插塞200的材料与所述衬垫金属层120的材料相同，能够使得第一选择性沉积工艺更易于在所述衬垫金属层120上沉积生长，进一步降低采用第一选择性沉积工艺形成栅极插塞200的难度。
本实施例中，在形成所述栅极插塞200的步骤中，还形成贯穿所述第二介质层70且与所述源漏互连层170相接触的源漏插塞210。源漏插塞210用于实现源漏互连层170与外部电路之间的电连接。
所述源漏插塞210的材料为导电材料，例如：W、Co、Ru、Cu和Al中的一种或多种。作为一实施例，所述源漏插塞210的材料与所述栅极插塞200的材料相同。
以下结合附图，对本实施例形成栅极插塞200的步骤进行详细说明。
如图8所示，形成贯穿所述顶部介质层160的栅极接触孔230，所述栅极接触孔230暴露出所述衬垫金属层120。
栅极接触孔230用于为形成栅极插塞提供空间位置。
本实施例中，在形成栅极接触孔230的步骤中，还形成贯穿所述第二介质层70的源漏接触孔220，暴露出所述源漏互连层170。
源漏接触孔220用于为形成源漏插塞提供空间位置。
如图9所示，采用第一选择性沉积工艺，在所述栅极接触孔230中形成与所述衬垫金属层120相接触的所述栅极插塞200。
通过采用第一选择性沉积工艺，从而能够选择性地仅在所述栅极接触孔230暴露出的所述衬垫金属层120上沉积栅极插塞200的材料，无需进行去除位于顶部介质层160顶面上的栅极插塞的材料，简化了工艺流程。
与传统的阻挡层导线制造相比，采用第一选择性沉积工艺能够实现自底而上的金属对金属沉积，从而有利于栅极插塞200体积的最大化，栅极插塞200电阻率得到了显著改善，较低的电阻率有利于提高器件密度并延伸了二维微缩。
具体地，本实施例中，采用第一选择性沉积工艺，在所述栅极接触孔230中形成所述栅极插塞200、以及在所述源漏接触孔220中形成所述源漏插塞210。
通过在同一步骤中，采用第一选择性沉积工艺形成所述栅极插塞200和源漏插塞210，提高工艺兼容性和工艺整合度。
具体地，在所述第一选择性沉积工艺的过程中，利用栅极插塞200和源漏插塞210的材料在金属材料上和非金属材料上的孵化（incubation）时间差，使得能够仅在栅极接触孔230中和源漏接触孔220中沉积导电材料。
作为一种示例，所述第一选择性沉积工艺包括选择性化学气相沉积工艺。
更具体地，本实施例中，所述栅极插塞200和源漏插塞210的材料为钨，所述第一选择性沉积工艺为选择性钨化学气相沉积(Selective W CVD)工艺。
所述源漏插塞210与所述源漏互连层170用于构成源漏接触结构，以实现源漏掺杂区与外部电路之间的电性连接。
需要说明的是，以上形成源漏接触结构的步骤仅作为一种示例，形成源漏接触结构的步骤不仅限于此。例如：在其他实施例中，形成源漏接触结构的步骤还可以包括：在形成顶部介质层之前，在所述底部介质层中形成与所述源漏掺杂区相接触的源漏互连层；在形成顶部介质层之后，在顶部介质层中形成与所述源漏互连层相接触的源漏插塞。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (22)

  1. 一种半导体结构，其特征在于，包括：
    基底；
    栅极结构，位于所述基底上；
    源漏掺杂区，位于所述栅极结构两侧的所述基底内；
    底部介质层，位于相邻所述栅极结构之间且覆盖所述源漏掺杂区；
    衬垫金属层，位于所述栅极结构的顶面上且与所述栅极结构相接触，所述衬垫金属层的材料为纯金属；
    顶部介质层，位于所述底部介质层上且覆盖所述衬垫金属层；
    栅极插塞，贯穿所述顶部介质层且与所述衬垫金属层相接触。
  2. 如权利要求1所述的半导体结构，其特征在于，所述衬垫金属层的材料包括钨、钌或钼。
  3. 如权利要求1所述的半导体结构，其特征在于，所述衬垫金属层的厚度为1.5nm至3nm。
  4. 如权利要求1所述的半导体结构，其特征在于，所述衬垫金属层中含有氯元素。
  5. 如权利要求1所述的半导体结构，其特征在于，所述栅极插塞的材料与所述衬垫金属层的材料相同。
  6. 如权利要求1所述的半导体结构，其特征在于，所述栅极插塞的材料包括钨和钌中的一种或两种。
  7. 如权利要求1所述的半导体结构，其特征在于，所述栅极结构为金属栅极结构；所述金属栅极结构包括功函数层，或者，所述金属栅极结构包括金属电极层以及位于所述金属电极层的底部和侧壁的功函数层。
  8. 如权利要求7所述的半导体结构，其特征在于，所述功函数层的材料包括：TiAl、TaAlN、TiAlN、MoN、TaCN、AlN、Ta、TiN、TaN、TaSiN和TiSiN中的任意一种或多种；所述金属电极层的材料包括W、Al、Cu、Ag、Au、Pt、Ni和Ti中的一种或多种。
  9. 如权利要求7所述的半导体结构，其特征在于，所述半导体结构还包括：栅极侧墙，位于所述栅极结构的侧壁上；
    栅介质层，位于所述栅极结构与所述基底之间。
  10. 如权利要求1所述的半导体结构，其特征在于，所述顶部介质层包括：第一介质层，位于所述底部介质层上且覆盖所述衬垫金属层；第二介质层，位于所述第一介质层上；
    所述半导体结构还包括：源漏互连层，贯穿所述源漏掺杂区顶部上的底部介质层以及所述第一介质层，且所述源漏互连层与所述源漏掺杂区相接触；源漏插塞，贯穿所述第二介质层且与所述源漏互连层相接触。
  11. 如权利要求1所述的半导体结构，其特征在于，所述基底包括鳍部，所述栅极结构横跨所述鳍部，所述源漏掺杂区位于所述栅极结构两侧的鳍部内；
    或者，所述基底包括沟道结构层，所述沟道结构层包括一个或多个间隔设置的沟道层；所述栅极结构横跨所述沟道结构层且包围所述沟道层。
  12. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底，所述基底上形成有栅极结构，所述栅极结构两侧的基底内形成有源漏掺杂区，所述源漏掺杂区上形成有位于相邻所述栅极结构之间的底部介质层；
    在所述栅极结构的顶面上形成与所述栅极结构相接触衬垫金属层，所述衬垫金属层的材料为纯金属；
    在所述底部介质层上形成顶部介质层，所述顶部介质层覆盖所述衬垫金属层；
    采用第一选择性沉积工艺，形成贯穿所述顶部介质层且与所述衬垫金属层相接触的栅极插塞。
  13. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述衬垫金属层的材料包括钨、钌或钼。
  14. 如权利要求12所述的半导体结构的形成方法，其特征在于，采用第二选择性沉积工艺，形成所述衬垫金属层。
  15. 如权利要求14所述的半导体结构的形成方法，其特征在于，所述衬垫金属层的材料为钨，所述第二选择性沉积工艺的参数包括：反应气体包括WCl 5和H 2。
  16. 如权利要求14所述的半导体结构的形成方法，其特征在于，所述第二选择性沉积工艺包括原子层沉积工艺。
  17. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述栅极插塞的材料与所述衬垫金属层的材料相同。
  18. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述栅极插塞的材料包括钨和钌中的一种或两种。
  19. 如权利要求12所述的半导体结构的形成方法，其特征在于，形成栅极插塞的步骤包括：形成贯穿所述顶部介质层的栅极接触孔，所述栅极接触孔暴露出所述衬垫金属层；采用第一选择性沉积工艺，在所述栅极接触孔中形成与所述衬垫金属层相接触的所述栅极插塞。
  20. 如权利要求12所述的半导体结构的形成方法，其特征在于，所述第一选择性沉积工艺包括选择性化学气相沉积工艺。
  21. 如权利要求12所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述栅极结构为金属栅极结构；所述金属栅极结构包括功函数层，或者，所述金属栅极结构包括金属电极层以及位于所述金属电极层的底部和侧壁的功函数层。
  22. 如权利要求12所述的半导体结构的形成方法，其特征在于，形成所述顶部介质层的步骤包括：在所述底部介质层上形成第一介质层，覆盖所述衬垫金属层；在所述第一介质层上形成第二介质层；
    所述半导体结构的形成方法还包括：在形成所述第一介质层之后，在形成所述第二介质层之前，形成贯穿所述源漏掺杂区顶部上的底部介质层和所述第一介质层的源漏互连层，所述源漏互连层与所述源漏掺杂区相接触；
    在形成贯穿所述顶部介质层且与所述衬垫金属层相接触的栅极插塞的步骤中，还形成贯穿所述第二介质层且与所述源漏互连层相接触的源漏插塞。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140191298A1 (en) * 2013-01-10 2014-07-10 United Microelectronics Corp. Semiconductor device and manufacturing method of the same
CN108695257A (zh) * 2017-04-06 2018-10-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109087885A (zh) * 2017-06-14 2018-12-25 Asm Ip 控股有限公司 金属膜的选择性沉积
CN109427677A (zh) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110767803A (zh) * 2019-10-15 2020-02-07 北京元芯碳基集成电路研究院 一种碳纳米管器件源漏金属全局制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140191298A1 (en) * 2013-01-10 2014-07-10 United Microelectronics Corp. Semiconductor device and manufacturing method of the same
CN108695257A (zh) * 2017-04-06 2018-10-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109087885A (zh) * 2017-06-14 2018-12-25 Asm Ip 控股有限公司 金属膜的选择性沉积
CN109427677A (zh) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110767803A (zh) * 2019-10-15 2020-02-07 北京元芯碳基集成电路研究院 一种碳纳米管器件源漏金属全局制作方法

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