WO2022267491A1 - 像素驱动电路及其驱动方法、显示面板及终端设备 - Google Patents

像素驱动电路及其驱动方法、显示面板及终端设备 Download PDF

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Publication number
WO2022267491A1
WO2022267491A1 PCT/CN2022/076208 CN2022076208W WO2022267491A1 WO 2022267491 A1 WO2022267491 A1 WO 2022267491A1 CN 2022076208 W CN2022076208 W CN 2022076208W WO 2022267491 A1 WO2022267491 A1 WO 2022267491A1
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Prior art keywords
transistor
module
light
light emission
reset
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PCT/CN2022/076208
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English (en)
French (fr)
Inventor
苏懿
安亚斌
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荣耀终端有限公司
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Application filed by 荣耀终端有限公司 filed Critical 荣耀终端有限公司
Priority to EP22827000.5A priority Critical patent/EP4195188A1/en
Priority to US18/043,615 priority patent/US11961453B2/en
Publication of WO2022267491A1 publication Critical patent/WO2022267491A1/zh

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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Definitions

  • the embodiments of the present application relate to the field of terminal technologies, and in particular, to a pixel driving circuit and a driving method thereof, a display panel, and a terminal device.
  • terminal devices such as mobile phones have become more commonly used tools in people's life and work.
  • Display panels are an important part of terminal devices, and their display effects have an important impact on the use of terminal devices.
  • the terminal device when the terminal device is displayed at low brightness (for example, the brightness is less than 2 nits), users can easily observe frequent flickering of the screen, which makes the user's eyes prone to fatigue when viewing.
  • Embodiments of the present application provide a pixel driving circuit and its driving method, a display panel, and a terminal device, which are applied to the terminal device to improve the problem of frequent screen flickering during low-brightness display.
  • the embodiment of the present application proposes a pixel driving circuit, which is used to drive light-emitting devices to emit light.
  • the pixel driving circuit includes: a first reset module, a light-emitting control module, and a driving module; the first reset module is respectively connected to the light-emitting control signal terminal , the first initialization signal terminal is connected to the first terminal of the light-emitting device, and is used to turn on under the control of the light-emitting control signal input from the light-emitting control signal terminal, and the first initialization signal input through the first initialization signal terminal has an effect on the first
  • the light emitting control module is connected to the light emitting control signal end, the driving module and the first end of the light emitting device respectively, and is used to turn on under the control of the light emitting control signal input by the light emitting control signal end, and drive the light emitting device to emit light through the driving module ; Wherein, one of the first reset module and the light-emitting control module is turned on when the light-emit
  • the pixel driving circuit of the present application includes a first reset module, a light emission control module and a driving module. Both the first reset module and the light emission control module are connected to the light emission control signal terminal, one of which is turned on when the light emission control signal is at a high level, and the other The latter is turned on when the light-emitting control signal is at a low level. Therefore, by increasing the frequency of the light-emitting control signal to greater than 120HZ, the problem of frequent flickering of the screen during low-brightness display can be improved, and the user’s eyes are prone to fatigue when watching The phenomenon.
  • the lighting control module includes a first lighting control unit and a second lighting control unit; the control terminal of the first lighting control unit is connected to the lighting control signal terminal, and the first terminal of the first lighting control unit is connected to the first voltage signal terminal connection, the second terminal of the first lighting control unit is connected to the first terminal of the driving module; the control terminal of the second lighting control unit is connected to the lighting control signal terminal, and the first terminal of the second lighting control unit is connected to the second terminal of the driving module.
  • the terminals are connected, and the second terminal of the second lighting control unit is connected to the first terminal of the light emitting device.
  • the light-emitting device is jointly controlled by the first light-emitting control unit and the second light-emitting control unit to emit light.
  • the first reset module includes a first reset transistor, the gate of the first reset transistor is connected to the light emission control signal terminal, the first electrode of the first reset transistor is connected to the first initialization signal terminal, and the first reset transistor of the first reset transistor is connected to the first initialization signal terminal.
  • the two poles are connected to the first end of the light emitting device;
  • the first light emission control unit includes a first light emission control transistor, the gate of the first light emission control transistor is connected to the light emission control signal terminal, and the first electrode of the first light emission control transistor is connected to the first light emission control transistor.
  • the voltage signal terminal is connected, the second pole of the first light emission control transistor is connected to the first end of the driving module; the second light emission control unit includes a second light emission control transistor, the gate of the second light emission control transistor is connected to the light emission control signal end, The first pole of the second light emission control transistor is connected to the second end of the driving module, and the second pole of the second light emission control transistor is connected to the first end of the light emitting device.
  • the first reset transistor is an N-type transistor
  • both the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors.
  • the first reset transistor is a P-type transistor
  • both the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors.
  • the drive module includes a drive transistor, the first pole of the drive transistor is connected to the second terminal of the first light emission control unit, and the second pole of the drive transistor is connected to the first terminal of the second light emission control unit.
  • the pixel drive circuit also includes: a data writing module, a second reset module, a threshold compensation module and a storage module;
  • the second reset module is connected to the reset signal terminal, the second initialization signal terminal and the control terminal of the drive module respectively , used to turn on under the control of the reset signal input from the reset signal terminal, and reset the control terminal of the drive module through the second initialization signal input from the second initialization signal terminal;
  • the data writing module is connected to the first scan signal terminal, The data signal end is connected to the first end of the drive module, and is used to turn on under the control of the first scan signal input by the first scan signal end, and write the data signal input by the data signal end to the drive module;
  • the threshold compensation module is respectively connected with The second scanning signal terminal, the second terminal of the driving module and the control terminal of the driving module are connected to be turned on under the control of the second scanning signal input by the second scanning signal terminal, and the threshold voltage of the driving module is compensated;
  • the storage module the first voltage signal terminal is respectively connected to the control terminal
  • the data writing module includes a data writing transistor, the gate of the data writing transistor is connected to the first scan signal terminal, the first electrode of the data writing transistor is connected to the data signal terminal, and the second pole of the data writing transistor is connected to the data signal terminal.
  • the pole is connected with the first end of the driving module.
  • the second reset module includes a second reset transistor, the gate of the second reset transistor is connected to the reset signal terminal, the first pole of the second reset transistor is connected to the second initialization signal terminal, and the second The pole is connected to the control terminal of the drive module.
  • the threshold compensation module includes a compensation transistor, the gate of the compensation transistor is connected to the second scanning signal terminal, the first pole of the compensation transistor is connected to the second terminal of the driving module, and the second pole of the compensation transistor is connected to the control terminal of the driving module. end connection.
  • the storage module includes a storage capacitor, the first plate of the storage capacitor is connected to the first voltage signal terminal, and the second plate of the storage capacitor is connected to the control terminal of the drive module.
  • the embodiment of the present application proposes a driving method, which is applied to driving the above-mentioned pixel driving circuit.
  • the driving method includes: in the reset phase, the first reset module is turned on, and the first end of the light emitting device is reset; In the entry stage, the first reset module is turned on to continue to reset the first end of the light-emitting device; in the light-emitting control stage, the light-emitting control module is turned on, and the light-emitting device is driven to emit light through the driving module.
  • the embodiment of the present application provides a display panel, including a plurality of the above-mentioned pixel driving circuits, and a light emitting device connected to each pixel driving circuit.
  • the embodiment of the present application provides a terminal device, including a casing and the above-mentioned display panel, and the display panel is installed on the casing.
  • FIG. 1 is a circuit diagram of a pixel driving circuit in the related art
  • FIG. 2 is a schematic diagram of a brightness curve when the pixel driving circuit shown in FIG. 1 drives the light emitting device to emit light;
  • FIG. 3 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 6 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 7 is a driving timing diagram corresponding to the pixel driving circuit shown in FIG. 6;
  • FIG. 8 is a circuit diagram of another pixel driving circuit provided by the embodiment of the present application.
  • FIG. 9 is a driving timing diagram corresponding to the pixel driving circuit shown in FIG. 8;
  • FIG. 10 is a schematic diagram of the brightness curve when the pixel driving circuit in the embodiment of the present application drives the light emitting device to emit light;
  • FIG. 11 is a circuit diagram of another pixel driving circuit provided by the embodiment of the present application.
  • FIG. 12 is a cascaded relationship diagram of pixel driving circuits in each row provided by the embodiment of the present application.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect.
  • the first chip and the second chip are only used to distinguish different chips, and their sequence is not limited.
  • words such as “first” and “second” do not limit the number and execution order, and words such as “first” and “second” do not necessarily limit the difference.
  • “at least one” means one or more, and “multiple” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • “At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • the pixel drive circuit includes a first reset transistor T1, a first light emission control transistor T2, a second light emission control transistor T3, a data write transistor T4, a drive transistor T5, and a second reset transistor T6. , compensation transistor T7 and storage capacitor Cst.
  • the first reset transistor T1 is a P-type transistor, the gate of the first reset transistor T1 and the gate of the data writing transistor T4 are both connected to the first scan signal terminal Scan1, and the first reset transistor T1 is used for scanning
  • the first scan signal input by the signal terminal Scan1 is turned on when it is low level, and the anode of the light emitting device EL is reset through the first initialization signal input by the first initialization signal terminal Init1;
  • the first light emission control transistor T2 and the second light emission control transistor T3 is also a P-type transistor, and the gates of the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are connected to the light-emitting control signal terminal EM, for when the light-emitting control signal input from the light-emitting control signal terminal EM is at a low level is turned on, and the light emitting device EL is driven to emit light through the driving transistor T5.
  • the display panel when the display panel is displaying at low brightness, it usually adopts pulse width modulation (Pulse Width Modulation, PWM) dimming technology to adjust the display brightness.
  • PWM Pulse Width Modulation
  • the duty cycle refers to the duration of the active level (that is, the level when the first light emission control transistor T2 and the second light emission control transistor T3 are turned on) in one cycle of the light emission control signal and the duration of the light emission control signal.
  • the ratio of the duration of the period, the luminous duration of the light-emitting device EL in the display process of a frame of image is positively correlated with the duty cycle of the light-emitting control signal, that is, the larger the duty cycle of the light-emitting control signal, the greater the duty cycle of the light-emitting device EL.
  • the frequency of the light-emitting control signal is increased from the original 120HZ to 240HZ, and the frequency of the light-emitting control signal is increased to improve the stroboscopic problem during low-brightness display.
  • the frequency of the light emission control signal is twice the frequency of the first scan signal, so that the first scan signal and the light emission control signal are not completely synchronized. Therefore, every time the first scanning signal passes through one cycle, the lighting control signal will go through two cycles. For example, as shown in FIG. 4.15ms.
  • the first scan signal and the light emission control signal are not synchronized, that is, at time A1
  • the light emission control signal changes from low level to high level, so that the first light emission control transistor T2 and the second light emission control transistor T2 T3 changes from the on state to the off state to reduce the brightness of the light emitting device EL, but at this time the first scanning signal is still maintained at a high level without any change, so that the first reset transistor T1 is still in the off state, then
  • the first reset transistor T1 cannot reset the anode of the light-emitting device EL, resulting in that the brightness of the light-emitting device EL is not reduced to 0 nits, and the brightness L1 of the light-emitting device EL can only be reduced to 1 nits; while the first scanning signal and the light-emitting control signal are synchronized , that is, at time A2, the light-emitting control signal changes from low level to high level, so that the first light-emitting control transistor T2 and the second light
  • the first scan signal It also changes from high level to low level, so that the first reset transistor T1 changes from the off state to the on state, and the first reset transistor T1 resets the anode of the light emitting device EL, so that the brightness of the light emitting device EL at this time can be adjusted. Reduced to 0nits.
  • the embodiment of the present application provides a pixel driving circuit, by connecting the light emission control module and the first reset module for resetting the light emitting device to the light emission control signal terminal EM, one of them is high when the light emission control signal is high It is usually turned on, and the other is turned on when the light-emitting control signal is at a low level, so that when the light-emitting control module is turned off, the first reset module that resets the light-emitting device EL can be turned on synchronously, that is, the first reset module and the light-emitting control module can be synchronized.
  • the light emitting control signal can reduce the brightness of the corresponding light emitting device EL to 0 nits in each cycle; and, increase the frequency of the light emitting control signal to greater than 120HZ, then
  • the changing frequency of the bright state and dark state of the light-emitting device EL in a frame display is increased, thereby improving the problem of frequent flickering of the screen during low-brightness display, and reducing the phenomenon that users are prone to eye fatigue when viewing.
  • the pixel driving circuit provided in the embodiment of the present application can be applied in a terminal device with a display function.
  • the terminal device may be a mobile phone, a tablet computer, an e-reader, a notebook computer, a vehicle-mounted device, a wearable device, a television, and the like.
  • the terminal device 100 includes a display panel 10 , a casing 20 , a circuit board 30 and a battery 40 .
  • the display panel 10 is installed on the casing 20, which is used for displaying images or videos, etc.; the display panel 10 and the casing 20 jointly enclose the receiving cavity of the terminal device 100, so that the terminal device 100 can be placed through the receiving cavity.
  • electronic devices, etc. and at the same time, it can seal and protect the electronic devices located in the accommodating cavity.
  • the circuit board 30 and the battery 40 of the terminal device 100 are located in the accommodating cavity.
  • the circuit board 30 may be a main board of the terminal device 100 , and one or more functional components such as a processor, a memory, a camera, a motor, a gyro sensor, and an acceleration sensor may be integrated on the circuit board 30 .
  • the display panel 10 is electrically connected to the circuit board 30, so as to control the display of the display panel 10 through the processor on the circuit board 30; the battery 40 is also electrically connected to the circuit board 30, and the terminal equipment is powered by the battery 40.
  • the circuit A power management module is arranged on the board 30, and the power management module receives the input of the battery 40 to supply power for each electronic device arranged in the terminal device.
  • the battery 40 supplies power for the processor, the memory, the display panel 10 and the camera through the power management module. .
  • the display panel 10 includes a plurality of pixel units distributed in an array, each pixel unit includes a plurality of sub-pixels, for example, each pixel unit includes a first sub-pixel 11a, a second sub-pixel 11b and a third sub-pixel
  • the first sub-pixel 11a may be a red sub-pixel
  • the second sub-pixel 11b may be a green sub-pixel
  • the third sub-pixel 11c may be a blue sub-pixel.
  • each sub-pixel includes a pixel driving circuit, and a light emitting device connected to each pixel driving circuit.
  • the light-emitting device may be an organic light-emitting diode (organic light-emitting diode, OLED), Miniled (miniature light-emitting diode), MicroLed (micro-light-emitting diode), quantum dot light-emitting diodes (quantum dot light-emitting diodes, QLED) and the like.
  • the terminal device 100 may include 1 or N display panels 10, where N is a positive integer greater than 1.
  • the pixel drive circuits of each sub-pixel are basically similar, except that the light-emitting device connected to it is different.
  • the sub-pixel is a red sub-pixel.
  • the sub-pixel is a green sub-pixel, and when the color of light emitted by the light-emitting device in the sub-pixel is blue, the sub-pixel is a blue sub-pixel.
  • the pixel driving circuit in each sub-pixel includes: a first reset module 21, a light emission control module 22, a data writing module 23, a driving module 24, a second reset module 25, a threshold compensation module 26 and a storage module 27.
  • the second reset module 25 is respectively connected with the control end of the reset signal terminal Reset, the second initialization signal terminal Init2 and the drive module 24, for opening under the control of the reset signal input by the reset signal terminal Reset, through the second initialization signal terminal Init2
  • the second initialization signal of input resets the control end of drive module 24
  • Data writing module 23 is connected with the first end of first scan signal end Scan1, data signal end Data and drive module 24 respectively, for scanning in the first Turn on under the control of the first scan signal input by the signal terminal Scan1, and write the data signal input by the data signal terminal Data to the drive module 24;
  • the control terminal of the drive module 24 is connected to be turned on under the control of the second scan signal input by the second scan signal terminal Scan2, and the threshold voltage of the drive module 24 is compensated;
  • the storage module 27 is respectively the first voltage signal terminal ELVDD and the drive
  • the control terminal of the module 24 is connected to stabilize the voltage of the control terminal of the drive module 24;
  • the first reset module 21 is respectively connected to the
  • one of the first reset module 21 and the lighting control module 22 is turned on when the lighting control signal is at a high level, and the other of the first reset module 21 and the lighting control module 22 is turned on when the lighting control signal is at a low level ; Moreover, the frequency of the lighting control signal is greater than 120HZ.
  • each pixel driving circuit needs to go through three stages, which are reset stage, data writing stage and light emission control stage.
  • the reset signal input by the reset signal terminal Reset is an effective signal, so that the second reset module 25 is turned on under the control of the reset signal input by the reset signal terminal Reset, and the second initialization signal input by the second initialization signal terminal Init2 passes through the second reset signal.
  • the second reset module 25 is transmitted to the control terminal of the driving module 24, and the control terminal of the driving module 24 is reset, thereby avoiding the residual charge of the control terminal of the driving module 24 when the last frame of picture is displayed, affecting the picture display of this frame and, in the reset phase, the light-emitting control signal input by the light-emitting control signal terminal EM is an effective signal for the first reset module 21, and the first reset module 21 is turned on under the control of the light-emitting control signal input by the light-emitting control signal terminal EM , the first initialization signal input by the first initialization signal terminal Init1 is transmitted to the first terminal of the light-emitting device EL through the first reset module 21, and the first terminal of the light-emitting device EL is reset, thereby preventing the light-emitting device from The charge remaining at the first terminal of the EL affects the picture display of this frame.
  • the first scan signal input by the first scan signal terminal Scan1 is an invalid signal, so that the data writing module 23 is closed;
  • the second scan signal input by the second scan signal terminal Scan2 is also an invalid signal, so that the threshold compensation module 26 is also closed.
  • the light emission control signal input by the light emission control signal terminal EM is an invalid signal for the light emission control module 22, so that the light emission control module 22 is also turned off.
  • the driving module 24 is also in the on state, but since the light emitting control module 22 is off, the driving current flowing into the first end of the light emitting device EL is 0, and the light emitting device EL does not emit light.
  • the first scanning signal input by the first scanning signal terminal Scan1 is a valid signal, so that the data writing module 23 is turned on under the control of the first scanning signal input by the first scanning signal terminal Scan1, and the data signal terminal Data
  • the input data signal is transmitted to the first end of the driving module 24 through the data writing module 23;
  • the second scanning signal input by the second scanning signal terminal Scan2 is a valid signal, so that the threshold compensation module 26 is in the second It is turned on under the control of the second scanning signal input from the scanning signal terminal Scan2.
  • the driving module 24 Since the driving module 24 is also in the open state, the data signal written to the first end of the driving module 24 will be written to the control end of the driving module 24 through the driving module 24 and the threshold compensation module 26, and, because the threshold compensation module 26 The threshold compensation module 26 will compensate the threshold voltage of the driving module 24. Therefore, when the data signal is written into the control terminal of the driving module 24, the threshold voltage of the driving module 24 will also be written into the driving module 24 at the same time.
  • the control terminal of the drive module 24 writes the data signal input from the data signal terminal Data and the threshold voltage of the drive module 24 into the control terminal of the drive module 24 through the data writing module 23 and the threshold compensation module 26 .
  • the storage module 27 Since the first terminal of the storage module 27 is connected to the first voltage signal terminal ELVDD, and the second terminal of the storage module 27 is connected to the control terminal of the driving module 24, therefore, when the data signal and the threshold voltage of the driving module 24 are written into the driving module 24, it is equivalent to storing the data signal and the threshold voltage of the driving module 24 in the storage module 27, the storage module 27 can stabilize the voltage of the control terminal of the driving module 24, and prevent the leakage current of the driving module 24 from being damaged. As a result, the voltage of the control terminal of the driving module 24 decreases.
  • the light emission control signal input by the light emission control signal terminal EM is still a valid signal for the first reset module 21, and the control of the light emission control signal input by the light emission control signal terminal EM by the first reset module 21
  • the first initialization signal input by the first initialization signal terminal Init1 is transmitted to the first terminal of the light emitting device EL through the first reset module 21, and continues to reset the first terminal of the light emitting device EL.
  • the reset signal input by the reset signal terminal Reset is an invalid signal, so that the second reset module 25 is closed; the light emission control signal input by the light emission control signal terminal EM is still an invalid signal for the light emission control module 22, so that the light emission control module 22 is also closed.
  • the driving module 24 is also in the on state, but since the light emitting control module 22 is off, the driving current flowing into the first end of the light emitting device EL is 0, and the light emitting device EL does not emit light.
  • the lighting control signal input from the lighting control signal terminal EM is an effective signal for the lighting control module 22, and the lighting control module 22 is turned on under the control of the lighting control signal input from the lighting control signal terminal EM, because the driving module 24 Also in the on state, the light emitting control module 22 can drive the light emitting device EL to emit light through the driving module 24 .
  • the reset signal input by the reset signal terminal Reset is an invalid signal, so that the second reset module 25 is closed;
  • the first scan signal input by the first scan signal terminal Scan1 is an invalid signal, so that the data writing module 23 is closed;
  • the second scan The second scan signal input by the signal terminal Scan2 is also an invalid signal, so that the threshold compensation module 26 is also closed;
  • the light emission control signal input by the light emission control signal terminal EM is an invalid signal for the first reset module 21, so that the first reset module 21 is also closed.
  • a valid signal refers to a signal that can control the corresponding module to be turned on
  • an invalid signal refers to a signal that can control the corresponding module to be turned off.
  • the valid signal refers to a high-level signal
  • the invalid signal refers to a low-level signal
  • the transistor in the module is a P-type transistor
  • the valid signal refers to a low-level signal signal
  • the invalid signal refers to the high level signal.
  • the first reset module 21 and the lighting control module 22 can reduce the voltage of the first terminal of the light emitting device EL at the same frequency, so that the lighting control signal is in each cycle.
  • the brightness of the corresponding light-emitting device EL can be reduced to 0 nits; and the frequency of the light-emitting control signal is adjusted to be greater than 120HZ, which has a better effect of improving the frequent flickering phenomenon of the screen during low-brightness display.
  • the first reset module 21 and the light emission control module 22 reduce the voltage of the first terminal of the light emitting device EL to 0 nits at the same frequency, where 0 nits refers to a value within the allowable range of error, not It must refer to the specific value of 0 nits, for example, within the allowable range of error, lowering the first terminal of the light emitting device EL to 0.1 nits also means reducing the voltage of the first terminal of the light emitting device EL to 0 nits by default.
  • the light emission control module 22 includes a first light emission control unit 221 and a second light emission control unit 222 .
  • the control end of the first light emission control unit 221 is connected to the light emission control signal end EM, the first end of the first light emission control unit 221 is connected to the first voltage signal end ELVDD, and the second end of the first light emission control unit 221 is connected to the driving module 24
  • the first end of the second light emission control unit 222 is connected to the light emission control signal end EM
  • the first end of the second light emission control unit 222 is connected to the second end of the driving module 24, the second light emission control unit 222
  • the second end is connected with the first end of the light emitting device EL.
  • the first reset module 21 includes a first reset transistor T1
  • the first light emission control unit 221 includes a first light emission control transistor T2
  • the second light emission control unit 222 includes a second light emission control unit 222.
  • the driving module 24 includes a driving transistor T5
  • the second reset module 25 includes a second reset transistor T6
  • the threshold compensation module 26 includes a compensation transistor T7
  • the storage module 27 includes a storage Capacitance Cst.
  • the gate of the first reset transistor T1 is connected to the light emitting control signal terminal EM, the first pole of the first reset transistor T1 is connected to the first initialization signal terminal Init1, and the second pole of the first reset transistor T1 is connected to the first pole of the light emitting device EL. end connection.
  • the gate of the first light emission control transistor T2 is connected to the light emission control signal terminal EM, the first pole of the first light emission control transistor T2 is connected to the first voltage signal terminal ELVDD, and the second pole of the first light emission control transistor T2 is connected to the driving module 24 The first end connection.
  • the control terminal of the first light emission control unit 221 refers to the gate of the first light emission control transistor T2, and the first terminal of the first light emission control unit 221 refers to the first pole of the first light emission control transistor T2.
  • the second end of the unit 221 refers to the second pole of the first light emission control transistor T2.
  • the second pole of the first light emission control transistor T2 is connected to the first pole of the driving transistor T5, that is, the first terminal of the driving module 24 refers to the first pole of the driving transistor T5.
  • the gate of the second light emission control transistor T3 is connected to the light emission control signal terminal EM, the first pole of the second light emission control transistor T3 is connected to the second end of the driving module 24, and the second pole of the second light emission control transistor T3 is connected to the light emitting device.
  • the first end of EL is connected.
  • the control terminal of the second light emission control unit 222 refers to the gate of the second light emission control transistor T3, the first end of the second light emission control unit 222 refers to the first pole of the second light emission control transistor T3, and the second light emission control transistor T3
  • the second end of the unit 222 refers to the second pole of the second light emission control transistor T3.
  • the first pole of the second light emission control transistor T3 is connected to the second pole of the driving transistor T5, that is, the second terminal of the driving module 24 refers to the second pole of the driving transistor T5.
  • the gate of the data writing transistor T4 is connected to the first scanning signal terminal Scan1, the first pole of the data writing transistor T4 is connected to the data signal terminal Data, and the second pole of the data writing transistor T4 is connected to the first terminal of the driving module 24. connect. Specifically, the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T5.
  • the gate of the driving transistor T5 is respectively connected to the second reset module 25, the second terminal of the storage module 27 and the threshold compensation module 26, and the first pole of the driving transistor T5 is connected to the data writing module 23 and the first light emitting control unit 221. Both the second ends are connected, and the second pole of the driving transistor T5 is respectively connected to the first ends of the threshold compensation module 26 and the second light emission control unit 222 .
  • the gate of the drive transistor T5 is respectively connected to the second pole of the second reset transistor T6, the second plate of the storage capacitor Cst, and the second pole of the compensation transistor T7, and the first pole of the drive transistor T5 is respectively connected to the data writing
  • the second pole of the input transistor T4 and the second pole of the first light emission control transistor T2 are connected, and the second pole of the driving transistor T5 is respectively connected with the first pole of the compensation transistor T7 and the first pole of the second light emission control transistor T3, that is
  • the control terminal of the driving module 24 refers to the gate of the driving transistor T5.
  • the gate of the second reset transistor T6 is connected to the reset signal terminal Reset, the first pole of the second reset transistor T6 is connected to the second initialization signal terminal Init2, and the second pole of the second reset transistor T6 is connected to the second pole of the storage module 27 respectively. terminal, the control terminal of the drive module 24 and the threshold compensation module 26 are connected. Specifically, the second pole of the second reset transistor T6 is respectively connected to the second plate of the storage capacitor Cst, the gate of the driving transistor T5 and the second pole of the compensation transistor T7.
  • the gate of the compensation transistor T7 is connected to the second scanning signal terminal Scan2, the first pole of the compensation transistor T7 is respectively connected to the second terminal of the driving module 24 and the first terminal of the second light emission control unit 222, and the second terminal of the compensation transistor T7
  • the poles are respectively connected to the second end of the storage module 27, the control end of the drive module 24 and the second reset module 25.
  • the first pole of the compensation transistor T7 is connected to the second pole of the driving transistor T5 and the first pole of the second light emission control transistor T3, and the second pole of the compensation transistor T7 is connected to the second plate of the storage capacitor Cst
  • the gate of the driving transistor T5 is connected to the second pole of the second reset transistor T6.
  • the first plate of the storage capacitor Cst is connected to the first voltage signal terminal ELVDD, and the second plate of the storage capacitor Cst is respectively connected to the control terminal of the driving module 24 , the second reset module 25 and the threshold compensation module 26 .
  • the second plate of the storage capacitor Cst is connected to the gate of the drive transistor T5, the second pole of the second reset transistor T6, and the second pole of the compensation transistor T7, and the first terminal of the storage module 27 refers to the storage
  • the first plate of the capacitor Cst, the second terminal of the storage module 27 refers to the second plate of the storage capacitor Cst.
  • the first reset transistor T1 is an N-type transistor
  • the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are both P-type transistors
  • the data writing transistor T4 and the driving transistor T5 are both P-type transistors.
  • Both the reset transistor T6 and the compensation transistor T7 are N-type transistors.
  • the reset signal input by the reset signal terminal Reset is at a high level, and the reset signal at this time is an effective signal, so that the second reset transistor T6 is turned on under the control of the reset signal input by the reset signal terminal Reset, and the second The second initialization signal input by the initialization signal terminal Init2 is transmitted to the gate of the driving transistor T5 (that is, the Vg node) through the second reset transistor T6, and the gate of the driving transistor T5 is reset, so that the gate voltage of the driving transistor T5 is adjusted is the second initialization voltage Vinit2 corresponding to the second initialization signal.
  • the voltage of the gate of the driving transistor T5 (that is, the Vg node) can be adjusted for -3V.
  • the light emission control signal input by the light emission control signal terminal EM is at a high level, and the light emission control signal at this time is a valid signal for the first reset transistor T1, so that the first reset transistor T1 is in the state of the light emission control signal.
  • the light-emitting control signal input from the terminal EM is turned on, and the first initialization signal input from the first initialization signal terminal Init1 is transmitted to the first terminal of the light-emitting device EL through the first reset transistor T1, and the first terminal of the light-emitting device EL is controlled. Reset, so that the voltage of the first terminal of the light emitting device EL is adjusted to the first initialization voltage Vinit1 corresponding to the first initialization signal.
  • the voltage of the first electrode of the driving transistor T5 (that is, the voltage of the Vs node) is the voltage Vdd of the first voltage signal terminal ELVDD, therefore, in the reset stage t11, the voltage of the Vs node
  • the voltage of the driving transistor T5 is basically equal to Vdd.
  • the first pole of the driving transistor T5 refers to the source of the driving transistor T5. Since the voltage difference Vgs between the gate and the source of the driving transistor T5 is less than the threshold voltage Vth of the driving transistor T5, the driving transistor T5 T5 is also in a conducting state.
  • the first scan signal input by the first scan signal terminal Scan1 is at a high level, and the first scan signal at this time is an invalid signal, so that the data writing transistor T4 is turned off;
  • the second scan signal terminal Scan2 inputs The second scan signal is low level, the second scan signal at this time is also an invalid signal, so that the compensation transistor T7 is also in an off state;
  • the light emission control signal input from the light emission control signal terminal EM is high level, at this time
  • the light-emitting control signal is an invalid signal for the first light-emitting control transistor T2 and the second light-emitting control transistor T3, so that the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are also in the cut-off state, and then the first light that flows into the light-emitting device EL
  • the driving current at the terminal is 0, and the light emitting device EL will not emit light.
  • the first scanning signal input by the first scanning signal terminal Scan1 is at a low level, and the first scanning signal at this time is a valid signal, so that the data writing transistor T4 is turned on, and the input of the data signal terminal Data
  • the data signal is transmitted to the first pole of the drive transistor T5 through the data writing transistor T4, and the voltage of the Vs node at this time is the data voltage Vdata corresponding to the data signal; in the data writing phase t12, the second scanning signal terminal Scan2 input
  • the scanning signal is a high-level signal, and the second scanning signal at this time is an effective signal, so that the compensation transistor T7 is turned on, and the data signal written to the first pole of the driving transistor T5 is sequentially written through the driving transistor T5 and the compensation transistor T7.
  • the gate voltage of the driving transistor T5 gradually increases until the gate voltage of the driving transistor T5 becomes Vdata+Vth, that is, the voltage of the Vg node is Vdata+ Vth.
  • the light emission control signal input by the light emission control signal terminal EM is still at a high level, and the light emission control signal at this time is still a valid signal for the first reset transistor T1, so that the first reset transistor T1 is turned on, the first initialization signal input by the first initialization signal terminal Init1 continues to be transmitted to the first terminal of the light emitting device EL through the first reset transistor T1, and continues to reset the first terminal of the light emitting device EL, so that the first terminal of the light emitting device EL The voltage at one terminal is maintained at the first initialization voltage Vinit1.
  • the reset signal input by the reset signal terminal Reset is low level, and the reset signal at this time is an invalid signal, so that the second reset transistor T6 is turned off; while the light emission control signal input by the light emission control signal terminal EM Still at high level, the light emission control signal at this time is still an invalid signal for the first light emission control transistor T2 and the second light emission control transistor T3, so that the first light emission control transistor T2 and the second light emission control transistor T3 are also cut off state, the driving current flowing into the first terminal of the light emitting device EL is 0, and the light emitting device EL will not emit light.
  • the light emission control signal input by the light emission control signal terminal EM is at a low level, and the light emission control signal at this time is a valid signal for the first light emission control transistor T2 and the second light emission control transistor T3, and the first light emission control transistor T3
  • the control transistor T2 and the second light emission control transistor T3 are turned on under the control of the light emission control signal input from the light emission control signal terminal EM.
  • K is a constant, and the specific value is determined by the characteristics of the driving transistor T5 itself.
  • the driving current flowing into the light-emitting device EL has nothing to do with the threshold voltage Vth of the driving transistor T5, and the compensation transistor T7 can make it flow into the light-emitting device.
  • the driving current of the EL has nothing to do with the threshold voltage Vth of the driving transistor T5, so as to prevent the fluctuation of the threshold voltage Vth of the driving transistor T5 from affecting the luminance of the light emitting device EL, and improve the brightness uniformity of the display panel.
  • the reset signal input by the reset signal terminal Reset is low level, and the reset signal at this time is an invalid signal, so that the second reset transistor T6 is turned off;
  • the first scan signal input by the first scan signal terminal Scan1 is High level, the first scanning signal at this time is an invalid signal, so that the data writing transistor T4 is turned off;
  • the second scanning signal input by the second scanning signal terminal Scan2 is low level, and the second scanning signal at this time is also invalid signal, so that the compensation transistor T7 is also in the cut-off state;
  • the light-emitting control signal input by the light-emitting control signal terminal EM is low level, and the light-emitting control signal at this time is an invalid signal for the first reset transistor T1, so that the first reset transistor T1 due.
  • the light emission control signal is at high level, so that the first reset transistor T1 is in the conduction state, while the first light emission control transistor T2 and the second light emission control transistor T3 are in the In the light-emitting control stage t13, the light-emitting control signal is at a low level, so that the first reset transistor T1 is in the cut-off state, and the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are in the on-state.
  • the control transistor T3 can reduce the voltage of the first terminal of the light-emitting device EL at the same frequency; and when the frequency of the light-emitting control signal is adjusted to be higher than 120HZ, it can effectively improve the frequent flickering phenomenon of the screen during low-brightness display.
  • the reset signal terminal Reset in the pixel driving circuit of the nth row is the same as that in the pixel driving circuit of the n-7th row.
  • the second scanning signal terminal Scan2 is connected, therefore, the time period between the reset phase t11 and the data writing phase t12 refers to the reset corresponding to the n-6th row of pixel driving circuits to the n-1th row of pixel driving circuits Stage t11;
  • there is also a short interval between the data writing stage t12 and the light emission control stage t13 which is to ensure sufficient time to stabilize the gate voltage of the driving transistor T5 at Vdata+Vth.
  • the first reset module 21 includes a first reset transistor T1
  • the first light emission control unit 221 includes a first light emission control transistor T2
  • the second light emission control unit 222 includes a second
  • the light emission control transistor T3 includes a data writing transistor T4
  • the driving module 24 includes a driving transistor T5
  • the second reset module 25 includes a second reset transistor T6
  • the threshold compensation module 26 includes a compensation transistor T7
  • the storage module 27 includes Storage capacitor Cst.
  • the connection relationship is the same, and will not be repeated here to avoid repetition.
  • the first reset transistor T1 is a P-type transistor
  • the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are both N-type transistors.
  • both the data writing transistor T4 and the driving transistor T5 are P-type transistors
  • the second reset transistor T6 and the compensation transistor T7 are both N-type transistors.
  • the reset signal input from the reset signal terminal Reset is at a high level, so that the second reset transistor T6 is turned on, and the second initialization signal input from the second initialization signal terminal Init2 is transmitted to the drive transistor T5 through the second reset transistor T6
  • the gate of the drive transistor T5 that is, the Vg node resets the gate of the driving transistor T5.
  • the light emission control signal at this time is an effective signal for the first reset transistor T1, so that the light emission control signal input by the light emission control signal terminal EM of the first reset transistor T1 Under the control of the signal, the first initialization signal input by the first initialization signal terminal Init1 is transmitted to the first terminal of the light emitting device EL through the first reset transistor T1 to reset the first terminal of the light emitting device EL.
  • the drive transistor T5 is also in the conduction state; in the reset phase t21, the first scan signal input by the first scan signal terminal Scan1 is at a high level, so that the data writing transistor T4 is cut off; the second scan signal input by the second scan signal terminal Scan2 The second scan signal is at low level, so that the compensation transistor T7 is also in the cut-off state; and the light-emitting control signal input from the light-emitting control signal terminal EM is at low level, and the light-emitting control signal at this time has an effect on the first light-emitting control transistor T2 and the second light-emitting control transistor T2.
  • the control transistor T3 is an invalid signal, so that the first light emission control transistor T2 and the second light emission control transistor T3 are also in the cut-off state, then the driving current flowing into the first terminal of the light emitting device EL is 0, and the light emitting device EL will not emit light.
  • the first scan signal input by the first scan signal terminal Scan1 is low level, so that the data write transistor T4 is turned on, and the second scan signal input by the second scan signal terminal Scan2 is a high level signal , so that the compensation transistor T7 is turned on, then the data signal input by the data signal terminal Data will be written into the gate of the driving transistor T5 through the data writing transistor T4, the driving transistor T5 and the compensation transistor T7 in sequence.
  • the gate voltage of the driving transistor T5 gradually increases until the gate voltage of the driving transistor T5 becomes Vdata+Vth, that is, the voltage of the Vg node is Vdata+Vth.
  • the light emission control signal input by the light emission control signal terminal EM is still at a low level, and the light emission control signal at this time is still a valid signal for the first reset transistor T1, so that the first reset transistor T1 is turned on, the first initialization signal input by the first initialization signal terminal Init1 continues to be transmitted to the first terminal of the light emitting device EL through the first reset transistor T1, and continues to reset the first terminal of the light emitting device EL.
  • the reset signal input by the reset signal terminal Reset is low level, so that the second reset transistor T6 is turned off; while the light emission control signal input by the light emission control signal terminal EM is still low level, at this time
  • the light-emitting control signal is still an invalid signal for the first light-emitting control transistor T2 and the second light-emitting control transistor T3, so that the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are also in the cut-off state, and then the first light-emitting device EL flows into The driving current at one end is 0, and the light emitting device EL will not emit light.
  • the light emission control signal input by the light emission control signal terminal EM is at a high level, and the light emission control signal at this time is a valid signal for the first light emission control transistor T2 and the second light emission control transistor T3.
  • the reset signal input by the reset signal terminal Reset is at a low level, so that the second reset transistor T6 is turned off;
  • the first scan signal input by the first scan signal terminal Scan1 is at a high level, so that the data is written into the transistor T6 T4 cuts off;
  • the second scanning signal input by the second scanning signal terminal Scan2 is low level, so that the compensation transistor T7 is also in an off state;
  • the light-emitting control signal input by the light-emitting control signal terminal EM is high-level, and the light-emitting control signal at this time It is an invalid signal for the first reset transistor T1, so that the first reset transistor T1 is turned off.
  • the light emission control signal is at low level, so that the first reset transistor T1 is in the conduction state, while the first light emission control transistor T2 and the second light emission control transistor T3 are in the In the light-emitting control stage t23, the light-emitting control signal is at a high level, so that the first reset transistor T1 is in the cut-off state, and the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are in the on-state.
  • the control transistor T3 can reduce the voltage of the first terminal of the light-emitting device EL at the same frequency; and when the frequency of the light-emitting control signal is adjusted to be higher than 120HZ, it can effectively improve the frequent flickering phenomenon of the screen during low-brightness display.
  • the reset signal terminal Reset in the pixel driving circuit of the nth row is connected to the second scanning signal terminal Scan2 in the pixel driving circuit of the n-7th row, therefore, in the reset phase t21 and the data writing phase t22
  • the time period between refers to the reset phase t11 corresponding to the n-6th row of pixel driving circuits to the n-1th row of pixel driving circuits; in addition, there is also between the data writing phase t22 and the light emission control phase t23
  • the short interval is to ensure enough time to stabilize the gate voltage of the driving transistor T5 at Vdata+Vth.
  • Fig. 10 shows a schematic diagram of the luminance curve of the pixel driving circuit in the embodiment of the present application when driving the light-emitting device to emit light.
  • the abscissa represents time, and the unit is s, and the ordinate represents brightness, and the unit is nits.
  • the test conditions are: The gate of the first reset transistor T1, the gate of the first light-emitting control transistor T2, and the gate of the second light-emitting control transistor T3 are all connected to the light-emitting control signal terminal EM, the first reset transistor T1 is an N-type transistor, and the first light-emitting Both the control transistor T2 and the second light emission control transistor T3 are P-type transistors, and the frequency of the light emission control signal input from the light emission control signal terminal EM is 240 Hz.
  • the light emission control signal changes from low level to high level, so that the first reset transistor T1 changes from off state to on state, and at the same time, the first light emission control transistor T2 and the second light emission control transistor T2
  • the second light emission control transistor T3 changes from the on state to the off state, and the first reset transistor T1, the first light emission control transistor T2 and the second light emission control transistor T3 reduce the voltage of the first end of the light emitting device EL at the same frequency to reduce the The brightness of the light emitting device EL, so that the brightness L2 of the light emitting device EL at this time can be reduced to 0 nits. Therefore, in two adjacent periods of the light emission control signal, the reduced brightness of the corresponding light emitting device EL is basically the same.
  • the gate of the first reset transistor T1 when the gate of the first reset transistor T1, the gate of the first light emission control transistor T2 and the gate of the second light emission control transistor T3 are all connected to the light emission control signal terminal EM, and the first reset transistor T1 is P type transistors, when the first light-emitting control transistor T2 and the second light-emitting control transistor T3 are N-type transistors, the first reset transistor T1, the first light-emitting control transistor T2 and the second light-emitting control transistor T3 can also reduce the light-emitting device EL at the same frequency
  • the voltage at the first terminal of the light-emitting device EL is used to reduce the brightness of the light-emitting device EL, so that the reduced brightness of the corresponding light-emitting device EL is basically the same in two adjacent cycles of the light-emitting control signal.
  • the frequency of the light-emitting control signal input from the light-emitting control signal terminal EM is increased to 240 Hz, and the first reset transistor T1, the first light-emitting control transistor T2 and the second light-emitting control transistor T3 reduce the brightness of the light-emitting device EL to 0 nits at the same frequency, then
  • the change frequency of the bright state and dark state of the light-emitting device EL can also be increased to 240HZ, and the change frequency of the bright state and dark state of the light-emitting device EL in a frame of picture display is correspondingly increased, thereby improving the appearance of the picture in low-brightness display. Frequent flickering phenomenon problem.
  • the first reset can be controlled simultaneously through one signal.
  • the transistor T1, the first light emission control transistor T2 and the second light emission control transistor T3 are controlled by one signal with respect to the first reset transistor T1, while the first light emission control transistor T2 and the second light emission control transistor T3 are controlled by another signal.
  • the embodiment of the application can reduce the number of signals input to each pixel driving circuit, correspondingly, also reduce the number of signal lines required for signal transmission, and simplify the routing design of the display panel.
  • the data writing transistor T4 can also be an N-type transistor
  • the second reset transistor T6 can also be a P-type transistor
  • the compensation transistor T7 can also be a P-type transistor.
  • the source and drain of each transistor can be interchanged under certain conditions, therefore, the description of the connection relationship between the source and drain of each transistor is not difference.
  • one of them is called the first pole, and the other is called the second pole.
  • the transistor can be divided into N according to the characteristics of the transistor. Type transistors and P-type transistors, for N-type transistors, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is turned on when the gate is input with a high level, and the P-type transistor is opposite.
  • the first reset transistor T1, the first light emission control transistor T2, the second light emission control transistor T3, the data write transistor T4, the drive transistor T5, the second reset transistor T6 and the compensation transistor T7 may be oxide semiconductor transistors or low temperature polysilicon transistors.
  • the above description increases the frequency of the light-emitting control signal from 120Hz to 240HZ to improve the problem of frequent flickering of the screen during low-brightness display. It is understandable that the frequency of the light-emitting control signal can also be increased to other frequencies, such as 150HZ, 360HZ, etc., as long as the frequency of the light-emitting control signal in the embodiment of the present application is greater than 120HZ, the frequent flickering of the screen during low-brightness display can be improved. The problem improvement effect is better.
  • the pixel driving circuit in the embodiment of the present application is a 7T1C circuit. It can be understood that the pixel driving circuit in the embodiment of the present application is not limited to the pixel driving circuit shown in FIG. 6 and FIG.
  • pixel driving circuits such as 4T1C, 5T1C or 6T1C pixel driving circuits, as long as it is ensured that in the pixel driving circuit, the gates of the transistors included in the light emission control module 22 and the gates of the transistors included in the first reset module 21 are both in line with The light emission control signal terminal EM is connected, and the transistor in the light emission control module 22 and the transistor in the first reset module 21, one of them is turned on when the light emission control signal is high level, and the other is turned on when the light emission control signal is low level conduction, are applicable to this application.
  • the present application can also use a 6T1C pixel drive circuit.
  • the second reset transistor T6 in the pixel drive circuit shown in FIG. 6 and FIG. 8 can be removed to obtain a 6T1C pixel drive circuit.
  • the pixel drive circuit The circuit does not include the second reset module 25 .
  • the present application can also use a 4T1C pixel drive circuit.
  • the second reset transistor T6, the compensation transistor T7, and the first light emission control transistor T2 in the pixel drive circuit shown in FIG. 6 can be removed to obtain
  • the pixel driving circuit at this time includes the first reset transistor T1, the second light emission control transistor T3, the data writing transistor T4, the driving transistor T5 and the storage capacitor Cst, but does not include the second reset transistor T1 Module 25, threshold compensation module 26, and first light emission control unit 221; and, the second pole of the data writing transistor T4 is connected to the gate of the driving transistor T5, and the first pole of the driving transistor T5 is connected to the first voltage signal terminal ELVDD .
  • the type of the first reset transistor T1 is opposite to that of the second light emission control transistor T3, that is, when the first reset transistor T1 is P
  • the second light emission control transistor T3 is an N-type transistor, or when the first reset transistor T1 is an N transistor, the second light emission control transistor T3 is a P-type transistor.
  • the light emission control module may only include the second light emission control unit 222 , or may include the first light emission control unit 22 and the second light emission control unit 222 .
  • the embodiment of the present application also provides a display panel, including a plurality of pixel driving circuits as shown in FIG. 6 , FIG. 8 or FIG. 11 , and a light emitting device EL connected to each pixel driving circuit.
  • the first end of the light emitting device EL refers to the anode of the light emitting device EL
  • the second end of the light emitting device EL refers to the cathode of the light emitting device EL
  • the second end of the light emitting device EL is connected to the second voltage signal terminal ELVSS .
  • the reset signal terminal Reset in the pixel driving circuit of the nth row is connected to the second scanning signal terminal Scan2 in the pixel driving circuit of the n-7th row, and n is a positive integer greater than 7.
  • each row of pixel driving circuits is respectively connected to the reset signal terminal Reset, the second initialization signal terminal Init2, the first initialization signal terminal Init1, the light emission control signal terminal EM, the first scanning signal terminal Scan1 and the second The scanning signal terminal Scan2 is connected, and the second scanning signal terminal Scan2 of the pixel driving circuit in the first row is also connected with the reset signal terminal Reset of the pixel driving circuit in the eighth row, and the second scanning signal terminal Scan2 of the pixel driving circuit in the second row is also connected with the pixel driving circuit in the second row.
  • the reset signal terminal Reset of the 9-row pixel driving circuit is connected, and so on.
  • the reset signal terminal Reset of the pixel driving circuit in the first row to the seventh row of the pixel driving circuit needs to receive a reset signal input from the outside.
  • the externally input reset signal can be reduced.
  • the display panel also includes a gate on array (GOA) circuit on the array substrate.
  • the GOA circuit includes an EM GOA circuit, a first scanning GOA circuit, and a second scanning GOA circuit.
  • the signal terminal EM is connected to input the luminescence control signal to the luminescence control signal terminal EM of each row of pixel drive circuits.
  • the first scanning signal terminal Scan1 inputs the first scanning signal
  • the second scanning GOA circuit is connected to the second scanning signal terminal Scan2 of each row of pixel driving circuits for inputting the second scanning signal to the second scanning signal terminal Scan2 of each row of pixel driving circuits.
  • a display panel includes a display area and a non-display area surrounding the display area, the pixel driving circuit and the light emitting device EL are located in the display area, and the GOA circuits are both located in the non-display area.

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Abstract

一种像素驱动电路及其驱动方法、显示面板及终端设备，应用于终端技术领域。像素驱动电路包括第一复位模块(21)、发光控制模块(22)和驱动模块(24)，第一复位模块(21)和发光控制模块(22)均与发光控制信号端(EM)连接，其中一者在发光控制信号(EM)为高电平时开启，另一者在发光控制信号(EM)为低电平时开启，因此，通过将发光控制信号的频率调高至大于120HZ，可改善低亮度显示时画面出现频繁的闪烁现象的问题，降低用户观看时眼睛容易出现疲劳感的现象。

Description

像素驱动电路及其驱动方法、显示面板及终端设备
本申请要求于2021年06月22日提交中国国家知识产权局、申请号为202110694418.7、申请名称为“像素驱动电路及其驱动方法、显示面板及终端设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及终端技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板及终端设备。
背景技术
随着信息时代的不断发展，手机等终端设备已成为人们生活和工作中较为常用的工具，显示面板作为终端设备中的重要组成部分，其显示效果对终端设备的使用有着重要的影响。
然而，终端设备在低亮度(如亮度小于2nits)显示时，用户很容易观察到画面出现频繁的闪烁现象，使得用户观看时眼睛容易出现疲劳感。
发明内容
本申请实施例提供一种像素驱动电路及其驱动方法、显示面板及终端设备，应用于终端设备，以改善低亮度显示时画面出现频繁闪烁的问题。
第一方面，本申请实施例提出一种像素驱动电路，应用于驱动发光器件发光，像素驱动电路包括：第一复位模块、发光控制模块和驱动模块；第一复位模块，分别与发光控制信号端、第一初始化信号端和发光器件的第一端连接，用于在发光控制信号端输入的发光控制信号的控制下开启，通过第一初始化信号端输入的第一初始化信号对发光器件的第一端进行复位；发光控制模块，分别与发光控制信号端、驱动模块和发光器件的第一端连接，用于在发光控制信号端输入的发光控制信号的控制下开启，通过驱动模块驱动发光器件发光；其中，第一复位模块和发光控制模块中的一者在发光控制信号为高电平时开启，第一复位模块和发光控制模块中的另一者在发光控制信号为低电平时开启；发光控制信号的频率大于120HZ。
本申请的像素驱动电路包括第一复位模块、发光控制模块和驱动模块，第一复位模块和发光控制模块均与发光控制信号端连接，其中一者在发光控制信号为高电平时开启，另一者在发光控制信号为低电平时开启，因此，通过将发光控制信号的频率调高至大于120HZ，可改善低亮度显示时画面出现频繁的闪烁现象的问题，降低用户观看时眼睛容易出现疲劳感的现象。
可选的，发光控制模块包括第一发光控制单元和第二发光控制单元；第一发光控制单元的控制端与发光控制信号端连接，第一发光控制单元的第一端与第一电压信号端连接，第一发光控制单元的第二端与驱动模块的第一端连接；第二发光控制单元的控制端与发光控制信号端连接，第二发光控制单元的第一端与驱动模块的第二端连接， 第二发光控制单元的第二端与发光器件的第一端连接。通过第一发光控制单元和第二发光控制单元共同来控制发光器件进行发光。
可选的，第一复位模块包括第一复位晶体管，第一复位晶体管的栅极与发光控制信号端连接，第一复位晶体管的第一极与第一初始化信号端连接，第一复位晶体管的第二极与发光器件的第一端连接；第一发光控制单元包括第一发光控制晶体管，第一发光控制晶体管的栅极与发光控制信号端连接，第一发光控制晶体管的第一极与第一电压信号端连接，第一发光控制晶体管的第二极与驱动模块的第一端连接；第二发光控制单元包括第二发光控制晶体管，第二发光控制晶体管的栅极与发光控制信号端连接，第二发光控制晶体管的第一极与驱动模块的第二端连接，第二发光控制晶体管的第二极与发光器件的第一端连接。
可选的，第一复位晶体管为N型晶体管，第一发光控制晶体管和第二发光控制晶体管均为P型晶体管。通过将第一复位晶体管从P型晶体管更改为N型晶体管，并使得第一发光控制晶体管和第二发光控制晶体管的类型保持不变，减小像素驱动电路的变化，防止因像素驱动电路的改变太大而导致制作难度增加。
可选的，第一复位晶体管为P型晶体管，第一发光控制晶体管和第二发光控制晶体管均为N型晶体管。通过将第一发光控制晶体管和第二发光控制晶体管从P型晶体管更改为N型晶体管，并使得第一复位晶体管的类型保持不变，减少发光控制信号处于高电平的时间，降低发光控制信号长时间处于高电平带来的功耗。
可选的，驱动模块包括驱动晶体管，驱动晶体管的第一极与第一发光控制单元的第二端连接，驱动晶体管的第二极与第二发光控制单元的第一端连接。
可选的，像素驱动电路还包括：数据写入模块、第二复位模块、阈值补偿模块和存储模块；第二复位模块，分别与复位信号端、第二初始化信号端和驱动模块的控制端连接，用于在复位信号端输入的复位信号的控制下开启，通过第二初始化信号端输入的第二初始化信号对驱动模块的控制端进行复位；数据写入模块，分别与第一扫描信号端、数据信号端和驱动模块的第一端连接，用于在第一扫描信号端输入的第一扫描信号的控制下开启，向驱动模块写入数据信号端输入的数据信号；阈值补偿模块，分别与第二扫描信号端、驱动模块的第二端和驱动模块的控制端连接，用于在第二扫描信号端输入的第二扫描信号的控制下开启，对驱动模块的阈值电压进行补偿；存储模块，分别第一电压信号端和驱动模块的控制端连接，用于稳定驱动模块的控制端的电压。基于第二复位模块对驱动模块的控制端进行复位，防止上一帧残留电荷对显示的影响，基于阈值补偿模块对驱动模块的阈值电压进行补偿，改善阈值电压漂移引起的显示不均的问题。
可选的，数据写入模块包括数据写入晶体管，数据写入晶体管的栅极与第一扫描信号端连接，数据写入晶体管的第一极与数据信号端连接，数据写入晶体管的第二极与驱动模块的第一端连接。
可选的，第二复位模块包括第二复位晶体管，第二复位晶体管的栅极与复位信号端连接，第二复位晶体管的第一极与第二初始化信号端连接，第二复位晶体管的第二极与驱动模块的控制端连接。
可选的，阈值补偿模块包括补偿晶体管，补偿晶体管的栅极与第二扫描信号端连 接，补偿晶体管的第一极与驱动模块的第二端连接，补偿晶体管的第二极与驱动模块的控制端连接。
可选的，存储模块包括存储电容，存储电容的第一极板与第一电压信号端连接，存储电容的第二极板与驱动模块的控制端连接。
第二方面，本申请实施例提出一种驱动方法，应用于驱动上述的像素驱动电路，驱动方法包括：在复位阶段，第一复位模块开启，对发光器件的第一端进行复位；在数据写入阶段，第一复位模块开启，对发光器件的第一端继续进行复位；在发光控制阶段，发光控制模块开启，通过驱动模块驱动发光器件发光。
第三方面，本申请实施例提出一种显示面板，包括多个上述的像素驱动电路，以及与每个像素驱动电路连接的发光器件。
第四方面，本申请实施例提出一种终端设备，包括壳体以及上述的显示面板，显示面板安装于壳体上。
应当理解的是，本申请的第二方面至第四方面与本申请的第一方面的技术方案相对应，各方面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
图1为相关技术中的像素驱动电路的电路图；
图2为图1所示的像素驱动电路在驱动发光器件发光时的亮度曲线示意图；
图3为本申请实施例提供的终端设备的结构示意图；
图4为本申请实施例中的显示面板的结构示意图；
图5为本申请实施例提供的像素驱动电路的结构示意图；
图6为本申请实施例提供的一种像素驱动电路的电路图；
图7为图6所示的像素驱动电路对应的驱动时序图；
图8为本申请实施例提供的另一种像素驱动电路的电路图；
图9为图8所示的像素驱动电路对应的驱动时序图；
图10为本申请实施例中的像素驱动电路在驱动发光器件发光时的亮度曲线示意图；
图11为本申请实施例提供的再一种像素驱动电路的电路图；
图12为本申请实施例提供的各行像素驱动电路的级联关系图。
具体实施方式
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。例如，第一芯片和第二芯片仅仅是为了区分不同的芯片，并不对其先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
需要说明的是，本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示 例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
在相关技术中，如图1所示，像素驱动电路包括第一复位晶体管T1、第一发光控制晶体管T2、第二发光控制晶体管T3、数据写入晶体管T4、驱动晶体管T5、第二复位晶体管T6、补偿晶体管T7和存储电容Cst。
其中，第一复位晶体管T1为P型晶体管，第一复位晶体管T1的栅极和数据写入晶体管T4的栅极均与第一扫描信号端Scan1连接，第一复位晶体管T1用于在第一扫描信号端Scan1输入的第一扫描信号为低电平时导通，通过第一初始化信号端Init1输入的第一初始化信号对发光器件EL的阳极进行复位；第一发光控制晶体管T2和第二发光控制晶体管T3也均为P型晶体管，第一发光控制晶体管T2和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接，用于在发光控制信号端EM输入的发光控制信号为低电平时导通，通过驱动晶体管T5驱动发光器件EL发光。
在终端设备中，显示面板在低亮度显示时，通常是采用脉冲宽度调制(pulse width modulation，PWM)调光技术来调整显示亮度的。具体的，通过调整发光控制信号端EM输入的发光控制信号的占空比，来控制发光器件EL的发光时长，从而调节发光器件EL的显示亮度。该占空比指的是在发光控制信号的一个周期内，有效电平(即控制第一发光控制晶体管T2和第二发光控制晶体管T3导通时的电平)的持续时长与发光控制信号的周期的时长的比值，发光器件EL在一帧图像的显示过程中的发光时长与发光控制信号的占空比呈正相关，也就是说，发光控制信号的占空比越大，发光器件EL在一帧图像显示过程中的发光时长越长，发光控制信号的占空比越小，发光器件EL在一帧图像显示过程中的发光时长越短。
但是，显示面板在低亮度显示时，由于发光控制信号的占空比很小，发光器件EL在一帧图像显示过程中的发光时长很短，用户很容易观察到画面出现频繁的闪烁现象，使得用户观看时眼睛容易出现疲劳感。
为了改善频闪现象，在另一相关技术中，会将发光控制信号的频率从原本的120HZ提高至240HZ，通过拉高发光控制信号的频率，来改善低亮度显示时的频闪问题。但是，由于第一扫描信号端Scan1输入的第一扫描信号为120HZ，发光控制信号的频率是第一扫描信号的频率的2倍，使得第一扫描信号和发光控制信号不完全同步。因此，第一扫描信号每经过一个周期，发光控制信号就要经过两个周期，例如，如图2所示，第一扫描信号的周期的时长为8.3ms，而发光控制信号的周期的时长为4.15ms。
如图2所示，在第一扫描信号和发光控制信号不同步时，即在A1时刻，发光控制信号从低电平变为高电平，使得第一发光控制晶体管T2和第二发光控制晶体管T3从导通状态变为截止状态，来降低发光器件EL的亮度，但是此时的第一扫描信号依 旧维持在高电平，未发生变化，则使得第一复位晶体管T1仍处于截止状态，则第一复位晶体管T1无法对发光器件EL的阳极进行复位，进而导致发光器件EL的亮度没有降低至0nits，发光器件EL的亮度L1仅能降低至1nits；而在第一扫描信号和发光控制信号同步时，即在A2时刻，发光控制信号从低电平变为高电平，使得第一发光控制晶体管T2和第二发光控制晶体管T3从导通状态变为截止状态，此时的第一扫描信号也从高电平变为低电平，使得第一复位晶体管T1从截止状态变为导通状态，第一复位晶体管T1对发光器件EL的阳极进行复位，使得此时的发光器件EL的亮度可降低至0nits。
因此，通过将发光控制信号的频率提高至240HZ，而第一扫描信号的频率依旧为120HZ时，会导致发光控制信号在相邻两个周期内，其对应的发光器件EL降低后的亮度不一致，进而导致低亮度显示时，仅拉高将发光控制信号的频率对画面闪烁的改善不明显。
基于此，本申请实施例提供了一种像素驱动电路，通过将发光控制模块以及对发光器件进行复位的第一复位模块均与发光控制信号端EM连接，其中一者在发光控制信号为高电平时开启，另一者在发光控制信号为低电平时开启，使得发光控制模块关闭时，对发光器件EL进行复位的第一复位模块可同步开启，即第一复位模块和发光控制模块可同频降低发光器件EL的第一端的电压，使得发光控制信号在各个周期内，都可以将对应的发光器件EL的亮度降低至0nits；并且，将发光控制信号的频率调高至大于120HZ，则相应增加了发光器件EL在一帧画面显示时的亮态与暗态的变化频率，从而改善低亮度显示时画面出现频繁的闪烁现象的问题，降低用户观看时眼睛容易出现疲劳感的现象。
本申请实施例提供的像素驱动电路，可以应用在具备显示功能的终端设备中。该终端设备可以是手机、平板电脑、电子阅读器、笔记本电脑、车载设备、可穿戴设备、电视等设备。
如图3所示，终端设备100包括显示面板10、壳体20、电路板30和电池40。其中，显示面板10安装于壳体20上，其用于显示图像或视频等；显示面板10和壳体20共同围设出终端设备100的容纳腔体，以便通过该容纳腔体放置终端设备100的电子器件等，同时对位于容纳腔体内的电子器件形成密封和保护的作用。例如，终端设备100的电路板30和电池40位于该容纳腔体内。
电路板30可以是终端设备100的主板，在电路板30上可集成有处理器、存储器、摄像头、马达、陀螺仪传感器、加速度传感器等功能组件中的一个或多个。显示面板10与电路板30电连接，以通过电路板30上的处理器对显示面板10的显示进行控制；电池40也与电路板30电连接，通过电池40为终端设备供电，具体的，电路板30上设置有电源管理模块，电源管理模块接收电池40的输入，为终端设备内设置的各个电子器件供电，例如，电池40通过电源管理模块为处理器、存储器、显示面板10以及摄像头等供电。
其中，如图4所示，显示面板10包括多个阵列分布的像素单元，每个像素单元包括多个子像素，例如，每个像素单元包括第一子像素11a、第二子像素11b和第三子像素11c，第一子像素11a可以为红色子像素，第二子像素11b可以为绿色子像素， 第三子像素11c可以为蓝色子像素。
并且，每个子像素包括像素驱动电路，以及与每个像素驱动电路连接的发光器件。该发光器件可以为有机发光二极管(organic light-emittingdiode，OLED)、Miniled(迷你发光二极管)、MicroLed(微发光二极管)以及量子点发光二极管(quantum dot lightemitting diodes，QLED)等。在一些实施例中，终端设备100可以包括1个或N个显示面板10，N为大于1的正整数。
需要说明的是，各个子像素的像素驱动电路基本类似，只是与其连接的发光器件不同，当子像素中的发光器件发出的光线颜色为红色时，该子像素为红色子像素，当子像素中的发光器件发出的光线颜色为绿色时，该子像素为绿色子像素，当子像素中的发光器件发出的光线颜色为蓝色时，该子像素为蓝色子像素。
如图5所示，每个子像素中的像素驱动电路包括：第一复位模块21、发光控制模块22、数据写入模块23、驱动模块24、第二复位模块25、阈值补偿模块26和存储模块27。
第二复位模块25分别与复位信号端Reset、第二初始化信号端Init2和驱动模块24的控制端连接，用于在复位信号端Reset输入的复位信号的控制下开启，通过第二初始化信号端Init2输入的第二初始化信号对驱动模块24的控制端进行复位；数据写入模块23分别与第一扫描信号端Scan1、数据信号端Data和驱动模块24的第一端连接，用于在第一扫描信号端Scan1输入的第一扫描信号的控制下开启，向驱动模块24写入数据信号端Data输入的数据信号；阈值补偿模块26分别与第二扫描信号端Scan2、驱动模块24的第二端和驱动模块24的控制端连接，用于在第二扫描信号端Scan2输入的第二扫描信号的控制下开启，对驱动模块24的阈值电压进行补偿；存储模块27分别第一电压信号端ELVDD和驱动模块24的控制端连接，用于稳定驱动模块24的控制端的电压；第一复位模块21分别与发光控制信号端EM、第一初始化信号端Init1和发光器件EL的第一端连接，用于在发光控制信号端EM输入的发光控制信号的控制下开启，通过第一初始化信号端Init1输入的第一初始化信号对发光器件EL的第一端进行复位；发光控制模块22分别与发光控制信号端EM、驱动模块24和发光器件EL的第一端连接，用于在发光控制信号端EM输入的发光控制信号的控制下开启，通过驱动模块24驱动发光器件EL发光。
其中，第一复位模块21和发光控制模块22中的一者在发光控制信号为高电平时开启，第一复位模块21和发光控制模块22中的另一者在发光控制信号为低电平时开启；并且，发光控制信号的频率大于120HZ。
在显示面板10显示每一帧画面时，每个像素驱动电路需要经过三个阶段，分别为复位阶段、数据写入阶段和发光控制阶段。
在复位阶段，复位信号端Reset输入的复位信号为有效信号，使得第二复位模块25在复位信号端Reset输入的复位信号的控制下开启，第二初始化信号端Init2输入的第二初始化信号通过第二复位模块25传输至驱动模块24的控制端，对驱动模块24的控制端进行复位，从而避免上一帧画面显示时驱动模块24的控制端残留的电荷，对这一帧的画面显示造成影响；并且，在复位阶段，发光控制信号端EM输入的发光控制信号，对第一复位模块21来说为有效信号，第一复位模块21在发光控制信号端EM 输入的发光控制信号的控制下开启，第一初始化信号端Init1输入的第一初始化信号通过第一复位模块21传输至发光器件EL的第一端，对发光器件EL的第一端进行复位，从而避免上一帧画面显示时发光器件EL的第一端残留的电荷，对这一帧的画面显示造成影响。
此时，第一扫描信号端Scan1输入的第一扫描信号为无效信号，使得数据写入模块23关闭；第二扫描信号端Scan2输入的第二扫描信号也为无效信号，使得阈值补偿模块26也关闭；发光控制信号端EM输入的发光控制信号，对发光控制模块22来说为无效信号，使得发光控制模块22也关闭。
需要说明的是，在复位阶段，驱动模块24也处于开启状态，但是由于发光控制模块22关闭，因此，流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在数据写入阶段，第一扫描信号端Scan1输入的第一扫描信号为有效信号，使得数据写入模块23在第一扫描信号端Scan1输入的第一扫描信号的控制下开启，数据信号端Data输入的数据信号通过数据写入模块23传输至驱动模块24的第一端；在数据写入阶段，第二扫描信号端Scan2输入的第二扫描信号为有效信号，使得阈值补偿模块26在第二扫描信号端Scan2输入的第二扫描信号的控制下开启。由于驱动模块24也处于开启状态，则写入驱动模块24的第一端的数据信号，会通过驱动模块24和阈值补偿模块26写入到驱动模块24的控制端，并且，由于阈值补偿模块26的存在，阈值补偿模块26会对驱动模块24的阈值电压进行补偿，因此，在将数据信号写入驱动模块24的控制端时，同时会将驱动模块24的阈值电压也写入到驱动模块24的控制端，即通过数据写入模块23和阈值补偿模块26，将数据信号端Data输入的数据信号和驱动模块24的阈值电压写入驱动模块24的控制端。
由于存储模块27的第一端与第一电压信号端ELVDD连接，存储模块27的第二端与驱动模块24的控制端连接，因此，在将数据信号和驱动模块24的阈值电压写入驱动模块24的控制端时，也就相当于将数据信号和驱动模块24的阈值电压存储至存储模块27，存储模块27可稳定驱动模块24的控制端的电压，防止因驱动模块24的漏电流的存在而导致驱动模块24的控制端的电压降低。
并且，在数据写入阶段，发光控制信号端EM输入的发光控制信号，对第一复位模块21来说依旧为有效信号，第一复位模块21在发光控制信号端EM输入的发光控制信号的控制下开启，第一初始化信号端Init1输入的第一初始化信号通过第一复位模块21传输至发光器件EL的第一端，继续对发光器件EL的第一端进行复位。
此时，复位信号端Reset输入的复位信号为无效信号，使得第二复位模块25关闭；发光控制信号端EM输入的发光控制信号，对发光控制模块22来说依旧为无效信号，使得发光控制模块22也关闭。
需要说明的是，在数据写入阶段，驱动模块24也处于开启状态，但是由于发光控制模块22关闭，因此，流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在发光控制阶段，发光控制信号端EM输入的发光控制信号对发光控制模块22来说为有效信号，发光控制模块22在发光控制信号端EM输入的发光控制信号的控制下 开启，由于驱动模块24也处于开启状态，则发光控制模块22可通过驱动模块24驱动发光器件EL发光。
此时，复位信号端Reset输入的复位信号为无效信号，使得第二复位模块25关闭；第一扫描信号端Scan1输入的第一扫描信号为无效信号，使得数据写入模块23关闭；第二扫描信号端Scan2输入的第二扫描信号也为无效信号，使得阈值补偿模块26也关闭；发光控制信号端EM输入的发光控制信号，对第一复位模块21来说为无效信号，使得第一复位模块21也关闭。
需要说明的是，有效信号指的是可控制对应模块开启时的信号，无效信号指的是控制对应模块关闭时的信号。当模块中的晶体管为N型晶体管时，有效信号指的是高电平信号，无效信号指的是低电平信号；当模块中的晶体管为P型晶体管时，有效信号指的是低电平信号，无效信号指的是高电平信号。
综上，可以看出，将发光控制模块22以及对发光器件EL进行复位的第一复位模块21均与发光控制信号端EM连接后，其中一者在发光控制信号为高电平时开启，另一者在发光控制信号为低电平时开启，使得发光控制模块22开启时，第一复位模块21可同步关闭，发光控制模块22关闭时，第一复位模块21可同步开启。
当发光控制模块22关闭，第一复位模块21同步开启时，第一复位模块21和发光控制模块22可同频降低发光器件EL的第一端的电压，使得发光控制信号在各个周期内，都可以将对应的发光器件EL的亮度降低至0nits；并且，将发光控制信号的频率调高至大于120HZ，其改善低亮度显示时画面出现频繁的闪烁现象的效果更好。
需要说明的是，本申请实施例中第一复位模块21和发光控制模块22同频将发光器件EL的第一端的电压降低至0nits，这里的0nits指的是误差允许范围内的数值，不一定指的是0nits这一具体数值，例如，在误差允许范围内，将发光器件EL的第一端降低至0.1nits，也默认为是将发光器件EL的第一端的电压降低至0nits。
其中，发光控制模块22包括第一发光控制单元221和第二发光控制单元222。第一发光控制单元221的控制端与发光控制信号端EM连接，第一发光控制单元221的第一端与第一电压信号端ELVDD连接，第一发光控制单元221的第二端与驱动模块24的第一端连接；第二发光控制单元222的控制端与发光控制信号端EM连接，第二发光控制单元222的第一端与驱动模块24的第二端连接，第二发光控制单元222的第二端与发光器件EL的第一端连接。
下面以两种可选的实施方式，介绍本申请实施例的像素驱动电路的具体结构和工作过程。
一种可选的实施方式，如图6所示，第一复位模块21包括第一复位晶体管T1，第一发光控制单元221包括第一发光控制晶体管T2，第二发光控制单元222包括第二发光控制晶体管T3，数据写入模块23包括数据写入晶体管T4，驱动模块24包括驱动晶体管T5，第二复位模块25包括第二复位晶体管T6，阈值补偿模块26包括补偿晶体管T7，存储模块27包括存储电容Cst。
第一复位晶体管T1的栅极与发光控制信号端EM连接，第一复位晶体管T1的第一极与第一初始化信号端Init1连接，第一复位晶体管T1的第二极与发光器件EL的第一端连接。
第一发光控制晶体管T2的栅极与发光控制信号端EM连接，第一发光控制晶体管T2的第一极与第一电压信号端ELVDD连接，第一发光控制晶体管T2的第二极与驱动模块24的第一端连接。第一发光控制单元221的控制端指的是第一发光控制晶体管T2的栅极，第一发光控制单元221的第一端指的是第一发光控制晶体管T2的第一极，第一发光控制单元221的第二端指的是第一发光控制晶体管T2的第二极。具体的，第一发光控制晶体管T2的第二极是与驱动晶体管T5的第一极连接，即驱动模块24的第一端指的是驱动晶体管T5的第一极。
第二发光控制晶体管T3的栅极与发光控制信号端EM连接，第二发光控制晶体管T3的第一极与驱动模块24的第二端连接，第二发光控制晶体管T3的第二极与发光器件EL的第一端连接。第二发光控制单元222的控制端指的是第二发光控制晶体管T3的栅极，第二发光控制单元222的第一端指的是第二发光控制晶体管T3的第一极，第二发光控制单元222的第二端指的是第二发光控制晶体管T3的第二极。具体的，第二发光控制晶体管T3的第一极是与驱动晶体管T5的第二极连接，即驱动模块24的第二端指的是驱动晶体管T5的第二极。
数据写入晶体管T4的栅极与第一扫描信号端Scan1连接，数据写入晶体管T4的第一极与数据信号端Data连接，数据写入晶体管T4的第二极与驱动模块24的第一端连接。具体的，数据写入晶体管T4的第二极是与驱动晶体管T5的第一极连接。
驱动晶体管T5的栅极分别与第二复位模块25、存储模块27的第二端和阈值补偿模块26均连接，驱动晶体管T5的第一极与数据写入模块23以及第一发光控制单元221的第二端均连接，驱动晶体管T5的第二极分别与阈值补偿模块26和第二发光控制单元222的第一端均连接。具体的，驱动晶体管T5的栅极分别与第二复位晶体管T6的第二极、存储电容Cst的第二极板和补偿晶体管T7的第二极连接，驱动晶体管T5的第一极分别与数据写入晶体管T4的第二极以及第一发光控制晶体管T2的第二极连接，驱动晶体管T5的第二极分别与补偿晶体管T7的第一极和第二发光控制晶体管T3的第一极连接，即驱动模块24的控制端指的是驱动晶体管T5的栅极。
第二复位晶体管T6的栅极与复位信号端Reset连接，第二复位晶体管T6的第一极与第二初始化信号端Init2连接，第二复位晶体管T6的第二极分别与存储模块27的第二端、驱动模块24的控制端和阈值补偿模块26连接。具体的，第二复位晶体管T6的第二极分别与存储电容Cst的第二极板、驱动晶体管T5的栅极和补偿晶体管T7的第二极连接。
补偿晶体管T7的栅极与第二扫描信号端Scan2连接，补偿晶体管T7的第一极分别与驱动模块24的第二端以及第二发光控制单元222的第一端连接，补偿晶体管T7的第二极分别与存储模块27的第二端、驱动模块24的控制端和第二复位模块25连接。具体的，补偿晶体管T7的第一极是与驱动晶体管T5的第二极和第二发光控制晶体管T3的第一极连接，补偿晶体管T7的第二极是与存储电容Cst的第二极板、驱动晶体管T5的栅极和第二复位晶体管T6的第二极连接。
存储电容Cst的第一极板与第一电压信号端ELVDD连接，存储电容Cst的第二极板分别与驱动模块24的控制端、第二复位模块25和阈值补偿模块26连接。具体的，存储电容Cst的第二极板是与驱动晶体管T5的栅极、第二复位晶体管T6的第二极和 补偿晶体管T7的第二极连接，存储模块27的第一端指的是存储电容Cst的第一极板，存储模块27的第二端指的是存储电容Cst的第二极板。
在图6中，第一复位晶体管T1为N型晶体管，第一发光控制晶体管T2和第二发光控制晶体管T3均为P型晶体管，数据写入晶体管T4和驱动晶体管T5均为P型晶体管，第二复位晶体管T6和补偿晶体管T7均为N型晶体管。
下面结合图7所示的时序图，说明图6所示的像素驱动电路的具体工作过程。
在复位阶段t11，复位信号端Reset输入的复位信号为高电平，此时的复位信号为有效信号，使得第二复位晶体管T6在复位信号端Reset输入的复位信号的控制下导通，第二初始化信号端Init2输入的第二初始化信号通过第二复位晶体管T6传输至驱动晶体管T5的栅极(即Vg节点)，对驱动晶体管T5的栅极进行复位，使得驱动晶体管T5的栅极电压被调整为第二初始化信号对应的第二初始化电压Vinit2。例如，第二初始化信号对应的第二初始化电压Vinit2为-3V，则第二复位晶体管T6对驱动晶体管T5的栅极进行复位后，可将驱动晶体管T5的栅极(即Vg节点)的电压调整为-3V。
并且，在复位阶段t11，发光控制信号端EM输入的发光控制信号为高电平，此时的发光控制信号对第一复位晶体管T1来说为有效信号，使得第一复位晶体管T1在发光控制信号端EM输入的发光控制信号的控制下导通，第一初始化信号端Init1输入的第一初始化信号通过第一复位晶体管T1传输至发光器件EL的第一端，对发光器件EL的第一端进行复位，使得发光器件EL的第一端的电压被调整为第一初始化信号对应的第一初始化电压Vinit1。
由于在上一帧显示驱动过程中的发光控制阶段，驱动晶体管T5的第一极的电压(即Vs节点的电压)为第一电压信号端ELVDD的电压Vdd，因此，在复位阶段t11，Vs节点的电压基本上等于Vdd，驱动晶体管T5的第一极指的是驱动晶体管T5的源极，由于驱动晶体管T5的栅极与源极的电压差Vgs小于驱动晶体管T5的阈值电压Vth，则驱动晶体管T5也处于导通状态。
另外，在复位阶段t11，第一扫描信号端Scan1输入的第一扫描信号为高电平，此时的第一扫描信号为无效信号，使得数据写入晶体管T4截止；第二扫描信号端Scan2输入的第二扫描信号为低电平，此时的第二扫描信号也为无效信号，使得补偿晶体管T7也处于截止状态；而发光控制信号端EM输入的发光控制信号为高电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说为无效信号，使得第一发光控制晶体管T2和第二发光控制晶体管T3也处于截止状态，则流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在数据写入阶段t12，第一扫描信号端Scan1输入的第一扫描信号为低电平，此时的第一扫描信号为有效信号，使得数据写入晶体管T4导通，数据信号端Data输入的数据信号通过数据写入晶体管T4传输至驱动晶体管T5的第一极，此时Vs节点的电压为数据信号对应的数据电压Vdata；在数据写入阶段t12，第二扫描信号端Scan2输入的第二扫描信号为高电平信号，此时的第二扫描信号为有效信号，使得补偿晶体管T7导通，则写入到驱动晶体管T5的第一极的数据信号依次通过驱动晶体管T5和补偿晶体管T7写入到驱动晶体管T5的栅极，随着数据信号的写入，驱动晶体管T5的栅极电压逐渐升高，直到驱动晶体管T5的栅极电压变为Vdata+Vth，即Vg节点的电压 为Vdata+Vth。
并且，在数据写入阶段t12，发光控制信号端EM输入的发光控制信号依旧为高电平，此时的发光控制信号对第一复位晶体管T1来说为依旧有效信号，使得第一复位晶体管T1导通，第一初始化信号端Init1输入的第一初始化信号继续通过第一复位晶体管T1传输至发光器件EL的第一端，继续对发光器件EL的第一端进行复位，使得发光器件EL的第一端的电压维持在第一初始化电压Vinit1。
此外，在数据写入阶段t12，复位信号端Reset输入的复位信号为低电平，此时的复位信号为无效信号，使得第二复位晶体管T6截止；而发光控制信号端EM输入的发光控制信号依旧为高电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说依旧为无效信号，使得第一发光控制晶体管T2和第二发光控制晶体管T3也处于截止状态，则流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在发光控制阶段t13，发光控制信号端EM输入的发光控制信号为低电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说为有效信号，第一发光控制晶体管T2和第二发光控制晶体管T3在发光控制信号端EM输入的发光控制信号的控制下导通。并且，由于第一发光控制晶体管T2导通，则Vs节点的电压从Vdata变为Vdd，而Vg节点的电压为Vdata+Vth，Vgs小于0，则使得驱动晶体管T5继续维持在导通状态，则流入发光器件EL的驱动电流I＝K(Vgs-Vth) 2＝K(Vdata+Vth-Vdd-Vth) 2＝K(Vdata-Vdd) 2。其中，K为常数，具体数值由驱动晶体管T5本身的特性来决定，可以看出，流入发光器件EL的驱动电流与驱动晶体管T5的阈值电压Vth无关，则通过补偿晶体管T7，可使得流入发光器件EL的驱动电流与驱动晶体管T5的阈值电压Vth无关，避免驱动晶体管T5的阈值电压Vth波动而影响发光器件EL的发光亮度，提高显示面板的亮度均一性。
而在发光控制阶段t13，复位信号端Reset输入的复位信号为低电平，此时的复位信号为无效信号，使得第二复位晶体管T6截止；第一扫描信号端Scan1输入的第一扫描信号为高电平，此时的第一扫描信号为无效信号，使得数据写入晶体管T4截止；第二扫描信号端Scan2输入的第二扫描信号为低电平，此时的第二扫描信号也为无效信号，使得补偿晶体管T7也处于截止状态；发光控制信号端EM输入的发光控制信号为低电平，此时的发光控制信号对第一复位晶体管T1来说为无效信号，使得第一复位晶体管T1截止。
因此，可以看出，针对图6所示的像素驱动电路，当第一复位晶体管T1的栅极、第一发光控制晶体管T2的栅极和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接时，在复位阶段t11和数据写入阶段t12，发光控制信号为高电平，使得第一复位晶体管T1处于导通状态，而第一发光控制晶体管T2和第二发光控制晶体管T3处于截止状态，而在发光控制阶段t13，发光控制信号为低电平，使得第一复位晶体管T1处于截止状态，第一发光控制晶体管T2和第二发光控制晶体管T3处于导通状态。
也就是说，第一发光控制晶体管T2和第二发光控制晶体管T3处于截止状态的同时，第一复位晶体管T1处于导通状态，则第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3可同频降低发光器件EL的第一端的电压；并且，当发 光控制信号的频率被调高至大于120HZ时，可有效改善低亮度显示时画面出现频繁的闪烁现象。
需要说明的是，在复位阶段t11和数据写入阶段t12，存在一定时长的间隔，其原因在于，第n行像素驱动电路中的复位信号端Reset，与第n-7行的像素驱动电路中的第二扫描信号端Scan2连接，因此，复位阶段t11和数据写入阶段t12之间的时间段，指的是第n-6行像素驱动电路至第n-1行像素驱动电路所对应的复位阶段t11；另外，在数据写入阶段t12与发光控制阶段t13之间也存在短暂的间隔，这是为了保证可以有足够的时间将驱动晶体管T5的栅极电压稳定在Vdata+Vth。
另一种可选的实施方式，如图8所示，第一复位模块21包括第一复位晶体管T1，第一发光控制单元221包括第一发光控制晶体管T2，第二发光控制单元222包括第二发光控制晶体管T3，数据写入模块23包括数据写入晶体管T4，驱动模块24包括驱动晶体管T5，第二复位模块25包括第二复位晶体管T6，阈值补偿模块26包括补偿晶体管T7，存储模块27包括存储电容Cst。
图8中的第一复位晶体管T1、第一发光控制晶体管T2、第二发光控制晶体管T3、数据写入晶体管T4、驱动晶体管T5、第二复位晶体管T6、补偿晶体管T7和存储电容Cst的连接关系，与图6中的第一复位晶体管T1、第一发光控制晶体管T2、第二发光控制晶体管T3、数据写入晶体管T4、驱动晶体管T5、第二复位晶体管T6、补偿晶体管T7和存储电容Cst的连接关系相同，为避免重复，在此不再赘述。
其不同之处在于，在图8中，第一复位晶体管T1为P型晶体管，第一发光控制晶体管T2和第二发光控制晶体管T3均为N型晶体管。
另外，在图8中，数据写入晶体管T4和驱动晶体管T5均为P型晶体管，第二复位晶体管T6和补偿晶体管T7均为N型晶体管。
下面结合图9所示的时序图，说明图8所示的像素驱动电路的具体工作过程。
在复位阶段t21，复位信号端Reset输入的复位信号为高电平，使得第二复位晶体管T6导通，第二初始化信号端Init2输入的第二初始化信号通过第二复位晶体管T6传输至驱动晶体管T5的栅极(即Vg节点)，对驱动晶体管T5的栅极进行复位。而发光控制信号端EM输入的发光控制信号为低电平，此时的发光控制信号对第一复位晶体管T1来说为有效信号，使得第一复位晶体管T1在发光控制信号端EM输入的发光控制信号的控制下导通，第一初始化信号端Init1输入的第一初始化信号通过第一复位晶体管T1传输至发光器件EL的第一端，对发光器件EL的第一端进行复位。
另外，在复位阶段t21，由于驱动晶体管T5的第一极的电压基本上等于第一电压信号端ELVDD的电压Vdd，驱动晶体管T5的栅极与源极的电压差小于驱动晶体管T5的阈值电压Vth，则驱动晶体管T5也处于导通状态；在复位阶段t21，第一扫描信号端Scan1输入的第一扫描信号为高电平，使得数据写入晶体管T4截止；第二扫描信号端Scan2输入的第二扫描信号为低电平，使得补偿晶体管T7也处于截止状态；而发光控制信号端EM输入的发光控制信号为低电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说为无效信号，使得第一发光控制晶体管T2和第二发光控制晶体管T3也处于截止状态，则流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在数据写入阶段t22，第一扫描信号端Scan1输入的第一扫描信号为低电平，使得数据写入晶体管T4导通，第二扫描信号端Scan2输入的第二扫描信号为高电平信号，使得补偿晶体管T7导通，则数据信号端Data输入的数据信号会依次通过数据写入晶体管T4、驱动晶体管T5和补偿晶体管T7写入到驱动晶体管T5的栅极，随着数据信号的写入，驱动晶体管T5的栅极电压逐渐升高，直到驱动晶体管T5的栅极电压变为Vdata+Vth，即Vg节点的电压为Vdata+Vth。
并且，在数据写入阶段t22，发光控制信号端EM输入的发光控制信号依旧为低电平，此时的发光控制信号对第一复位晶体管T1来说为依旧有效信号，使得第一复位晶体管T1导通，第一初始化信号端Init1输入的第一初始化信号继续通过第一复位晶体管T1传输至发光器件EL的第一端，继续对发光器件EL的第一端进行复位。
此外，在数据写入阶段t22，复位信号端Reset输入的复位信号为低电平，使得第二复位晶体管T6截止；而发光控制信号端EM输入的发光控制信号依旧为低电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说依旧为无效信号，使得第一发光控制晶体管T2和第二发光控制晶体管T3也处于截止状态，则流入发光器件EL的第一端的驱动电流为0，发光器件EL不会发光。
在发光控制阶段t23，发光控制信号端EM输入的发光控制信号为高电平，此时的发光控制信号对第一发光控制晶体管T2和第二发光控制晶体管T3来说为有效信号，第一发光控制晶体管T2和第二发光控制晶体管T3在发光控制信号端EM输入的发光控制信号的作用下导通，将Vs节点的电压从Vdata变为Vdd，而Vg节点的电压为Vdata+Vth，Vgs小于0，则使得驱动晶体管T5继续维持在导通状态，则流入发光器件EL的驱动电流I＝K(Vdata-Vdd) 2，流入发光器件EL的驱动电流与驱动晶体管T5的阈值电压Vth无关。
而在发光控制阶段t23，复位信号端Reset输入的复位信号为低电平，使得第二复位晶体管T6截止；第一扫描信号端Scan1输入的第一扫描信号为高电平，使得数据写入晶体管T4截止；第二扫描信号端Scan2输入的第二扫描信号为低电平，使得补偿晶体管T7也处于截止状态；发光控制信号端EM输入的发光控制信号为高电平，此时的发光控制信号对第一复位晶体管T1来说为无效信号，使得第一复位晶体管T1截止。
因此，可以看出，针对图8所示的像素驱动电路，当第一复位晶体管T1的栅极、第一发光控制晶体管T2的栅极和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接时，在复位阶段t21和数据写入阶段t22，发光控制信号为低电平，使得第一复位晶体管T1处于导通状态，而第一发光控制晶体管T2和第二发光控制晶体管T3处于截止状态，而在发光控制阶段t23，发光控制信号为高电平，使得第一复位晶体管T1处于截止状态，第一发光控制晶体管T2和第二发光控制晶体管T3处于导通状态。
也就是说，第一发光控制晶体管T2和第二发光控制晶体管T3处于截止状态的同时，第一复位晶体管T1处于导通状态，则第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3可同频降低发光器件EL的第一端的电压；并且，当发光控制信号的频率被调高至大于120HZ时，可有效改善低亮度显示时画面出现频繁的闪烁现象。
需要说明的是，第n行像素驱动电路中的复位信号端Reset，与第n-7行的像素驱 动电路中的第二扫描信号端Scan2连接，因此，在复位阶段t21和数据写入阶段t22之间的时间段，指的是第n-6行像素驱动电路至第n-1行像素驱动电路所对应的复位阶段t11；另外，在数据写入阶段t22与发光控制阶段t23之间也存在短暂的间隔，这是为了保证可以有足够的时间将驱动晶体管T5的栅极电压稳定在Vdata+Vth。
图10示出的是本申请实施例的像素驱动电路在驱动发光器件发光时的亮度曲线示意图，横坐标表示时间，单位为s，纵坐标表示亮度，单位为nits，其测试的条件是，将第一复位晶体管T1的栅极、第一发光控制晶体管T2的栅极和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接，第一复位晶体管T1为N型晶体管，第一发光控制晶体管T2和第二发光控制晶体管T3均为P型晶体管，且发光控制信号端EM输入的发光控制信号的频率为240HZ。
经测试，如图10所示，在A3时刻，发光控制信号从低电平变为高电平，使得第一复位晶体管T1从截止状态变为导通状态，同时第一发光控制晶体管T2和第二发光控制晶体管T3从导通状态变为截止状态，通过第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3，同频降低发光器件EL的第一端的电压，来降低发光器件EL的亮度，使得此时的发光器件EL的亮度L2可降低至0nits。因此，发光控制信号在相邻两个周期内，其对应的发光器件EL的降低后的亮度基本一致。
相应的，当将第一复位晶体管T1的栅极、第一发光控制晶体管T2的栅极和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接，且第一复位晶体管T1为P型晶体管，第一发光控制晶体管T2和第二发光控制晶体管T3为N型晶体管时，第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3，也可以同频降低发光器件EL的第一端的电压，来降低发光器件EL的亮度，使得发光控制信号在相邻两个周期内，其对应的发光器件EL的降低后的亮度基本一致。
由于将发光控制信号端EM输入的发光控制信号的频率提高至240HZ，且第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3同频降低发光器件EL的亮度至0nits，则可以使得发光器件EL的亮态与暗态的变化频率也提高至240HZ，则相应增加了发光器件EL在一帧画面显示时的亮态与暗态的变化频率，从而改善低亮度显示时画面出现频繁的闪烁现象的问题。
并且，由于第一复位晶体管T1的栅极、第一发光控制晶体管T2的栅极和第二发光控制晶体管T3的栅极均与发光控制信号端EM连接，通过一路信号即可同时控制第一复位晶体管T1、第一发光控制晶体管T2和第二发光控制晶体管T3，相对于第一复位晶体管T1采用一路信号控制，而第一发光控制晶体管T2和第二发光控制晶体管T3采用另一路信号控制，本申请实施例可减小了输入至每个像素驱动电路的信号数量，相应的，也就减少了传输信号所需的信号线的数量，简化了显示面板的走线设计。
可以理解的是，数据写入晶体管T4也可以为N型晶体管，第二复位晶体管T6也可以为P型晶体管，补偿晶体管T7也可以为P型晶体管。当数据写入晶体管T4、第二复位晶体管T6和补偿晶体管T7的类型发生改变时，其栅极连接的信号端所输入的信号也要发生翻转，例如，当数据写入晶体管T4变为N型晶体管时，在复位阶段和发光控制阶段，将第一扫描信号端Scan1输入的第一扫描信号变为低电平，而在数据写入阶段，将第一扫描信号端Scan1输入的第一扫描信号变为高电平。
在此需要说明的是，在本申请实施例中，各个晶体管的源极和漏极在一定条件下是可以互换的，因此，各个晶体管的源极、漏极从连接关系的描述上是没有区别的。在本申请实施例中，为了区分晶体管的源极和漏极，将其中的一极称为第一极，另一极称为第二极，此外，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管，对于N型晶体管，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时导通，P型晶体管相反。
并且，第一复位晶体管T1、第一发光控制晶体管T2、第二发光控制晶体管T3、数据写入晶体管T4、驱动晶体管T5、第二复位晶体管T6和补偿晶体管T7，可以为氧化物半导体晶体管或者低温多晶硅晶体管。
上述说明将发光控制信号的频率从120Hz提高至240HZ，来改善低亮度显示时画面出现频繁的闪烁现象的问题，可以理解的是，也可以将发光控制信号的频率提高至其他频率，如150HZ、360HZ等，只要保证本申请实施例中的发光控制信号的频率大于120HZ，就可以改善低亮度显示时画面出现频繁的闪烁现象，当发光控制信号的频率越高时，低亮度显示时的频闪问题改善效果更好。
另外，上述说明了本申请实施例中的像素驱动电路为7T1C电路，可以理解的是，本申请实施例中的像素驱动电路不局限于图6和图8所示的像素驱动电路，其还可以为其他类型的像素驱动电路，如4T1C、5T1C或6T1C的像素驱动电路，只要保证像素驱动电路中，发光控制模块22包括的晶体管的栅极和第一复位模块21包括的晶体管的栅极均与发光控制信号端EM连接，且发光控制模块22中的晶体管与第一复位模块21中的晶体管，其中一者在发光控制信号为高电平时导通，另一者在发光控制信号为低电平时导通，均可适用于本申请。
例如，本申请也可采用6T1C的像素驱动电路，具体的，可以将图6和图8所示的像素驱动电路中的第二复位晶体管T6去除，得到6T1C的像素驱动电路，此时的像素驱动电路不包括第二复位模块25。
或者，本申请还可以采用4T1C的像素驱动电路，具体的，可以将图6所示的像素驱动电路中的第二复位晶体管T6、补偿晶体管T7和第一发光控制晶体管T2去除，以得到如图11所示的4T1C的像素驱动电路，此时的像素驱动电路包括第一复位晶体管T1、第二发光控制晶体管T3、数据写入晶体管T4、驱动晶体管T5和存储电容Cst，而不包括第二复位模块25、阈值补偿模块26和第一发光控制单元221；并且，数据写入晶体管T4的第二极与驱动晶体管T5的栅极连接，驱动晶体管T5的第一极与第一电压信号端ELVDD连接。当发光控制模块22包括第二发光控制单元222而不包括第一发光控制单元221时，第一复位晶体管T1的类型与第二发光控制晶体管T3的类型相反，即当第一复位晶体管T1为P型晶体管时，第二发光控制晶体管T3为N型晶体管，或者，当第一复位晶体管T1为N晶体管时，第二发光控制晶体管T3为P型晶体管。
因此，当第一复位模块21包括的晶体管为N型晶体管，发光控制模块22包括的晶体管为P型晶体管；当第一复位模块21包括的晶体管为P型晶体管，发光控制模块22包括的晶体管为N型晶体管。发光控制模块可以仅包括第二发光控制单元222，也可以包括第一发光控制单元22和第二发光控制单元222。
本申请实施例还提供了一种显示面板，包括多个如图6、图8或图11所示的像素驱动电路，以及与每个像素驱动电路连接的发光器件EL。
其中，发光器件EL的第一端指的是发光器件EL的阳极，发光器件EL的第二端指的是发光器件EL的阴极，而发光器件EL的第二端与第二电压信号端ELVSS连接。
在本申请实施例中，第n行像素驱动电路中的复位信号端Reset，与第n-7行的像素驱动电路中的第二扫描信号端Scan2连接，n为大于7的正整数。
例如，如图12所示，每行像素驱动电路均分别与复位信号端Reset、第二初始化信号端Init2、第一初始化信号端Init1、发光控制信号端EM、第一扫描信号端Scan1和第二扫描信号端Scan2连接，第1行像素驱动电路的第二扫描信号端Scan2还与第8行像素驱动电路的复位信号端Reset连接，第2行像素驱动电路的第二扫描信号端Scan2还与第9行像素驱动电路的复位信号端Reset连接，以此类推。而第1行像素驱动电路至第7行像素驱动电路的复位信号端Reset，是需要接收外部输入的复位信号。
当第n行像素驱动电路中的复位信号端Reset，与第n-7行的像素驱动电路中的第二扫描信号端Scan2连接时，可减小外部输入的复位信号。
此外，显示面板还包括阵列基板行驱动(gate on array，GOA)电路，GOA电路包括EM GOA电路、第一扫描GOA电路和第二扫描GOA电路等，EM GOA电路与各行像素驱动电路的发光控制信号端EM连接，用于向各行像素驱动电路的发光控制信号端EM输入发光控制信号，第一扫描GOA电路与各行像素驱动电路的第一扫描信号端Scan1连接，用于向各行像素驱动电路的第一扫描信号端Scan1输入第一扫描信号，第二扫描GOA电路与各行像素驱动电路的第二扫描信号端Scan2连接，用于向各行像素驱动电路的第二扫描信号端Scan2输入第二扫描信号。
通常，显示面板包括显示区和围绕显示区的非显示区，像素驱动电路和发光器件EL位于显示区，GOA电路均位于非显示区。
以上的实施方式、结构示意图或仿真示意图仅为示意性说明本申请的技术方案，其中的尺寸比例并不构成对该技术方案保护范围的限定，任何在上述实施方式的精神和原则之内所做的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (14)

  1. 一种像素驱动电路，其特征在于，用于驱动发光器件发光，所述像素驱动电路包括：第一复位模块、发光控制模块和驱动模块；
    所述第一复位模块，分别与发光控制信号端、第一初始化信号端和所述发光器件的第一端连接，用于在所述发光控制信号端输入的发光控制信号的控制下开启，通过所述第一初始化信号端输入的第一初始化信号对所述发光器件的第一端进行复位；
    所述发光控制模块，分别与所述发光控制信号端、所述驱动模块和所述发光器件的第一端连接，用于在所述发光控制信号端输入的发光控制信号的控制下开启，通过所述驱动模块驱动所述发光器件发光；
    其中，所述第一复位模块和所述发光控制模块中的一者在所述发光控制信号为高电平时开启，所述第一复位模块和所述发光控制模块中的另一者在所述发光控制信号为低电平时开启；所述发光控制信号的频率大于120HZ。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述发光控制模块包括第一发光控制单元和第二发光控制单元；
    所述第一发光控制单元的控制端与所述发光控制信号端连接，所述第一发光控制单元的第一端与第一电压信号端连接，所述第一发光控制单元的第二端与所述驱动模块的第一端连接；
    所述第二发光控制单元的控制端与所述发光控制信号端连接，所述第二发光控制单元的第一端与所述驱动模块的第二端连接，所述第二发光控制单元的第二端与所述发光器件的第一端连接。
  3. 根据权利要求2所述的像素驱动电路，其特征在于，所述第一复位模块包括第一复位晶体管，所述第一复位晶体管的栅极与所述发光控制信号端连接，所述第一复位晶体管的第一极与所述第一初始化信号端连接，所述第一复位晶体管的第二极与所述发光器件的第一端连接；
    所述第一发光控制单元包括第一发光控制晶体管，所述第一发光控制晶体管的栅极与所述发光控制信号端连接，所述第一发光控制晶体管的第一极与所述第一电压信号端连接，所述第一发光控制晶体管的第二极与所述驱动模块的第一端连接；
    所述第二发光控制单元包括第二发光控制晶体管，所述第二发光控制晶体管的栅极与所述发光控制信号端连接，所述第二发光控制晶体管的第一极与所述驱动模块的第二端连接，所述第二发光控制晶体管的第二极与所述发光器件的第一端连接。
  4. 根据权利要求3所述的像素驱动电路，其特征在于，所述第一复位晶体管为N型晶体管，所述第一发光控制晶体管和所述第二发光控制晶体管均为P型晶体管。
  5. 根据权利要求3所述的像素驱动电路，其特征在于，所述第一复位晶体管为P型晶体管，所述第一发光控制晶体管和所述第二发光控制晶体管均为N型晶体管。
  6. 根据权利要求2所述的像素驱动电路，其特征在于，所述驱动模块包括驱动晶体管，所述驱动晶体管的第一极与所述第一发光控制单元的第二端连接，所述驱动晶体管的第二极与所述第二发光控制单元的第一端连接。
  7. 根据权利要求1至6中任一项所述的像素驱动电路，其特征在于，所述像素驱动电路还包括：数据写入模块、第二复位模块、阈值补偿模块和存储模块；
    所述第二复位模块，分别与复位信号端、第二初始化信号端和所述驱动模块的控制端连接，用于在所述复位信号端输入的复位信号的控制下开启，通过所述第二初始化信号端输入的第二初始化信号对所述驱动模块的控制端进行复位；
    所述数据写入模块，分别与第一扫描信号端、数据信号端和所述驱动模块的第一端连接，用于在所述第一扫描信号端输入的第一扫描信号的控制下开启，向所述驱动模块写入所述数据信号端输入的数据信号；
    所述阈值补偿模块，分别与第二扫描信号端、所述驱动模块的第二端和所述驱动模块的控制端连接，用于在所述第二扫描信号端输入的第二扫描信号的控制下开启，对所述驱动模块的阈值电压进行补偿；
    所述存储模块，分别第一电压信号端和所述驱动模块的控制端连接，用于稳定所述驱动模块的控制端的电压。
  8. 根据权利要求7所述的像素驱动电路，其特征在于，所述数据写入模块包括数据写入晶体管，所述数据写入晶体管的栅极与所述第一扫描信号端连接，所述数据写入晶体管的第一极与所述数据信号端连接，所述数据写入晶体管的第二极与所述驱动模块的第一端连接。
  9. 根据权利要求7所述的像素驱动电路，其特征在于，所述第二复位模块包括第二复位晶体管，所述第二复位晶体管的栅极与所述复位信号端连接，所述第二复位晶体管的第一极与所述第二初始化信号端连接，所述第二复位晶体管的第二极与所述驱动模块的控制端连接。
  10. 根据权利要求7所述的像素驱动电路，其特征在于，所述阈值补偿模块包括补偿晶体管，所述补偿晶体管的栅极与所述第二扫描信号端连接，所述补偿晶体管的第一极与所述驱动模块的第二端连接，所述补偿晶体管的第二极与所述驱动模块的控制端连接。
  11. 根据权利要求7所述的像素驱动电路，其特征在于，所述存储模块包括存储电容，所述存储电容的第一极板与所述第一电压信号端连接，所述存储电容的第二极板与所述驱动模块的控制端连接。
  12. 一种驱动方法，其特征在于，应用于驱动如权利要求1至11中任一项所述的像素驱动电路，所述方法包括：
    在复位阶段，第一复位模块开启，对发光器件的第一端进行复位；
    在数据写入阶段，所述第一复位模块开启，对所述发光器件的第一端继续进行复位；
    在发光控制阶段，发光控制模块开启，通过所述驱动模块驱动所述发光器件发光。
  13. 一种显示面板，其特征在于，包括多个如权利要求1至11中任一项所述的像素驱动电路，以及与每个所述像素驱动电路连接的发光器件。
  14. 一种终端设备，其特征在于，包括：壳体以及如权利要求13所述的显示面板，所述显示面板安装于所述壳体上。
PCT/CN2022/076208 2021-06-22 2022-02-14 像素驱动电路及其驱动方法、显示面板及终端设备 WO2022267491A1 (zh)

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