WO2022094738A1 - 像素电路及驱动方法、显示面板、显示装置 - Google Patents

像素电路及驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2022094738A1
WO2022094738A1 PCT/CN2020/126034 CN2020126034W WO2022094738A1 WO 2022094738 A1 WO2022094738 A1 WO 2022094738A1 CN 2020126034 W CN2020126034 W CN 2020126034W WO 2022094738 A1 WO2022094738 A1 WO 2022094738A1
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Prior art keywords
transistor
circuit
signal terminal
control
coupled
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Application number
PCT/CN2020/126034
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English (en)
French (fr)
Inventor
肖丽
郑皓亮
陈昊
玄明花
刘冬妮
韩承佑
陈亮
赵蛟
董学
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002627.4A priority Critical patent/CN114766048B/zh
Priority to EP20960201.0A priority patent/EP4145434A4/en
Priority to PCT/CN2020/126034 priority patent/WO2022094738A1/zh
Priority to US17/620,398 priority patent/US11688347B2/en
Priority to TW110135545A priority patent/TWI779845B/zh
Publication of WO2022094738A1 publication Critical patent/WO2022094738A1/zh
Priority to US18/308,385 priority patent/US20230260461A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a driving method, a display panel, and a display device.
  • a pixel circuit in one aspect, includes a driving circuit, a first control circuit and a second control circuit.
  • the driving circuit is coupled to at least a data signal terminal, a scan signal terminal, a first voltage terminal and a first enable signal terminal.
  • the first control circuit is coupled to at least a second enable signal terminal, a first control signal terminal, a first input signal terminal, a second control signal terminal, a second input signal terminal and a third input signal terminal.
  • the second control circuit is coupled to the driving circuit, the first control circuit and the element to be driven.
  • the driver circuit is configured to write a data signal received at the data signal terminal in response to a scan signal received at the scan signal terminal, and, in response to a scan signal received at the first enable signal terminal
  • the first enable signal of the first voltage terminal generates a driving signal according to the first voltage of the first voltage terminal and the written data signal.
  • the second control circuit is configured to respond to and receive one of the third input signal and the second enable signal, transmit a drive signal from the drive circuit to the element to be driven, and control The working time of the element to be driven.
  • the first control circuit is further coupled to a third control signal terminal, the first enable signal terminal and a second voltage terminal.
  • the first control circuit is further configured to transmit a second voltage at the second voltage terminal to the second control circuit in response to a third control signal received at the third control signal terminal; the first control circuit A control circuit is also configured to transmit the third input signal to the second control circuit in response to the first enable signal and the first input signal received at the first enable signal terminal.
  • the first control circuit includes a first input subcircuit.
  • the first input sub-circuit is coupled to the first control signal terminal, the first input signal terminal and the third input signal terminal.
  • the first input subcircuit is configured to write a first input signal received at the first input signal terminal in response to a first control signal received at the first control signal terminal, and, in response to The first input signal transmits the third input signal received at the third input signal terminal to the second control circuit.
  • the first input subcircuit is also coupled to the second control circuit.
  • the first input subcircuit includes: a first transistor, a second transistor and a first capacitor.
  • the control electrode of the first transistor is coupled to the first control signal terminal, and the first electrode of the first transistor is coupled to the first input signal terminal.
  • the control electrode of the second transistor is coupled to the second electrode of the first transistor, the first electrode of the second transistor is coupled to the third input signal terminal, and the second electrode of the second transistor coupled to the second control circuit.
  • the first capacitor is coupled to the second pole of the first transistor.
  • the first input subcircuit includes: a third transistor, a fourth transistor, and a second capacitor.
  • the control electrode of the third transistor is coupled to the first control signal terminal, and the first electrode of the third transistor is coupled to the first input signal terminal.
  • the control electrode of the fourth transistor is coupled to the second electrode of the third transistor, the first electrode of the fourth transistor is coupled to the third input signal terminal, and the second electrode of the fourth transistor is coupled to the voltage regulator sub-circuit.
  • the second capacitor is coupled to the second pole of the third transistor.
  • the voltage regulator sub-circuit includes: a fifth transistor and a sixth transistor.
  • the control electrode of the fifth transistor is coupled to the first enable signal terminal, the first electrode of the fifth transistor is coupled to the first input sub-circuit, and the second electrode of the fifth transistor is coupled to the first input sub-circuit.
  • the second control circuit is coupled.
  • the control electrode of the sixth transistor is coupled to the third control signal terminal, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the second voltage terminal.
  • the second control circuit is coupled.
  • the first control circuit further includes a second input subcircuit.
  • the second input sub-circuit is connected to the second control signal terminal, the second input signal terminal, the second enable signal terminal and the second control circuit.
  • the second input subcircuit is configured to write a second input signal received at the second input signal terminal in response to a second control signal received at the second control signal terminal, and, in response to The second input signal transmits the second enable signal received at the second enable signal terminal to the second control circuit.
  • the second input subcircuit includes: a seventh transistor, an eighth transistor, and a third capacitor.
  • the control electrode of the seventh transistor is coupled to the second control signal end, and the first electrode of the seventh transistor is coupled to the second input signal end.
  • the control electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, the first electrode of the eighth transistor is coupled to the second enable signal terminal, and the second electrode of the eighth transistor is coupled to the second enable signal terminal.
  • the pole is coupled to the second control circuit.
  • the third capacitor is coupled to the second pole of the seventh transistor.
  • the driving circuit further includes: a driving sub-circuit, a driving control sub-circuit, a data writing sub-circuit and a compensation sub-circuit.
  • the driving subcircuit includes a driving transistor and a fourth capacitor. The first terminal of the fourth capacitor is coupled to the first voltage terminal, and the second terminal of the fourth capacitor is coupled to the control electrode of the driving transistor.
  • the driving control sub-circuit is coupled to at least the first enable signal terminal, the first voltage terminal, and the driving sub-circuit.
  • the data writing subcircuit is coupled to the scan signal terminal, the data signal terminal and the driving subcircuit.
  • the compensation sub-circuit is coupled to the scan signal terminal, the control electrode of the driving transistor and the second electrode of the driving transistor.
  • the drive control sub-circuit is configured to pass the first voltage terminal and the second control circuit through the drive sub-circuit in response to a first enable signal received at the first enable signal terminal
  • the drive transistor forms a conductive path.
  • the driving sub-circuit is configured to generate the driving signal according to the written data signal and the first voltage of the first voltage terminal.
  • the data writing subcircuit is configured to write the data signal received at the data signal terminal into the driving subcircuit in response to the scan signal received at the scan signal terminal.
  • the compensation subcircuit is configured to write the data signal and the threshold voltage of the drive transistor to the gate of the drive transistor in response to the scan signal received at the scan signal terminal.
  • the drive control sub-circuit includes a tenth transistor.
  • the control electrode of the tenth transistor is coupled to the first enable signal terminal, the first electrode of the tenth transistor is coupled to the first voltage terminal, and the second electrode of the tenth transistor is coupled to the first voltage terminal.
  • the first electrode of the driving transistor is coupled.
  • the second pole of the driving transistor is coupled to the second control circuit.
  • the driving control sub-circuit includes: a tenth transistor and an eleventh transistor.
  • the control electrode of the tenth transistor is coupled to the first enable signal terminal, the first electrode of the tenth transistor is coupled to the first voltage terminal, and the second electrode of the tenth transistor is coupled to the first voltage terminal.
  • the first electrode of the driving transistor is coupled.
  • the control electrode of the eleventh transistor is coupled to the first enable signal terminal, the first electrode of the eleventh transistor is coupled to the second electrode of the driving transistor, and the The second pole is coupled to the second control circuit.
  • the data writing subcircuit includes a twelfth transistor.
  • the control electrode of the twelfth transistor is coupled to the scan signal end, the first electrode of the twelfth transistor is coupled to the data signal end, and the second electrode of the twelfth transistor is coupled to the data signal end.
  • the first pole of the driving transistor is coupled.
  • the compensation subcircuit includes a thirteenth transistor.
  • the control electrode of the thirteenth transistor is coupled to the scan signal terminal, the first electrode of the thirteenth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the thirteenth transistor is coupled to the control electrode of the driving transistor.
  • the drive circuit further includes a reset subcircuit.
  • the reset sub-circuit is coupled to the driving sub-circuit, the to-be-driven element, a reset signal terminal and an initial signal terminal.
  • the reset subcircuit is configured to transmit the initial signal received at the initial signal terminal to the driving subcircuit and the element to be driven in response to the reset signal received at the reset signal terminal.
  • the reset subcircuit includes: a fourteenth transistor and a fifteenth transistor.
  • the control electrode of the fourteenth transistor is coupled to the reset signal end, the first electrode of the fourteenth transistor is coupled to the initial signal end, and the second electrode of the fourteenth transistor is coupled to the initial signal end.
  • the gate electrode of the driving transistor is coupled.
  • the control electrode of the fifteenth transistor is coupled to the reset signal end, the first electrode of the fifteenth transistor is coupled to the initial signal end, and the second electrode of the fifteenth transistor is coupled to the initial signal end.
  • the element to be driven is coupled.
  • the first control signal terminal and the reset signal terminal are the same signal terminal
  • the second control signal terminal and the scan signal terminal are the same signal terminal
  • the first input signal terminal and the The second input signal terminal is the same signal terminal.
  • the first control signal terminal and the second control signal terminal are both the reset signal terminal or the scan signal terminal, and the first input signal terminal and the second control signal terminal are both the same.
  • the input signal terminals are different signal terminals.
  • the first control signal terminal and the second control signal terminal of a row of pixel circuits are respectively coupled to two first signal lines, and the first input signal terminal and the second input signal terminal of a column of pixel circuits are respectively connected to the same A second signal line is coupled.
  • a method for driving a pixel circuit includes a driving circuit, a first control circuit and a second control circuit.
  • the driving circuit is coupled to at least a data signal terminal, a scan signal terminal, a first voltage terminal and a first enable signal terminal.
  • the first control circuit is coupled to at least a second enable signal terminal, a first control signal terminal, a first input signal terminal, a second control signal terminal, a second input signal terminal and a third input signal terminal.
  • the second control circuit is coupled to the driving circuit, the first control circuit and the element to be driven.
  • the driving method includes:
  • the first control circuit writes a first input signal received at the first input signal terminal in response to a first control signal received at the first control signal terminal, responsive to the first input signal , transmitting the third input signal received at the third input signal terminal; or, the first control circuit, in response to the second control signal received at the second control signal terminal, writes in the third input signal
  • the second input signal received at the two input signal terminals transmits the second enable signal received at the second enable signal terminal in response to the second input signal;
  • the frequency of the third input signal is greater than the frequency of the second enable signal.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is a structural diagram of a sub-pixel according to some embodiments.
  • FIG. 3 is a structural diagram of a pixel circuit according to some embodiments.
  • FIG. 4 is another structural diagram of a pixel circuit according to some embodiments.
  • 5B is another structural diagram of a pixel circuit according to some embodiments.
  • 6C is yet another structural diagram of a pixel circuit according to some embodiments.
  • 6D is yet another structural diagram of a pixel circuit according to some embodiments.
  • 7C is another structural diagram of a display panel according to some embodiments.
  • FIG. 8 is a timing diagram of driving signals of a pixel circuit according to some embodiments.
  • FIG. 13 is another structural diagram of a display panel according to some embodiments.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components are in physical contact or that there is an electrical signal path, such as conducting a signal line between two components, or There may be other electrical components or circuits in between, but there is a signal path between the two components through the other electrical components.
  • the terms “coupled” or “communication coupling” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • the display device may be any device that displays text or images, whether in motion (eg, video) or stationary (eg, still images). More specifically, the display device may be one of a variety of electronic devices in which the embodiments may be implemented or associated with a variety of electronic devices, such as (but not limited to) Mobile Phones, Wireless Devices, Personal Data Assistants (PS1), Handheld or Portable Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, TV Monitors, Flat panel displays, computer monitors, automotive displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, camera view displays (eg, displays for rear view cameras in vehicles), electronic photos, electronic billboards Or signage, projectors, architectural structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • the embodiments of the present disclosure do not specifically limit the embodiments of the present disclosure do not specifically limit the embodiments of the present
  • the display device 200 includes the display panel 100 .
  • the display panel 100 has a display area (Active Area, AA) and a peripheral area S.
  • the peripheral area S is located at least on the outer side of the AA area.
  • the first pole of the element to be driven L is coupled to the pixel circuit 101, and the second pole of the element to be driven L is coupled to the third voltage terminal V3.
  • the third voltage terminal V3 is configured to transmit a DC voltage signal, eg, a DC low voltage (VSS); eg, the third voltage is -3V.
  • the element to be driven includes a current-driven device, further, a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED) or Organic Light Emitting Diode (OLED) or Quantum Light Emitting Diode (QLED).
  • a current-type light-emitting diode such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED) or Organic Light Emitting Diode (OLED) or Quantum Light Emitting Diode (QLED).
  • the working duration of the element to be driven can be understood as the light-emitting duration of the element to be driven
  • the operating frequency of the element to be driven can be understood as the light-emit
  • controlling the brightness of the element to be driven can be achieved by adjusting its lighting duration and/or driving current.
  • the driving currents of the two to-be-driven elements are the same and the light-emitting durations are different, the brightness displayed by the two to-be-driven elements is different; if the driving currents of the two to-be-driven elements are different and the light-emitting durations are the same, then the two The brightness displayed by the two to-be-driven elements is also different; if the two to-be-driven elements have different driving currents and light emission durations, specific analysis is required to determine whether the two to-be-driven elements display the same brightness.
  • the display panel further includes a base substrate on which the pixel circuit and the element to be driven are located.
  • the substrate substrate may include: a rigid substrate such as glass (or referred to as a rigid substrate), or a flexible substrate such as PI (Polyimide, polyimide); it may also include: disposed on the rigid substrate Or thin films such as buffer layers on flexible substrates.
  • Embodiments of the present disclosure provide a pixel circuit.
  • the pixel circuit 101 includes a first control circuit 10 , a second control circuit 20 and a driving circuit 30 .
  • the driving circuit 30 is coupled to at least the data signal terminal DATA, the scan signal terminal GATE, the first voltage terminal V1 and the first enable signal terminal EM.
  • the second control circuit 20 is coupled to the driving circuit 30 , the first control circuit 10 and the element L to be driven.
  • the drive circuit 30 is configured to write the data signal received at the data signal terminal DATA in response to the scan signal received at the scan signal terminal GATE, and, in response to the first enable signal terminal EM received at the first enable signal terminal EM An enable signal generates a driving signal according to the first voltage of the first voltage terminal V1 and the written data signal.
  • the first control circuit 10 is configured to write the first input signal received at the first input signal terminal S1 in response to the first control signal received at the first control signal terminal Q1, and to transmit in response to the first input signal The third input signal received at the third input signal terminal S3.
  • the first control circuit 10 is configured to write the second input signal received at the second input signal terminal S2 in response to the second control signal received at the second control signal terminal Q2, in response to the second input signal , and transmit the second enable signal received at the second enable signal terminal EM'.
  • the second control circuit 20 is configured to respond to and receive one of the third input signal and the second enable signal, transmit the driving signal from the driving circuit 30 to the element L to be driven, and control the working duration of the element L to be driven .
  • the operating frequency in the embodiment refers to the emitting frequency of the element to be driven in the working stage
  • the working duration in the embodiment refers to the emitting duration of the element to be driven in the working stage.
  • the first voltage received at the first voltage terminal is a DC voltage, eg, a DC high voltage; eg, the first voltage is 7V.
  • the third voltage received at the third voltage terminal is a low voltage, or the first voltage received at the first voltage terminal In the case of a low voltage, the third voltage received at the third voltage terminal is a high voltage.
  • the second enable signal terminal and the first enable signal terminal are the same signal terminal; for example, the second enable signal is the same as the first enable signal; for example, when the first enable signal is at an active level, The duration of the active level of the second enable signal is equal to the duration of the active level of the first enable signal.
  • the second enable signal terminal and the first enable signal terminal are different signal terminals; for example, in the stage when the first enable signal is at the active level, the duration of the active level of the second enable signal is shorter than the first enable signal The duration of the active level of an enable signal. For example, in the stage when the first enable signal is at the active level, the total duration of the active level of the third input signal is less than the duration of the active level of the second enable signal.
  • the second enable signal is the same as the first enable signal; or, for example, in the case where the sub-pixel where the pixel circuit is located displays a medium gray level, the driving signal
  • the amplitude of is maintained within a higher value range, and the duration of the active level of the second enable signal is controlled to be shorter than the duration of the active level of the first enable signal.
  • the third input signal received at the third input signal terminal is a pulse signal, for example, within an image frame, the third input signal has a plurality of pulses.
  • the frequency of the third input signal is greater than the frequency of the second enable signal. For example, in a unit time, the number of times that the second enable signal has a valid level period is less than the number of times that the third input signal has a valid level period.
  • the third input signal is a high-frequency pulse signal, for example, the frequency of the third input signal ranges from 3000 Hz to 60000 Hz, for example, it may be 3000 Hz or 60000 Hz.
  • the frequency of the first enable signal and the frequency of the second enable signal take values between 60 Hz and 120 Hz, for example, may be 60 Hz or 120 Hz.
  • the frame frequency of the display panel is 60 Hz, that is, within 1 s, the display panel can display 60 frames of images, and the display duration of each frame of images is equal.
  • the element to be driven when the third input signal is a high-frequency signal with a frequency of 3000 Hz, in an image frame, if the element to be driven is to emit low gray-scale brightness, the element to be driven can approximately receive the high-frequency signal during the light-emitting stage 50 valid time periods.
  • the first input signal is a high-level signal during the valid period of the first control signal received by the first control signal terminal Q1
  • the second input signal is a high-level signal.
  • the valid period of the second control signal received by the second control signal terminal Q2 it is a low level signal;
  • the first input signal is received at the first control signal terminal Q1.
  • the first control signal is a low-level signal during the valid period of time
  • the second input signal is a high-level signal during the valid period of the second control signal received by the second control signal terminal Q2.
  • the first control circuit does not transmit the second enable signal and the third input signal to the second control circuit at the same time.
  • the first control circuit transmits the second enable signal to the second control circuit; when the sub-pixel where the pixel circuit is located displays a low gray level, The first control circuit transmits the third input signal to the second control circuit.
  • the first control signal terminal Q1 and the second control signal terminal Q2 belonging to the same pixel circuit may be connected to the scan signal terminal GATE and the reset signal terminal RESET respectively, that is, the first control signal terminal belonging to the same pixel circuit
  • One of the terminal Q1 and the second control signal terminal Q2 can be connected to the same scan signal line with the scan signal terminal GATE, and the other is connected to the same reset signal line with the reset signal terminal RESET; the first input belonging to the same pixel circuit
  • the signal terminal S1 and the second input signal terminal S2 can be coupled to the same signal line, such as the second signal line in the following, by controlling the amplitude of the signal transmitted by the second signal line, to the first input signal terminal S1 and the second
  • the input signal terminal S2 provides signals with different amplitudes.
  • the first control circuit is controlled to transmit the second enable signal or the third input signal to the second control circuit, and the conduction of the second control circuit is controlled ( Turn on) frequency, control the frequency at which the drive circuit and the element to be driven form a conductive path, and can control the frequency at which the drive signal is transmitted to the element to be driven, the frequency at which the conductive path is formed determines the total working time of the element to be driven, and the total working time of the element to be driven.
  • the duration is the superposition of the sub-durations of the operation of the element to be driven when the conductive path is formed multiple times. In this way, the luminous intensity of the to-be-driven element can be controlled by controlling the frequency at which the drive signal is transmitted to the to-be-driven element by the amplitude of the drive signal, thereby realizing corresponding grayscale display.
  • the range of the amplitude of the driving signal should be within the range that the element to be driven works in a range with high and stable luminous efficiency, good uniformity of color coordinates and stable dominant wavelength of light, such as the amplitude of the driving signal. Therefore, the data signal provided by the data signal terminal when the element to be driven displays medium and high gray scales can have the same value range as the data signal provided by the data signal terminal when the element to be driven displays low gray scale.
  • the first control circuit transmits the second enable signal to the second control circuit, and in the light-emitting stage of the sub-pixel, the second control circuit keeps responding to the second enable signal.
  • the driving circuit and the element to be driven have always formed a conductive path, and the driving signal is continuously transmitted to the element to be driven. Since the amplitude of the driving signal corresponding to the middle, high and low gray scales is relatively high, the element to be driven can be driven at a higher amplitude. It works under the driving of a driving signal with a high value to ensure the working efficiency (luminous efficiency) of the element to be driven.
  • the first control circuit transmits the third input signal to the second control circuit, and in the light-emitting stage of the sub-pixel, the second control circuit responds to the third input signal with a high frequency
  • the pulse signal is in the state of being on and off alternately, so that the driving signal is intermittently transmitted to the element to be driven, and the element to be driven receives the driving signal periodically. Stop for a period of time after receiving the driving signal for a period of time. In this way, the time for the driving circuit to form a conductive path with the element to be driven is shortened, and the time for the driving signal to be transmitted to the element to be driven is shortened.
  • the amplitude of the driving signal can be maintained within a relatively high value range or a relatively large fixed amplitude, and by changing the working time of the element to be driven, the The sub-pixel realizes corresponding low grayscale display, thereby improving the working efficiency of the element to be driven, avoiding the problems of low working efficiency and high power consumption of the element to be driven in the case of realizing low grayscale display with a small current amplitude, avoiding the display
  • the uniformity of gray scale is reduced, the color shift of the display is avoided, and the display effect of the display panel is improved.
  • the magnitude of the driving signal is related to the data signal received at the data signal terminal, and the data signal may be a signal that enables the element to be driven to have higher working efficiency, for example, the data signal may be in a higher amplitude range.
  • the pixel circuit controls the amplitude range of the drive signal through the drive circuit, and controls the time and frequency at which the drive signal is transmitted to the element to be driven through the first control circuit and the second control circuit, so as to control the gray scale corresponding to the sub-pixel show.
  • the sub-pixels display a low gray scale in an image frame
  • the human eye will obviously feel the flickering situation.
  • the element to be driven is intermittently in the working state, that is, the working state and the non-working state of the element to be driven alternate and the alternating frequency is high, that is, the alternating frequency of light and dark of the element to be driven is high, and the human eye is not easy to observe the flicker, so Improved display.
  • embodiments of the present disclosure provide a pixel circuit, and the driving circuit generates a driving signal according to a first voltage and a written data signal.
  • the first control circuit writes the first input signal in response to the first control signal, transmits the third input signal in response to the first input signal; and, in response to the second control signal, writes the second input signal, in response to the second input signal to transmit the second enable signal.
  • the second control circuit transmits the received driving signal from the driving circuit to the element to be driven, and controls the working time of the element to be driven.
  • the first control circuit transmits the second enable signal to the second control circuit, so that the to-be-to-be-driven signal is transmitted to the second control circuit.
  • the driving element always works under the driving of a higher-amplitude driving signal to ensure the working efficiency of the element to be driven; when the sub-pixel where the pixel circuit is located displays a low gray scale, the first control circuit transmits the third input signal to the first control circuit.
  • the second control circuit makes the element to be driven intermittently in the working state, and by controlling the working time of the element to be driven, the element to be driven can also realize the corresponding grayscale display under the driving of the driving signal of higher amplitude, which improves the The working efficiency of the element to be driven. Moreover, the operating frequency of the element to be driven is relatively high, which can prevent the human eye from seeing flicker and improve the display effect.
  • the second control circuit 20 includes a ninth transistor T9.
  • the control electrode of the ninth transistor T9 is coupled to the first control circuit 10
  • the first electrode of the ninth transistor T9 is coupled to the driving circuit 30
  • the second electrode of the ninth transistor T9 is coupled to the element L to be driven.
  • the first control circuit 10 is further coupled to the third control signal terminal Q3 , the first enable signal terminal EM and the second voltage terminal V2 .
  • the first control circuit 10 is further configured to transmit the second voltage of the second voltage terminal V2 to the second control circuit 20 in response to the third control signal received at the third control signal terminal Q3; the first control circuit 10 is further is configured to transmit the third input signal to the second control circuit 20 in response to the first enable signal and the second input signal received at the first enable signal terminal EM.
  • the second voltage received at the second voltage terminal is a DC voltage, for example, the second voltage is a DC high voltage.
  • the first control circuit 10 may also transmit the second voltage to the second control circuit 20 to control the second control circuit 20 to receive the DC voltage.
  • the stability of the voltage of the internal elements of the second control circuit 20 is avoided when the third input signal is a pulse signal.
  • the first control circuit 10 includes a first input sub-circuit 11A.
  • the first input sub-circuit 11A is coupled to the first control signal terminal Q1, the first input signal terminal S1 and the third input signal terminal S3.
  • the first input subcircuit 11A is configured to write the first input signal received at the first input signal terminal S1 in response to the first control signal received at the first control signal terminal Q1, and, in response to the first input signal, the third input signal received at the third input signal terminal S3 is transmitted to the second control circuit 20 .
  • the first input sub-circuit 11A is also coupled to the second control circuit 20 .
  • the first input sub-circuit 11A includes a first transistor T1 , a second transistor T2 and a first capacitor C1 .
  • the control electrode of the first transistor T1 is coupled to the first control signal end Q1, and the first electrode of the first transistor T1 is coupled to the first input signal end S1.
  • the control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the third input signal terminal S3, and the second electrode of the second transistor T2 is coupled to the second control circuit 20 is coupled.
  • the second electrode of the second transistor T2 is coupled to the control electrode of the ninth transistor T9.
  • the first capacitor C1 is coupled to the second pole of the first transistor T1.
  • the first end of the first capacitor C1 is coupled to the second electrode of the first transistor T1, and the second end of the first capacitor C1 is coupled to the fixed voltage end.
  • the fixed voltage terminal is configured to transmit a fixed voltage signal, eg, the fixed voltage signal includes a DC voltage signal; eg, the fixed voltage signal is equal to or approximately equal to a ground signal; eg, the fixed voltage terminal may be a ground terminal.
  • the first capacitor in the first input sub-circuit can store the written first input signal, so as to control the voltage of the control electrode of the second transistor to be the voltage of the first input signal.
  • the first control circuit 10 further includes a voltage regulator sub-circuit 12 .
  • the voltage regulator sub-circuit 12 is coupled to the first input sub-circuit 11B, the first enable signal terminal EM, the third control signal terminal Q3 , the second voltage terminal V2 and the second control circuit 20 .
  • the voltage regulator sub-circuit 12 is configured to transmit the second voltage at the second voltage terminal V2 to the second control circuit 20 in response to the third control signal received at the third control signal terminal Q3;
  • the first enable signal received at the enable signal terminal EM transmits the signal from the first input sub-circuit 11B to the second control circuit 20 .
  • the third input signal is transmitted to the second control circuit 20.
  • the third input signal It will not be transmitted to the second control circuit 20 to prevent the third input signal from affecting the voltage of the second control circuit 20.
  • the voltage of the control electrode of the ninth transistor T9 in the second control circuit 20 is stable, which can prevent the third input signal from being
  • the high-frequency pulse signal affects the stability of the voltage of the second control circuit 20, for example, the voltage of the control electrode of the ninth transistor T9 in the second control circuit 20 oscillates, causing the problem that the voltage of the driving circuit 30 is affected, and, here In the stage, the voltage regulator sub-circuit 12 transmits the second voltage to the second control circuit 20, so that the second control circuit 20 receives a stable voltage, that is, the voltage of the control electrode of the ninth transistor T9 is stable, which ensures the stability of the second control circuit 20. Voltage stability.
  • the first input sub-circuit 11B includes: a third transistor T3 , a fourth transistor T4 and a first capacitor C1 .
  • the control electrode of the third transistor T3 is coupled to the first control signal end Q1, and the first electrode of the third transistor T3 is coupled to the first input signal end S1.
  • the control electrode of the fourth transistor T4 is coupled to the second electrode of the third transistor T3, the first electrode of the fourth transistor T4 is coupled to the third input signal terminal S3, and the second electrode of the fourth transistor T4 is coupled to the voltage regulator sub-circuit 12 Coupling.
  • the first capacitor C1 is coupled to the second pole of the third transistor T3.
  • the first terminal of the first capacitor C1 is coupled to the second terminal of the third transistor T3, and the second terminal of the first capacitor C1 is coupled to the fixed voltage terminal.
  • the fixed voltage terminal is configured to transmit a fixed voltage signal, eg, the fixed voltage signal includes a DC voltage signal; eg, the fixed voltage signal is equal to or approximately equal to a ground signal; eg, the fixed voltage terminal may be a ground terminal.
  • the second capacitor in the second input sub-circuit can store the written first input signal to control the voltage of the control electrode of the fourth transistor to be the voltage of the first input signal.
  • the voltage regulator sub-circuit 12 includes: a fifth transistor T5 and a sixth transistor T6.
  • the control electrode of the fifth transistor T5 is coupled to the first enable signal terminal EM, the first electrode of the fifth transistor T5 is coupled to the first input sub-circuit 11B, and the second electrode of the fifth transistor T5 is coupled to the second control circuit 20 coupled.
  • the control electrode of the sixth transistor T6 is coupled to the third control signal terminal Q3, the first electrode of the sixth transistor T6 is coupled to the second voltage terminal V2, and the second electrode of the sixth transistor T6 is coupled to the second control circuit 20 .
  • the first input sub-circuit 11B includes the fourth transistor T4
  • the first pole of the fifth transistor T5 is coupled with the second pole of the fourth transistor T4.
  • the second control circuit 20 includes the ninth transistor T9
  • the second electrode of the sixth transistor T6 is coupled to the control electrode of the ninth transistor T9.
  • the first control circuit 10 further includes a second input sub-circuit 13 .
  • the second input sub-circuit 13 is coupled to the second control signal terminal Q2, the second input signal terminal S2, the second enable signal terminal EM' and the second control circuit 20.
  • the second input subcircuit 13 is configured to write the second input signal received at the second input signal terminal S2 in response to the second control signal received at the second control signal terminal Q2, and, in response to the second input signal to transmit the second enable signal received at the second enable signal terminal EM′ to the second control circuit 20 .
  • the second input sub-circuit 13 includes a seventh transistor T7 , an eighth transistor T8 and a third capacitor C3 .
  • the control electrode of the seventh transistor T7 is coupled to the second control signal end Q2, and the first electrode of the seventh transistor T7 is coupled to the second input signal end S2.
  • the control electrode of the eighth transistor T8 is coupled to the second electrode of the seventh transistor T7, the first electrode of the eighth transistor T8 is coupled to the second enable signal terminal EM', and the second electrode of the eighth transistor T8 is coupled to the second enable signal terminal EM'.
  • the control circuit 20 is coupled.
  • the third capacitor C3 is coupled to the second pole of the seventh transistor T7.
  • the first terminal of the third capacitor C3 is coupled to the second terminal of the seventh transistor T7, and the second terminal of the third capacitor C3 is coupled to the fixed voltage terminal.
  • the fixed voltage terminal is configured to transmit a fixed voltage signal, eg, the fixed voltage signal includes a DC voltage signal; eg, the fixed voltage signal is equal to or approximately equal to a ground signal; eg, the fixed voltage terminal may be a ground terminal.
  • the third capacitor in the second input sub-circuit can store the written second input signal to control the voltage of the control electrode of the eighth transistor to be the voltage of the second input signal.
  • the second control circuit 20 includes the ninth transistor T9
  • the second electrode of the eighth transistor T8 is coupled to the control electrode of the ninth transistor T9.
  • the driving circuit 20 further includes a driving subcircuit 21 , a driving control subcircuit 22 , a data writing subcircuit 23 and a compensation subcircuit 24 .
  • the driving sub-circuit 21 includes a driving transistor DT and a fourth capacitor C4.
  • the first terminal of the fourth capacitor C4 is coupled to the first voltage terminal V1, and the second terminal of the fourth capacitor C4 is coupled to the control electrode of the driving transistor DT.
  • the data writing sub-circuit 23 is coupled to the scanning signal terminal GATE, the data signal terminal DATA and the driving sub-circuit 21 .
  • the compensation sub-circuit 24 is coupled to the scanning signal terminal GATE, the control electrode of the driving transistor DT and the second electrode of the driving transistor DT.
  • the driving control sub-circuit 24 is coupled to at least the first enable signal terminal EM, the first voltage terminal V1 and the driving sub-circuit 21 .
  • the data writing subcircuit 23 is configured to write the data signal received at the data signal terminal DATA into the driving subcircuit 21 in response to the scan signal received at the scan signal terminal GATE.
  • the driving sub-circuit 21 is configured to generate a driving signal according to the written data signal and the first voltage of the first voltage terminal V1.
  • the drive control sub-circuit 22 is configured to cause the first voltage terminal V1 and the second control circuit 20 to be formed by the drive transistor DT in the drive sub-circuit 21 in response to the first enable signal received at the first enable signal terminal EM conductive path.
  • the compensation sub-circuit 24 is configured to write the data signal and the threshold voltage of the driving transistor DT to the gate of the driving transistor DT in response to the scanning signal received at the scanning signal terminal GATE. In this way, the influence of the threshold voltage of the driving transistor DT on the driving signal can be avoided.
  • the driving control sub-circuit 22 includes a tenth transistor T10 .
  • the control electrode of the tenth transistor T10 is coupled to the first enable signal terminal EM, the first electrode of the tenth transistor T10 is coupled to the first voltage terminal V1, and the second electrode of the tenth transistor T10 is coupled to the first electrode of the driving transistor DT. Extremely coupled.
  • the second pole of the driving transistor DT is coupled to the second control circuit 20 .
  • the second control circuit 20 includes the ninth transistor T9
  • the second pole of the driving transistor DT is coupled to the first pole of the ninth transistor T9.
  • the driving control sub-circuit 22 includes a tenth transistor T10 and an eleventh transistor T11 .
  • the control electrode of the tenth transistor T10 is coupled to the first enable signal terminal EM, the first electrode of the tenth transistor T10 is coupled to the first voltage terminal V1, and the second electrode of the tenth transistor T10 is coupled to the first electrode of the driving transistor DT. Extremely coupled.
  • the control electrode of the eleventh transistor T11 is coupled to the first enable signal terminal EM, the first electrode of the eleventh transistor T11 is coupled to the second electrode of the driving transistor DT, and the second electrode of the eleventh transistor T11 is coupled to the second electrode of the driving transistor DT.
  • the two control circuits 20 are coupled.
  • the second control circuit 20 includes the ninth transistor T9
  • the second pole of the eleventh transistor T11 is coupled to the first pole of the ninth transistor T9.
  • the eleventh transistor T11 is in an off state in response to the first enable signal, so that the driving transistor DT is disconnected from the second control circuit 20, It is avoided that when the second control circuit 20 receives the third input signal, the pulse signal of the third input signal affects the voltage of the second pole of the driving transistor DT, thereby affecting the accuracy of data signal writing.
  • the data writing sub-circuit 23 includes a twelfth transistor T12 .
  • the control electrode of the twelfth transistor T12 is coupled to the scan signal end GATE, the first electrode of the twelfth transistor T12 is coupled to the data signal end DATA, and the second electrode of the twelfth transistor T12 is coupled to the first electrode of the driving transistor DT coupled.
  • the compensation sub-circuit 24 includes a thirteenth transistor T13 .
  • the control electrode of the thirteenth transistor T13 is coupled to the scan signal terminal GATE, the first electrode of the thirteenth transistor T13 is coupled to the second electrode of the driving transistor DT, and the second electrode of the thirteenth transistor T13 is coupled to the driving transistor DT.
  • the control pole is coupled.
  • the thirteenth transistor T13 can write the data signal and the threshold voltage of the driving transistor DT into the control electrode of the driving transistor DT, so as to realize threshold voltage compensation.
  • the driver circuit 30 further includes a reset sub-circuit 25 .
  • the reset sub-circuit 25 is coupled to the driving sub-circuit 21 , the element to be driven L, the reset signal terminal RESET and the initial signal terminal INIT.
  • the reset subcircuit 25 is configured to transmit the initial signal received at the initial signal terminal INIT to the driving subcircuit 21 and the element L to be driven in response to the reset signal received at the reset signal terminal RESET. In this way, the driving sub-circuit 21 and the element to be driven L can be reset to avoid signal interference.
  • the voltage of the initial signal can be selected according to the actual situation, which is not limited here.
  • the initial signal may be a high-level signal or a low-level signal.
  • the reset sub-circuit 25 resets the driving sub-circuit 21 and the element L to be driven.
  • the control terminal of the fifteenth transistor T15 is coupled to the reset signal terminal RESET, the first terminal of the fifteenth transistor T15 is coupled to the initial signal terminal INIT, and the second terminal of the fifteenth transistor T15 is coupled to the element L to be driven.
  • the second electrode of the fourteenth transistor T14 is coupled to the control electrode of the driving transistor DT.
  • the second pole of the fifteenth transistor T15 is coupled to the first pole of the element L to be driven.
  • the fourteenth transistor T14 can transmit an initial signal to the control electrode of the driving transistor DT to reset the voltage of the control electrode of the driving transistor DT.
  • the fifteenth transistor T15 may transmit an initial signal to the element L to be driven to reset the voltage of the first pole of the element L to be driven.
  • the specific implementation mode of the driving circuit is not limited to the above-described mode, and it can be any implementation mode, such as a conventional connection mode well-known to those skilled in the art. Circuits that realize the functions of the above-mentioned driving circuits, such as circuits that can provide driving signals together, are all within the protection scope of the present disclosure.
  • the scan signal terminal GATE of each pixel circuit corresponding to a row of sub-pixels is coupled to a scan signal line GL
  • the first enable signal terminal EM is coupled to an enable signal line E
  • the reset signal terminal RESET is coupled to a reset signal line.
  • Line RL is coupled.
  • a data signal terminal DATA of each pixel circuit corresponding to a column of sub-pixels is coupled to a data signal line DL.
  • the second enable signal terminal and the first enable signal terminal may be coupled to the same enable signal line; or, a row of pixel circuits is coupled to two enable signal lines, and the second enable signal
  • the enable signal terminal and the first enable signal terminal are respectively coupled to different enable signal lines (not shown in the figure).
  • the display panel 100 further includes a plurality of first signal lines LQ and a plurality of second signal lines LS.
  • the first control signal terminal Q1 and the second control signal terminal Q2 of a row of pixel circuits are respectively coupled to the same first signal line LQ
  • the first input signal terminal S1 and the second input signal terminal S2 of a column of pixel circuits are respectively coupled to the two second signal lines LS.
  • one row of sub-pixels is respectively coupled to the same first signal line LQ
  • one column of sub-pixels is respectively coupled to two second signal lines LS.
  • a first signal line LQ coupled to a row of sub-pixels may be a scan signal line GL.
  • the first control signal terminal Q1 and the second control signal terminal Q2 are both scan signal terminals GATE;
  • a first signal line LQ coupled to the pixel may be a reset signal line RL.
  • the first control signal terminal Q1 and the second control signal terminal Q2 are both the reset signal terminal RESET.
  • the first control circuit 10 writes the first input signal and the second input signal simultaneously in response to the first control signal terminal Q1 and the second control signal terminal Q2, so that the first input signal terminal S1 is coupled to The connected input signal line and the input signal line coupled to the second input signal end S2 are different, that is, the first input signal end S1 and the second input signal end S2 are different signal ends.
  • the reset signal terminal RESET and the first control signal terminal Q1 of each pixel circuit are coupled to the same reset signal line, and the scanning signal terminal GATE and the second control signal terminal Q2 of each pixel circuit are connected. is coupled to the same scan signal line; or, the scan signal end and the first control signal end of each pixel circuit are coupled to the same scan signal line, and the reset signal end and the second control signal end of each pixel circuit are coupled to the same reset line signal line.
  • the first control signal terminal Q1 and the second control signal terminal Q2 of a row of pixel circuits are respectively coupled to two first signal lines LQ
  • the first input signal terminal S1 and the second input signal terminal S2 of a column of pixel circuits are They are respectively coupled to the same second signal line LS.
  • a row of sub-pixels is respectively coupled to two first signal lines LQ
  • a column of sub-pixels is respectively coupled to the same second signal line LS, that is, in the same column of pixel circuits, each Both the first input signal terminal S1 and the second input signal terminal S2 of the pixel circuit are coupled to the same second signal line LS.
  • the two first signal lines LQ coupled to one row of sub-pixels may be the scan signal line GL and the reset signal line RL, respectively.
  • the first control signal end Q1 is coupled to the reset signal line RL, that is, the first control signal end Q1 and the reset signal end RESET are the same signal end;
  • the second control signal end Q2 is coupled to the scan signal line GL, that is, The second control signal terminal Q2 and the scanning signal terminal GATE are the same signal terminal.
  • the first control signal end Q1 is coupled to the scan signal line GL, that is, the first control signal end Q1 and the scan signal end GATE are the same signal end;
  • the second control signal end Q2 is coupled to the reset signal line RL, That is, the second control signal terminal Q2 and the reset signal terminal RESET are the same signal terminal.
  • the first control circuit 10 writes the first input signal and the second input signal at different times in response to the first control signal terminal Q1 and the second control signal terminal Q2 respectively, so that the first input signal terminal S1 and the second input signal terminal S2 can be coupled to the same input signal line, that is, the first input signal terminal S1 and the second input signal terminal S2 are the same signal terminal, so as to write different first input signals and second input signal.
  • the first control signal terminal Q1 and the second control signal terminal Q2 of a row of pixel circuits are respectively coupled to two first signal lines LQ
  • the first input signal terminal S1 and the second input signal terminal S2 of a column of pixel circuits are respectively coupled to the two second signal lines LS.
  • one row of sub-pixels is respectively coupled to two first signal lines LQ
  • one column of sub-pixels is respectively coupled to two second signal lines LS.
  • the two first signal lines LQ are different from the scan signal line GL and the reset signal line RL
  • the two first signal lines LQ respectively provide the first control signal terminal Q1 and the second control signal terminal Q2 with the first control.
  • signal and the second control signal, the two second signal lines LS respectively provide the first input signal and the second input signal to the first input signal terminal S1 and the second input signal terminal S2.
  • the multiple input signal lines are parallel to the scanning signal lines, and at this time, one row of sub-pixels is coupled to one input signal line; one row of pixel circuits is The third input signal terminal of the is coupled to an input signal line.
  • the third input signal, the first enable signal and the second enable signal received by the pixel circuit in the sub-pixel are signals of the same level , such as the same high-level signal.
  • the first control signal terminal Q1 and the reset signal terminal RESET are the same signal terminal
  • the second control signal terminal Q2 and the scanning signal terminal GATE are the same signal terminal
  • the first input signal terminal SS1 and the second input signal terminal S2 is the same signal terminal.
  • the first control signal terminal Q1 and the second control signal terminal Q2 are both the reset signal terminal RESET or the scanning signal terminal GATE, and the first input signal terminal S1 and the second input signal terminal S2 are different signal terminal.
  • each sub-pixel displaying different gray levels needs to be coupled with two second signal lines, and the pixel circuit can write different first input signals and second input signals at the same time, so that each pixel circuit can control the element to be driven The corresponding grayscale is displayed.
  • the transistors used in the pixel circuits provided by the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT), field effect transistors (Field Effect Transistor, FET) or other switching devices with the same characteristics.
  • TFT Thin Film Transistor
  • FET Field Effect Transistor
  • the control electrode of each transistor used in the pixel circuit is the gate electrode of the transistor, the first electrode is one of the source electrode and the drain electrode of the transistor, and the second electrode is the other one of the source electrode and the drain electrode of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes may be indistinguishable in structure.
  • one image frame period includes each line scanning stage and working stage.
  • the scan phase includes a scan period of each row of sub-pixels.
  • each signal terminal such as the first input signal terminal, the second input signal terminal, the third input signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the third control signal terminal, the third control signal terminal, the each signal (for example, first input signal, second input signal, third input signal, first control signal, second control signal, third control signal, scan signal, data signal, reset signal, first enable signal, second enable Signal, first voltage, second voltage and third voltage, etc.) are represented by the same symbols, but their actual meanings are different.
  • the initial signal received at the initial signal terminal INIT can eliminate the influence of the signal of the previous frame on the voltage of the control electrode of the driving transistor DT and the voltage of the first electrode of the element L to be driven.
  • the initial signal may be a low-level signal or a high-level signal; for example, when the driving transistor is a P-type transistor, the voltage of the initial signal is greater than zero.
  • the timing of the first control signal received at the first control signal terminal Q1 and the timing of the second control signal received at the second control signal terminal Q2 The timing is the same as the timing of the reset signal received at the reset signal terminal RESET.
  • the first control signal terminal and the second control signal terminal may both be reset signal terminals.
  • the second input sub-circuit 13 in the first control circuit 10 writes the second input sub-circuit 13 received at the second input signal terminal S2 in response to the second control signal received at the second control signal terminal Q2.
  • Two input signals and, in response to the second input signal, transmitting the second enable signal received at the second enable signal terminal EM' to the second control circuit 20 .
  • the seventh transistor T7 in the second input sub-circuit 13 responds to the second control signal of low level received at the second control signal terminal Q2, the eighth transistor T8 is turned on, and the write Input the second input signal received at the second input signal terminal S2.
  • the third capacitor C3 stores the second input signal.
  • the first input subcircuit 11A in the first control circuit 10 writes the first input signal received at the first input signal terminal S1 in response to the first control signal received at the first control signal terminal Q1 , and, in response to the first input signal, the third input signal received at the third input signal terminal S3 is transmitted to the second control circuit 20 .
  • the first transistor T1 is turned on in response to a first control signal of a low level received at the first control signal terminal Q1, and the first transistor T1 is turned on to write the first control signal received at the first input signal terminal S1.
  • the first input signal, the first capacitor C1 stores the first input signal.
  • the voltage regulator sub-circuit 12 in the first control circuit 10 transmits the second voltage of the second voltage terminal V2 to the second control circuit 20 in response to the third control signal received at the third control signal terminal Q3 .
  • the first input sub-circuit 11B in the first control circuit 10 writes the first input signal received at the first input signal terminal S1 in response to the first control signal received at the first control signal terminal Q1, the first input In response to the first input signal, the sub-circuit 11B transmits the third input signal to the second control circuit 20, and the voltage regulator sub-circuit 12, in response to the first enable signal received at the first enable signal terminal EM, transfers the signal from the second control circuit 20.
  • a signal input to the sub-circuit 11B (ie, the third input signal) is transmitted to the second control circuit 20 .
  • the sixth transistor T6 in the voltage regulator sub-circuit 12 responds to the low-level third control signal (refer to FIG. 11 ) received at the third control signal terminal Q3 , turns the second voltage terminal V2 The two voltages are transmitted to the second control circuit 20 .
  • the ninth transistor T9 in the second control circuit 20 is turned off, and the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the third transistor T3 in the first input sub-circuit 11B responds to the low-level first control signal received at the first control signal terminal Q1, the third transistor T3 is turned on, and is written at the first input signal terminal S1 Upon receiving the first input signal, the first capacitor C1 stores the first input signal.
  • the second transistor T2 in the first input sub-circuit 11A is turned on in response to the first input signal of low level, and transmits the third input signal received at the third input signal terminal S3 to the second control circuit 20 .
  • the third input signal is a high level signal.
  • the ninth transistor T9 in the second control circuit 20 is turned off, and the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the fourth transistor T4 in the first input sub-circuit 11B is turned on in response to the low-level first input signal
  • the fifth transistor T5 in the voltage regulator sub-circuit 12 is in response to the first input signal at the low level.
  • the fifth transistor T5 With the first enable signal of high level received at the enable signal terminal EM, the fifth transistor T5 is turned off, and the fourth transistor T4 and the fifth transistor T5 will not transmit the third input signal received at the third input signal terminal S3 transmitted to the second control circuit 20 .
  • the second input signal is a low-level signal
  • the first input signal is a high-level signal.
  • the eighth transistor T8 in the second input sub-circuit 13 responds to the second input signal at a low level, the eighth transistor T8 is turned on, and will receive the signal received at the second enable signal terminal EM'.
  • the high-level second enable signal is transmitted to the second control circuit 20 .
  • the ninth transistor T9 in the second control circuit 20 is turned off, and the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the second transistor T2 in the first input sub-circuit 11A responds to the first input signal at a high level, and the second transistor T2 is turned off, and will not transmit the third input signal received at the third input signal terminal S3 transmitted to the second control circuit 20 .
  • the fourth transistor T4 in the first input sub-circuit 11B responds to the first input signal at a high level, the fourth transistor T4 is turned off, and the fifth transistor T5 in the voltage regulator sub-circuit 12 responds to the first input signal.
  • the third input signal will not be transmitted to the second control circuit 20 .
  • the third input signal will not affect the voltage of the gate of the ninth transistor T9, which can avoid the need for the drive transistor DT in the drive circuit 30 to which the ninth transistor T9 is coupled.
  • the voltage of the second pole avoids affecting the accuracy of the subsequent data signal written by the driving circuit 30 .
  • the level of the third input signal may not be limited, for example, the third input signal may be a high-level signal, or a signal whose high-level and low-level alternate.
  • the timing of the first control signal received at the first control signal terminal Q1 is the same as the timing of the reset signal received at the reset signal terminal RESET , at this time, the first control signal terminal and the reset signal terminal are the same signal terminal.
  • the first control circuit writes the first input signal and does not write the second input signal.
  • the voltage amplitude of the first input signal matches the voltage amplitude of the first control signal and the voltage amplitude of the second enable signal, that is, the first input signal and the first control signal need to be guaranteed to receive both.
  • the first input signal and the second enable signal need to ensure the complete turn-on and turn-off of the transistor receiving these two signals.
  • the transistor is a P-type transistor
  • the voltage range of the first input signal is 7V to 10V.
  • the voltage of the first control signal is -10V
  • the voltage range of the first input signal is -7V to -10V.
  • the voltage of the second enable signal is -7V
  • the voltage range of the first input signal is -7V to -10V.
  • the voltage amplitude of the second input signal matches the voltage amplitude of the second control signal and the voltage amplitude of the third input signal, that is, the second input signal and the second control signal need to ensure that the two signals are received.
  • the complete turn-on and cut-off of the transistor, the second input signal and the third input signal need to ensure the complete turn-on and cut-off of the transistor receiving these two signals, for example, if the transistor adopts a P-type transistor, the voltage of the second control signal In the case of 10V, the voltage range of the second input signal is 7V ⁇ 10V, and in the case of the voltage of the second control signal being -10V, the voltage range of the second input signal is -7V ⁇ -10V, and the third input signal When the voltage of the second input signal is -7V, the voltage range of the second input signal is -7V ⁇ -10V.
  • the first input signal is a low-level signal
  • the second input signal is a high-level signal.
  • the first control circuit 10 transmits the third input signal to the second control circuit 20, and controls the second control circuit 20 so that the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the first input signal is a high-level signal
  • the second input signal is a low-level signal.
  • the first control circuit 10 controls the second The enable signal is transmitted to the second control circuit 20, and by controlling the second control circuit 20, the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the first control circuit 10 can also transmit the second voltage to the second control circuit 20, and by controlling the second control circuit 20, the driving circuit 30 and the element L to be driven do not form a conductive path.
  • the element L to be driven does not work.
  • the data writing sub-circuit 23 in the driving circuit 30 responds to the data received at the scanning signal terminal GATE
  • the scanning signal is used to write the data signal received at the data signal terminal DATA into the driving sub-circuit 21 .
  • the twelfth transistor T12 in the data writing sub-circuit 23 is turned on in response to the low-level scan signal received at the scan signal terminal GATE, and the data is The data signal received at the signal terminal DATA is written into the driving sub-circuit 21, that is, into the first pole of the driving transistor DT.
  • the compensation sub-circuit 24 writes the data signal and the threshold voltage of the driving transistor DT to the gate of the driving transistor DT in response to the scanning signal received at the scanning signal terminal GATE. For example, in response to the low-level scan signal received at the scan signal terminal GATE, the thirteenth transistor T13 in the compensation sub-circuit 24 is turned on to connect the control electrode of the driving transistor DT to the second electrode.
  • the voltage of the control electrode of the driving transistor DT is the sum of the voltage of the first electrode of the driving transistor DT and the pre-made voltage of the driving transistor DT, that is, the data signal and the threshold voltage of the driving transistor DT is written to the gate of the driving transistor DT.
  • V data is the voltage of the data signal
  • V th is the threshold voltage of the driving transistor DT.
  • the voltage of the second terminal of the fourth capacitor C4 coupled to the control electrode of the driving transistor DT is also V data +V th
  • the first terminal of the fourth capacitor C4 is coupled to the first voltage terminal V1 namely , the voltage of the first end of the fourth capacitor C4 is the first voltage V DD , at this time, both ends of the fourth capacitor C4 are charged.
  • a potential difference exists between the two ends of the fourth capacitor C4 as V DD -V data -V th .
  • the operation of each sub-circuit in the first control circuit is the same as that of each sub-circuit in the above-mentioned first control circuit.
  • the working situation is similar, and the specific description can be referred to the above description, which will not be repeated here.
  • the first pole of the transistor T10 is coupled to the first voltage terminal V1 through the tenth transistor T10, and the second pole of the driving transistor DT is coupled to the first pole of the ninth transistor T9 in the second control circuit 20, so that the driving sub-circuit 21
  • the driving transistor DT forms a conductive path with the first voltage terminal V1 and the second control circuit 20 .
  • K W/L ⁇ C ⁇ u
  • W/L is the width-length ratio of the driving transistor DT
  • C is the channel insulating layer capacitance
  • u is the channel carrier mobility.
  • the size of the driving current is related to the characteristics of the driving transistor.
  • the driving current ie, the driving signal
  • the driving transistor For a pixel circuit that provides driving signals to sub-pixels of different colors (such as red sub-pixels, green sub-pixels, and blue sub-pixels), The optoelectronic properties of light-emitting elements for realizing different color sub-pixels need to be considered, and different driving capabilities can be achieved by designing the size of the driving transistors.
  • the drive circuit 30 outputs a drive signal to the second control circuit 20 .
  • the first electrode of the ninth transistor T9 in the second control circuit 20 receives the driving signal.
  • the first input subcircuit 11A in the first control circuit 10 transmits the third input signal received at the third input signal terminal S3 to the second control circuit 20 in response to the first input signal.
  • the first input sub-circuit 11B in the first control circuit 10 transmits the third input signal to the second control circuit 10 in response to the first input signal, and the voltage regulator sub-circuit 12 responds to the first enable signal terminal
  • the first enable signal received at the EM transmits the signal from the first input sub-circuit 11B (ie, the third input signal) to the second control circuit 20 .
  • the seventh transistor T7 in the second input sub-circuit 13 is turned off to stop writing in response to the second control signal of a high level received at the second control signal terminal Q2 into the second input signal.
  • the first transistor T1 in the first input sub-circuit 11A is turned off in response to a first control signal of a high level received at the first control signal terminal Q1, and stops writing the first input signal.
  • the sixth transistor T6 in the voltage regulator sub-circuit 12 is turned off in response to the third control signal of high level (refer to FIG. 11 ) received at the third control signal terminal Q3 , and stops the The second voltage is transmitted to the second control circuit 20 .
  • the second input signal written in the first control circuit 10 is a high-level signal
  • the written first input signal is a low-level signal.
  • the fourth transistor T4 in the first input sub-circuit 11B is turned on in response to the low-level first input signal
  • the fifth transistor T5 in the voltage regulator sub-circuit 12 is in response to With the first enable signal of low level received at the first enable signal terminal EM, the fifth transistor T5 is turned on, and the fourth transistor T4 and the fifth transistor T5 will receive the third input at the third input signal terminal S3 The signal is transmitted to the second control circuit 20 .
  • the first control circuit transmits the third input signal to the second control circuit, and controls the conduction frequency of the second control circuit 20 through the third input signal, so as to Control the frequency at which the driving circuit 30 and the element to be driven L form a conductive path, and control the frequency at which the element to be driven L receives the driving signal, so that the element to be driven is intermittently in a working state, so as to control the working time of the element to be driven L, so that the
  • the driving element can also realize corresponding gray scale display under the driving of a driving signal with a higher amplitude, which improves the working efficiency of the element to be driven.
  • the operating frequency of the element to be driven is relatively high, which can prevent the human eye from seeing flicker and improve the display effect.
  • the first capacitor C1 in the first input sub-circuit 11A stores the first input signal at a high level
  • the second transistor T2 is turned off in response to the first input signal at a high level, and does not
  • the third input signal received at the third input signal terminal S3 is transmitted to the second control circuit 20 .
  • the ninth transistor T9 in the second control circuit 20 is always in a conducting state, and the driving signal from the driving circuit 30 can be transmitted until the time to be driven element L, so that the element L to be driven works all the time. In this way, when the driving signal is a high current signal, the light emission brightness of the element L to be driven can be guaranteed.
  • the first control circuit transmits the second enable signal to the second control circuit, so that the to-be-driven element is always driven by a higher-amplitude driving signal to ensure that The working efficiency of the element to be driven.
  • the display panel 100 further includes a plurality of cascaded shift register circuits RS.
  • Each shift register circuit is coupled to the third input signal terminal S3 of one row of pixel circuits 101 .
  • each shift register circuit RS is coupled to the third input signal terminal S3 of one row of pixel circuits 101 through one input signal line LS.
  • the shift register circuit RS is configured to transmit a third input signal to the third input signal terminal S3 of the pixel circuit 101 to which it is coupled.
  • the voltage of the control electrode of the ninth transistor T9 is alternately at a high voltage and a low voltage during the inactive phase of the element to be driven, so that the ninth The voltages of the first pole of the transistor T9 and the second pole of the driving transistor DT are floating, which will affect the accuracy of the written data signal.
  • the timing sequence of the third input signal is the same as the timing sequence of the first enable signal.
  • the first enable signal is a high-level signal
  • the third input signal is also a high-level signal Signal.
  • a plurality of cascaded shift register circuits may shift and transmit the third input signal to the corresponding pixel circuit.
  • the enable signal is shifted sequentially row by row. For example, when the display panel has n rows of sub-pixels, n is a positive integer. Referring to FIG.
  • the first enable signal EM(1) received by the pixel circuits of the first row when the first enable signal EM(1) received by the pixel circuits of the first row is at a high level, the first When the third input signal S3(1) received by the pixel circuit of the second row is also high level, and the first enable signal EM(2) received by the pixel circuit of the second row is high level, the pixel circuit of the second row is at a high level.
  • the received third input signal S3(2) is also high level, and by analogy, when the first enable signal EM(n) received by the pixel circuit in the nth row is high level, the pixel circuit in the nth row is at a high level.
  • the received third input signal S3(n) is also high.
  • the display panel includes a plurality of scan drive circuits, the plurality of scan drive circuits are at least three scan drive circuits, and the at least three scan drive circuits include a first scan drive circuit, a second scan drive circuit, and a third scan drive circuit Drive circuit.
  • each scan driver circuit includes a plurality of cascaded shift register circuits. The first scan driver circuit is configured to output a scan signal, the second scan driver circuit is configured to output a reset signal, and the third scan driver circuit is configured to output an enable signal, eg, a first enable signal and a second enable signal.
  • the plurality of scan driving circuits are at least four scan driving circuits, and the at least four scan driving circuits include: the above-mentioned first scan driving circuit, second scan driving circuit, third scan driving circuit, and fourth scan driving circuit scan driver circuit.
  • the fourth scan driving circuit is configured to output the third input signal, for example, the fourth scan driving circuit includes the above-mentioned multiple cascaded shift register circuits RS.
  • the shift register circuits in different scan driving circuits are not exactly the same; for example, the shift register circuits in the fourth scan driving circuit are different from those in the first scan driving circuit, the second scan driving circuit and the third scan driving circuit shift register circuit.
  • two scan driving circuits of the first scan driving circuit, the second scan driving circuit, the third scan driving circuit and the fourth scan driving circuit are located on one side of the opposite sides outside the AA area, and the other two The scan driver circuit is located on the other of the opposite sides outside the AA area.
  • the opposite sides outside the AA area may be the opposite sides outside the AA area along the row direction of the pixel circuit arrangement.
  • the first scan driver circuit and the second scan driver circuit are located on one side of the opposite sides outside the AA area
  • the third scan driver circuit and the fourth scan driver circuit are located on the other side of the opposite sides outside the AA area.
  • the display device 200 further includes a driver chip 210 .
  • the driving chip 210 is coupled to the display panel 100 .
  • the driving chip 210 is configured to provide signals to the display panel 100 .
  • the driver chip is a driver IC (Integrated Circuit).
  • one driver chip 210 may provide data signals to the display panel 100 ; the one driver chip 210 may also provide the display panel 100 with the first input signal, the second input signal and the third input signal.
  • the display device 200 includes a plurality of driving chips, and the plurality of driving chips respectively provide the data signal, the first input signal, the second input signal and the third input signal to the display panel.
  • the third input signal is provided by the driving chip
  • all pixel circuits in the display panel receive the same third input signal, which simplifies the design.
  • the third input signal is provided by the shift register circuit
  • the third input signal received by all pixel circuits in the display panel is different, eg, one row of pixel circuits receives the same third input signal.
  • the voltage of the third input signal is adjusted.
  • the third input signal does not need to maintain a high level signal , can reduce power consumption.
  • Embodiments of the present disclosure provide a driving method of a pixel circuit.
  • the pixel circuit includes: a driving circuit, a first control circuit and a second control circuit.
  • the driving circuit is coupled to at least the data signal terminal, the scan signal terminal, the first voltage terminal and the first enable signal terminal.
  • the first control circuit is coupled to at least the second enable signal terminal, the first control signal terminal, the first input signal terminal, the second control signal terminal, the second input signal terminal and the third input signal terminal.
  • the second control circuit is coupled to the driving circuit, the first control circuit and the element to be driven.
  • the driving method of the pixel circuit includes:
  • the drive circuit writes the data signal received at the data signal terminal in response to the scan signal received at the scan signal terminal, and, in response to the first enable signal received at the first enable signal terminal, according to the first voltage
  • the first voltage at the terminal and the written data signal generate a driving signal.
  • the first control circuit writes the first input signal received at the first input signal terminal in response to the first control signal received at the first control signal terminal, and transmits the first input signal at the third input in response to the first input signal the third input signal received at the signal terminal; alternatively, the first control circuit writes the second input signal received at the second input signal terminal in response to the second control signal received at the second control signal terminal, in response to the second input signal received at the second input signal terminal
  • the second input signal transmits the second enable signal received at the second enable signal terminal.
  • the second control circuit responds to and receives one of the third input signal and the second enable signal, transmits the driving signal from the driving circuit to the element to be driven, and controls the working duration of the element to be driven.
  • the frequency of the third input signal is greater than the frequency of the second enable signal.
  • the first control circuit transmits the third input signal to the second control circuit.
  • the first input signal is a high-level signal
  • the first control circuit The second input signal is a low-level signal; when the sub-pixel where the pixel circuit is located displays a low gray scale, the first control circuit transmits the second enable signal to the second control circuit.
  • the first input signal is A low-level signal
  • the second input signal is a high-level signal.
  • the above-mentioned driving method of the pixel circuit has the same beneficial effects as the above-mentioned pixel circuit, so it will not be repeated.

Abstract

一种像素电路(101)，包括驱动电路(30)、第一控制电路(10)和第二控制电路(20)，驱动电路(30)响应于扫描信号端(GATE)的扫描信号写入数据信号端(DATA)的数据信号，及响应于第一使能信号端(EM)的第一使能信号，根据第一电压端(V1)的第一电压和写入的数据信号生成驱动信号；第一控制电路(10)响应于第一控制信号端(Q1)的第一控制信号写入第一输入信号端(S1)的第一输入信号，响应于第一输入信号传输第三输入信号端(S3)的第三输入信号；或者第一控制电路(10)响应于第二控制信号端(Q2)的第二控制信号写入第二输入信号端(S2)的第二输入信号，响应于第二输入信号传输第二使能信号端(EM')的第二使能信号；第二控制电路(20)响应并接收第三输入信号和第二使能信号中的其中一者，将驱动信号传输至待驱动元件(L)，控制待驱动元件(L)的工作时长。

Description

像素电路及驱动方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及驱动方法、显示面板、显示装置。
背景技术
显示市场目前正在蓬勃发展，并且随着消费者对笔记本电脑、智能手机、电视、平板电脑、智能手表和健身腕带等各类显示产品的需求的持续提升，将来会涌现出更多的新显示产品。
发明内容
一方面，提供一种像素电路。所述像素电路包括驱动电路、第一控制电路和第二控制电路。所述驱动电路至少与数据信号端、扫描信号端、第一电压端和第一使能信号端耦接。所述第一控制电路至少与第二使能信号端、第一控制信号端、第一输入信号端、第二控制信号端、第二输入信号端和第三输入信号端耦接。所述第二控制电路与所述驱动电路、所述第一控制电路和待驱动元件耦接。
所述驱动电路被配置为响应于在所述扫描信号端处接收的扫描信号，写入在所述数据信号端处接收的数据信号，及，响应于在所述第一使能信号端处接收的第一使能信号，根据所述第一电压端的第一电压和写入的数据信号，生成驱动信号。
所述第一控制电路被配置为响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，响应于所述第一输入信号，传输在所述第三输入信号端处接收的第三输入信号；或者，所述第一控制电路被配置为响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号端处接收的第二输入信号，响应于所述第二输入信号，传输在所述第二使能信号端处接收的第二使能信号。
所述第二控制电路被配置为响应并接收所述第三输入信号和所述第二使能信号中的其中一者，将来自所述驱动电路的驱动信号传输至所述待驱动元件，控制所述待驱动元件的工作时长。
在一些实施例中，所述第一控制电路还与第三控制信号端、所述第一使能信号端和第二电压端耦接。所述第一控制电路还被配置为响应于在所述第三控制信号端处接收的第三控制信号，将所述第二电压端的第二电压传输至所述第二控制电路；所述第一控制电路还被配置为响应于在所述第一使能信 号端处接收的第一使能信号和所述第一输入信号，将所述第三输入信号传输至所述第二控制电路。
在一些实施例中，所述第一控制电路包括第一输入子电路。所述第一输入子电路与所述第一控制信号端、所述第一输入信号端和所述第三输入信号端耦接。所述第一输入子电路被配置为响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，及，响应于所述第一输入信号，向所述第二控制电路传输在所述第三输入信号端处接收的第三输入信号。
在一些实施例中，所述第一输入子电路还与所述第二控制电路耦接。所述第一输入子电路包括：第一晶体管、第二晶体管和第一电容器。所述第一晶体管的控制极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述第一输入信号端耦接。所述第二晶体管的控制极与所述第一晶体管的第二极耦接，所述第二晶体管的第一极与所述第三输入信号端耦接，所述第二晶体管的第二极与所述第二控制电路耦接。所述第一电容器与所述第一晶体管的第二极耦接。
在一些实施例中，所述第一控制电路还包括稳压子电路。所述稳压子电路与所述第一使能信号端、所述第一输入子电路、所述第二控制电路、第三控制信号端和第二电压端耦接。所述稳压子电路被配置为响应于在所述第三控制信号端处接收的第三控制信号，将所述第二电压端的第二电压传输至所述第二控制电路；及，响应于在所述第一使能信号端处接收的第一使能信号，将来自所述第一输入子电路的信号传输至所述第二控制电路。
在一些实施例中，所述第一输入子电路包括：第三晶体管、第四晶体管和第二电容器。所述第三晶体管的控制极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述第一输入信号端耦接。所述第四晶体管的控制极与所述第三晶体管的第二极耦接，所述第四晶体管的第一极与所述第三输入信号端耦接，所述第四晶体管的第二极与所述稳压子电路耦接。所述第二电容器与所述第三晶体管的第二极耦接。
所述稳压子电路包括：第五晶体管和第六晶体管。所述第五晶体管的控制极与所述第一使能信号端耦接，所述第五晶体管的第一极与所述第一输入子电路耦接，所述第五晶体管的第二极与所述第二控制电路耦接。所述第六晶体管的控制极与所述第三控制信号端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述第二控制电路耦接。
在一些实施例中，所述第一控制电路还包括第二输入子电路。所述第二 输入子电路与所述第二控制信号端、所述第二输入信号端、所述第二使能信号端和所述第二控制电路。所述第二输入子电路被配置为响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号端处接收的第二输入信号，及，响应于所述第二输入信号，将在所述第二使能信号端处接收的第二使能信号传输至所述第二控制电路。
在一些实施例中，所述第二输入子电路包括：第七晶体管、第八晶体管和第三电容器。所述第七晶体管的控制极与所述第二控制信号端耦接，所述第七晶体管的第一极与所述第二输入信号端耦接。所述第八晶体管的控制极与所述第七晶体管的第二极耦接，所述第八晶体管的第一极与所述第二使能信号端耦接，所述第八晶体管的第二极与所述第二控制电路耦接。所述第三电容器与所述第七晶体管的第二极耦接。
在一些实施例中，所述第二控制电路包括第九晶体管。所述第九晶体管的控制极与所述第一控制电路耦接，所述第九晶体管的第一极与所述驱动电路耦接，所述第九晶体管的第二极与所述待驱动元件耦接。
在一些实施例中，所述驱动电路还包括：驱动子电路、驱动控制子电路、数据写入子电路和补偿子电路。所述驱动子电路包括驱动晶体管和第四电容器。所述第四电容器的第一端与所述第一电压端耦接，所述第四电容器的第二端与所述驱动晶体管的控制极耦接。
所述驱动控制子电路至少与所述第一使能信号端、所述第一电压端、所述驱动子电路耦接。所述数据写入子电路与所述扫描信号端、所述数据信号端和所述驱动子电路耦接。所述补偿子电路与所述扫描信号端、所述驱动晶体管的控制极和所述驱动晶体管的第二极耦接。
所述驱动控制子电路被配置为响应于在所述第一使能信号端处接收的第一使能信号，使所述第一电压端和所述第二控制电路通过所述驱动子电路中的驱动晶体管形成导电通路。所述驱动子电路被配置为根据写入的数据信号和所述第一电压端的第一电压，生成所述驱动信号。所述数据写入子电路被配置为响应于在所述扫描信号端处接收的扫描信号，将在所述数据信号端处接收的数据信号写入所述驱动子电路。所述补偿子电路被配置为响应于在所述扫描信号端处接收的扫描信号，将所述数据信号和所述驱动晶体管的阈值电压写入所述驱动晶体管的控制极。
在一些实施例中，所述驱动控制子电路包括第十晶体管。所述第十晶体管的控制极与所述第一使能信号端耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述驱动晶体管的第一极耦接。 其中，所述驱动晶体管的第二极与所述第二控制电路耦接。
在一些实施例中，所述驱动控制子电路包括：第十晶体管和第十一晶体管。所述第十晶体管的控制极与所述第一使能信号端耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述驱动晶体管的第一极耦接。所述第十一晶体管的控制极与所述第一使能信号端耦接，所述第十一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第十一晶体管的第二极与所述第二控制电路耦接。
在一些实施例中，所述数据写入子电路包括第十二晶体管。所述第十二晶体管的控制极与所述扫描信号端耦接，所述第十二晶体管的第一极与所述数据信号端耦接，所述第十二晶体管的第二极与所述驱动晶体管的第一极耦接。
在一些实施例中，所述补偿子电路包括第十三晶体管。所述第十三晶体管的控制极与所述扫描信号端耦接，所述第十三晶体管的第一极与所述驱动晶体管的第二极耦接，所述第十三晶体管的第二极与所述驱动晶体管的控制极耦接。
在一些实施例中，所述驱动电路还包括复位子电路。所述复位子电路与所述驱动子电路、所述待驱动元件、复位信号端和初始信号端耦接。所述复位子电路被配置为响应于在所述复位信号端处接收的复位信号，将在所述初始信号端处接收的初始信号传输至所述驱动子电路和所述待驱动元件。
在一些实施例中，所述复位子电路包括：第十四晶体管和第十五晶体管。所述第十四晶体管的控制极与所述复位信号端耦接，所述第十四晶体管的第一极与所述初始信号端耦接，所述第十四晶体管的第二极与所述驱动晶体管的控制极耦接。所述第十五晶体管的控制极与所述复位信号端耦接，所述第十五晶体管的第一极与所述初始信号端耦接，所述第十五晶体管的第二极与所述待驱动元件耦接。
在一些实施例中，所述第一控制信号端与所述复位信号端为同一信号端，所述第二控制信号端与所述扫描信号端为同一信号端，所述第一输入信号端与所述第二输入信号端为同一信号端。
在一些实施例中，所述第一控制信号端与所述第二控制信号端同为所述复位信号端，或者同为所述扫描信号端，所述第一输入信号端与所述第二输入信号端为不同信号端。
另一方面，提供一种显示面板。所述显示面板包括：如上述任一实施例所述的像素电路和待驱动元件。所述待驱动元件与所述像素电路耦接。
在一些实施例中，所述显示面板还包括多条第一信号线和多条第二信号线。一行像素电路的第一控制信号端和第二控制信号端分别与同一条第一信号线耦接，一列像素电路的第一输入信号端和第二输入信号端分别与两条第二信号线耦接。
在一些实施例中，一行像素电路的第一控制信号端和第二控制信号端分别与两条第一信号线耦接，一列像素电路的第一输入信号端和第二输入信号端分别与同一条第二信号线耦接。
在一些实施例中，所述显示面板还包括多个级联的移位寄存电路，每个移位寄存电路与一行像素电路的第三输入信号端耦接。所述移位寄存电路被配置为向其所耦接的像素电路的第三输入信号端传输第三输入信号。
又一方面，提供一种显示装置。所述显示装置包括上述任一实施例所述的显示面板和驱动芯片。所述驱动芯片与所述显示面板耦接。所述驱动芯片被配置为向所述显示面板提供信号。
再一方面，提供一种像素电路的驱动方法。所述像素电路包括驱动电路、第一控制电路和第二控制电路。所述驱动电路至少与数据信号端、扫描信号端、第一电压端和第一使能信号端耦接。所述第一控制电路至少与第二使能信号端、第一控制信号端、第一输入信号端、第二控制信号端、第二输入信号端和第三输入信号端耦接。所述第二控制电路与所述驱动电路、所述第一控制电路和待驱动元件耦接。
所述驱动方法包括：
所述驱动电路响应于在所述扫描信号端处接收的扫描信号，写入在所述数据信号端处接收的数据信号，及，响应于在所述第一使能信号端处接收的第一使能信号，根据所述第一电压端的第一电压和写入的数据信号，生成驱动信号；
所述第一控制电路响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，响应于所述第一输入信号，传输在所述第三输入信号端处接收的第三输入信号；或者，所述第一控制电路响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号端处接收的第二输入信号，响应于所述第二输入信号，传输在所述第二使能信号端处接收的第二使能信号；
所述第二控制电路响应并接收所述第三输入信号和所述第二使能信号中的其中一者，将来自所述驱动电路的驱动信号传输至所述待驱动元件，控制所述待驱动元件的工作时长。
其中，所述第三输入信号的频率大于所述第二使能信号的频率。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的子像素的一种结构图；
图3为根据一些实施例的像素电路的一种结构图；
图4为根据一些实施例的像素电路的另一种结构图；
图5A为根据一些实施例的像素电路的又一种结构图；
图5B为根据一些实施例的像素电路的又一种结构图；
图6A为根据一些实施例的像素电路的又一种结构图；
图6B为根据一些实施例的像素电路的又一种结构图；
图6C为根据一些实施例的像素电路的又一种结构图；
图6D为根据一些实施例的像素电路的又一种结构图；
图7A为根据一些实施例的显示面板的一种结构图；
图7B为根据一些实施例的显示面板的另一种结构图；
图7C为根据一些实施例的显示面板的又一种结构图；
图7D为根据一些实施例的显示面板的又一种结构图；
图8为根据一些实施例的像素电路的驱动信号一种时序图；
图9为根据一些实施例的像素电路的驱动信号另一种时序图；
图10为根据一些实施例的像素电路的驱动信号又一种时序图；
图11为根据一些实施例的像素电路的驱动信号又一种时序图；
图12为根据一些实施例的像素电路的驱动信号又一种时序图；
图13为根据一些实施例的显示面板的又一种结构图；
图14为根据一些实施例的像素电路的驱动信号又一种时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他 实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有物理接触或存在电信号通路，例如两个部件之间通过信号线导通，或者两个部件之间可以存在其他的电学元件或者电路，但两个部件通过其他电学元件之间存在信号通路。然而，术语“耦接”或“通信耦合(Communication coupling)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定 值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
自发光器件因其亮度高，色域广的特点，受到广泛关注。然而，由于自发光器件的光电转换特性(包括光电转换效率、均一性和色坐标等)，会随着流过该自发光器件的电流的变化而发生改变，例如，在低电流密度下，自发光器件的发光效率会随着电流密度降低而降低，不同自发光器件之间发光亮度均一性较差，如果应用在显示装置中，会降低显示灰阶的均一性，造成灰阶紊乱，导致色偏，影响显示面板的显示效果。
本公开的实施例提供一种显示装置。示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，显示装置可以是多种电子装置中的一种，所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PS1)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。本公开的实施例对上述显示装置的具体形式不做特殊限制。
在本公开的一些实施例中，如图1所示，显示装置200包括显示面板100。显示面板100具有显示区(Active Area，AA)和周边区S。其中，周边区S至少位于AA区外一侧。
其中，显示面板100包括设置于AA区中的多个子像素P。示例性地，多个子像素P可以呈阵列排布。例如，沿图1中X方向排列成一排的子像素P称为同一像素，沿图1中Y方向排列成一排的子像素P称为同一列像素。
在一些实施例中，如图2所示，每个子像素P包括像素电路101和待驱动元件L。像素电路101与待驱动元件L耦接，像素电路101用于向驱动待驱动元件L提供驱动信号，以驱动待驱动元件L工作。
示例性地，待驱动元件L的第一极与像素电路101耦接，待驱动元件L的第二极与第三电压端V3耦接。示例性地，第三电压端V3被配置为传输直流电压信号，例如，直流低电压(VSS)；例如，第三电压为-3V。
示例性地，待驱动元件包括电流驱动型器件，进一步地，可以采用电流 型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)或者有机电致发光二极管(Organic Light Emitting Diode，OLED)或者量子点发光二极管(Quantum Light Emitting Diode，QLED)。在这种情况下，文中所述的待驱动元件工作时长可以被理解为待驱动元件的发光时长；待驱动元件的工作频率可以被理解为待驱动元件的发光频率。示例性地，待驱动元件的第一极和第二极分别为发光二极管的阳极和阴极。
在待驱动元件发光的情况下，由于待驱动元件在发光时所呈现的亮度与其发光时长和驱动电流相关，因此控制待驱动元件的亮度可通过调整其发光时长和/或驱动电流来实现。示例性地，若两个待驱动元件的驱动电流相同，发光时长不同，则该两个待驱动元件所显示的亮度不同；若两个待驱动元件的驱动电流不同，发光时长相同，则该两个待驱动元件所显示的亮度也不同；若两个待驱动元件的驱动电流和发光时长均不相同，则该两个待驱动元件所显示的亮度是否相同，需要具体分析。
其中，显示面板还包括衬底基板，像素电路和待驱动元件均位于衬底基板上。示例性地，该衬底基板可以包括：玻璃等刚性衬底(或称为硬质衬底)，或者PI(Polyimide，聚酰亚胺)等柔性衬底；还可以包括：设置在刚性衬底或柔性衬底上的缓冲层等薄膜。
本公开的实施例提供一种像素电路。如图3所示，像素电路101包括第一控制电路10、第二控制电路20和驱动电路30。
驱动电路30至少与数据信号端DATA、扫描信号端GATE、第一电压端V1和第一使能信号端EM耦接。
第一控制电路10至少与第二使能信号端EM’、第一控制信号端Q1、第一输入信号端S1、第二控制信号端Q2、第二输入信号端S2和第三输入信号端S3耦接。
第二控制电路20与驱动电路30、第一控制电路10和待驱动元件L耦接。
其中，驱动电路30被配置为响应于在扫描信号端GATE处接收的扫描信号，写入在数据信号端DATA处接收的数据信号，及，响应于在第一使能信号端EM处接收的第一使能信号，根据第一电压端V1的第一电压和写入的数据信号，生成驱动信号。
第一控制电路10被配置为响应于在第一控制信号端Q1处接收的第一控制信号，写入在第一输入信号端S1处接收的第一输入信号，响应于第一输入信号，传输在第三输入信号端S3处接收的第三输入信号。或者，第一控制电 路10被配置为响应于在第二控制信号端Q2处接收的第二控制信号，写入在第二输入信号端S2处接收的第二输入信号，响应于第二输入信号，传输在第二使能信号端EM’处接收的第二使能信号。
第二控制电路20被配置为响应并接收第三输入信号和第二使能信号中的其中一者，将来自驱动电路30的驱动信号传输至待驱动元件L，控制待驱动元件L的工作时长。
需要说明的是，在第一使能信号处于有效电平的阶段，即认为待驱动元件处于工作阶段(例如下文中的一图像帧中的第三阶段)。示例性地，可以理解的是，在待驱动元件的工作阶段，存在驱动信号无法使得待驱动元件处于工作状态的情况，例如待驱动元件为发光二极管时，待驱动元件接收到的驱动信号无法使得待驱动元件被点亮，即此时待驱动元件显示零灰阶。在待驱动元件为发光二极管时，实施例中的工作频率指的是待驱动元件在工作阶段的发光频率，实施例中的工作时长指的是待驱动元件在工作阶段的发光时长。
示例性地，第一电压端处接收的第一电压为直流电压，例如，直流高电压；例如第一电压为7V。例如，在第一电压端处接收的第一电压为高电平电压的情况下，在第三电压端处接收的第三电压为低电压，或者，在第一电压端处接收的第一电压为低电压的情况下，在第三电压端处接收的第三电压为高电压。
例如，第二使能信号端与第一使能信号端为同一信号端；例如，第二使能信号与第一使能信号相同；例如，在第一使能信号为有效电平的阶段，第二使能信号的有效电平的时长等于第一使能信号的有效电平的时长。或者，例如，第二使能信号端与第一使能信号端为不同信号端；例如，在第一使能信号为有效电平的阶段，第二使能信号的有效电平的时长小于第一使能信号的有效电平的时长。例如，在第一使能信号为有效电平的阶段，第三输入信号的有效电平的总时长小于第二使能信号的有效电平的时长。
例如，在像素电路所在子像素显示中高灰阶的情况下，第二使能信号与第一使能信号相同；或者，例如，在像素电路所在子像素显示中灰阶的情况下，将驱动信号的幅值维持在较高值范围内，控制第二使能信号的有效电平的时长小于第一使能信号的有效电平的时长。
示例性地，第三输入信号端处接收的第三输入信号为脉冲信号，例如，在一图像帧内，第三输入信号具有多个脉冲。示例性地，第三输入信号的频率大于第二使能信号的频率。例如，在单位时间内，第二使能信号出现有效 电平时间段的次数小于第三输入信号出现有效电平时间段的次数。
示例性地，第三输入信号为高频脉冲信号，例如，第三输入信号的频率在3000Hz～60000Hz之间取值，例如可以为3000Hz或者60000Hz。例如，第一使能信号的频率和第二使能信号的频率在60Hz～120Hz之间取值，例如可以为60Hz或者120Hz。例如，显示面板的帧频率为60Hz，即在1s的时间内，显示面板可以显示60帧图像，且每帧图像的显示时长相等。这样，在第三输入信号是频率为3000Hz的高频信号的情况下，在一图像帧中，若待驱动元件要发出低灰阶亮度，则待驱动元件在发光阶段大约可以接收到高频信号的50个有效时间段。
示例性地，在像素电路所在子像素显示中高灰阶的情况下，第一输入信号在第一控制信号端Q1接收的第一控制信号的有效时间段内为高电平信号，第二输入信号在第二控制信号端Q2接收的第二控制信号的有效时间段内为低电平信号；在像素电路所在子像素显示低灰阶的情况下，第一输入信号在第一控制信号端Q1接收的第一控制信号的有效时间段内为低电平信号，第二输入信号在第二控制信号端Q2接收的第二控制信号的有效时间段内为高电平信号。
其中，第一控制电路不会将第二使能信号和第三输入信号同时传输至第二控制电路。示例性地，在像素电路所在子像素显示中高灰阶的情况下，第一控制电路将第二使能信号传输至第二控制电路；在像素电路所在的子像素显示低灰阶的情况下，第一控制电路将第三输入信号传输至第二控制电路。
在一些实施例中，属于同一像素电路中的第一控制信号端Q1和第二控制信号端Q2可以分别与扫描信号端GATE和复位信号端RESET连接，即属于同一像素电路中的第一控制信号端Q1和第二控制信号端Q2中的其中一个可以与扫描信号端GATE连接到同一条扫描信号线，另一个与复位信号端RESET连接到同一条复位信号线；属于同一像素电路的第一输入信号端S1和第二输入信号端S2可以与同一条信号线，如下文中的第二信号线耦接，通过控制第二信号线传输的信号幅值，来向第一输入信号端S1和第二输入信号端S2提供不同幅值的信号。如此设计，在多个像素电路阵列排布时，能够具有较宽松的布线空间，以便于实现更高分辨率。
在此情况下，在待驱动元件进行不同灰阶的显示时，通过控制第一控制电路将第二使能信号或第三输入信号传输至第二控制电路，控制第二控制电路的导通(开启)频率，控制驱动电路与待驱动元件形成导电通路的频率，可以控制驱动信号传输至待驱动元件的频率，形成导电通路的频率决定了待 驱动元件工作的总时长，待驱动元件工作的总时长是多次形成导电通路时待驱动元件工作的子时长的叠加。这样，可以通过控制驱动信号的幅值驱动信号传输至待驱动元件的频率，来控制待驱动元件的发光强度，进而实现对应的灰阶显示。
可以理解的是，驱动信号的幅值的取值范围，应该能够是的待驱动元件工作在发光效率高且稳定，色坐标均一度好且出光主波长稳定的范围内，例如为驱动信号幅值较大的区间；因此，待驱动元件显示中高灰阶时数据信号端所提供的数据信号，可以与待驱动元件显示低灰阶时数据信号端所提供的数据信号取值范围相同。
在像素电路所在子像素显示中高灰阶的情况下，第一控制电路将第二使能信号传输至第二控制电路，在子像素的发光阶段，第二控制电路响应于第二使能信号一直处于导通状态，驱动电路与待驱动元件一直形成导电通路，驱动信号持续传输至待驱动元件，由于中高低灰阶对应的驱动信号的幅值相对较高，使得待驱动元件可以在较高幅值的驱动信号的驱动下工作，保证待驱动元件的工作效率(发光效率)。
在像素电路所在子像素显示低灰阶的情况下，第一控制电路将第三输入信号传输至第二控制电路，在子像素的发光阶段，第二控制电路响应于第三输入信号为高频脉冲信号，即处于导通和截止交替的状态，使得驱动信号间歇性地传输至待驱动元件，待驱动元件周期性接收驱动信号，例如，待驱动元件接收一段时间驱动信号后停止一段时间，再接收一段时间驱动信号后停止一段时间。这样，驱动电路与待驱动元件形成导电通路的时间被缩短，驱动信号传输至待驱动元件的时间被缩短。因此，在像素电路所在子像素显示低灰阶的情况下，可以将驱动信号的幅值维持在较高值范围内或者保持在较大的固定幅值，通过改变待驱动元件的工作时长，使得子像素实现对应的低灰阶显示，从而提高了待驱动元件的工作效率，避免小电流幅值实现低灰阶显示的情况下待驱动元件工作效率较低、功耗较高的问题，避免显示灰阶均一性下降，避免显示出现色偏，提高了显示面板的显示效果。
示例性地，驱动信号的大小与数据信号端处接收的数据信号有关，数据信号可以为使待驱动元件能够具有较高的工作效率的信号，例如，数据信号可以是在较高幅值范围内变化的信号或者具有较高的固定幅值的信号。在此情况下，像素电路通过驱动电路控制驱动信号的幅值范围，通过第一控制电路和第二控制电路来控制驱动信号传输至待驱动元件的时间和频率，以控制子像素对应的灰阶显示。
并且，在一图像帧内，子像素显示低灰阶的情况下，相比于待驱动元件工作较短时间后长时间不工作，人眼会明显感受到闪烁的情况，本公开的实施例中的待驱动元件间歇性处于工作状态，即，待驱动元件的工作状态和非工作状态交替且交替频率较大，即，待驱动元件的亮暗交替频率较高，人眼不易观察到闪烁，从而提高了显示效果。
因此，本公开的实施例提供一种像素电路，驱动电路根据第一电压和写入的数据信号生成驱动信号。第一控制电路响应于第一控制信号写入第一输入信号，响应于第一输入信号传输第三输入信号；及，响应于第二控制信号，写入第二输入信号，响应于第二输入信号，传输第二使能信号。第二控制电路响应于接收到的来自第一控制电路的信号，将接收到的来自驱动电路的驱动信号传输至待驱动元件，控制待驱动元件的工作时长。在此情况下，在待驱动元件进行不同灰阶的显示时，在像素电路所在子像素显示中高灰阶的情况下，第一控制电路将第二使能信号传输至第二控制电路，使得待驱动元件一直在较高幅值的驱动信号的驱动下工作，保证待驱动元件的工作效率；在像素电路所在子像素显示低灰阶的情况下，第一控制电路将第三输入信号传输至第二控制电路，使得待驱动元件间歇性地处于工作状态，通过控制待驱动元件工作时长，使得待驱动元件可以在较高幅值的驱动信号的驱动下也可以实现对应的灰阶显示，提高了待驱动元件的工作效率。并且待驱动元件的工作频率相对较高，可以避免人眼观看到闪烁，提高显示效果。
示例性地，如图6A至图6C所示，第二控制电路20包括第九晶体管T9。第九晶体管T9的控制极与第一控制电路10耦接，第九晶体管T9的第一极与驱动电路30耦接，第九晶体管T9的第二极与待驱动元件L耦接。
在一些实施例中，如图4所示，第一控制电路10还与第三控制信号端Q3、第一使能信号端EM和第二电压端V2耦接。
第一控制电路10还被配置为响应于在第三控制信号端Q3处接收的第三控制信号，将第二电压端V2的第二电压传输至第二控制电路20；第一控制电路10还被配置为响应于在第一使能信号端EM处接收的第一使能信号和第二输入信号，将第三输入信号传输至第二控制电路20。
示例性地，第二电压端处接收的第二电压为直流电压，例如，第二电压为直流高电压。
在此情况下，第一控制电路10还可以将第二电压传输至第二控制电路20，以控制第二控制电路20接收直流电压。在子像素不发光的阶段，避免在第三输入信号为脉冲信号的情况下影响第二控制电路20内部元件的电压的稳定 性。
在一些实施例中，如图5A所示，第一控制电路10包括第一输入子电路11A。第一输入子电路11A与第一控制信号端Q1、第一输入信号端S1和第三输入信号端S3耦接。
第一输入子电路11A被配置为响应于在第一控制信号端Q1处接收的第一控制信号，写入在第一输入信号端S1处接收的第一输入信号，及，响应于第一输入信号，向第二控制电路20传输在第三输入信号端S3处接收的第三输入信号。
示例性地，如图5A所示，第一输入子电路11A还与第二控制电路20耦接。
示例性地，如图6A所示，第一输入子电路11A包括第一晶体管T1、第二晶体管T2和第一电容器C1。
第一晶体管T1的控制极与第一控制信号端Q1耦接，第一晶体管T1的第一极与第一输入信号端S1耦接。
第二晶体管T2的控制极与第一晶体管T1的第二极耦接，第二晶体管T2的第一极与第三输入信号端S3耦接，第二晶体管T2的第二极与第二控制电路20耦接。
示例性地，在第二控制电路20包括第九晶体管T9的情况下，第二晶体管T2的第二极与第九晶体管T9的控制极耦接。
第一电容器C1与第一晶体管T1的第二极耦接。例如，第一电容器C1的第一端与第一晶体管T1的第二极耦接，第一电容器C1的第二端与固定电压端耦接。
示例性地，该固定电压端被配置为传输固定电压信号，例如，固定电压信号包括直流电压信号；例如，固定电压信号等于或近似等于接地信号；例如，固定电压端可以为接地端。
可以理解的是，第一输入子电路中的第一电容器可以将写入的第一输入信号存储，以控制第二晶体管的控制极的电压为第一输入信号的电压。
在另一些实施例中，如图5B所示，第一控制电路10还包括稳压子电路12。
稳压子电路12与第一输入子电路11B、第一使能信号端EM、第三控制信号端Q3、第二电压端V2和第二控制电路20耦接。
稳压子电路12被配置为响应于在第三控制信号端Q3处接收的第三控制信号，将第二电压端V2的第二电压传输至第二控制电路20；及，响应于在 第一使能信号端EM处接收的第一使能信号，将来自第一输入子电路11B的信号传输至第二控制电路20。
在此情况下，通过稳压子电路12，在第一使能信号有效的情况下，将第三输入信号传输至第二控制电路20，这样，在待驱动元件不发光阶段，第三输入信号不会传输至第二控制电路20，避免第三输入信号影响第二控制电路20的电压，例如第二控制电路20中的第九晶体管T9的控制极的电压稳定，可以避免第三输入信号为高频脉冲信号影响第二控制电路20的电压的稳定性，例如第二控制电路20中的第九晶体管T9的控制极的电压振荡，导致驱动电路30的电压受到影响的问题，并且，在此阶段，稳压子电路12将第二电压传输至第二控制电路20，使得第二控制电路20接收稳定的电压，即第九晶体管T9的控制极的电压稳定，保证了第二控制电路20的电压稳定性。
示例性地，如图6B所示，第一输入子电路11B包括：第三晶体管T3、第四晶体管T4和第一电容器C1。
第三晶体管T3的控制极与第一控制信号端Q1耦接，第三晶体管T3的第一极与第一输入信号端S1耦接。
第四晶体管T4的控制极与第三晶体管T3的第二极耦接，第四晶体管T4的第一极与第三输入信号端S3耦接，第四晶体管T4的第二极与稳压子电路12耦接。
第一电容器C1与第三晶体管T3的第二极耦接。例如，第一电容器C1的第一端与第三晶体管T3的第二极耦接，第一电容器C1的第二端与固定电压端耦接。
示例性地，该固定电压端被配置为传输固定电压信号，例如，固定电压信号包括直流电压信号；例如，固定电压信号等于或近似等于接地信号；例如，固定电压端可以为接地端。
可以理解的是，第二输入子电路中的第二电容器可以将写入的第一输入信号存储，以控制第四晶体管的控制极的电压为第一输入信号的电压。
稳压子电路12包括：第五晶体管T5和第六晶体管T6。
第五晶体管T5的控制极与第一使能信号端EM耦接，第五晶体管T5的第一极与第一输入子电路11B耦接，第五晶体管T5的第二极与第二控制电路20耦接。
第六晶体管T6的控制极与第三控制信号端Q3耦接，第六晶体管T6的第一极与第二电压端V2耦接，第六晶体管T6的第二极与第二控制电路20耦接。
示例性地，在第一输入子电路11B包括第四晶体管T4的情况下，第五晶体管T5的第一极与第四晶体管T4的第二极耦接。示例性地，在第二控制电路20包括第九晶体管T9的情况下，第六晶体管T6的第二极与第九晶体管T9的控制极耦接。
在一些实施例中，如图5A和图5B所示，第一控制电路10还包括第二输入子电路13。
第二输入子电路13与第二控制信号端Q2、第二输入信号端S2、第二使能信号端EM’和第二控制电路20耦接。
第二输入子电路13被配置为响应于在第二控制信号端Q2处接收的第二控制信号，写入在第二输入信号端S2处接收的第二输入信号，及，响应于第二输入信号，将在第二使能信号端EM’处接收的第二使能信号传输至第二控制电路20。
示例性地，如图6A至图6C所示，第二输入子电路13包括第七晶体管T7、第八晶体管T8和第三电容器C3。
第七晶体管T7的控制极与第二控制信号端Q2耦接，第七晶体管T7的第一极与第二输入信号端S2耦接。
第八晶体管T8的控制极与第七晶体管T7的第二极耦接，第八晶体管T8的第一极与第二使能信号端EM’耦接，第八晶体管T8的第二极与第二控制电路20耦接。
第三电容器C3与第七晶体管T7的第二极耦接。例如，第三电容器C3的第一端与第七晶体管T7的第二极耦接，第三电容器C3的第二端与固定电压端耦接。
示例性地，该固定电压端被配置为传输固定电压信号，例如，固定电压信号包括直流电压信号；例如，固定电压信号等于或近似等于接地信号；例如，固定电压端可以为接地端。
可以理解的是，第二输入子电路中的第三电容器可以将写入的第二输入信号存储，以控制第八晶体管的控制极的电压为第二输入信号的电压。
示例性地，在第二控制电路20包括第九晶体管T9的情况下，第八晶体管T8的第二极与第九晶体管T9的控制极耦接。
在一些实施例中，如图5A和图5B所示，驱动电路20还包括驱动子电路21、驱动控制子电路22、数据写入子电路23和补偿子电路24。
如图6A至图6C所示，驱动子电路21包括驱动晶体管DT和第四电容器C4。第四电容器C4的第一端与第一电压端V1耦接，第四电容器C4的第二 端与驱动晶体管DT的控制极耦接。
数据写入子电路23与扫描信号端GATE、数据信号端DATA和驱动子电路21耦接。补偿子电路24与扫描信号端GATE、驱动晶体管DT的控制极和驱动晶体管DT的第二极耦接。驱动控制子电路24至少与第一使能信号端EM、第一电压端V1和驱动子电路21耦接。
数据写入子电路23被配置为响应于在扫描信号端GATE处接收的扫描信号，将在数据信号端DATA处接收的数据信号写入驱动子电路21。
驱动子电路21被配置为根据写入的数据信号和第一电压端V1的第一电压，生成驱动信号。
驱动控制子电路22被配置为响应于在第一使能信号端EM处接收的第一使能信号，使第一电压端V1和第二控制电路20通过驱动子电路21中的驱动晶体管DT形成导电通路。
补偿子电路24被配置为响应于在扫描信号端GATE处接收的扫描信号，将数据信号和驱动晶体管DT的阈值电压写入驱动晶体管DT的控制极。这样，可以避免驱动晶体管DT的阈值电压对驱动信号的影响。
示例性地，如图6A和图6B所示，驱动控制子电路22包括第十晶体管T10。
第十晶体管T10的控制极与第一使能信号端EM耦接，第十晶体管T10的第一极与第一电压端V1耦接，第十晶体管T10的第二极与驱动晶体管DT的第一极耦接。
其中，驱动晶体管DT的第二极与第二控制电路20耦接。例如，在第二控制电路20包括第九晶体管T9的情况下，驱动晶体管DT的第二极与第九晶体管T9的第一极耦接。
又示例性地，如图6C所示，驱动控制子电路22包括第十晶体管T10和第十一晶体管T11。
第十晶体管T10的控制极与第一使能信号端EM耦接，第十晶体管T10的第一极与第一电压端V1耦接，第十晶体管T10的第二极与驱动晶体管DT的第一极耦接。
第十一晶体管T11的控制极与第一使能信号端EM耦接，第十一晶体管T11的第一极与驱动晶体管DT的第二极耦接，第十一晶体管T11的第二极与第二控制电路20耦接。
例如，在第二控制电路20包括第九晶体管T9的情况下，第十一晶体管T11的第二极与第九晶体管T9的第一极耦接。
可以理解的是，在子像素不发光的阶段，例如数据信号写入的阶段，第十一晶体管T11响应于第一使能信号处于截止状态，使得驱动晶体管DT与第二控制电路20断开，避免第二控制电路20接收到第三输入信号的情况下，第三输入信号的脉冲信号影响驱动晶体管DT的第二极的电压，而影响数据信号写入的准确性。
示例性地，如图6A至图6C所示，数据写入子电路23包括第十二晶体管T12。
第十二晶体管T12的控制极与扫描信号端GATE耦接，第十二晶体管T12的第一极与数据信号端DATA耦接，第十二晶体管T12的第二极与驱动晶体管DT的第一极耦接。
示例性地，如图6A至图6C所示，补偿子电路24包括第十三晶体管T13。
第十三晶体管T13的控制极与扫描信号端GATE耦接，第十三晶体管T13的第一极与驱动晶体管DT的第二极耦接，第十三晶体管T13的第二极与驱动晶体管DT的控制极耦接。
可以理解的是，第十三晶体管T13可以将数据信号和驱动晶体管DT的阈值电压写入驱动晶体管DT的控制极，以实现阈值电压补偿。
在一些实施例中，如图5A和图5B所示，驱动电路30还包括复位子电路25。复位子电路25与驱动子电路21、待驱动元件L、复位信号端RESET和初始信号端INIT耦接。
复位子电路25被配置为响应于在复位信号端RESET处接收的复位信号，将在初始信号端INIT处接收的初始信号传输至驱动子电路21和待驱动元件L。这样，可以对驱动子电路21和待驱动元件L进行复位，避免信号干扰。
需要说明的是，可以根据实际情况，对初始信号的电压进行选择，在此不作限定。例如，初始信号可以为高电平信号，也可以为低电平信号。
在此情况下，复位子电路25对驱动子电路21和待驱动元件L进行复位。
示例性地，如图6A至图6C所示，复位子电路26包括第十四晶体管T14和第十五晶体管T15。
第十四晶体管T14的控制极与复位信号端RESET耦接，第十四晶体管T14的第一极与初始信号端INIT耦接，第十四晶体管T14的第二极与驱动子电路21耦接。
第十五晶体管T15的控制极与复位信号端RESET耦接，第十五晶体管T15的第一极与初始信号端INIT耦接，第十五晶体管T15第二极与待驱动元件L耦接。
例如，第十四晶体管T14的第二极与驱动晶体管DT的控制极耦接。第十五晶体管T15的第二极与待驱动元件L的第一极耦接。
可以理解的是，第十四晶体管T14可以将初始信号传输至驱动晶体管DT的控制极，以对驱动晶体管DT的控制极的电压进行复位。第十五晶体管T15可以将初始信号传输至待驱动元件L，以对待驱动元件L的第一极的电压进行复位。
在一些实施例中，第一使能信号端与第二使能信号端为同一信号端，参考图6D，第八晶体管T8的第一极与第一使能信号端EM耦接。
需要说明的是，驱动电路的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可，能够实现上述驱动电路的功能的电路，例如能共提供驱动信号的电路，均在本公开的保护范围内。
在一些实施例中，如图7A至图7D所示，显示面板100还包括多条扫描信号线GL、多条数据信号线DL、多条使能信号线E和多条复位信号线RL。
可以理解的是，一行子像素对应的各像素电路的扫描信号端GATE与一条扫描信号线GL，第一使能信号端EM与一条使能信号线E耦接，复位信号端RESET与一条复位信号线RL耦接。一列子像素对应的各像素电路的数据信号端DATA与一条数据信号线DL耦接。例如，参考图7A至图7D，第二使能信号端和第一使能信号端可以耦接同一条使能信号线；或者，一行像素电路与两条使能信号线耦接，第二使能信号端和第一使能信号端分别耦接不同的使能信号线(图中未示出)。
在一些实施例中，如图7A至图7D所示，显示面板100还包括多条第一信号线LQ和多条第二信号线LS。
示例性地，一行像素电路的第一控制信号端Q1和第二控制信号端Q2分别与同一条第一信号线LQ耦接，一列像素电路的第一输入信号端S1和第二输入信号端S2分别与两条第二信号线LS耦接。在此情况下，如图7A所示，一行子像素分别与同一条第一信号线LQ耦接，一列子像素分别与两条第二信号线LS耦接。
示例性地，一行子像素所耦接的一条第一信号线LQ可以是扫描信号线GL，例如，第一控制信号端Q1与第二控制信号端Q2同为扫描信号端GATE；或者，一行子像素所耦接的一条第一信号线LQ可以是复位信号线RL，例如，第一控制信号端Q1与第二控制信号端Q2同为复位信号端RESET。
在此情况下，第一控制电路10分别响应于第一控制信号端Q1与第二控 制信号端Q2，同时写入第一输入信号和第二输入信号，这样，第一输入信号端S1所耦接的输入信号线和第二输入信号端S2所耦接的输入信号线不同，即，第一输入信号端S1与第二输入信号端S2为不同的信号端。
可以理解的是，同一行像素电路中，各个像素电路的复位信号端RESET和第一控制信号端Q1与同一条复位信号线耦接，各个像素电路的扫描信号端GATE和第二控制信号端Q2与同一条扫描信号线耦接；或者，各个像素电路的扫描信号端与第一控制信号端耦接同一条扫描信号线，各个像素电路的复位信号端与第二控制信号端耦接同一条复位信号线。这样，在多个像素电路阵列排布的情况下，可以减少每行像素电路所耦接的信号线的数量，使得显示面板可以具有较宽松的布线空间，以便显示面板实现较高的分辨率。
示例性地，一行像素电路的第一控制信号端Q1和第二控制信号端Q2分别与两条第一信号线LQ耦接，一列像素电路的第一输入信号端S1和第二输入信号端S2分别与同一条第二信号线LS耦接。在此情况下，如图7B所示，一行子像素分别与两条第一信号线LQ耦接，一列子像素分别与同一条第二信号线LS耦接，即，同一列像素电路中，各个像素电路的第一输入信号端S1和第二输入信号端S2均与同一条第二信号线LS耦接。这样，通过控制第二信号线LS传输的信号幅值，来向一列像素电路中的第一输入信号端S1和第二输入信号端S2提供不同幅值的信号。在多个像素电路阵列排布的情况下，可以减少每列像素电路所耦接的信号线的数量，使得显示面板可以具有较宽松的布线空间，以便显示面板实现较高的分辨率。
示例性地，一行子像素所耦接的两条第一信号线LQ可以分别是扫描信号线GL和复位信号线RL。例如，第一控制信号端Q1与复位信号线RL耦接，即，第一控制信号端Q1与复位信号端RESET为同一信号端；第二控制信号端Q2与扫描信号线GL耦接，即，第二控制信号端Q2与扫描信号端GATE为同一信号端。或者，例如，第一控制信号端Q1与扫描信号线GL耦接，即，第一控制信号端Q1与扫描信号端GATE为同一信号端；第二控制信号端Q2与复位信号线RL耦接，即，第二控制信号端Q2与复位信号端RESET为同一信号端。
在此情况下，第一控制电路10分别响应于第一控制信号端Q1与第二控制信号端Q2，在不同时刻分别写入第一输入信号和第二输入信号，这样，第一输入信号端S1和第二输入信号端S2可以耦接同一条输入信号线，即，第一输入信号端S1与第二输入信号端S2为同一信号端，以在不同时刻写入不同的第一输入信号和第二输入信号。
示例性地，一行像素电路的第一控制信号端Q1和第二控制信号端Q2分别与两条第一信号线LQ耦接，一列像素电路的第一输入信号端S1和第二输入信号端S2分别与两条第二信号线LS耦接。在此情况下，如图7C所示，一行子像素分别与两条第一信号线LQ耦接，一列子像素分别与两条第二信号线LS耦接。示例性地，两条第一信号线LQ与扫描信号线GL和复位信号线RL不相同，两条第一信号线LQ分别向第一控制信号端Q1和第二控制信号端Q2提供第一控制信号和第二控制信号，两条第二信号线LS分别向第一输入信号端S1和第二输入信号端S2提供第一输入信号和第二输入信号。
示例性地，在第一驱动电路10还与第三控制信号端Q3耦接的情况下，一行像素电路的第三控制信号端Q3与一条第一信号线LQ耦接，且第三控制信号端Q3所耦接的控制信号线与第一控制信号端Q1所耦接的控制信号线和第二控制信号端Q2所耦接的控制信号线均不同。在此情况下，如图7D所示，一行子像素至少与两条第一信号线LQ耦接。
在一些实施例中，如图7A至图7D所示，显示面板100还包括多条输入信号线LH。其中，像素电路的第三输入信号端与输入信号线耦接。示例性地，在多条输入信号线传输相同的第三输入信号的情况下，多条输入信号线可以呈网格状分布，例如，多条输入信号线中的一部分输入信号线与扫描信号线平行，多条输入信号线中的另一部分输入信号线与数据信号线平行，此时，一行子像素与一条输入信号线耦接；一行像素电路的第三输入信号端与一条输入信号线耦接。例如，一列子像素与一条输入信号线耦接；一列像素电路的第三输入信号端与一条输入信号线耦接。
又示例性地，在多条输入信号线传输不同的第三输入信号的情况下，多条输入信号线与扫描信号线平行，此时，一行子像素与一条输入信号线耦接；一行像素电路的第三输入信号端与一条输入信号线耦接。例如，在子像素不发光阶段，例如数据信号写入阶段和复位阶段，子像素中的像素电路所接收的第三输入信号和第一使能信号及第二使能信号为相同电平的信号，例如同为高电平信号。
此外，如图7A至图7D所示，显示面板100还包括多条第一电压线L V1和多条第三电压线L V3。在第一驱动电路10还与第二电压端V2耦接的情况下，如图7D所示，显示面板100还包括多条第二电压线L V2。
需要说明的是，本领域技术人员可以根据显示面板的空间结构，设置第一电压线L V1、第二电压线L V2和第三电压线L V3的布线方式，以及各自与子像素对应的像素电路的耦接方式，在此不作限定。例如，参考图7D，一列子 像素中的像素电路的第一电压端可以与一条第一电压线L V1，第二电压端可以与一条第二电压线L V2，待驱动元件所耦接的第三电压端可以与一条第三电压线L V3耦接。在此情况下，第一电压线L V1为第一电压端V1提供第一电压，第二电压线L V2为第二电压端V2提供第二电压，第三电压线L V3为第三电压端V3提供第三电压。
在一些实施例中，第一控制信号端Q1与复位信号端RESET为同一信号端，第二控制信号端Q2与扫描信号端GATE为同一信号端，第一输入信号端SS1与第二输入信号端S2为同一信号端。
可以理解的是，第一控制信号的时序与复位信号的时序相同，第二控制信号的时序与扫描信号的时序相同，第一输入信号的时序和第二输入信号的时序相同。这样，显示不同灰阶的各子像素可以与一条第二信号线耦接，像素电路可以在不同时刻写入不同的第一输入信号和第二输入信号，以使各像素电路控制待驱动元件显示对应的灰阶。
在另一些实施例中，第一控制信号端Q1与第二控制信号端Q2同为复位信号端RESET，或者同为扫描信号端GATE，第一输入信号端S1与第二输入信号端S2为不同信号端。
可以理解的是，第一控制信号的时序和第二控制信号的时序相同，第一输入信号的时序和第二输入信号的时序不同。这样，显示不同灰阶的各子像素需要与两条第二信号线耦接，像素电路可以在同一时刻写入不同的第一输入信号和第二输入信号，以使各像素电路控制待驱动元件显示对应的灰阶。
需要说明的是，本公开的实施例提供的像素电路中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)、场效应晶体管(Field Effect Transistor，FET)或其他特性相同的开关器件，本公开的实施例对此并不设限。
在一些实施例中，像素电路所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的像素电路中，各个电路和各个子电路的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例 并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路和各个子电路中的一个或多个，基于前述各电路和各个子电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
需要说明的是，一个图像帧周期包括各行扫描阶段和工作阶段。示例性地，扫描阶段包括每行子像素的扫描时段。
示例性地，显示面板的各行子像素可以逐行依次进行扫描阶段和工作阶段，例如，第一行子像素至最后一行子像素逐行进入扫描阶段，在最后一行子像素的扫描阶段结束之后，第一行子像素至最后一行子像素逐行进入工作阶段。其中，每一子像素在工作阶段对应的第一使能信号的有效时长相同。或者，显示面板的各行子像素可以在逐行依次进入扫描阶段之后，再同时进行工作阶段。
或者，示例性地，各像素电路也可以在每一行子像素的扫描阶段结束后直接进入该行子像素的工作阶段，如在第一行子像素的扫描阶段结束后进入第一行子像素的工作阶段，在第一行子像素的扫描阶段结束后，第二行子像素进入扫描阶段，并在第二行子像素扫描阶段结束后，进入第二行子像素的工作阶段，依次类推，直至最后一行子像素的扫描阶段结束后进入最后一行子像素的工作阶段。
需要说明的是，在每个行扫描阶段，一行子像素对应的各像素电路同时被写入不同的或者相同的数据信号，也就是说数据信号为一组信号。各个像素电路所写入的数据信号对应的子像素需要显示的灰阶有关。
以下，以上述像素电路中的各个晶体管均为P型晶体管为例，对一个像素电路在一图像帧的不同阶段的工作情况进行举例说明。其中，第一使能信号和第二使能信号为相同的信号。
需要说明的是，为了方便描述，文中将各个信号端(例如第一输入信号端、第二输入信号端、第三输入信号端、第一控制信号端、第二控制信号端、第三控制信号端、扫描信号端、数据信号端、复位信号端、第一使能信号端、第二使能信号端、第一电压端、第二电压端和第三电压端等)所传输的各个信号(例如第一输入信号、第二输入信号、第三输入信号、第一控制信号、第二控制信号、第三控制信号、扫描信号、数据信号、复位信号、第一使能信号、第二使能信号、第一电压、第二电压和第三电压等)采用相同的符号表示，但两者实际含义不相同。
示例性地，下文中的一图像帧中的第一阶段(U1)和第二阶段(U2)的时长约为微秒(μs)级，一图像帧中的第三阶段(U3)的时长约为毫秒(ms)级。
在如图8所示的一图像帧(F)中的第一阶段(U1)，参考图5A和图5B，驱动电路30中的复位子电路25响应于在复位信号端RESET处接收的复位信号，将在初始信号端INIT处接收的初始信号传输至驱动子电路21和待驱动元件L。
例如，参考图6A至图6C，复位子电路25中的第十四晶体管T14响应于在复位信号端RESET处接收的低电平的复位信号，第十四晶体管T14导通，将在初始信号端INIT处接收的初始信号传输至驱动子电路21中驱动晶体管DT的控制极，对驱动晶体管DT进行复位。第十五晶体管T15响应于在复位信号端RESET处接收的低电平的复位信号，第十五晶体管T15导通，将在初始信号端INIT处接收的初始信号传输至待驱动元件L的第一极，对待驱动元件L进行复位。其中，驱动晶体管DT的控制极的电压和待驱动元件L的第一极的电压均为初始信号的电压。
在此情况下，初始信号端INIT处接收的初始信号能够消除上一帧的信号对驱动晶体管DT的控制极的电压和待驱动元件L的第一极的电压的影响。示例性地，该初始信号可以为低电平信号，也可以为高电平信号；例如，在驱动晶体管为P型晶体管的情况下，初始信号的电压大于零。
示例性地，在如图8所示的第一阶段(U1)，在第一控制信号端Q1处接收的第一控制信号的时序和在第二控制信号端Q2处接收的第二控制信号的时序，与在复位信号端RESET处接收的复位信号的时序相同。此时，第一控制信号端与第二控制信号端可以同为复位信号端。
参考图5A和图5B，第一控制电路10中的第二输入子电路13响应于在第二控制信号端Q2处接收的第二控制信号，写入在第二输入信号端S2处接收的第二输入信号，及，响应于第二输入信号，将在第二使能信号端EM’处接收的第二使能信号传输至第二控制电路20。例如，参考图6A至图6C，第二输入子电路13中的第七晶体管T7响应于在第二控制信号端Q2处接收的低电平的第二控制信号，第八晶体管T8导通，写入在第二输入信号端S2处接收的第二输入信号。第三电容器C3存储第二输入信号。
参考图5A，第一控制电路10中的第一输入子电路11A响应于在第一控制信号端Q1处接收的第一控制信号，写入在第一输入信号端S1处接收的第一输入信号，及，响应于第一输入信号，将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。例如，参考图6A，第一晶体管T1响应于在第一控制信号端Q1处接收的低电平的第一控制信号，第一晶体管T1导通，写入在第一输入信号端S1处接收的第一输入信号，第一电容器C1存储 第一输入信号。
参考图5B，第一控制电路10中的稳压子电路12响应于第三控制信号端Q3处接收的第三控制信号，将第二电压端V2的第二电压传输至第二控制电路20。第一控制电路10中的第一输入子电路11B响应于在第一控制信号端Q1处接收的第一控制信号，写入在第一输入信号端S1处接收的第一输入信号，第一输入子电路11B响应于第一输入信号，向第二控制电路20传输至第三输入信号，稳压子电路12响应于在第一使能信号端EM处接收的第一使能信号，将来自第一输入子电路11B的信号(即第三输入信号)传输至第二控制电路20。
例如，参考图6B，稳压子电路12中的第六晶体管T6响应于第三控制信号端Q3处接收的低电平的第三控制信号(参考图11)，将第二电压端V2的第二电压传输至第二控制电路20。第二控制电路20中的第九晶体管T9响应于高电平的第二电压，第九晶体管T9截止，驱动电路30与待驱动元件L不形成导电通路。第一输入子电路11B中的第三晶体管T3响应于在第一控制信号端Q1处接收的低电平的第一控制信号，第三晶体管T3导通，写入在第一输入信号端S1处接收的第一输入信号，第一电容器C1存储第一输入信号。
在像素电路对应的子像素显示低灰阶的情况下，第二输入信号为高电平信号，第一输入信号为低电平信号。参考图6A至图6C，第二输入子电路13中的第八晶体管T8响应于高电平的第二输入信号，第八晶体管T8截止，不会将在第二使能信号端EM’处接收的第二使能信号传输至第二控制电路20。
参考图6A，第一输入子电路11A中的第二晶体管T2响应于低电平的第一输入信号，第二晶体管T2导通，将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。此时，第三输入信号为高电平信号。第二控制电路20中的第九晶体管T9响应于来自第一控制电路10的高电平的第三输入信号，第九晶体管T9截止，驱动电路30与待驱动元件L不形成导电通路。
参考图6B，第一输入子电路11B中的第四晶体管T4响应于低电平的第一输入信号，第四晶体管T4导通，稳压子电路12中的第五晶体管T5响应于在第一使能信号端EM处接收的高电平的第一使能信号，第五晶体管T5截止，第四晶体管T4和第五晶体管T5不会将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
在像素的显示灰阶为中灰阶或高灰阶的情况下，第二输入信号为低电平信号，第一输入信号为高电平信号。参考图6A至图6C，第二输入子电路13中的第八晶体管T8响应于低电平的第二输入信号，第八晶体管T8导通，将 在第二使能信号端EM’处接收的高电平的第二使能信号传输至第二控制电路20。第二控制电路20中的第九晶体管T9响应于高电平的第二使能信号，第九晶体管T9截止，驱动电路30与待驱动元件L不形成导电通路。
参考图6A，第一输入子电路11A中的第二晶体管T2响应于高电平的第一输入信号，第二晶体管T2截止，不会将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
参考图6B，第一输入子电路11B中的第四晶体管T4响应于高电平的第一输入信号，第四晶体管T4截止，稳压子电路12中的第五晶体管T5响应于在第一使能信号端EM处接收的高电平的第一使能信号，第五晶体管T5截止，第四晶体管T4和第五晶体管T5不会将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
在此情况下，无论第三输入信号为高电平信号还是低电平信号，第三输入信号不会传输至第二控制电路20。这样，在第三输入信号为脉冲信号的情况下，第三输入信号不会影响第九晶体管T9的控制极的电压，可以避免对第九晶体管T9所耦接的驱动电路30中的驱动晶体管DT的第二极的电压，避免影响驱动电路30后续写入数据信号的准确性。示例性地，在第一阶段，第三输入信号的电平可以不作限定，例如第三输入信号可以是高电平信号，也可以是高电平和低电平交替的信号。
另外，示例性地，在如图9所示一图像帧(F)中，在第一控制信号端Q1处接收的第一控制信号的时序与在复位信号端RESET处接收的复位信号的时序相同，此时，第一控制信号端与复位信号端为同一信号端。在此情况下，在第一阶段，第一控制电路写入第一输入信号，不写入第二输入信号。
示例性地，第一输入信号的电压幅值与第一控制信号的电压幅值和第二使能信号的电压幅值相匹配，即，第一输入信号和第一控制信号需要保证接收这两个信号的晶体管的完全导通和截止，第一输入信号和第二使能信号需要保证接收这两个信号的晶体管的完全导通和截止，例如，如果晶体管采用P型晶体管，在第一控制信号的电压为10V的情况下，第一输入信号的电压范围为7V～10V，在第一控制信号的电压为-10V的情况下，第一输入信号的电压范围为-7V～-10V，第二使能信号的电压为-7V的情况下，第一输入信号的电压范围为-7V～-10V。
相应地，第二输入信号的电压幅值与第二控制信号的电压幅值和第三输入信号的电压幅值相匹配，即，第二输入信号和第二控制信号需要保证接收这两个信号的晶体管的完全导通和截止，第二输入信号和第三输入信号需要 保证接收这两个信号的晶体管的完全导通和截止，例如，如果晶体管采用P型晶体管，在第二控制信号的电压为10V的情况下，第二输入信号的电压范围为7V～10V，在第二控制信号的电压为-10V的情况下，第二输入信号的电压范围为-7V～-10V，第三输入信号的电压为-7V的情况下，第二输入信号的电压范围为-7V～-10V。
综上，在第一阶段，在像素电路对应的子像素显示低灰阶的情况下，第一输入信号为低电平信号，第二输入信号为高电平信号，此时，第一控制电路10将第三输入信号传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。在像素电路对应的子像素显示中灰阶或高灰阶的情况下，第一输入信号为高电平信号，第二输入信号为低电平信号，此时，第一控制电路10将第二使能信号传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。另外，第一控制电路10还可以将第二电压传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。待驱动元件L不工作。
在如图8所示的一图像帧(F)中的第二阶段(U2)，参考图5A和图5B，驱动电路30中的数据写入子电路23响应于在扫描信号端GATE处接收的扫描信号，将在数据信号端DATA处接收的数据信号写入驱动子电路21。例如，参考图6A至图6C，数据写入子电路23中的第十二晶体管T12响应于在扫描信号端GATE处接收的低电平的扫描信号，第十二晶体管T12导通，将在数据信号端DATA处接收的数据信号写入驱动子电路21，即，写入驱动晶体管DT的第一极。
补偿子电路24响应于在扫描信号端GATE处接收的扫描信号，将数据信号和驱动晶体管DT的阈值电压写入驱动晶体管DT的控制极。例如，补偿子电路24中的第十三晶体管T13响应于在扫描信号端GATE处接收的低电平的扫描信号，第十三晶体管T13导通，将驱动晶体管DT的控制极与第二极相连接，使驱动晶体管DT处于自饱和状态(或二极管导通状态)，驱动晶体管DT的控制极的电压为驱动晶体管DT的第一极的电压和驱动晶体管DT的预制电压之和，即，数据信号和驱动晶体管DT的阈值电压写入至驱动晶体管DT的控制极。此时，驱动晶体管DT的控制极的电压Vg＝V data+V th，V data为数据信号的电压，V th为驱动晶体管DT的阈值电压。
在此情况下，与驱动晶体管DT的控制极耦接的第四电容器C4的第二端的电压也为V data+V th，第四电容器C4的第一端与第一电压端V1耦接，即， 第四电容器C4的第一端的电压为第一电压V DD，此时，对第四电容器C4的两端充电。第四电容器C4的两端存在电位差为V DD-V data-V th。
示例性地，如图10所示的一图像帧(F)中，在第一控制信号端Q1处接收的第一控制信号的时序和在第二控制信号端Q2处接收的第二控制信号的时序，与在扫描信号端GATE处接收的扫描信号的时序相同。即，第一控制信号端与第二控制信号端可以同为扫描信号端。在此情况下，第一控制电路在第二阶段写入第一输入信号和第二输入信号，在第一阶段不写入第一输入信号和第二输入信号。
需要说明的是，在第一控制信号端与第二控制信号端可以同为扫描信号端的情况下第一控制电路中的各子电路的工作情况，与上述的第一控制电路中的各子电路在第一控制信号端与第二控制信号端同为复位信号端的情况下的工作情况类似，具体可参考上述描述，在此不再赘述。
在此情况下，在第二阶段，在像素电路对应的子像素显示低灰阶的情况下，第一输入信号为低电平信号，第二输入信号为高电平信号，此时，第一控制电路10将第三输入信号传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。在像素电路对应的子像素显示中灰阶或高灰阶的情况下，第一输入信号为高电平信号，第二输入信号为低电平信号，此时，第一控制电路10将第二使能信号传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。另外，第一控制电路10还可以将第二电压传输至第二控制电路20，通过控制第二控制电路20，使得驱动电路30和待驱动元件L不形成导电通路。待驱动元件L不工作。
此外，由于第一使能信号为高电平信号，因此驱动电路30中的驱动控制子电路22中的各个晶体管响应于该高电平的第一使能信号处于截止状态。例如，驱动控制子电路22中的第十晶体管T10和第十一晶体管T11均为截止状态，第十晶体管T10不会将第一电压端V1的第一电压传输至驱动晶体管DT的第一极。
并且，在第一控制电路10将第三输入信号传输至第二控制电路20的情况下，第三输入信号为脉冲信号，第二控制电路20中的第九晶体管T9的控制极的电压会受到波动，相应地第九晶体管T9的第一极的电压也会受到波动。因此，图6C中的像素电路101，驱动电路中的驱动控制子电路22中的第十一晶体管T11响应于高电平的第一使能信号处于截止状态，使得驱动晶体管DT与第二控制电路20中的第九晶体管T9不相连，避免第九晶体管T9影响 驱动晶体管DT的电压，保证写入的数据信号的准确性。
另外，对于图6A中的像素电路101，第九晶体管T9的第一极与驱动晶体管DT的第二极耦接，在第二阶段，参考图12，第三输入信号为高电平信号，使得第九晶体管T9的控制极的电压为固定电压，这样，可以避免第三输入信号的脉冲信号影响第九晶体管T9的电压而导致驱动晶体管DT的第二极的电压受到波动。示例性地，参考图12，在第一阶段和第二阶段，第三输入信号的时序与第一使能信号的时序相同。
在如图8所示的一图像帧(F)的第三阶段(U3)，参考图6A至图6C，驱动电路30中的驱动控制子电路22响应于在第一使能信号端EM处接收的第一使能信号，使驱动子电路21中的驱动晶体管DT与第一电压端V1和第二控制电路20形成导电通路。例如，参考图6A，驱动控制子电路22中的第十晶体管T10响应于在第一使能信号端EM处接收的低电平的第一使能信号，第十晶体管T10导通，驱动晶体管DT的第一极通过第十晶体管T10与第一电压端V1耦接，驱动晶体管DT的第二极与第二控制电路20中的第九晶体管T9的第一极耦接，使驱动子电路21中的驱动晶体管DT与第一电压端V1和第二控制电路20形成导电通路。例如，参考图6C，驱动控制子电路22中的第十晶体管T10和第十一晶体管T11响应于在第一使能信号端EM处接收的低电平的第一使能信号，第十晶体管T10和第十一晶体管T11均导通，驱动晶体管DT的第一极通过第十晶体管T10与第一电压端V1耦接，驱动晶体管DT的第二极通过第十一晶体管T11与第二控制电路20中的第九晶体管T9的第一极耦接，使驱动子电路21中的驱动晶体管DT与第一电压端V1和第二控制电路20形成导电通路。此时，驱动晶体管DT的第一极的电压为第一电压。
在此情况下，驱动子电路21根据写入的数据信号和第一电压端V1的第一电压，生成驱动信号。例如，根据电容的电荷保持定律，驱动子电路21中的第四电容器C4的第一端和第二端的电位差保持不变，在第四电容器C4的第一端的电压保持为第一电压的情况下，第四电容器C4的第二端的电压仍为V data+V th，此时驱动晶体管DT的控制极的电压为V data+V th。
可以理解的是，在驱动晶体管DT的栅源电压差大于或等于其阈值电压V th时，驱动晶体管DT导通，并产生驱动信号，该驱动信号从驱动晶体管DT的第二极输出。由于驱动晶体管DT的控制极的电压为V data+V th，驱动晶体管DT的第一极的电压为第一电压V DD，此时，驱动晶体管DT的栅源电压差V gs＝V data+V th-V DD。因此，经过驱动晶体管DT的驱动电流I＝1/2·K·(V gs-V th) 2＝ 1/2·K·(V data+V th-V DD-V th) 2＝1/2·K·(V data-V DD) 2，该驱动电流I作为驱动子电路21生成的驱动信号。其中，K＝W/L·C·u，W/L为驱动晶体管DT的宽长比，C为沟道绝缘层电容，u为沟道载流子迁移率。
可以理解的是，驱动电路10生成的驱动信号只与数据信号和第一电压有关，与驱动晶体管DT的阈值电压无关，从而实现了对驱动电路中驱动晶体管的阈值电压的补偿，从而避免了驱动晶体管DT的阈值电压对待驱动元件L工作情况(例如发光亮度)的影响，提高了待驱动元件L亮度的均一性。
需要说明的是，驱动电流(即驱动信号)的大小与驱动晶体管的特性有关，对于向不同颜色的子像素(例如红色子像素、绿色子像素和蓝色子像素)提供驱动信号的像素电路，需要考虑实现不同颜色子像素的发光元件的光电特性，可以通过设计驱动晶体管的尺寸来实现不同的驱动能力。例如，向红色子像素提供驱动信号的像素电路的驱动晶体管的宽长比、向绿色子像素提供驱动信号的像素电路的驱动晶体管的宽长比和向蓝色子像素提供驱动信号的像素电路的驱动晶体管中，至少两个驱动晶体管的宽长比不同。这样，在不同颜色的子像素均显示相同的灰阶时，理论上来讲，如果向不同颜色的子像素提供驱动信号的像素电路中的驱动晶体管的尺寸完全相同，不同子像素需要的驱动信号幅值可能存在差异，也即向不同子像素的像素电路提供的数据信号的幅值不同，设计复杂度会大大提升；而通过对各像素电路中的驱动晶体管的尺寸进行设计，例如，改变驱动晶体管的宽长比来调整驱动信号的大小，可以向不同子像素提供相同幅值的数据信号。
示例性地，在像素电路对应的子像素显示不同灰阶的情况下，由于第一电压端V1的第一电压为直流电压信号，因此，可以通过控制数据信号的电压V data，来改变驱动信号的大小，以使驱动信号的幅值维持在较高值范围内，提高待驱动元件L的发光效率，避免使用小电流幅值实现低灰阶显示的情况下待驱动元件L发光效率较低、功耗较高的问题，从而提高显示面板的显示效果。
在此情况下，驱动电路30向第二控制电路20输出驱动信号。例如，第二控制电路20中的第九晶体管T9的第一极接收驱动信号。
参考图5A和图5B，第一控制电路10中的第二输入子电路13响应于在第二控制信号端Q2处接收的第二控制信号，写入在第二输入信号端S2处接收的第二输入信号，及，响应于第二输入信号，将在第二使能信号端EM’处接收的第二使能信号传输至第二控制电路20。
参考图5A，第一控制电路10中的第一输入子电路11A响应于第一输入 信号，将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
参考图5B，第一控制电路10中的第一输入子电路11B响应于第一输入信号，向第二控制电路10传输第三输入信号，稳压子电路12响应于在第一使能信号端EM处接收的第一使能信号，将来自第一输入子电路11B的信号(即第三输入信号)传输至第二控制电路20。
例如，参考图6A至图6C，第二输入子电路13中的第七晶体管T7响应于在第二控制信号端Q2处接收的高电平的第二控制信号，第七晶体管T7截止，停止写入第二输入信号。
例如，参考图6A，第一输入子电路11A中的第一晶体管T1响应于在第一控制信号端Q1处接收的高电平的第一控制信号，第一晶体管T1截止，停止写入第一输入信号。
例如，参考图6B，稳压子电路12中的第六晶体管T6响应于第三控制信号端Q3处接收的高电平的第三控制信号(参考图11)，第六晶体管T6截止，停止将第二电压传输至第二控制电路20。
示例性地，在像素电路对应的子像素显示低灰阶的情况下，第一控制电路10中写入的第二输入信号为高电平信号，写入的第一输入信号为低电平信号。
例如，参考图6A至图6C，第二输入子电路13中的第三电容器C3存储高电平的第二输入信号，第二输入子电路13中的第八晶体管T8响应于高电平的第二输入信号，第八晶体管T8截止，不会将在第二使能信号端EM’处接收的第二使能信号传输至第二控制电路20。
例如，参考图6B，第一输入子电路11B中的第四晶体管T4响应于低电平的第一输入信号，第四晶体管T4导通，稳压子电路12中的第五晶体管T5响应于在第一使能信号端EM处接收的低电平的第一使能信号，第五晶体管T5导通，第四晶体管T4和第五晶体管T5将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
例如，参考图6A，第一输入子电路11A中的第一电容器C1存储低电平的第一输入信号，第二晶体管T2响应于低电平的第一输入信号，第二晶体管T2导通，将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
因此，在像素电路对应的子像素显示低灰阶的情况下，第一控制电路10将第三输入信号传输至第二控制电路20。在第三阶段，第三输入信号为高电 平和低电平交替的脉冲信号。在第三输入信号为低电平信号的情况下，第二控制电路20中的第九晶体管T9响应于来自第一控制电路10的低电平的第三输入信号，第九晶体管T9导通，驱动电路30与待驱动元件L形成导电通路，第二控制电路20将来自驱动电路30的驱动信号传输至待驱动元件L，驱动待驱动元件L工作。在第三输入信号为高电平信号的情况下，第二控制电路20中的第九晶体管T9响应于来自第一控制电路10的高电平的第三输入信号，第九晶体管T9截止，驱动电路30与待驱动元件L不形成导电通路，驱动信号不会传输至待驱动元件L，待驱动元件L不工作。在此情况下，待驱动元件L的工作状态和不工作状态交替进行，在待驱动元件L的工作状态为发光状态的情况下，待驱动元件L呈亮暗交替的发光状态。
因此，在像素电路对应的子像素显示低灰阶的情况下，第一控制电路将第三输入信号传输至第二控制电路，通过第三输入信号控制第二控制电路20导通的频率，以控制驱动电路30和待驱动元件L形成导电通路的频率，控制待驱动元件L接收到驱动信号的频率，使得待驱动元件间歇性地处于工作状态，从而控制待驱动元件L的工作时长，使得待驱动元件可以在较高幅值的驱动信号的驱动下也可以实现对应的灰阶显示，提高了待驱动元件的工作效率。并且待驱动元件的工作频率相对较高，可以避免人眼观看到闪烁，提高显示效果。
在像素的显示灰阶为中灰阶或高灰阶的情况下，写入的第二输入信号为低电平信号，写入的第一输入信号为高电平信号。
例如，参考图6A，第一输入子电路11A中的第一电容器C1存储高电平的第一输入信号，第二晶体管T2响应于高电平的第一输入信号，第二晶体管T2截止，不会将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
例如，参考图6B，第一输入子电路11B中的第一电容器C1存储高电平的第一输入信号，第四晶体管T4响应于高电平的第一输入信号，第四晶体管T4截止，稳压子电路12中的第五晶体管T5响应于在第一使能信号端EM处接收的低电平的第一使能信号，第五晶体管T5导通，不会将在第三输入信号端S3处接收的第三输入信号传输至第二控制电路20。
例如，参考图6A至图6C，第二输入子电路13中的第三电容器C3存储低电平的第二输入信号，第二输入子电路13中的第八晶体管T8响应于低电平的第二输入信号，第八晶体管T8导通，将在第二使能信号端EM’处接收的低电平的第二使能信号传输至第二控制电路20。第二控制电路20中的第九晶 体管T9响应于低电平的第二使能信号，第九晶体管T9导通，使得驱动电路30与待驱动元件L形成导电通路，此时，通过第二控制电路20，将来自驱动电路30的驱动信号传输至待驱动元件L，驱动待驱动元件L工作。
由于在第三阶段，第二使能信号为直流低电平信号，因此，第二控制电路20中的第九晶体管T9一直处于导通状态，来自驱动电路30的驱动信号可以一直传输至待驱动元件L，使得待驱动元件L一直工作。这样，在驱动信号为高电流信号的情况下，可以保证待驱动元件L的发光亮度。在像素电路所在子像素显示中高灰阶的情况下，第一控制电路将第二使能信号传输至第二控制电路，使得待驱动元件一直在较高幅值的驱动信号的驱动下工作，保证待驱动元件的工作效率。
在一些实施例中，如图13所示，显示面板100还包括多个级联的移位寄存电路RS。每个移位寄存电路与一行像素电路101的第三输入信号端S3耦接。示例性地，每个移位寄存电路RS通过一条输入信号线LS与一行像素电路101的第三输入信号端S3耦接。移位寄存电路RS被配置为向其所耦接的像素电路101的第三输入信号端S3传输第三输入信号。
示例性地，参考图6A中的像素电路101，由于第三输入信号为脉冲信号，在待驱动元件不工作阶段，第九晶体管T9的控制极的电压交替处于高电压和低电压，使得第九晶体管T9的第一极和驱动晶体管DT的第二极的电压浮动，会影响写入的数据信号的准确性。因此，对于一行像素电路，在第二控制电路20接收到来自第一控制电路10的第三输入信号的情况下，驱动电路的驱动控制子电路响应于第一使能信号处于截止状态，则第二控制电路响应于第三输入信号也处于截止状态，这样，可以避免第三输入信号对驱动电路的影响。
在此情况下，在待驱动元件不工作阶段，第三输入信号的时序与第一使能信号的时序相同。例如，参考图12，在待驱动元件的不工作阶段(图12中的第一阶段U1和第二阶段U2)，第一使能信号为高电平信号，第三输入信号也为高电平信号。
示例性地，多个级联的移位寄存电路可以将第三输入信号移位传输至对应的像素电路。例如，每行子像素中的各像素电路在第三输入信号端S3处接收的第三输入信号，随着每行子像素中的各像素电路在第一使能信号端EM处接收的第一使能信号逐行依次移位。例如，在显示面板具有n行子像素的情况下，n为正整数，参考图14，第一行像素电路接收到的第一使能信号EM(1)为高电平的情况下，第一行像素电路接收到的第三输入信号S3(1)也为高电平， 第二行像素电路接收到的第一使能信号EM(2)为高电平的情况下，第二行像素电路接收到的第三输入信号S3(2)也为高电平，依次类推，第n行像素电路接收到的第一使能信号EM(n)为高电平的情况下，第n行像素电路接收到的第三输入信号S3(n)也为高电平。
需要说明的是，可以根据实际情况选择移位寄存电路的具体电路结构，在此不作限定，能够实现上述功能的电路和器件均可作为本公开的实施例所述的移位寄存电路。
在一些实施例中，显示面板包括多个扫描驱动电路，多个扫描驱动电路为至少三个扫描驱动电路，至少三个扫描驱动电路包括第一扫描驱动电路、第二扫描驱动电路和第三扫描驱动电路。例如，每个扫描驱动电路包括多个级联的移位寄存电路。第一扫描驱动电路被配置为输出扫描信号，第二扫描驱动电路被配置为输出复位信号，第三扫描驱动电路被配置为输出使能信号，例如第一使能信号和第二使能信号。
在一些实施例中，多个扫描驱动电路为至少四个扫描驱动电路，至少四个扫描驱动电路包括：上述的第一扫描驱动电路、第二扫描驱动电路和第三扫描驱动电路、以及第四扫描驱动电路。其中，第四扫描驱动电路被配置为输出第三输入信号，例如，第四扫描驱动电路包括上述的多个级联的移位寄存电路RS。例如，不同扫描驱动电路中的移位寄存电路不完全相同；例如，第四扫描驱动电路中的移位寄存电路不同于第一扫描驱动电路、第二扫描驱动电路和第三扫描驱动电路中的移位寄存电路。
示例性地，第一扫描驱动电路、第二扫描驱动电路、第三扫描驱动电路和第四扫描驱动电路中的两个扫描驱动电路位于AA区外相对两侧中的一侧，其余的两个扫描驱动电路位于AA区外相对两侧中的另一侧。例如，AA区外相对两侧可以为沿像素电路排列的行方向上，AA区外相对的两侧。例如，第一扫描驱动电路、第二扫描驱动电路位于AA区外相对两侧中的一侧，第三扫描驱动电路和第四扫描驱动电路位于AA区外相对两侧中的另一侧。这样，显示面板中电路的分布较为均匀，使得显示面板的膜层厚度较为均一。
在一些实施例中，如图1所示，显示装置200还包括驱动芯片210。驱动芯片210与显示面板100耦接。驱动芯片210被配置为向显示面板100提供信号。例如驱动芯片为驱动IC(Integrated Circuit)。
例如，一个驱动芯片210可以向显示面板100提供数据信号；该一个驱动芯片210也可以向显示面板100提供第一输入信号、第二输入信号和第三输入信号。或者，显示装置200包括多个驱动芯片，多个驱动芯片分别向显 示面板提供数据信号、第一输入信号、第二输入信号和第三输入信号。
示例性地，在第三输入信号由驱动芯片提供的情况下，显示面板中的所有像素电路接收相同的第三输入信号，简化设计。
示例性地，在第三输入信号由移位寄存电路提供的情况下，显示面板中的所有像素电路接收的第三输入信号不同，例如，一行像素电路接收相同的第三输入信号。这样，根据像素电路的实际工作情况，调整第三输入信号的电压，例如，对于图6B中的像素电路，在其工作的第一阶段和第二阶段，第三输入信号不用保持高电平信号，可以降低功耗。
本公开的实施例提供一种像素电路的驱动方法。其中，像素电路包括：驱动电路、第一控制电路和第二控制电路。驱动电路至少与数据信号端、扫描信号端、第一电压端和第一使能信号端耦接。第一控制电路至少与第二使能信号端、第一控制信号端、第一输入信号端、第二控制信号端、第二输入信号端和第三输入信号端耦接。第二控制电路与驱动电路、第一控制电路和待驱动元件耦接。
其中，像素电路的驱动方法包括：
驱动电路响应于在扫描信号端处接收的扫描信号，写入在数据信号端处接收的数据信号，及，响应于在第一使能信号端处接收的第一使能信号，根据第一电压端的第一电压和写入的数据信号，生成驱动信号。
第一控制电路响应于在所述第一控制信号端处接收的第一控制信号，写入在第一输入信号端处接收的第一输入信号，响应于第一输入信号，传输在第三输入信号端处接收的第三输入信号；或者，第一控制电路响应于在第二控制信号端处接收的第二控制信号，写入在第二输入信号端处接收的第二输入信号，响应于第二输入信号，传输在第二使能信号端处接收的第二使能信号。
第二控制电路响应于并接收第三输入信号和第二使能信号中的其中一者，将来自驱动电路的驱动信号传输至待驱动元件，控制待驱动元件的工作时长。
其中，第三输入信号的频率大于第二使能信号的频率。
示例性地，在像素电路所在的子像素显示中高灰阶的情况下，第一控制电路将第三输入信号传输至第二控制电路，此时，例如第一输入信号为高电平信号，第二输入信号为低电平信号；在像素电路所在的子像素显示低灰阶的情况下，第一控制电路将第二使能信号传输至第二控制电路，此时，例如第一输入信号为低电平信号，第二输入信号为高电平信号。
上述的像素电路的驱动方法具有与上述的像素电路相同的有益效果，因此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种像素电路，包括：
    驱动电路，至少与数据信号端、扫描信号端、第一电压端和第一使能信号端耦接；所述驱动电路被配置为，响应于在所述扫描信号端处接收的扫描信号，写入在所述数据信号端处接收的数据信号，及，响应于在所述第一使能信号端处接收的第一使能信号，根据所述第一电压端的第一电压和写入的数据信号，生成驱动信号；
    第一控制电路，至少与第二使能信号端、第一控制信号端、第一输入信号端、第二控制信号端、第二输入信号端和第三输入信号端耦接；所述第一控制电路被配置为，响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，响应于所述第一输入信号，传输在所述第三输入信号端处接收的第三输入信号；或者所述第一控制电路被配置为响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号端处接收的第二输入信号，响应于所述第二输入信号，传输在所述第二使能信号端处接收的第二使能信号；和
    第二控制电路，与所述驱动电路、所述第一控制电路和待驱动元件耦接；所述第二控制电路被配置为，响应并接收所述第三输入信号和所述第二使能信号中的其中一者，将来自所述驱动电路的驱动信号传输至所述待驱动元件，控制所述待驱动元件的工作时长。
  2. 根据权利要求1所述的像素电路，其中，所述第一控制电路还与第三控制信号端、所述第一使能信号端和第二电压端耦接；
    所述第一控制电路还被配置为，响应于在所述第三控制信号端处接收的第三控制信号，将所述第二电压端的第二电压传输至所述第二控制电路；所述第一控制电路还被配置为，响应于在所述第一使能信号端处接收的第一使能信号和所述第一输入信号，将所述第三输入信号传输至所述第二控制电路。
  3. 根据权利要求1或2所述的像素电路，其中，所述第一控制电路包括：
    第一输入子电路，与所述第一控制信号端、所述第一输入信号端和所述第三输入信号端耦接；
    所述第一输入子电路被配置为，响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，及，响应于所述第一输入信号，向所述第二控制电路传输在所述第三输入信号端处接收的第三输入信号。
  4. 根据权利要求3所述的像素电路，其中，所述第一输入子电路还与所 述第二控制电路耦接；所述第一输入子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述第一输入信号端耦接；
    第二晶体管，所述第二晶体管的控制极与所述第一晶体管的第二极耦接，所述第二晶体管的第一极与所述第三输入信号端耦接，所述第二晶体管的第二极与所述第二控制电路耦接；和
    第一电容器，所述第一电容器与所述第一晶体管的第二极耦接。
  5. 根据权利要求3所述的像素电路，其中，所述第一控制电路还包括：
    稳压子电路，与所述第一使能信号端、所述第一输入子电路、所述第二控制电路、第三控制信号端和第二电压端耦接；
    所述稳压子电路被配置为，响应于在所述第三控制信号端处接收的第三控制信号，将所述第二电压端的第二电压传输至所述第二控制电路；及，响应于在所述第一使能信号端处接收的第一使能信号，将来自所述第一输入子电路的信号传输至所述第二控制电路。
  6. 根据权利要求5所述的像素电路，其中，所述第一输入子电路包括：
    第三晶体管，所述第三晶体管的控制极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述第一输入信号端耦接；
    第四晶体管，所述第四晶体管的控制极与所述第三晶体管的第二极耦接，所述第四晶体管的第一极与所述第三输入信号端耦接，所述第四晶体管的第二极与所述稳压子电路耦接；和
    第二电容器，所述第二电容器与所述第三晶体管的第二极耦接；
    所述稳压子电路包括：
    第五晶体管，所述第五晶体管的控制极与所述第一使能信号端耦接，所述第五晶体管的第一极与所述第一输入子电路耦接，所述第五晶体管的第二极与所述第二控制电路耦接；和
    第六晶体管，所述第六晶体管的控制极与所述第三控制信号端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述第二控制电路耦接。
  7. 根据权利要求1～6中任一项所述的像素电路，其中，所述第一控制电路还包括：
    第二输入子电路，与所述第二控制信号端、所述第二输入信号端、所述第二使能信号端和所述第二控制电路；所述第二输入子电路被配置为，响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号 端处接收的第二输入信号，及，响应于所述第二输入信号，将在所述第二使能信号端处接收的第二使能信号传输至所述第二控制电路。
  8. 根据权利要求7所述的像素电路，其中，所述第二输入子电路包括：
    第七晶体管，所述第七晶体管的控制极与所述第二控制信号端耦接，所述第七晶体管的第一极与所述第二输入信号端耦接；
    第八晶体管，所述第八晶体管的控制极与所述第七晶体管的第二极耦接，所述第八晶体管的第一极与所述第二使能信号端耦接，所述第八晶体管的第二极与所述第二控制电路耦接；和
    第三电容器，所述第三电容器与所述第七晶体管的第二极耦接。
  9. 根据权利要求1～8中任一项所述的像素电路，其中，所述第二控制电路包括：
    第九晶体管；所述第九晶体管的控制极与所述第一控制电路耦接，所述第九晶体管的第一极与所述驱动电路耦接，所述第九晶体管的第二极与所述待驱动元件耦接。
  10. 根据权利要求1～9中任一项所述的像素电路，其中，所述驱动电路还包括：
    驱动子电路，所述驱动子电路包括驱动晶体管和第四电容器，所述第四电容器的第一端与所述第一电压端耦接，所述第四电容器的第二端与所述驱动晶体管的控制极耦接；
    驱动控制子电路，至少与所述第一使能信号端、所述第一电压端、所述驱动子电路耦接；所述驱动控制子电路被配置为，响应于在所述第一使能信号端处接收的第一使能信号，使所述第一电压端和所述第二控制电路通过所述驱动子电路中的驱动晶体管形成导电通路；
    所述驱动子电路被配置为，根据写入的数据信号和所述第一电压端的第一电压，生成所述驱动信号；
    数据写入子电路，与所述扫描信号端、所述数据信号端和所述驱动子电路耦接；所述数据写入子电路被配置为响应于在所述扫描信号端处接收的扫描信号，将在所述数据信号端处接收的数据信号写入所述驱动子电路；和
    补偿子电路，与所述扫描信号端、所述驱动晶体管的控制极和所述驱动晶体管的第二极耦接；所述补偿子电路被配置为，响应于在所述扫描信号端处接收的扫描信号，将所述数据信号和所述驱动晶体管的阈值电压写入所述驱动晶体管的控制极。
  11. 根据权利要求10所述的像素电路，其中，所述驱动控制子电路包括：
    第十晶体管，所述第十晶体管的控制极与所述第一使能信号端耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述驱动晶体管的第一极耦接；
    其中，所述驱动晶体管的第二极与所述第二控制电路耦接。
  12. 根据权利要求10所述的像素电路，其中，所述驱动控制子电路包括：
    第十晶体管，所述第十晶体管的控制极与所述第一使能信号端耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述驱动晶体管的第一极耦接；和
    第十一晶体管，所述第十一晶体管的控制极与所述第一使能信号端耦接，所述第十一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第十一晶体管的第二极与所述第二控制电路耦接。
  13. 根据权利要求10～12中任一项所述的像素电路，其中，所述数据写入子电路包括：
    第十二晶体管，所述第十二晶体管的控制极与所述扫描信号端耦接，所述第十二晶体管的第一极与所述数据信号端耦接，所述第十二晶体管的第二极与所述驱动晶体管的第一极耦接；
    和/或，
    所述补偿子电路包括：
    第十三晶体管，所述第十三晶体管的控制极与所述扫描信号端耦接，所述第十三晶体管的第一极与所述驱动晶体管的第二极耦接，所述第十三晶体管的第二极与所述驱动晶体管的控制极耦接。
  14. 根据权利要求10～13中任一项所述的像素电路，其中，所述驱动电路还包括：
    复位子电路，与所述驱动子电路、所述待驱动元件、复位信号端和初始信号端耦接；所述复位子电路被配置为，响应于在所述复位信号端处接收的复位信号，将在所述初始信号端处接收的初始信号传输至所述驱动子电路和所述待驱动元件。
  15. 根据权利要求14所述的像素电路，其中，所述复位子电路包括：
    第十四晶体管，所述第十四晶体管的控制极与所述复位信号端耦接，所述第十四晶体管的第一极与所述初始信号端耦接，所述第十四晶体管的第二极与所述驱动晶体管的控制极耦接；和
    第十五晶体管，所述第十五晶体管的控制极与所述复位信号端耦接，所述第十五晶体管的第一极与所述初始信号端耦接，所述第十五晶体管的第二 极与所述待驱动元件耦接。
  16. 根据权利要求14或15所述的像素电路，其中，所述第一控制信号端与所述复位信号端为同一信号端，所述第二控制信号端与所述扫描信号端为同一信号端，所述第一输入信号端与所述第二输入信号端为同一信号端；
    或者，
    所述第一控制信号端与所述第二控制信号端同为所述复位信号端，或者同为所述扫描信号端，所述第一输入信号端与所述第二输入信号端为不同信号端。
  17. 一种显示面板，包括：
    如权利要求1～16中任一项所述的像素电路；和
    待驱动元件，所述待驱动元件与所述像素电路耦接。
  18. 根据权利要求17所述的显示面板，还包括：多条第一信号线和多条第二信号线；
    一行像素电路的第一控制信号端和第二控制信号端分别与同一条第一信号线耦接，一列像素电路的第一输入信号端和第二输入信号端分别与两条第二信号线耦接；
    或者，一行像素电路的第一控制信号端和第二控制信号端分别与两条第一信号线耦接，一列像素电路的第一输入信号端和第二输入信号端分别与同一条第二信号线耦接。
  19. 根据权利要求17或18所述的显示面板，还包括：
    多个级联的移位寄存电路，每个移位寄存电路与一行像素电路的第三输入信号端耦接；所述移位寄存电路被配置为向其所耦接的像素电路的第三输入信号端传输第三输入信号。
  20. 一种显示装置，包括：
    如权利要求17～19中任一项所述的显示面板；
    驱动芯片，与所述显示面板耦接；所述驱动芯片被配置为向所述显示面板提供信号。
  21. 一种像素电路的驱动方法，其中，所述像素电路包括：驱动电路、第一控制电路和第二控制电路；所述驱动电路至少与数据信号端、扫描信号端、第一电压端和第一使能信号端耦接；所述第一控制电路至少与第二使能信号端、第一控制信号端、第一输入信号端、第二控制信号端、第二输入信号端和第三输入信号端耦接；所述第二控制电路与所述驱动电路、所述第一控制电路和待驱动元件耦接；
    所述驱动方法包括：
    所述驱动电路响应于在所述扫描信号端处接收的扫描信号，写入在所述数据信号端处接收的数据信号，及，响应于在所述第一使能信号端处接收的第一使能信号，根据所述第一电压端的第一电压和写入的数据信号，生成驱动信号；
    所述第一控制电路响应于在所述第一控制信号端处接收的第一控制信号，写入在所述第一输入信号端处接收的第一输入信号，响应于所述第一输入信号，传输在所述第三输入信号端处接收的第三输入信号；或者所述第一控制电路响应于在所述第二控制信号端处接收的第二控制信号，写入在所述第二输入信号端处接收的第二输入信号，响应于所述第二输入信号，传输在所述第二使能信号端处接收的第二使能信号；
    所述第二控制电路响应并接收所述第三输入信号和所述第二使能信号中的其中一者，将来自所述驱动电路的驱动信号传输至所述待驱动元件，控制所述待驱动元件的工作时长；
    其中，所述第三输入信号的频率大于所述第二使能信号的频率。
PCT/CN2020/126034 2020-11-03 2020-11-03 像素电路及驱动方法、显示面板、显示装置 WO2022094738A1 (zh)

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