WO2023092346A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2023092346A1
WO2023092346A1 PCT/CN2021/132874 CN2021132874W WO2023092346A1 WO 2023092346 A1 WO2023092346 A1 WO 2023092346A1 CN 2021132874 W CN2021132874 W CN 2021132874W WO 2023092346 A1 WO2023092346 A1 WO 2023092346A1
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Prior art keywords
electrically connected
signal
data
sub
transistor
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Application number
PCT/CN2021/132874
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English (en)
French (fr)
Inventor
肖丽
韩承佑
刘冬妮
郑皓亮
玄明花
赵蛟
陈亮
崔晓荣
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21965084.3A priority Critical patent/EP4350677A1/en
Priority to CN202180003550.7A priority patent/CN116868262A/zh
Priority to PCT/CN2021/132874 priority patent/WO2023092346A1/zh
Priority to TW111143532A priority patent/TWI846144B/zh
Publication of WO2023092346A1 publication Critical patent/WO2023092346A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a driving method thereof, and a display device.
  • the display market is currently booming, and more new displays will emerge in the future as consumer demand continues to increase for a wide variety of display products such as laptops, smartphones, TVs, tablets, smart watches, and fitness wristbands product.
  • a display substrate is provided.
  • a plurality of data lines extending along a first direction on the display substrate; and a plurality of sub-pixels.
  • the sub-pixel includes a pixel driving circuit and a light emitter.
  • the pixel driving circuit includes: a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light emitting device.
  • the current control circuit is configured to generate a driving signal to drive the light emitting device to emit light;
  • the duration control circuit is configured to generate a duration control signal to control the current control circuit and the light emitting device on-time.
  • the current control circuit and the duration control circuit are electrically connected to the same data line.
  • the plurality of sub-pixels are arranged in multiple columns in the second direction.
  • the same data line is electrically connected to at least one column of sub-pixels.
  • At least one column of sub-pixels is arranged between any two adjacent data lines.
  • the display substrate further includes: a multiple output selection circuit electrically connected to the multiple data lines; multiple data transmission lines electrically connected to the multiple output selection circuit; and, connected to the multiple output selection circuit Multiple selection signal lines electrically connected to the multiple output selection circuit.
  • the multiple output selection circuit is configured to, under the control of the selection signals transmitted by the multiple selection signal lines, time-divisionally transmit the data signals transmitted by the multiple data transmission lines to the multiple data lines.
  • the plurality of data lines at least includes: a plurality of first data lines, a plurality of second data lines and a plurality of third data lines.
  • the multiple data transmission lines at least include: multiple first data transmission lines, multiple second data transmission lines and multiple third data transmission lines.
  • the multiple output selection circuit includes: a plurality of selection transistor groups; the selection transistor groups are electrically connected to the selection signal line, the first data line, the second data line and the third data line.
  • the first data transmission line is electrically connected to at least two selection transistor groups, and is electrically connected to the corresponding first data line through the at least two selection transistor groups.
  • the second data transmission line is electrically connected to the at least two selection transistor groups, and is electrically connected to the corresponding second data line through the at least two selection transistor groups.
  • the third data transmission line is electrically connected to the at least two selection transistor groups, and is electrically connected to the corresponding third data line through the at least two selection transistor groups.
  • the first data transmission line, the second data transmission line and the third data transmission line are arranged periodically. And/or, the first data lines, the second data lines and the third data lines are arranged periodically.
  • the selection transistor group at least includes: a first selection transistor, a second selection transistor and a third selection transistor.
  • the control electrode of the first selection transistor is electrically connected to the selection signal line, the first electrode of the first selection transistor is electrically connected to the first data transmission line, and the second electrode of the first selection transistor is electrically connected to the selection signal line.
  • the first data line is electrically connected.
  • the control electrode of the second selection transistor is electrically connected to the selection signal line, the first electrode of the second selection transistor is electrically connected to the second data transmission line, and the second electrode of the second selection transistor is electrically connected to the selection signal line.
  • the second data line is electrically connected.
  • the control electrode of the third selection transistor is electrically connected to the selection signal line
  • the first electrode of the third selection transistor is electrically connected to the third data transmission line
  • the second electrode of the third selection transistor is electrically connected to the selection signal line.
  • the third data line is electrically connected.
  • the same data line is electrically connected to a column of sub-pixels.
  • the same data line is electrically connected to at least two columns of sub-pixels.
  • the display substrate further includes: a plurality of gate lines extending along the first direction; one sub-pixel is electrically connected to one gate line. Wherein, the plurality of sub-pixels are arranged in multiple rows along the second direction; a row of sub-pixels is electrically connected to at least two gate lines.
  • the at least two gate lines are configured to respectively transmit scan signals to corresponding sub-pixels, so as to control the row of sub-pixels to time-divisionally receive the data signals transmitted by the data lines.
  • the number of columns of sub-pixels electrically connected to the same data line is equal to the number of gate lines electrically connected to sub-pixels of the same row.
  • the at least two gate lines are respectively arranged on opposite sides of the row of sub-pixels.
  • any two adjacent sub-pixels are respectively electrically connected to different gate lines.
  • the display substrate further includes: a substrate; the plurality of data lines and the plurality of sub-pixels are arranged on one side of the substrate; and, a plurality of subpixels arranged on the edge of the substrate Connect the wiring.
  • One end of the connection wiring is electrically connected to at least one of the data lines, and the other end of the connection wiring extends to the other side of the substrate.
  • the display substrate further includes a multiple output selection circuit and multiple data transmission lines
  • one end of the connection wiring is electrically connected to the data transmission line, and is electrically connected to multiple data lines through the multiple output selection circuit .
  • the current control circuit is at least electrically connected to the scan signal terminal, the data signal terminal, the first enable signal terminal, the first voltage signal terminal and the first node; the current control circuit is configured to respond to The scan signal received at the scan signal terminal, the data signal received at the data signal terminal, the first enable signal received at the first enable signal terminal, and the first voltage signal received at the first enable signal terminal A first voltage signal received at the terminal generates a drive signal.
  • the duration control circuit is at least connected to the data signal terminal, the first reset signal terminal, the second reset signal terminal, the first enabling signal terminal, the second enabling signal terminal, the first node and the light emitting
  • the devices are electrically connected; the duration control circuit is configured to, in response to the data signal and the first reset signal received at the first reset signal end, according to the first reset signal received at the second enable signal end
  • Two enable signals control the conduction duration between the first node and the light emitting device; or, in response to the data signal and the second reset signal received at the second reset signal terminal, according to the
  • the first enabling signal controls the conduction duration between the first node and the light emitting device.
  • both the current control circuit and the duration control circuit are electrically connected to the data line through the data signal terminal.
  • the active levels of the first reset signal and the second reset signal do not coincide with each other.
  • one of a level corresponding to the active level of the first reset signal and a level corresponding to the active level of the second reset signal is an active level.
  • the time when the level of the data signal transitions to an active level is earlier than the time when the level of the scan signal transitions to an active level.
  • the duration control circuit includes: a first control subcircuit, a second control subcircuit and a third control subcircuit.
  • the first control sub-circuit is at least electrically connected to the data signal terminal, the first reset signal terminal, the second enable signal terminal and the second node.
  • the first control subcircuit is configured to transmit the second enable signal to the second node in response to the data signal and the first reset signal.
  • the second control subcircuit is at least electrically connected to the data signal terminal, the second reset signal terminal, the first enable signal terminal and the second node.
  • the second control subcircuit is configured to transmit the first enable signal to the second node in response to the data signal and the second reset signal.
  • the third control sub-circuit is electrically connected to the first node, the second node and the light emitting device.
  • the third control subcircuit is configured to, under the control of the signal from the second node, control the conduction duration between the first node and the light emitting device.
  • the first control sub-circuit includes: a first transistor, a second transistor and a first capacitor.
  • the control electrode of the first transistor is electrically connected to the first reset signal end, the first electrode of the first transistor is electrically connected to the data signal end, and the second electrode of the first transistor is electrically connected to the third node electrical connection.
  • the control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second enable signal terminal, and the second electrode of the second transistor is electrically connected to the The second node is electrically connected.
  • the first pole of the first capacitor is electrically connected to the initial signal terminal, and the second pole of the first capacitor is electrically connected to the third node.
  • the second control sub-circuit includes: a third transistor, a fourth transistor and a second capacitor.
  • the control electrode of the third transistor is electrically connected to the second reset signal end, the first electrode of the third transistor is electrically connected to the data signal end, and the second electrode of the third transistor is electrically connected to the fourth node electrical connection.
  • the control pole of the fourth transistor is electrically connected to the fourth node, the first pole of the fourth transistor is electrically connected to the first enable signal terminal, and the second pole of the fourth transistor is electrically connected to the The second node is electrically connected.
  • a first pole of the second capacitor is electrically connected to the initial signal terminal, and a second pole of the second capacitor is electrically connected to the fourth node.
  • the third control sub-circuit includes: a fifth transistor.
  • the control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the light emitting device. connect.
  • the current control circuit includes: a data writing subcircuit, a driving subcircuit, a compensation subcircuit, and a light emission control subcircuit.
  • the data writing sub-circuit is electrically connected to the scanning signal terminal, the data signal terminal and the fifth node; the data writing sub-circuit is configured to, under the control of the scanning signal, transmit the data signal to the fifth node.
  • the driving subcircuit is at least electrically connected to the first node, the fifth node, and the sixth node; the driving subcircuit is configured to, under the control of the voltage of the sixth node, The signal of the node is transmitted to the first node.
  • the compensation subcircuit is electrically connected to the scanning signal terminal, the first node, and the sixth node; the compensation subcircuit is configured to, under the control of the scanning signal, The signal is transmitted to the sixth node to compensate the threshold voltage of the driving sub-circuit.
  • the light emission control subcircuit is electrically connected to the first enable signal terminal, the first voltage signal end and the fifth node; the light emission control subcircuit is configured to, under the control of the first enable signal Next, the first voltage signal is transmitted to the fifth node.
  • the data writing sub-circuit includes: a sixth transistor.
  • the control electrode of the sixth transistor is electrically connected to the scan signal end, the first electrode of the sixth transistor is electrically connected to the data signal end, and the second electrode of the sixth transistor is electrically connected to the fifth node. electrical connection.
  • the driving sub-circuit includes: a seventh transistor and a third capacitor.
  • the control electrode of the seventh transistor is electrically connected to the sixth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the first node electrical connection.
  • a first pole of the third capacitor is electrically connected to the sixth node, and a second pole of the third capacitor is electrically connected to the first voltage signal terminal.
  • the compensation sub-circuit includes: an eighth transistor.
  • the control electrode of the eighth transistor is electrically connected to the scanning signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the sixth node. electrical connection.
  • the light emission control sub-circuit includes: a ninth transistor. The control pole of the ninth transistor is electrically connected to the first enable signal terminal, the first pole of the ninth transistor is electrically connected to the first voltage signal terminal, and the second pole of the ninth transistor is electrically connected to the first voltage signal terminal. The fifth node is electrically connected.
  • the current control circuit further includes: a reset subcircuit.
  • the reset subcircuit is electrically connected to the first reset signal terminal, the initial signal terminal, the sixth node and the light emitting device; the reset subcircuit is configured to, in response to the first reset signal, set The initial signal received at the initial signal terminal is transmitted to the sixth node and the light emitting device.
  • the reset subcircuit includes: a tenth transistor and an eleventh transistor.
  • the control pole of the tenth transistor is electrically connected to the first reset signal terminal, the first pole of the tenth transistor is electrically connected to the initial signal terminal, and the second pole of the tenth transistor is electrically connected to the first reset signal terminal.
  • Six nodes are electrically connected.
  • the control pole of the eleventh transistor is electrically connected to the first reset signal terminal, the first pole of the eleventh transistor is electrically connected to the initial signal terminal, and the second pole of the eleventh transistor is electrically connected to the initial signal terminal.
  • the light emitting devices are electrically connected.
  • a method for driving a display substrate is provided.
  • the driving method is used to drive the display substrate described in any one of the above embodiments.
  • the driving method includes: transmitting data signals to multiple data lines of the display substrate, and the current control circuit and the duration control circuit of the same sub-pixel receive the data signals at the same time.
  • the current control circuit includes a data writing subcircuit, a driving subcircuit, a compensation subcircuit, and a light emission control subcircuit
  • the duration control circuit includes a first control subcircuit, a second control subcircuit, and a second control subcircuit.
  • the driving method further includes: a first stage, a second stage, a third stage and a fourth stage.
  • the first control subcircuit in response to the first reset signal received at the first reset signal terminal and the data signal , the first control subcircuit is turned off; in the second phase, in response to the second reset signal and the data signal received at the second reset signal terminal, the second control subcircuit is turned on, and the The first enable signal received at the first enable signal terminal is transmitted to the second node.
  • the first control subcircuit in the first stage, in response to the first reset signal and the data signal, the first control subcircuit conducts through, and transmit the second enable signal received at the second enable signal terminal to the second node; in the second stage, in response to the second reset signal and the data signal, the first The second control sub-circuit is turned off.
  • the data writing sub-circuit and the compensation sub-circuit are turned on, and the data signal is sequentially passed through the fifth node, the The driving sub-circuit, the first node and the compensation sub-circuit are transmitted to the sixth node to perform threshold voltage compensation for the driving sub-circuit.
  • the light emission control subcircuit in response to the first enabling signal, the light emission control subcircuit is turned on, and the first voltage signal received at the first voltage signal terminal passes through the fifth node and the driving subcircuit sequentially. circuit for transmission to the first node.
  • the data line is configured to store the data signal.
  • the scan signal terminal is configured to transmit the scan signal after the data line stores the data signal in the third stage, so as to control the conduction of the data writing sub-circuit and the compensation sub-circuit Pass.
  • a display device in yet another aspect, includes: at least one display substrate as described in any one of the above embodiments.
  • the display substrate includes a substrate and a plurality of connection wirings arranged on the edge of the substrate; one end of the plurality of connection wirings is located on one side of the substrate, and the plurality of connection wirings The other end of the connection wiring extends to the other side of the substrate.
  • the display device further includes: a driving chip disposed on the other side of the substrate. The driver chip is electrically connected to the other end of the plurality of connecting wires.
  • FIG. 1 is a structural diagram of a display substrate according to an implementation manner
  • FIG. 2 is a timing diagram corresponding to the display substrate shown in FIG. 1 according to an implementation
  • FIG. 3 is another timing diagram corresponding to the display substrate shown in FIG. 1 according to another implementation
  • FIG. 4 is another timing diagram corresponding to the display substrate shown in FIG. 1 according to another implementation
  • Fig. 5 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • Fig. 6 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 8 is a distribution diagram of a pad and a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 9 is a distribution diagram of another pad and pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a timing diagram corresponding to the sub-pixel shown in FIG. 7 according to some embodiments of the present disclosure.
  • FIG. 11 is another timing diagram corresponding to the sub-pixel shown in FIG. 7 according to some embodiments of the present disclosure.
  • Fig. 12 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 13 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • FIG. 14 is a timing diagram corresponding to the display substrate shown in FIG. 13 according to some embodiments of the present disclosure.
  • FIG. 15 is another timing diagram corresponding to the display substrate shown in FIG. 13 according to some embodiments of the present disclosure.
  • Fig. 16 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 17 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • FIG. 18 is a timing diagram corresponding to the display substrate shown in FIG. 17 according to some embodiments of the present disclosure.
  • Fig. 19 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 20 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 21 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Fig. 22 is a structural diagram of another display device according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used. For example, the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that " or “if [the stated condition or event] is detected” are optionally construed to mean “when determining ! or “in response to determining ! depending on the context Or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the gate of each transistor employed in each circuit is the gate of the transistor, the first is one of the source and drain of the transistor, and the second is the other of the source and drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, there may be no structural difference between the source and the drain, that is to say, the first and second electrodes of the transistor in the embodiments of the present disclosure
  • the two poles may be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first pole of the transistor is the source
  • the second pole is the drain
  • the second pole is the source.
  • nodes do not represent actual components, but represent the confluence points of relevant electrical connections in the circuit diagram, that is, these nodes are confluence points of relevant electrical connections in the circuit diagram, etc. Nodes that are made effective.
  • the transistors included in each circuit provided in the embodiments of the present disclosure may be all N-type transistors, or all may be P-type transistors. Alternatively, some of the transistors included in each circuit may be N-type transistors, and the other part may be P-type transistors.
  • active level refers to a level at which a transistor can be turned on.
  • the circuits provided in the embodiments of the present disclosure will be described by taking the transistors as P-type transistors (at this time, the active level is low level) as an example. It should be noted that the transistors in the circuits mentioned below adopt the same conduction type, which can simplify the process flow, reduce process difficulty, and improve the yield of products (such as the display substrate 100 and the display device 1000 ).
  • Some embodiments of the present disclosure provide a display substrate 100 , a method for driving the display substrate, and a display device 1000 , and the display substrate 100 , a method for driving the display substrate, and the display device 1000 are respectively introduced below.
  • the display device 1000 may be any device that displays images, whether moving (eg, video) or stationary (eg, still images), and whether text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Cameras GPS Receivers/Navigators
  • Cameras GPS
  • the above display device 1000 may include: at least one display substrate 100 . That is, the display device 1000 may include one display substrate 100 , or may include multiple display substrates 100 .
  • the display device 1000 when the display device 1000 includes a plurality of display substrates 100 , the plurality of display substrates 100 can be spliced together so that the display device 1000 can have a larger screen size.
  • the above-mentioned display substrate 100 may be called a spliced display substrate
  • the above-mentioned display device 1000 may be called a spliced display device.
  • the above display device 1000 may further include, for example: a driver chip 200 and other electronic accessories.
  • the driver chip 200 may include, but not limited to: a source driver circuit for providing data signals or a power supply circuit for providing first voltage signals.
  • the display substrate 100 may include: a substrate 1 , a plurality of sub-pixels 2 , a plurality of data lines DL and a plurality of gate lines GL.
  • the substrate 1 may be a rigid substrate.
  • the material of the rigid substrate may include glass, quartz or plastic, for example.
  • the substrate 1 may be a flexible substrate.
  • the material of this flexible substrate can comprise PET (Polyethylene terephthalate, polyethylene terephthalate), PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) or PI (Polyimide, polyethylene glycol ester) for example. imide), etc.
  • the plurality of sub-pixels 2 , the plurality of data lines DL and the plurality of gate lines GL are all disposed on one side of the substrate 1 .
  • the plurality of data lines DL may extend along the first direction Y
  • the plurality of gate lines GL may extend along the second direction X.
  • Each sub-pixel 2 is electrically connected to one data line DL and one gate line GL.
  • the plurality of sub-pixels 2 may be arranged in multiple columns along the second direction X and in multiple rows along the first direction Y. Wherein, the number of sub-pixels 2 included in any two adjacent columns of sub-pixels may or may not be equal; the number of sub-pixels 2 included in any two adjacent rows of sub-pixels may or may not be equal.
  • first direction Y and the second direction X cross each other.
  • the included angle between the first direction Y and the second direction X can be selected and set according to actual needs.
  • the included angle between the first direction Y and the second direction X may be 85°, 88°, 90°, 92° or 95° and so on.
  • the above-mentioned plurality of sub-pixels 2 may include sub-pixels of various colors.
  • the plurality of sub-pixels 2 may include: red sub-pixels, green sub-pixels and blue sub-pixels.
  • the plurality of sub-pixels 2 may also include, for example: white sub-pixels.
  • the three sub-pixels can be arranged in horizontal parallel, vertical parallel or square font.
  • the four sub-pixels can be arranged horizontally, vertically, or in an array. No limit.
  • each sub-pixel 2 may include a pixel driving circuit 21 and a light emitting device 22 electrically connected to the pixel driving circuit 21 .
  • the pixel driving circuit 21 can provide a driving signal to the light emitting device 22 to drive the light emitting device 22 to emit light.
  • the light emitting device 22 may emit light of different colors according to the color type of the sub-pixel.
  • the light-emitting device 22 in the red sub-pixel can emit red light
  • the light-emitting device 22 in the green sub-pixel can emit green light
  • the light-emitting device 22 in the blue sub-pixel can emit blue light
  • the light-emitting device 22 in the white sub-pixel can emit blue light. Can emit white light.
  • the light emitting devices 22 in the red sub-pixel, the green sub-pixel, the blue sub-pixel and the white sub-pixel can all emit blue light.
  • the red sub-pixel, green sub-pixel and white sub-pixel can convert blue light into red light, green light and white light by cooperating with color transfer materials (such as quantum dots, phosphors, etc.) Corresponding colors of green, blue and white emit light.
  • the arrangement manner of the above-mentioned sub-pixels 2 may refer to the arrangement manner of the light emitting devices 22 .
  • the above-mentioned light emitting device 22 is a current-type driving element.
  • the light emitting device 22 can be selected and set according to actual needs.
  • the above-mentioned light emitting device 22 may be: Micro Light Emitting Diodes (Micro LED for short), Mini Light Emitting Diodes (Mini LED for short), or Light Emitting Diodes (LED for short), etc.
  • the brightness displayed by the light-emitting device 22 is related to the current amplitude of the driving signal (ie, the current signal) and the duration of the received driving signal.
  • the duration of the driving signal received by the light-emitting device 22 is a constant value
  • the greater the current amplitude of the driving signal the greater the brightness displayed by the light-emitting device 22, and the smaller the current amplitude of the driving signal
  • the brightness exhibited by the light emitting device 22 is smaller.
  • the current amplitude of the driving signal received by the light-emitting device 22 is a constant value, the longer the duration of the driving signal it receives, the greater the brightness it presents, and the shorter the duration of the driving signal it receives. Then the brightness presented is smaller.
  • the above-mentioned light-emitting device 22 is prone to drift in color coordinates and low external quantum efficiency, which in turn causes the display substrate 100
  • the phenomenon of poor brightness uniformity occurs, that is to say, it is difficult to accurately display low gray scales only by controlling the magnitude of the current amplitude of the driving signal. Therefore, on the basis of controlling the current amplitude of the driving signal, the time length of the driving signal provided to the light emitting device 22 can be controlled to realize accurate low gray scale display.
  • the pixel driving circuit 21 may include: a current control circuit 211 , and a duration control circuit 212 electrically connected to the current control circuit 211 and the light emitting device 22 .
  • the current control circuit 211 is configured to generate a driving signal to drive the light emitting device 22 to emit light.
  • the duration control circuit 212 is configured to generate a duration control signal to control the conduction duration between the current control circuit 211 and the light emitting device 22 .
  • the above-mentioned current control circuit 211 can generate a driving signal, and the light emitting device 22 can emit light under the action of the driving signal.
  • the current amplitude of the driving signal is variable, and correspondingly, the brightness of the light emitted by the light emitting device 22 is also variable.
  • the light emitting device 22 can display different gray scales.
  • the duration control circuit 212 is disposed between the current control circuit 211 and the light emitting device 22 .
  • the duration control circuit 212 can control whether the current control circuit 211 and the light emitting device 22 are connected. That is, when the duration control circuit 212 does not generate a duration control signal, the current control circuit 211 and the light-emitting device 22 are disconnected and not conducted. Even if the current control circuit 211 generates a driving signal, the driving signal is difficult to apply to the light-emitting device. twenty two.
  • the duration control signal generated by the duration control circuit 212 can control the conduction duration between the current control circuit 211 and the light emitting device 22 . That is, when the level of the duration control signal is an active level, the current control circuit 211 and the light emitting device 22 can be electrically connected to each other to form a path; when the level of the duration control signal is an inactive level Next, the current control circuit 211 and the light emitting device 22 are disconnected.
  • the duty ratio of the duration control signal is variable, that is, the duration during which the level of the duration control signal is an active level is variable.
  • the conduction duration between the current control circuit 211 and the light-emitting device 22 can be adjusted, and then the light-emitting duration of the light-emitting device 22 can be adjusted, so that the light-emitting device 22 displays different gray scales.
  • the present disclosure can use the time length control signal generated by the time length control circuit 212 to control the time length of the driving signal transmitted to the light emitting device 22, jointly Controlling the brightness displayed by the light-emitting device 22 is beneficial to improving the brightness uniformity of the display substrate 100 and improving the display effect of the display substrate 100 .
  • the higher current amplitude range of the driving signal may be within the range where the light emitting device 22 operates with high and stable luminous efficiency, good uniformity of color coordinates and stable dominant wavelength of light. Therefore, no matter whether the gray scale displayed by the light emitting device 22 is a higher gray scale or a lower gray scale, the current amplitude range of the driving signal may be the same.
  • the data signal terminals electrically connected to the pixel driving circuit in the sub-pixel include two types, that is, the current data signal terminal electrically connected to the current control circuit, and the current data signal terminal electrically connected to the duration control circuit. Electrically connected duration data signal end; the current control circuit can control the current amplitude of the driving signal according to the current data line number transmitted by the current data signal end, and the duration control circuit can select according to the duration data signal transmitted by the duration data signal end The duty cycle of the duration control signal.
  • the data lines included in the display substrate may include: a current data line DI electrically connected to a current data signal terminal, and a duration data line DT electrically connected to a time data signal terminal.
  • the i-th current data line DI i and the i-th time length data line DT i are respectively located on opposite sides of the i-th column of sub-pixels, and two data lines are arranged between the i-th column of sub-pixels and the i+1-th column of sub-pixels .
  • the two data lines can be, for example: the i-th time-length data line DT i and the i+1-th current data line DI i+1 , or the i-th current data line DI i and the i+1-th time-length data line DT i+1 . Both n and i are positive integers.
  • the current data signal in the i+1th current data line DI i+1 will jump due to the level change of the duration data signal, which will cause a certain subpixel in the i+1th column of subpixels to
  • the driving signal generated by the current control circuit in the current control circuit changes, which in turn leads to a change in the luminance displayed by a certain sub-pixel in the i+1th column of sub-pixels, and a bad phenomenon of column-wise brightness difference occurs.
  • the level of the duration data signal written to the i-th duration data line DT i changes from a high level to a low level, correspondingly, the current in the i+1th current data line DI i+1
  • the level of the data signal will be pulled down, causing the current amplitude of the driving signal generated by the current control circuit of a sub-pixel in the i+1th column of sub-pixels to increase, which in turn will cause a certain sub-pixel in the i+1th column to
  • the brightness displayed by the pixels becomes larger, and there is a bad phenomenon of column-to-brightness difference.
  • the current control circuit 211 and the duration control circuit 212 are electrically connected to the same data line DL.
  • the current control circuit 211 and the duration control circuit 212 electrically connected to the same data line DL belong to the pixel driving circuit 21 of the same sub-pixel 2 .
  • the same sub-pixel 2 is electrically connected to the same data line DL, and the data signal transmitted by the same data line DL can be transmitted to the current control circuit 211 and the duration control circuit 212 at the same time.
  • the present disclosure can write the active level of the data signal to the current control circuit 211 and duration control circuit 212 .
  • the active level of the data signal written into the current control circuit 211 may be referred to as a first active level
  • the active level of the data signal written into the duration control circuit 212 may be referred to as a second active level.
  • the data signal with the second active level can be written into the duration control circuit 212 first, so that the duration control circuit 212 generates a duration control signal (the duty cycle of the duration control signal is based on the sub-pixel 2 required gray scale displayed), and then the data signal with the first effective level can be written into the current control circuit 211, so that the current control circuit 211 generates a driving signal (the current amplitude of the driving signal depends on the sub-pixel 2 required depends on the displayed gray scale).
  • the effective level of the data signal is time-divisionally written into the current control circuit 211 and the duration control circuit 212, so that the current control circuit 211 can
  • the corresponding write-in and compensation stages and the stage corresponding to the duration control circuit 212 for generating the duration control signal are separated and do not overlap, and the level of the data signal basically does not change in each stage.
  • signal crosstalk between two adjacent data lines DL can be effectively avoided, and the level of the data signal written into the current control circuit 211 caused by the change of the level of the data signal written into the duration control circuit 212 can be avoided.
  • the jump occurs, which in turn helps to improve the poor phenomenon of column-wise brightness and darkness differences.
  • the display substrate 100 by electrically connecting the current control circuit 211 and the duration control circuit 212 included in the pixel driving circuit 21 in the same sub-pixel 2 to the same data line DL, it can The active level of the data signal is written into the current control circuit 211 and the duration control circuit 212 in time division.
  • the phase in which the current control circuit 211 generates the driving signal and the phase in which the duration control circuit 212 generates the duration control signal do not overlap, which is conducive to ensuring the stability of the data signal in each phase and avoiding signal crosstalk between two adjacent data lines DL.
  • this can effectively reduce the number of data lines DL, reduce the space occupied by the data lines DL, and increase the wiring space of the display substrate 100 .
  • the current control circuit 211 is at least connected to the scan signal terminal Gate, the data signal terminal Data, the first enable signal terminal EM, the first voltage signal terminal VDD and the first node N1 electrical connection. Wherein, the current control circuit 211 is configured to respond to the scan signal received at the scan signal terminal Gate, the data signal received at the data signal terminal Data, the first enable signal received at the first enable signal terminal EM and the first voltage signal received at the first voltage signal terminal VDD to generate a driving signal.
  • the duration control circuit 212 is at least electrically connected to the data signal terminal Data, the first reset signal terminal Res_A, the second reset signal terminal Res_B, the first enable signal terminal EM, the second enable signal terminal Hf, the first node N1 and the light emitting device 22. connect.
  • the duration control circuit 212 is configured to, in response to the data signal and the first reset signal received at the first reset signal terminal Res_A, control the first The conduction duration between the node N1 and the light emitting device 22; or, in response to the data signal and the second reset signal received at the second reset signal terminal Res_B, according to the first enable signal, control the first node N1 and the light emitting device The conduction time between devices 22 . That is, the duration control signal is the first enabling signal or the second enabling signal.
  • the anode of the light emitting device 22 is electrically connected to the first node N1
  • the cathode of the light emitting device 22 is electrically connected to the second voltage signal terminal VSS.
  • the first voltage signal terminal VDD is configured to transmit a DC high-level signal, which is referred to herein as a first voltage signal.
  • the second voltage signal terminal VSS is configured to transmit a DC low-level signal, which is referred to as a second voltage signal herein.
  • the "high level” and “low level” in this article are relative terms, and therefore do not limit the magnitude of the voltage value.
  • the second enabling signal transmitted by the second enabling signal terminal Hf is a high-frequency pulse signal.
  • the second enable signal includes a plurality of pulses.
  • the frequency of the second enabling signal is greater than the frequency of the first enabling signal.
  • the number of time periods in which an active level appears in the second enabling signal is greater than the number of time periods in which an active level appears in the first enabling signal.
  • the second enabling signal may be simultaneously transmitted to a plurality of sub-pixels 2 included in the display substrate 100 .
  • the frequency of the second enable signal can be divided according to the number of sub-pixel rows included in the display substrate 100 .
  • the frame frequency of the display substrate 100 is 60 Hz, that is, within a time period of 1 second, the display substrate 100 can display 60 frames of images, and the display duration of each frame of images is equal. In each display period of a frame, for example, every 4th or 5th row of sub-pixel refresh time, an active level appears once in the second enable signal.
  • the conduction frequency between the current control circuit 211 and the light emitting device 22 can be controlled, and by controlling the duty ratio of the duration control signal, the conduction frequency between the current control circuit 211 and the light emitting device 22 can be controlled. of conduction time.
  • the conduction frequency between the control current control circuit 211 and the light-emitting device 22 and the conduction duration of each conduction determine the total duration of the light-emitting device 22 emitting light (that is, multiple conduction the sum of the duration of communication).
  • the duration control circuit 212 may use the first enable signal as a duration control signal, so that in the light emitting phase, the current control circuit 211 and the light emitting device 22 It is always in the conduction state, and a conductive path is always formed between the pixel driving circuit 21 and the light emitting device 22 . At this time, the driving signal generated by the current control circuit 211 can be continuously transmitted to the light-emitting device 22 , so as to realize higher gray scale display.
  • the duration control circuit 212 may use the second enable signal as the duration control signal, so that in the light emitting phase, the current control circuit 211 and the light emitting device 22 are connected at the first Under the control of the high-frequency pulse signal of the second enable signal, it is in an alternate state of on and off.
  • the driving signal generated by the current control circuit 211 may be intermittently transmitted to the light emitting device 22, so that the light emitting device 22 receives the driving signal periodically. For example, the light emitting device 22 stops for a period of time after receiving the driving signal for a period of time, and stops for a period of time after receiving the driving signal for a period of time.
  • the time for forming a conductive path between the pixel driving circuit 21 and the light-emitting device 22 is shortened, the time for the driving signal to be transmitted to the light-emitting device 22 is shortened, and the total time for the light-emitting device 22 to emit light is shortened, thereby realizing a display with a lower gray scale .
  • the current control circuit 211 and the duration control circuit 212 in the same sub-pixel 2 are both electrically connected to the same data line DL through the data signal terminal Data. That is, both the current control circuit 211 and the duration control circuit 212 are electrically connected to the same data signal terminal Data, and are electrically connected to the same data line DL through the data signal terminal Data.
  • the data signal transmitted by the data line DL can be simultaneously transmitted to the current control circuit 211 and the duration control circuit 212 through the data signal terminal Data.
  • a multi-output selection circuit 4' is provided, and the multi-output selection circuit 4' is respectively connected to a plurality of current data lines DI, a plurality of duration data lines DT, a first The current selection signal line DI_MUX 1 , the second current selection signal line DI_MUX 2 , the first duration selection signal line DT_MUX 1 and the second duration selection signal line DT_MUX 2 are electrically connected.
  • the multi-channel output selection circuit 4' transmits the current data signal to the current data line DI in time division under the control of the first current selection signal and the second current selection signal, and can select the signal between the first duration and the second duration. Under the control of the selection signal, the duration data signal is transmitted to the duration data line DT.
  • DI_MUX 2 represents the second current selection signal
  • DT_MUX 1 represents the first duration selection signal
  • Gate represents the scanning signal received by sub-pixels in the nth row
  • DT i (below the threshold gray scale) represents the first
  • DT i (higher than the threshold grayscale) means that the sub-pixel in the i-th column of the nth row has a display grayscale greater than the threshold grayscale
  • DI i+1 represents the current data signal received by the sub-pixel in the nth row and the i+1th column.
  • both the current control circuit and the duration control circuit are electrically connected to the scanning signal terminal. It can be seen from Figure 2 that for two adjacent subpixels in the same row of subpixels, the writing and compensation phase corresponding to the current control circuit of one subpixel, and the duration control of the other subpixel The phases corresponding to the circuits for generating the duration control signals overlap.
  • the scan signal is at an active level (i.e. low level)
  • the voltage of the second current selection signal level becomes inactive level, so that the i+1th current data line DI i+1 is in a floating state.
  • the duration data signal is written into the i-th duration data line DT i along with the first duration selection signal.
  • the level of the duration data signal will jump from high level to low level, and correspondingly, the i+1th current
  • the level of the current data signal in the data line DI i+1 will be pulled down, which will cause the brightness of the sub-pixels in the nth row and the i+1th column to increase, resulting in poor brightness and darkness differences in the column direction.
  • the current control circuit 211 is electrically connected to the scanning signal terminal Gate
  • the duration control circuit 212 is electrically connected to other signal terminals
  • the current control circuit 211 and the duration control circuit 212 are both connected to the same data line DL.
  • the electrical connection can ensure the writing and compensation phase corresponding to the current control circuit 211 of a certain sub-pixel 2 while writing the effective level of the data signal in time-division, and ensure the phase of writing and compensation corresponding to the current control circuit 211 of a certain sub-pixel 2, and the current control circuit 211 corresponding to another sub-pixel 2 (the sub-pixel 2
  • the stages of generating the duration control signal by the duration control circuit 212 located in the same row and adjacent to the above-mentioned certain sub-pixel 2 do not overlap. In this way, signal crosstalk between two adjacent data lines DL can be further avoided, and the level of the data signal written into the duration control circuit 212 of a certain sub-pixel 2 changes, resulting in writing to another sub-pixel 2.
  • the level of the data signal of the current control circuit 211 of the pixel 2 jumps, it is further beneficial to improve the phenomenon of the difference between brightness and darkness in the column direction.
  • the active levels of the first reset signal and the second reset signal do not overlap in time.
  • one of a level corresponding to the active level of the first reset signal and a level corresponding to the active level of the second reset signal is an active level.
  • the level of the data signal when the level of the first reset signal is an active level, the level of the data signal may be an active level or an inactive level.
  • the level of the second reset signal when the level of the second reset signal is an active level, the level of the data signal may be an active level or an inactive level.
  • the level of the data signal is reversed between the period when the level of the first reset signal is an active level and the period when the level of the second reset signal is an active level.
  • the relationship among the active levels of the first reset signal, the second reset signal and the data signal may include two types.
  • One of the relationships is: when the level of the first reset signal is an active level, the level of the data signal is an active level, and when the level of the second reset signal is an active level, the level of the data signal is Level is inactive level.
  • Another relationship is: when the level of the first reset signal is an active level, the level of the data signal is an inactive level, and when the level of the second reset signal is an active level, the level of the data signal is The level is the active level.
  • the present disclosure does not limit the order of the phases in which the level of the first reset signal is an active level and the phase in which the level of the second reset signal is an active level, which can be selected and set according to actual needs.
  • the duration control circuit 212 For the same sub-pixel 2, by setting the first reset signal, the second reset signal and the data signal in the above-mentioned setting method, it is possible to make the duration control circuit 212 only in the common phase of the data signal and the first reset signal at the stage of generating the duration control signal. Under the control, the second enable signal is used as the duration control signal, or only under the common control of the data signal and the second reset signal, the first enable signal is used as the duration control signal. This helps ensure the working performance of the duration control circuit 212, ensures that the duration control circuit 212 can only select one of the first enable signal and the second enable signal as the duration control signal, improves the stability of signal selection, and then improves the stability of the signal selection. Controllability of the gray scale displayed by the light emitting device 22 .
  • the duration control circuit 212 includes: a first control subcircuit 2121 , a second control subcircuit 2122 and a third control subcircuit 2123 .
  • the first control subcircuit 2121 is at least electrically connected to the data signal terminal Data, the first reset signal terminal Res_A, the second enable signal terminal Hf and the second node N2. Wherein, the first control sub-circuit 2121 is configured to transmit the second enabling signal to the second node N2 in response to the data signal and the first reset signal.
  • the first control subcircuit 2121 may, under the control of the data signal and the first reset signal, set The second enable signal is transmitted to the second node N2 as a duration control signal.
  • the second control subcircuit 2122 is at least electrically connected to the data signal terminal Data, the second reset signal terminal Res_B, the first enable signal terminal EM and the second node N2. Wherein, the second control sub-circuit 2122 is configured to transmit the first enable signal to the second node N2 in response to the data signal and the second reset signal.
  • the second control subcircuit 2122 may, under the control of the data signal and the second reset signal, set The first enabling signal is transmitted to the second node N2 as a duration control signal.
  • the third control subcircuit 2123 is electrically connected to the first node N1 , the second node N2 and the light emitting device 22 . Wherein, the third control sub-circuit 2123 is configured to control the conduction duration between the first node N1 and the light emitting device 22 under the control of the signal from the second node N2.
  • the third control subcircuit 2123 may, under the control of the second enable signal, transfer the first node N1 and Conduction between light emitting devices 22 .
  • the second enabling signal is a high-frequency pulse signal
  • the first node N1 and the light-emitting device 22 will be in an alternate on and off state
  • the conduction period between the first node N1 and the light-emitting device 22 is The total duration depends on the multiple conduction states.
  • the third control subcircuit 2123 may, under the control of the first enable signal, conduction between. Wherein, in the light-emitting phase, the first node N1 and the light-emitting device 22 may always be connected.
  • the first control sub-circuit 2121 and the second control sub-circuit 2122 can be made One of them is working, and then the selection of the duration control signal can be realized, avoiding the situation that the first control sub-circuit 2121 and the second control sub-circuit 2122 work at the same time, resulting in abnormal gray scale displayed by the light emitting device 22 .
  • the current control circuit 211 includes: a data writing subcircuit 2111 , a driving subcircuit 2112 , a compensation subcircuit 2113 and a light emission control subcircuit 2114 .
  • the data writing sub-circuit 2111 is electrically connected to the scan signal terminal Gate, the data signal terminal Data and the fifth node N5. Wherein, the data writing sub-circuit 2111 is configured to transmit the data signal to the fifth node N5 under the control of the scan signal.
  • the data writing sub-circuit 2111 may be turned on under the control of the scan signal, and receive and transmit the data signal to the fifth node N5.
  • the driving sub-circuit 2112 is at least electrically connected to the first node N1 , the fifth node N5 and the sixth node N6 . Wherein, the driving sub-circuit 2112 is configured to transmit the signal from the fifth node N5 to the first node N1 under the control of the voltage of the sixth node N6.
  • the signal from the fifth node N5 may be a data signal transmitted by the data writing sub-circuit 2111 .
  • the driving sub-circuit 2112 can be turned on under the control of the voltage of the sixth node N6 to transmit the signal from the fifth node N5 to the first node N1.
  • the compensation sub-circuit 2113 is electrically connected to the scan signal terminal Gate, the first node N1 and the sixth node N6. Wherein, the compensation sub-circuit 2113 is configured to transmit the signal from the first node N1 to the sixth node N6 under the control of the scanning signal, so as to compensate the threshold voltage of the driving sub-circuit 2112 .
  • the signal from the first node N1 may be a data signal transmitted by the data writing sub-circuit 2111 .
  • the compensation sub-circuit 2113 can be turned on under the control of the scan signal, and transmit the signal from the first node N1 to the sixth node N6, so as to perform the driving sub-circuit 2112 threshold voltage compensation.
  • the data writing sub-circuit 2111 and the compensation sub-circuit 2113 are electrically connected to the scanning signal terminal Gate, the data writing sub-circuit 2111 and the compensation sub-circuit 2113 can be turned on simultaneously under the control of the scanning signal.
  • the data signal transmitted by the data signal terminal Data can be sequentially transmitted to the sixth node N6 through the data writing sub-circuit 2111, the driving sub-circuit 2112, and the compensation sub-circuit 2113, until the driving sub-circuit 2112 is cut off, and the driving sub-circuit 2112 is completed. threshold voltage compensation.
  • the light emission control subcircuit 2114 is electrically connected to the first enable signal terminal EM, the first voltage signal terminal VDD and the fifth node N5. Wherein, the light emission control sub-circuit 2114 is configured to transmit the first voltage signal to the fifth node N5 under the control of the first enable signal.
  • the lighting control subcircuit 2114 can be turned on under the control of the first enabling signal, and receive and transmit the first voltage signal to the fifth node N5.
  • the driving sub-circuit 2112 may be based on the first voltage signal from the fifth node N5 and the voltage written to the sixth node N6.
  • the data signal generates a driving signal and transmits the driving signal to the light emitting device 22 to drive the light emitting device 22 to emit light.
  • the data signal is time-divisionally written into the current control circuit 211 and the duration control circuit 212, and the data writing sub-circuit 2111 is electrically connected to the scan signal terminal Gate, the first control sub-circuit 2121 is electrically connected to the first reset signal terminal Res_A, the second The second control sub-circuit 2122 is electrically connected to the second reset signal terminal Res_B, therefore, the active level time of the scanning signal does not coincide with the active level time of the first reset signal and the second reset signal.
  • the stage of threshold voltage compensation for the driving sub-circuit 2112 and the stage of selecting the duration control signal by the first control sub-circuit 2121 and the second control sub-circuit 2122 do not overlap, which is conducive to avoiding two adjacent data lines DL Signal crosstalk occurs between them, avoiding the situation that the level of the data signal written to the driving sub-circuit 2112 jumps due to the change in the level of the data signal written to the duration control circuit 212, which is conducive to improving the column Towards the poor phenomenon of difference between light and dark.
  • the current control circuit 211 further includes: a reset sub-circuit 2115 .
  • the reset subcircuit 2115 is electrically connected to the first reset signal terminal Res_A, the initial signal terminal Vinit, the sixth node N6 and the light emitting device 22 .
  • the reset sub-circuit 2115 is configured to transmit the initial signal received at the initial signal terminal Vinit to the sixth node N6 and the light emitting device 22 in response to the first reset signal.
  • the reset sub-circuit 2115 is electrically connected to the anode of the light emitting device 22 .
  • the initial signal transmitted by the initial signal terminal Vinit may be a DC low-level signal.
  • the reset subcircuit 2115 can be turned on under the control of the first reset signal, receive and transmit the initial signal to the sixth node N6 and the light emitting device The anode of the light emitting device 22 resets the sixth node N6 and the anode of the light emitting device 22 .
  • a reference voltage can be provided for the sixth node N6 and the anode of the light emitting device 22 , to eliminate the charge remaining in the display process of the previous frame, and improve the controllability of the pixel driving circuit 21 .
  • each sub-circuit included in the current control circuit 211 and the sub-circuit included in the duration control circuit 212 is schematically described, of course, each sub-circuit included in the current control circuit 211 and the duration control circuit 212
  • the structures of the included sub-circuits are not limited thereto.
  • the first control sub-circuit 2121 includes: a first transistor T1 , a second transistor T2 and a first capacitor C1 .
  • control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Res_A
  • first electrode of the first transistor T1 is electrically connected to the data signal terminal Data
  • second electrode of the first transistor T1 pole is electrically connected to the third node N3.
  • the first transistor T1 may be turned on under the control of the first reset signal to receive and transmit the data signal to the third node N3.
  • control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the second enable signal terminal Hf, and the first electrode of the second transistor T2 is electrically connected to the second enabling signal terminal Hf.
  • the diodes are electrically connected to the second node N2.
  • the voltage of the third node N3 depends on the level of the data signal.
  • the level of the data signal transmitted to the third node N3 is low level
  • the voltage of the third node N3 is low level
  • the second transistor T2 can be turned on under the control of the level of the third node N3 is turned on, the second enable signal is received and transmitted to the second node N2 as a duration control signal.
  • the first pole of the first capacitor C1 is electrically connected to the initial signal terminal Vinit, and the second pole of the first capacitor C1 is electrically connected to the third node N3.
  • the first capacitor C1 has a storage function and can store the data signal transmitted to the third node N3.
  • the level of the above-mentioned data signal is an inactive level (that is, a high level)
  • the voltage of the third node N3 is a high level
  • the second transistor T2 may be at the voltage of the third node N3 shut down under control.
  • the first transistor T1 is turned off, the first capacitor C1 can be discharged, so that the voltage of the third node N3 is maintained at a high level, and thus the second transistor T2 is kept in an off state.
  • the second transistor T2 can be turned on under the control of the voltage of the third node N3.
  • the first capacitor C1 can be discharged, so that the voltage of the third node N3 is maintained at a low level, and then the second transistor T2 is kept in a conductive state, and the second enabling signal is continuously transmitted to the The second node N2.
  • the second control subcircuit 2122 includes: a third transistor T3 , a fourth transistor T4 and a second capacitor C2 .
  • control electrode of the third transistor T3 is electrically connected to the second reset signal terminal Res_B
  • first electrode of the third transistor T3 is electrically connected to the data signal terminal Data
  • second electrode of the third transistor T3 pole is electrically connected to the fourth node N4.
  • the third transistor T3 may be turned on under the control of the second reset signal to receive and transmit the data signal to the fourth node N4.
  • control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected to the first enable signal terminal EM, and the first electrode of the fourth transistor T4 The diodes are electrically connected to the second node N2.
  • the voltage of the fourth node N4 depends on the level of the data signal.
  • the level of the data signal transmitted to the fourth node N4 is low level
  • the voltage of the fourth node N4 is low level
  • the fourth transistor T4 can be turned on under the control of the level of the fourth node N4. pass, receive and transmit the first enabling signal as a duration control signal to the second node N2.
  • the first pole of the second capacitor C2 is electrically connected to the initial signal terminal Vinit, and the second pole of the second capacitor C2 is electrically connected to the fourth node N4.
  • the second capacitor C2 has a storage function and can store the data signal transmitted to the fourth node N4.
  • the fourth transistor T4 can be turned off under the control of the voltage of the fourth node N4.
  • the second capacitor C2 can be discharged, so that the voltage of the fourth node N4 is maintained at a high level, and then the fourth transistor T4 is kept in an off state.
  • the fourth transistor T4 when the level of the data signal is low level, the voltage of the fourth node N4 is low level, and the fourth transistor T4 can be turned on under the control of the voltage of the fourth node N4. After the third transistor T3 is turned off, the second capacitor C2 can be discharged, so that the voltage of the fourth node N4 is maintained at a low level, so that the fourth transistor T4 is kept in an on state, and continuously transmits the first enable signal to The second node N2.
  • only the second transistor T2 can be turned on and the second enable The signal is transmitted to the second node N2 as a duration control signal, or only the fourth transistor T4 is turned on, and the first enabling signal is transmitted to the second node N2 as a duration control signal, so that the selection of the duration control signal can be realized, Avoid the situation that the second transistor T2 and the fourth transistor T4 are turned on at the same time, resulting in abnormal gray scale displayed by the light emitting device 22 .
  • the third control sub-circuit 2123 includes: a fifth transistor T5.
  • control electrode of the fifth transistor T5 is electrically connected to the second node N2
  • first electrode of the fifth transistor T5 is electrically connected to the first node N1
  • second electrode of the fifth transistor T5 is electrically connected to the first node N1.
  • the light emitting device 22 is electrically connected.
  • the fifth transistor T5 can be controlled by the second enabling signal Next, turn on and turn off alternately, so that the first node N1 and the light emitting device 22 will be in a state of being on and off alternately.
  • the fifth transistor T5 can be kept in a continuous conduction state under the control of the first enable signal, so that the first node N1 It can always be connected with the light emitting device 22 .
  • the data writing sub-circuit 2111 includes: a sixth transistor T6.
  • control electrode of the sixth transistor T6 is electrically connected to the scan signal terminal Gate
  • first electrode of the sixth transistor T6 is electrically connected to the data signal terminal Date
  • second electrode of the sixth transistor T6 is electrically connected to the data signal terminal Date.
  • the fifth node N5 is electrically connected.
  • the sixth transistor T6 may be turned on under the control of the scan signal, and receive and transmit the data signal to the fifth node N5.
  • the driving subcircuit 2112 includes: a seventh transistor T7 and a third capacitor C3.
  • control electrode of the seventh transistor T7 is electrically connected to the sixth node N6, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.
  • the first node N1 is electrically connected.
  • the seventh transistor T7 may be turned on under the control of the voltage of the sixth node N6 to transmit the data signal from the fifth node N5 to the first node N1.
  • the first pole of the third capacitor C3 is electrically connected to the sixth node N6
  • the second pole of the third capacitor C3 is electrically connected to the first voltage signal terminal VDD.
  • the third capacitor C3 has a storage function, can store the signal transmitted to the sixth node N6, and can discharge to maintain the level of the sixth node N6.
  • the compensation subcircuit 2113 includes: an eighth transistor T8.
  • control electrode of the eighth transistor T8 is electrically connected to the scanning signal terminal Gate
  • first electrode of the eighth transistor T8 is electrically connected to the first node N1
  • second electrode of the eighth transistor T8 is electrically connected to the first node N1.
  • the sixth node N6 is electrically connected.
  • the eighth transistor T8 can be turned on under the control of the scanning signal, and transmit the data signal from the first node N1 to the sixth node N6, until the seventh transistor T8 T7 is turned off, and the compensation for the threshold voltage of the seventh transistor T7 is completed.
  • the third capacitor C3 can be discharged to maintain the voltage of the sixth node N6.
  • the light emission control subcircuit 2114 includes: a ninth transistor T9.
  • control electrode of the ninth transistor T9 is electrically connected to the first enable signal terminal EM
  • first electrode of the ninth transistor T9 is electrically connected to the first voltage signal terminal VDD
  • ninth transistor T9 The second pole of is electrically connected to the fifth node N5.
  • the ninth transistor T9 may be turned on under the control of the first enable signal, and receive and transmit the first voltage signal to the fifth node N5.
  • the reset subcircuit 2115 includes: a tenth transistor T10 and an eleventh transistor T11 .
  • the control electrode of the tenth transistor T10 is electrically connected to the first reset signal terminal Res_A
  • the first electrode of the tenth transistor T10 is electrically connected to the initial signal terminal Vinit
  • the second electrode of the tenth transistor T10 pole is electrically connected to the sixth node N6.
  • the control pole of the eleventh transistor T11 is electrically connected to the first reset signal terminal Res_A
  • the first pole of the eleventh transistor T11 is electrically connected to the initial signal terminal Vinit
  • the second pole of the eleventh transistor T11 is electrically connected to the light emitting device 22 .
  • the tenth transistor T10 and the eleventh transistor T11 can be turned on simultaneously under the control of the first reset signal, and the tenth transistor T10 can receive and transmit the initial The signal is sent to the sixth node N6 to reset the sixth node N6; the eleventh transistor T11 can receive and transmit the initial signal to the light emitting device 22 to reset the light emitting device 22 .
  • the display substrate 100 may further include: a plurality of pads P disposed on the side of the pixel driving circuit 21 away from the substrate 1 .
  • the plurality of pads P includes a plurality of anode pads P1 and a plurality of cathode pads P2, and one anode pad P1 and one cathode pad P2 may constitute a pad pair.
  • one pixel driving circuit 21 may correspond to at least one pad pair.
  • the display substrate 100 may further include: a plurality of second voltage signal lines.
  • the anode pad P1 can be electrically connected with one end of the reset sub-circuit 2115 and the third control sub-circuit 2123 in a pixel driving circuit 21, and receive the initial signal transmitted by the reset sub-circuit 2115 and the first terminal of the third control sub-circuit 2123.
  • Three control the driving signal transmitted by the sub-circuit 2123; the cathode pad P2 can be electrically connected to a second voltage signal line to receive the second voltage signal transmitted by the second voltage signal line.
  • the cathode pad P2 can serve as the second voltage signal terminal VSS, for example.
  • one pixel driving circuit 21 corresponds to one pad pair
  • the plurality of sub-pixels 2 included in the display substrate 100 include red sub-pixels, green sub-pixels and blue sub-pixels.
  • one red sub-pixel, one green sub-pixel and one blue sub-pixel may constitute a pixel unit (as shown by the dotted line box in FIG. 8 and FIG. 9 ), for example.
  • the light emitting device 22 electrically connected to the pixel driving circuit 21 may include an anode electrode pin and a cathode electrode pin.
  • the anode electrode pin can be bound to the anode pad P1 in the pad pair to realize electrical connection with the reset sub-circuit 2115 and the third control sub-circuit 2123, and the cathode electrode pin can be connected to the pad The cathode pad P2 in the pair is bound to realize the electrical connection with the second voltage signal terminal VSS.
  • the above-mentioned orthographic projections of the plurality of pads P on the substrate 1 do not overlap with the orthographic projections of the seventh transistor T7 in each pixel driving circuit 21 on the substrate 1. .
  • adverse effects on the seventh transistor T7 can be avoided, ensuring better driving performance of the seventh transistor T7.
  • the structure types of the light emitting device 22 include various types, which can be selected and set according to actual needs.
  • the structure type of the light emitting device 22 may be a front-mount structure, a vertical structure or a flip-chip structure.
  • the pad pairs which can meet the spacing requirements between the pixel units (macroscopically visible pixel units are composed of light-emitting devices in the pixel units) (the spacing requirements here are, for example, It refers to the distance between visible pixel units macroscopically) and the binding ability between the light emitting device 22 and the pair of pads.
  • each pad pair is the same as the arrangement of the light emitting devices 22 in each sub-pixel.
  • each pixel unit the light emitting devices 22 are arranged in a square shape.
  • the pairs of pads corresponding to each pixel unit may be arranged in a character-shaped manner.
  • the center of each pad pair forms a triangle (for example, an acute triangle). This is beneficial to ensure that there is a relatively large distance between any two adjacent pairs of pads, so that there is a relatively large distance between any two adjacent light-emitting devices 22, which can not only meet the requirements for the distance between the pixel units, but also can The difficulty of binding the light emitting device 22 is reduced.
  • each pixel unit the light emitting devices 22 are arranged horizontally in parallel.
  • the pairs of pads corresponding to each pixel unit may be arranged horizontally in parallel.
  • the pixel driving circuit 21 is closer to the first gap area GA1; among the sub-pixels of the 2N-th row and the 2N+1-th row of sub-pixels, the pixel driving circuit 21 is farther away from The second gap area GA2.
  • N is a positive integer.
  • each pixel driving circuit 21 is arranged symmetrically with respect to the first gap area GA1, and each pixel driving circuit 21 is closer to the first gap area GA1, and each pad pair is closer to the first gap area GA1. away from the first gap area GA1.
  • each pixel driving circuit 21 is arranged symmetrically with respect to the first gap area GA2, and each pixel driving circuit 21 is farther away from the second gap area GA2, and each pad pair is closer to the first gap area GA2.
  • the size of the second gap area GA2 is larger than the size of the first gap area GA1 .
  • the distribution uniformity of each pixel unit can be improved on the premise of satisfying the spacing requirement between each pixel unit, the compact arrangement of the pixel driving circuit 21 can be realized, and the wiring space can be effectively used.
  • the distance between any two adjacent pixel units is equal. In the same row of pixel units, the distance between any adjacent pixel units is equal.
  • this example only limits the positions of the pixel driving circuit and pad pairs in each sub-pixel, and does not limit whether the specific structure of the pixel driving circuit 21 is symmetrical. Since the pixel driving circuit 21 includes multiple film layers, in the process of preparing the multiple film layers, there may be differences in the dimensions of the film layers included in different pixel driving circuits 21 due to unavoidable reasons such as process errors.
  • the pixel driving circuit 21 in the sub-pixels in the 2N-1 row and the pixel driving circuit 21 in the sub-pixels in the 2N-th row cannot be arranged strictly symmetrically with respect to the first gap area GA1, and the pixels in the sub-pixels in the 2N-th row cannot
  • the driving circuit 21 and the pixel driving circuit 21 in the sub-pixels in the 2N+1th row are arranged strictly symmetrically with respect to the second gap area GA2.
  • the same data line DL is electrically connected to at least one column of sub-pixels.
  • one data line DL may be electrically connected to a column of sub-pixels, that is, there is a one-to-one correspondence between the two.
  • the number of data lines DL is equal to the number of columns of sub-pixels. At this time, the data signal transmitted by each data line DL is only written into a corresponding column of sub-pixels.
  • one data line DL may be electrically connected to multiple columns of sub-pixels.
  • the number of data lines DL is less than the number of columns of sub-pixels.
  • the data signals transmitted by each data line DL can be time-divisionally written into corresponding columns of sub-pixels.
  • At least one column of sub-pixels is arranged between any two adjacent data lines DL.
  • a column of sub-pixels is arranged between any two adjacent data lines DL.
  • each data line DL may be electrically connected to a column of sub-pixels.
  • each data line DL may be electrically connected to multiple columns of sub-pixels.
  • any two adjacent data lines DL can be separated by using the at least one column of sub-pixels. This not only helps to reduce the space occupied by the data lines DL in the display substrate 100, reduces the difficulty of wiring, but also avoids signal crosstalk between two adjacent data lines DL, and is conducive to ensuring the data transmitted by each data line DL. signal accuracy.
  • the display substrate 100 further includes: a plurality of connecting wires 3 arranged on the edge of the substrate 1 .
  • the multiple sub-pixels 2 included in the display substrate 100 may be arranged on one side of the substrate 1
  • the driving chip 200 included in the display device 1000 may be arranged on the other side of the substrate 1 .
  • each connection wire 3 may be U-shaped.
  • One end of the connection wiring 3 can be located on one side of the substrate 1, and is electrically connected to at least one data line DL (for example, including a direct electrical connection or an indirect electrical connection), and the other end of the connection wiring 3 can extend to the side of the substrate 1.
  • the other side As shown in FIG. 22 , the other end of the connecting wire 3 may be electrically connected to the driver chip 200 .
  • the driving chip 200 can, for example, provide a data signal to the connection wiring 3 , and the connection wiring 3 can transmit the data signal to the corresponding data line DL.
  • the above arrangement manner may be referred to as a side routing manner.
  • the electrical connection between the sub-pixels 2 and the driving chip 200 is facilitated by reducing the size of the frame of the display substrate 100 and realizing a narrow frame or even a frameless design by using side wiring.
  • the size of the splicing seam can be effectively reduced, and even splicing without splicing can be realized. This in turn facilitates the realization of narrow bezels or even bezel-less designs.
  • the display substrate 100 provided by the present disclosure has a relatively small number of data lines DL, the number of connection wiring 3 can be correspondingly reduced, which in turn helps to improve the process yield of side wiring, and improves the display substrate 100 and display device. 1000's yield.
  • the number of connecting wires 3 can be further reduced, which is conducive to further improving the process yield of side wiring, and further improving the display substrate 100 and display device 1000. yield rate.
  • the display substrate 100 further includes: a multi-output selection circuit 4 , multiple data transmission lines DTL and multiple selection signal lines Mux.
  • the above multiple output selection circuit 4 and the sub-pixel 2 may be located on the same side of the substrate 1 .
  • the multiplex output selection circuit 4 may be electrically connected to a plurality of data lines DL included in the display substrate 100 .
  • the above multiple data transmission lines DTL may be located on the same side of the substrate 1 as the sub-pixels 2 .
  • the plurality of data transmission lines DTL may extend along the first direction Y, and be electrically connected to the above-mentioned multiple output selection circuit 4 .
  • a part of each data transmission line DTL may extend along the first direction Y, and another part may extend along the second direction X.
  • the above multiple selection signal lines Mux may be located on the same side of the substrate 1 as the sub-pixels 2 .
  • the plurality of selection signal lines Mux may extend along the second direction X, and be electrically connected to the above-mentioned multi-output selection circuit 4 .
  • a part of each selection signal line Mux may extend along the first direction Y, and another part may extend along the second direction X.
  • the multiple output selection circuit 4 is configured to, under the control of the selection signals transmitted by the multiple selection signal lines Mux, time-divisionally transmit the data signals transmitted by the multiple data transmission lines DTL to The above-mentioned plurality of data lines DL.
  • the number of data transmission lines DTL is less than the number of data lines DL, and one data transmission line DTL corresponds to multiple data lines DL.
  • the above multiple output selection circuit 4 has a selection function. Under the action of the selection control signal, the multiple output selection circuit 4 can only transmit the data signal transmitted by each data transmission line DTL to the corresponding A certain data line DL among the plurality of data lines DL, and then only transmit to another data line DL among the corresponding plurality of data lines DL in the next time period.
  • the plurality of data lines DL may be electrically connected to a source driver circuit (for example, the driver chip 200 ) generating data signals through the plurality of data transmission lines DTL. Since the number of data transmission lines DTL is less than the number of data lines DL, the number of pins used to electrically connect with the driver chip 200 can be reduced, which is conducive to improving the yield rate of the electrical connection with the pins, and improving the display device 1000. yield rate.
  • connection wiring 3 one end of each connection wiring 3 on one side of the substrate 1 can be electrically connected to a data transmission line DTL, so that the data transmission line DTL can be sequentially passed through the multiple output selection
  • the circuit 4 is electrically connected to a corresponding plurality of data lines DL.
  • the number of data transmission lines DTL is less than the number of data lines DL, the number of connecting wires 3 can be reduced, which can effectively improve the yield rate of side wiring.
  • the plurality of data lines DL at least include: a plurality of first data lines DL 1 , a plurality of second data lines DL 2 and a plurality of third data lines DL 3 .
  • the above multiple data transmission lines DTL at least include: multiple first data transmission lines DTL 1 , multiple second data transmission lines DTL 2 and multiple third data transmission lines DTL 3 .
  • the above multiple output selection circuit 4 may include: a plurality of selection transistor groups 41 .
  • the selection transistor group 41 may be electrically connected to the selection signal line Mux, the first data line DL 1 , the second data line DL 2 and the third data line DL 3 .
  • each selection transistor group 41 may be electrically connected to one selection signal line Mux, one first data line DL 1 , one second data line DL 2 and one third data line DL 3 .
  • the first data transmission line DTL 1 is electrically connected to at least two selection transistor groups 41 , and is electrically connected to the corresponding first data line DL 1 through the at least two selection transistor groups 41 .
  • each selection transistor group 41 can be electrically connected to one selection signal line Mux and one first data line DL1
  • each first data transmission line DTL1 can be connected to at least two selection signal lines Mux and at least two first data lines DL1.
  • the data line DL 1 corresponds.
  • the data signal transmitted by the first data transmission line DTL 1 can be transmitted to a corresponding first data line DL 1 under the control of the selection signal transmitted by one of the selection signal lines Mux, and then transmitted to the corresponding first data line DL 1 by the other selection signal line Mux. Under the control of the transmitted selection signal, it is transmitted to another corresponding first data line DL 1 to realize time-sharing writing of the data signal transmitted by the first data transmission line DTL 1 .
  • the first data transmission line DTL 1 can be electrically connected to two, three, four or six selection transistor groups 41, etc., correspondingly, the first data transmission line DTL 1 can be connected to two, three, four or six The first data line DL1 and the like are electrically connected.
  • the second data transmission line DTL 2 is electrically connected to the above-mentioned at least two selection transistor groups 41, and is electrically connected to the corresponding second data line DL 2 through the at least two selection transistor groups 41. .
  • each second data transmission line DTL 2 can be connected to at least two selection signal lines Mux and at least two second data lines DL2.
  • Data line DL 2 corresponds.
  • the data signal transmitted by the second data transmission line DTL 2 can be transmitted to a corresponding second data line DL 2 under the control of the selection signal transmitted by one of the selection signal lines Mux, and then transmitted by the other selection signal line Mux. Under the control of the transmitted selection signal, it is transmitted to another corresponding second data line DL 2 to realize time-sharing writing of the data signal transmitted by the second data transmission line DTL 2 .
  • the second data transmission line DTL 2 may be electrically connected to two, three, four or six selection transistor groups 41, and correspondingly, the second data transmission line DTL 2 may be connected to two, three, four or six The second data line DL 2 and the like are electrically connected.
  • the third data transmission line DTL 3 is electrically connected to the above-mentioned at least two selection transistor groups 41, and is electrically connected to the corresponding third data line DL 3 through the at least two selection transistor groups 41. .
  • each third data transmission line DTL 3 can be connected to at least two selection signal lines Mux and at least two third data lines DL3.
  • the data line DL 3 corresponds.
  • the data signal transmitted by the third data transmission line DTL 3 can be transmitted to a corresponding third data line DL 3 under the control of the selection signal transmitted by one of the selection signal lines Mux, and can be transmitted by the other selection signal line Mux. Under the control of the transmitted selection signal, it is transmitted to another corresponding third data line DL 3 to realize time-sharing writing of the data signal transmitted by the third data transmission line DTL 3 .
  • the third data transmission line DTL 3 can be electrically connected with two, three, four or six selection transistor groups 41, etc., correspondingly, the third data transmission line DTL 3 can be connected with two, three, four or six The third data line DL 3 and so on are electrically connected.
  • the number of the plurality of selection signal lines Mux may be six, and correspondingly, the number of the plurality of selection transistor groups 41 may be 6i.
  • the first selection signal line Mux 1 can be electrically connected to the 6i-5th selection transistor group 41
  • the second selection signal line Mux 2 can be electrically connected to the 6i-4th selection transistor group 41
  • the third selection signal line Mux 2 can be electrically connected to the 6i-4th selection transistor group 41.
  • the selection signal line Mux 3 may be electrically connected to the 6i-3 selection transistor group 41
  • the fourth selection signal line Mux 4 may be electrically connected to the 6i-2 selection transistor group 41
  • the fifth selection signal line Mux 5 may be To be electrically connected to the 6i-1th selection transistor group 41
  • the sixth selection signal line Mux 6 may be electrically connected to the 6ith selection transistor group 41 .
  • i is a positive integer.
  • each selection transistor group 41 and the data transmission line DTL and the data line DL will be schematically described with reference to FIG. 13 .
  • the i-th first data transmission line DTL 1 may be electrically connected to the 6i-5th selection transistor group 41, and through the 6i-5th selection transistor group 41 and the 6i-5th first data line DL 1 is electrically connected; the i-th first data transmission line DTL 1 can also be electrically connected to the 6i-4th selection transistor group 41, and through the 6i-4th selection transistor group 41 and the 6i-4th first data line DL 1 is electrically connected; the i-th first data transmission line DTL 1 can also be electrically connected to the 6i-3 selection transistor group 41, and through the 6i-3 selection transistor group 41 and the 6i-3 first data transmission line The line DL 1 is electrically connected; the i-th first data transmission line DTL 1 can also be electrically connected to the 6i-2th selection transistor group 41, and the 6i-2th selection transistor group 41 is connected to the 6i-2th first data transmission line.
  • the data line DL 1 is electrically connected; the i-th first data transmission line DTL 1 can also be electrically connected to the 6i-1th selection transistor group 41, and through the 6i-1th selection transistor group and the 6i-1th selection transistor group.
  • the data line DL 1 is electrically connected; the i-th first data transmission line DTL 1 can also be electrically connected to the 6i-th selection transistor group, and is electrically connected to the 6i-th first data line DL 1 through the 6i-th selection transistor group.
  • the i-th second data transmission line DTL 2 may be electrically connected to the 6i-5th selection transistor group 41, and connected to the 6i-5th second data line DL 2 through the 6i-5th selection transistor group Electrically connected; the i-th second data transmission line DTL 2 can also be electrically connected to the 6i-4th selection transistor group 41, and through the 6i-4th selection transistor group 41 and the 6i-4th second data line DL 2 are electrically connected; the i-th second data transmission line DTL 2 can also be electrically connected to the 6i-3th selection transistor group 41, and communicate with the 6i-3th second data transmission line through the 6i-3th selection transistor group The line DTL 2 is electrically connected; the i-th second data transmission line DTL 2 can also be electrically connected to the 6i-2th selection transistor group 41, and through the 6i-2th selection transistor group 41 and the 6i-2th second data transmission line.
  • the data line DL 2 is electrically connected; the i-th second data transmission line DTL 2 can also be electrically connected to the 6i-1th selection transistor group 41, and through the 6i-1th selection transistor group and the 6i-1th second data transmission line.
  • the data line DL 2 is electrically connected; the i-th second data transmission line DTL 2 can also be electrically connected to the 6i-th selection transistor group 41, and is electrically connected to the 6i-th second data line DL 2 through the 6i-th selection transistor group .
  • the i-th third data transmission line DTL 3 may be electrically connected to the 6i-5th selection transistor group 41, and through the 6i-5th selection transistor group 41 and the 6i-5th third data line DL 3 are electrically connected; the i-th third data transmission line DTL 3 can also be electrically connected to the 6i-4th selection transistor group 41, and through the 6i-4th selection transistor group and the 6i-4th third data line DL 3 are electrically connected; the i-th third data transmission line DTL 3 can also be electrically connected to the 6i-3 selection transistor group 41, and through the 6i-3 selection transistor group 41 and the 6i-3 third data line DL 3 is electrically connected; the i-th third data transmission line DTL 3 can also be electrically connected to the 6i-2th selection transistor group 41, and through the 6i-2th selection transistor group 41 and the 6i-2th third data transmission line
  • the line DL 3 is electrically connected; the i-th third data transmission line DTL 3 can also be electrically connected to the 6i-1th selection transistor
  • the first data transmission line DTL 1 , the second data transmission line DTL 2 and the third data transmission line DTL 3 are arranged periodically. That is, the first data transmission line DTL 1 , the second data transmission line DTL 2 and the third data transmission line DTL 3 may be arranged cyclically in a certain order.
  • the above arrangement sequence may include multiple types, and the setting may be selected according to actual needs.
  • the arrangement order of a period may be: the first data transmission line DTL 1 , the second data transmission line DTL 2 and the third data transmission line DTL 3 ; or, the second data transmission line DTL 2 , the first data transmission line DTL 1 and the third data transmission line DTL 3 ; or, the third data transmission line DTL 3 , the first data transmission line DTL 1 and the second data transmission line DTL 2 and so on.
  • the first data line DL 1 , the second data line DL 2 and the third data line DL 3 are arranged periodically. That is, the first data line DL 1 , the second data line DL 2 and the third data line DL 3 may be arranged circularly in sequence according to a certain sequence.
  • the above arrangement sequence may include multiple types, and the setting may be selected according to actual needs.
  • the arrangement order of a period may be: the first data line DL 1 , the second data line DL 2 and the third data line DL 3 ; or, the second data line DL 2 , the first data line DL 1 and the third data line DL 3 ; or, the third data line DL 3 , the first data line DL 1 and the second data line DL 2 and so on.
  • the arrangement order of the data transmission lines DTL may be the same as that of the data lines DL. This helps to improve the regularity of wiring and reduce the difficulty of wiring.
  • the sub-pixels 2 electrically connected to the first data line DL1 may all be red sub-pixels
  • the sub-pixels 2 electrically connected to the second data line DL2 may be all green sub-pixels
  • the third data line DL2 may be all green sub-pixels.
  • the sub-pixels 2 electrically connected by the line DL 3 may all be blue sub-pixels.
  • the data line DL may include, for example, a fourth data line DL 4
  • the data transmission line DTL may, for example, include a fourth data transmission line DTL 4
  • the connection relationship between the fourth data line DL 4 , the fourth data transmission line DTL 4 and each selection transistor group 41 can refer to the description in the following examples above, and will not be repeated here.
  • the selection transistor group 41 at least includes: a first selection transistor 411 , a second selection transistor 412 and a third selection transistor 413 .
  • the control electrode of the first selection transistor 411 is electrically connected to the selection signal line Mux, the first electrode of the first selection transistor 411 is electrically connected to the first data transmission line DTL 1 , and the first selection transistor The second pole of 411 is electrically connected to the first data line DL1 .
  • the first selection transistor 411 may be turned on under the control of the selection signal, and the data from the first data transmission line DTL 1 The signal is transmitted to the first data line DL 1 .
  • control electrode of the second selection transistor 412 is electrically connected to the selection signal line Mux
  • first electrode of the second selection transistor 412 is electrically connected to the second data transmission line DTL2
  • second selection transistor The second pole of 412 is electrically connected to the second data line DL2 .
  • the second selection transistor 412 can be turned on under the control of the selection signal, and the data from the second data transmission line DTL 2 The signal is transmitted to the second data line DL 2 .
  • control electrode of the third selection transistor 413 is electrically connected to the selection signal line Mux
  • first electrode of the third selection transistor 413 is electrically connected to the third data transmission line DTL3
  • third selection transistor The second pole of 413 is electrically connected to the third data line DL3 .
  • the third selection transistor 413 may be turned on under the control of the selection signal, and the data from the third data transmission line DTL 3 The signal is transmitted to the third data line DL 3 .
  • the number of selection signal lines Mux is six and the number of selection transistor groups 41 is 6i.
  • the i-th first data transmission line DTL 1 may be electrically connected to the first selection transistors 411 in the 6i-5th to 6i-th selection transistor groups 41 .
  • the data signal transmitted by the i-th first data transmission line DTL 1 can be respectively the selection signal transmitted by the first selection signal line Mux 1 , the selection signal transmitted by the second selection signal line Mux 2 , the selection signal transmitted by the third selection signal line
  • the selection signal transmitted by the selection signal line Mux 3 , the selection signal transmitted by the fourth selection signal line Mux 4 , the selection signal transmitted by the fifth selection signal line Mux 5 , the selection signal transmitted by the sixth selection signal line Mux 6 Under the control of the selection signal, it is time-divisionally transmitted to the 6i-5th to 6i-th first data lines DL 1 to realize time-division writing of the data signal.
  • the i-th second data transmission line DTL 2 may be electrically connected to the second selection transistors 412 in the 6i-5th to 6i-th selection transistor groups 41 .
  • the data signal transmitted by the i-th second data transmission line DTL 2 can be respectively the selection signal transmitted by the first selection signal line Mux 1 , the selection signal transmitted by the second selection signal line Mux 2 , the selection signal transmitted by the third selection signal line
  • the selection signal transmitted by the selection signal line Mux 3 , the selection signal transmitted by the fourth selection signal line Mux 4 , the selection signal transmitted by the fifth selection signal line Mux 5 , the selection signal transmitted by the sixth selection signal line Mux 6 Under the control of the selection signal, it is time-divisionally transmitted to the 6i-5th to 6i-th second data lines DL 2 to realize time-division writing of the data signal.
  • the i-th third data transmission line DTL 3 may be electrically connected to the third selection transistor 413 in the 6i-5th to 6i-th selection transistor groups 41 .
  • the data signal transmitted by the i-th third data transmission line DTL 3 can be respectively the selection signal transmitted by the first selection signal line Mux 1 , the selection signal transmitted by the second selection signal line Mux 2 , the selection signal transmitted by the third selection signal line.
  • the selection signal transmitted by the selection signal line Mux 3 , the selection signal transmitted by the fourth selection signal line Mux 4 , the selection signal transmitted by the fifth selection signal line Mux 5 , the selection signal transmitted by the sixth selection signal line Mux 6 Under the control of the selection signal, it is time-divisionally transmitted to the 6i-5th to 6i-th third data line DL 3 , so as to realize the time-division writing of the data signal.
  • the selection transistor group 41 may further include, for example, a fourth selection transistor.
  • a fourth selection transistor for the electrical connection relationship of the fourth selection transistor, reference may be made to the description in the following example above, and details are not repeated here.
  • the same data line DL may be electrically connected to a column of sub-pixels. That is, the number of data lines DL is equal to the number of columns of sub-pixels.
  • the same row of sub-pixels may be electrically connected to only one gate line GL. That is, the scanning signal transmitted by each gate line GL can simultaneously control the working conditions of the data writing sub-circuit 2111 and the compensation sub-circuit 2113 in the same row of sub-pixels.
  • the same data line DL is electrically connected to at least two columns of sub-pixels, and one row of sub-pixels is electrically connected to at least two gate lines GL.
  • the at least two gate lines GL are configured to respectively transmit scan signals to corresponding sub-pixels, so as to control the row of sub-pixels to time-divisionally receive data signals transmitted by the data line DL.
  • each gate line GL is only connected to a part of sub-pixels in the same row of sub-pixels. 2; and, in the same row of sub-pixels, at least two sub-pixels 2 are electrically connected to one data line DL at the same time.
  • At least two sub-pixels 2 electrically connected to the same data line DL are respectively electrically connected to different gate lines GL.
  • the active level times of the scanning signals received by the at least two sub-pixels 2 may not overlap, so that the at least two sub-pixels 2 can work at different times (for example, the data in different sub-pixels 2 is written into the sub-circuit 2111 and the compensation
  • the sub-circuit 2113 can be turned on at different times), and sequentially receives the data signal transmitted by the data line DL, so as to realize the time-division writing of the data signal.
  • the number of data lines DL is less than the number of sub-pixels 2 in the same row of sub-pixels.
  • Arranging the gate lines GL and the data lines DL in the above arrangement manner can effectively reduce the number of data lines DL included in the display substrate 100 , reduce the space occupied by the data lines DL, and increase the wiring space of the display substrate 100 .
  • one data line DL may be electrically connected to one connection wiring 3 . That is, the number of data lines DL and the number of connection wires 3 may be equal. Since the number of data lines DL is less than the number of sub-pixels 2 in the same row of sub-pixels, the number of connecting wires 3 can be effectively reduced, which can effectively improve the yield of side wiring.
  • any two adjacent sub-pixels 2 are respectively electrically connected to different gate lines GL.
  • the above-mentioned two adjacent sub-pixels 2 (or even more adjacent sub-pixels 2) can be electrically connected to the same data line DL, which is beneficial to arrange the data line DL on the above-mentioned two adjacent sub-pixels 2 Besides, it is beneficial to reduce the distance between the data line DL and the corresponding electrically connected sub-pixels 2 , and reduce the complexity of wiring between the data line DL and the corresponding electrically connected sub-pixels 2 .
  • the number of columns of sub-pixels 2 electrically connected to the same data line DL is equal to the number of gate lines GL electrically connected to the same row of sub-pixels.
  • the number of columns of sub-pixels 2 electrically connected to the same data line DL is n
  • the number of gate lines GL electrically connected to the same row of sub-pixels is n.
  • the n sub-pixels 2 electrically connected to the same data line DL are respectively electrically connected to the n gate lines GL in a one-to-one correspondence.
  • the number of columns of sub-pixels 2 electrically connected to the same data line DL and the number of gate lines GL electrically connected to the same row of sub-pixels can be selected and set according to actual needs.
  • the number of columns of sub-pixels 2 electrically connected to the same data line DL may be two columns, three columns, four columns or six columns, etc.
  • the number of gate lines GL electrically connected to the same row of sub-pixels may be two, three, four or six, and so on.
  • the number of columns of sub-pixels 2 electrically connected to the same data line DL is six columns, and correspondingly, the number of gate lines GL electrically connected to the same row of sub-pixels is six.
  • the first gate line GL 1 can be electrically connected to the 6i-5th sub-pixel 2
  • the second gate line GL 2 can be electrically connected to the 6i-4th sub-pixel 2
  • the third gate line GL 2 can be electrically connected to the 6i-4th sub-pixel 2.
  • the gate line GL 3 can be electrically connected to the 6i-3th sub-pixel 2
  • the fourth gate line GL4 can be electrically connected to the 6i-2th sub-pixel 2
  • the fifth gate line GL5 can be electrically connected to the 6i-1th sub-pixel 2
  • the sixth gate line GL 6 may be electrically connected to the 6i-th sub-pixel.
  • the i-th data line DL may be electrically connected to the 6i-5th to 6ith columns of sub-pixels.
  • the level jumps to the active level in turn, and among the six scanning signals, the active level times of any two adjacent scanning signals do not overlap.
  • the data writing sub-circuit 2111 and the compensation sub-circuit 2113 can sequentially receive the data signal transmitted by the i-th data line DL, so as to implement time-sharing writing of the data signal.
  • At least two gate lines GL electrically connected to the same row of sub-pixels are respectively arranged on opposite sides of the row of sub-pixels. That is, the at least two gate lines GL can be divided into two parts, one part of the gate lines GL can be arranged on one side of the row of sub-pixels, and the other part of the gate lines GL can be arranged on the other side of the row of sub-pixels. Wherein, the number of the two parts of gate lines GL may be equal, for example.
  • the number of gate lines GL electrically connected to the same row of sub-pixels is six. At this time, three of the gate lines GL may be disposed on one side of the row of sub-pixels, and the other three gate lines GL may be disposed on the other side of the row of sub-pixels.
  • the number of gate lines GL is relatively large, and correspondingly, the number of shift registers (for generating scan signals) required to be provided in the display substrate 100 will also be relatively large.
  • the arrangement of the gate lines GL and the data lines DL in this embodiment can be applied to a display substrate with a lower resolution, so as to avoid adverse effects on the resolution of the display substrate 100 .
  • the first current selection signal, the second The second current selection signal, the first time length selection signal and the second time length selection signal all jump to low level in time division, so as to realize the time division writing of the current data signal and the length data signal.
  • a time interval is added between signals (as shown by the double-headed arrows in Figure 3 and Figure 4 ) to prevent signals from being written incorrectly.
  • the writing and compensation stages corresponding to the current control circuit of a certain sub-pixel are taken as an example.
  • the current data signal is written into the corresponding current data line DI.
  • the last frame when the first current selection signal corresponding to the sub-pixel jumps to a high level, the previously written current data signal will be stored on the current data line DI through the parasitic capacitance on the current data line DI .
  • the current data signal may not be normally written into the current control circuit (that is, the control electrode of the driving transistor in the current control circuit).
  • the level of the current data signal is low level (its voltage value is Vdata(n-1)).
  • the current data signal stored on the current data line DI will first be written into the in the current control circuit. After the first current selection signal jumps to a low level, as shown in Figure 3, if the level of the current data signal (its voltage value is Vdata(n)) in the next frame display is higher than the current display in the previous frame The level of the data signal, the data current signal can be continuously written into the current control circuit (as shown by Vg in Figure 3, Vth is the threshold voltage in the current control circuit); as shown in Figure 4, if the next frame is displayed If the level of the current data signal (its voltage value is Vdata(n)) is lower than the level of the current data signal displayed in the previous frame, it will continue to write the data signal of the previous frame (as shown by Vg in Figure 4 ), the data signal displayed in this frame cannot be written normally, which makes it difficult to normally turn on the driving transistor in the current control circuit
  • the period during which the level of the data signal jumps to an active level is earlier than that of the scan signal The period when the level jumps to a valid level.
  • the data signal in the stage of generating the driving signal, can be transmitted to the corresponding data line DL first, and stored on the parasitic capacitance of the corresponding data line DL, and then the level of the scanning signal is changed to an active level, so that The data signal is sequentially written into the sixth node N6 through the data writing sub-circuit 2111 , the driving sub-circuit 2112 and the compensation sub-circuit 2113 , to complete the compensation of the threshold voltage of the driving sub-circuit 2112 .
  • the current control circuit 211 In the stage where the current control circuit 211 generates the driving signal, by setting the period of time when the level of the data signal jumps to an active level earlier than the period when the level of the scan signal changes to an active level, it can be displayed in the next frame. Before, the data signal stored in the data line DL is refreshed to avoid remaining the data signal displayed in the previous frame, so that after the level of the scanning signal jumps to an active level, the refreshed data signal can be received. This avoids that the data signal displayed in the next frame cannot be written normally due to the residual data signal of the previous frame, so that each sub-pixel 2 can display the required gray scale, and the display effect of the display substrate 100 is improved.
  • the effective level period of the selection signal transmitted by each selection signal line Mux is earlier than The period during which the level of the scanning signal transitions to an active level.
  • each selection signal has successively jumped to an active level, and the data signal is time-divisionally written to the corresponding data line DL, and passed through the data line DL.
  • the parasitic capacitance of the capacitor completes the storage of the corresponding data signal.
  • the current control circuit 211 In the stage of generating the driving signal, the period when the level of the data signal jumps to an active level is earlier than the period when the level of the scanning signal jumps to an active level;
  • the scanning signal may have a plurality of intervals of effective levels corresponding to the different sub-pixels 2. At this time, the levels of different data signals are all within the range of the corresponding scanning signal Before the effective level of the jump to the effective level.
  • Some embodiments of the present disclosure provide a driving method of a display substrate.
  • the driving method includes: transmitting data signals to multiple data lines DL of the display substrate 100 , and the current control circuit 211 and the duration control circuit 212 of the same sub-pixel 2 receive the data signals simultaneously.
  • the active level of the data signal is written into the current control circuit 211 and the duration control circuit 212 in time division.
  • phase of writing and compensation corresponding to the current control circuit 211 and the phase of generating the duration control signal corresponding to the duration control circuit 212 can be separated without overlapping, and the level of the data signal basically does not change at each stage .
  • signal crosstalk between two adjacent data lines DL can be effectively avoided, and the level of the data signal written into the current control circuit 211 caused by the change of the level of the data signal written into the duration control circuit 212 can be avoided.
  • the jump occurs, which in turn helps to improve the poor phenomenon of column-wise brightness and darkness differences.
  • the above-mentioned current control circuit 211 includes a data writing sub-circuit 2111, a driving sub-circuit 2112, a compensation sub-circuit 2113, and a lighting control sub-circuit 2114.
  • the duration control circuit 212 includes a first A control subcircuit 2121 , a second control subcircuit 2122 and a third control subcircuit 2123 .
  • the driving method of the display substrate 100 in the display stage of one frame will be schematically described below in conjunction with the structure of the sub-pixel 2 shown in FIG. 7 .
  • the above driving method further includes: a first stage S1 , a second stage S2 , a third stage S3 and a fourth stage S4 .
  • a first stage S1 when the gray scales displayed by the sub-pixels 2 of the display substrate 100 are different, the above-mentioned first stage S1 and the second stage S2 are slightly different.
  • the gray scale displayed by the sub-pixel 2 of the display substrate 100 is greater than or equal to the threshold gray scale.
  • a conductive path may always be formed between the pixel driving circuit 21 and the light emitting device 22, and correspondingly, the duration control signal may be the first enabling signal.
  • the level of the first reset signal is low level
  • the level of the second reset signal is high level
  • the level of the data signal is high level.
  • the first control sub-circuit 2121 is turned off.
  • the first transistor T1 in the first control sub-circuit 2121 can be turned on under the control of the first reset signal to transmit the data signal to the third node N3. Since the level of the data signal is at a high level, the second transistor T2 in the first control sub-circuit 2121 can be turned off under the control of the data signal from the third node N3. At this time, the second enable signal cannot transmitted to the second node N2. At the same time, the first capacitor C1 in the first control sub-circuit 2121 can store a high-level data signal.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned off under the control of the second reset signal.
  • the current control circuit 211 further includes a reset sub-circuit 2115
  • the tenth transistor T10 and the eleventh transistor T11 in the reset sub-circuit 2115 can be turned on simultaneously under the control of the first reset signal, and the tenth transistor T10 can transmit the initial signal to the sixth node N6 to reset the sixth node N6; the eleventh transistor T11 can transmit the initial signal to the light emitting device 22 to reset the light emitting device 22 .
  • the level of the first reset signal is high level
  • the level of the second reset signal is low level
  • the level of the data signal is low level.
  • the second control subcircuit 2122 In response to the second reset signal and data signal received at the second reset signal terminal Res_B, the second control subcircuit 2122 is turned on, and transmits the first enable signal received at the first enable signal terminal EM to the second Node N2.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned on under the control of the second reset signal to transmit the data signal to the fourth node N4. Since the level of the data signal is low level, the fourth transistor T4 in the second control sub-circuit 2122 can be turned on under the control of the data signal from the fourth node N4, and transmit the first enable signal to the second Two nodes N2. At the same time, the second capacitor C2 in the second control sub-circuit 2122 can store the low-level data signal.
  • the first transistor T1 in the first control sub-circuit 2121 can be turned off under the control of the first reset signal. At this time, the first capacitor C1 is discharged, so that the voltage of the third node N3 remains at a high level.
  • the level of the scan signal is low level
  • the level of the data signal is low level
  • the level of the first reset signal is high level
  • the level of the second reset signal Ping is high level.
  • the data writing sub-circuit 2111 and the compensation sub-circuit 2113 are turned on, and the data signal passes through the fifth node N5, the driving sub-circuit 2112, the first node N1 and the compensation sub-circuit in sequence 2113, transmit to the sixth node N6, and perform threshold voltage compensation for the driving sub-circuit 2112.
  • the seventh transistor T7 in the driving sub-circuit 2112 can be turned on under the control of the initial signal from the sixth node N6.
  • the sixth transistor T6 in the data writing sub-circuit 2111 and the eighth transistor T8 in the compensation sub-circuit 2113 can be turned on simultaneously under the control of the scan signal.
  • the sixth transistor T6 can receive the data signal and transmit it to the sixth node N6 through the fifth node N5, the seventh transistor T7, the first node N1 and the eighth transistor T8 in sequence.
  • the data signal can be continuously transmitted to the sixth node N6 until the seventh transistor T7 is turned off.
  • the compensation of the threshold voltage of the seventh transistor T7 is completed.
  • the first transistor T1 in the first control sub-circuit 2121 can be turned off under the control of the first reset signal.
  • the first capacitor C1 is discharged, so that the voltage of the third node N3 remains at a high level.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned off under the control of the second reset signal.
  • the second capacitor C2 starts to discharge, so that the voltage of the fourth node N4 is kept at a low level, so that the fourth transistor T4 continues to transmit the first enabling signal to the second node N2.
  • the level of the first enabling signal is low level
  • the level of the scanning signal is high level
  • the level of the first reset signal is high level
  • the level of the second The level of the reset signal is high level.
  • the light emission control sub-circuit 2114 In response to the first enable signal, the light emission control sub-circuit 2114 is turned on, and transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1 through the fifth node N5 and the driving sub-circuit 2112 in sequence.
  • the ninth transistor T9 in the light emission control sub-circuit 2114 is turned on under the control of the first enable signal, so that a conductive path is formed between the fifth node N5 and the first voltage signal terminal VDD.
  • the fifth transistor T5 in the third control sub-circuit 2123 is turned on under the control of the first enable signal from the second node N2 , so that a conductive path is formed between the first node N1 and the light emitting device 22 .
  • the seventh transistor T7 in the driving sub-circuit 2112 is turned on to transmit the first voltage signal to the first node N1.
  • the seventh transistor T7 can generate a driving signal according to the voltage value of the data signal written to the sixth node N6 and the voltage value of the first voltage signal.
  • the first enable signal can make the connection between the first node N1 and the light emitting device 22 continuous.
  • the driving signal can be continuously transmitted to the light-emitting device 22, so that the light-emitting device 22 can continue to emit light, thereby realizing higher gray scale display.
  • the gray scale displayed by the sub-pixel 2 of the display substrate 100 is smaller than the threshold gray scale.
  • the pixel driving circuit 21 and the light emitting device 22 are in an alternate state of on and off, and correspondingly, the duration control signal may be a second enabling signal.
  • the level of the first reset signal is low level
  • the level of the second reset signal is high level
  • the level of the data signal is low level
  • the first control sub-circuit 2121 In response to the first reset signal and the data signal, the first control sub-circuit 2121 is turned on, and transmits the second enable signal received at the second enable signal terminal EM to the second node N2.
  • the first transistor T1 in the first control sub-circuit 2121 can be turned on under the control of the first reset signal to transmit the data signal to the third node N3. Since the level of the data signal is low level, the second transistor T2 in the first control sub-circuit 2121 can be turned on under the control of the data signal from the third node N3, and transmit the second enabling signal to the first Two nodes N2. At the same time, the first capacitor C1 in the first control sub-circuit 2121 can store the low-level data signal.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned off under the control of the second reset signal.
  • the current control circuit 211 further includes a reset sub-circuit 2115
  • the tenth transistor T10 and the eleventh transistor T11 in the reset sub-circuit 2115 can be turned on simultaneously under the control of the first reset signal, and the tenth transistor T10 can send an initial signal to the sixth node N6 to reset the sixth node N6; the eleventh transistor T11 can send an initial signal to the light emitting device 22 to reset the light emitting device 22 .
  • the level of the first reset signal is high level
  • the level of the second reset signal is low level
  • the level of the data signal is high level
  • the second control subcircuit 2122 is turned off.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned on under the control of the second reset signal to transmit the data signal to the fourth node N4. Since the level of the data signal is at a high level, the fourth transistor T4 in the second control sub-circuit 2122 can be turned off under the control of the data signal from the fourth node N4. At this time, the first enable signal cannot transmitted to the second node N2. At the same time, the second capacitor C2 in the second control sub-circuit 2122 can store the high-level data signal.
  • the first transistor T1 in the first control sub-circuit 2121 may be turned off under the control of the first reset signal.
  • the first capacitor C1 is discharged, so that the voltage of the third node N3 remains at a low level.
  • the level of the scan signal is low level
  • the level of the data signal is low level
  • the level of the first reset signal is high level
  • the level of the second reset signal Ping is high level.
  • the data writing sub-circuit 2111 and the compensation sub-circuit 2113 are turned on, and the data signal passes through the fifth node N5, the driving sub-circuit 2112, the first node N1 and the compensation sub-circuit in sequence 2113, transmit to the sixth node N6, and perform threshold voltage compensation for the driving sub-circuit 2112.
  • the seventh transistor T7 in the driving sub-circuit 2112 can be turned on under the control of the initial signal from the sixth node N6.
  • the sixth transistor T6 in the data writing sub-circuit 2111 and the eighth transistor T8 in the compensation sub-circuit 2113 can be turned on simultaneously under the control of the scan signal.
  • the sixth transistor T6 can receive the data signal and transmit it to the sixth node N6 through the fifth node N5, the seventh transistor T7, the first node N1 and the eighth transistor T8 in sequence.
  • the data signal can be continuously transmitted to the sixth node N6 until the seventh transistor T7 is turned off.
  • the compensation of the threshold voltage of the seventh transistor T7 is completed.
  • the third transistor T3 in the second control sub-circuit 2122 can be turned off under the control of the second reset signal.
  • the second capacitor C2 is discharged, so that the voltage of the fourth node N4 remains at a high level.
  • the first transistor T1 in the first control sub-circuit 2121 can be turned off under the control of the first reset signal.
  • the first capacitor C1 starts to discharge, so that the voltage of the third node N3 remains at a low level, and then the second transistor T2 continues to transmit the second enabling signal to the second node N2.
  • the level of the first enabling signal is low level
  • the second enabling signal is a high-frequency pulse signal
  • the level of the scanning signal is high level
  • the first reset signal The level of the second reset signal is high level
  • the level of the second reset signal is high level.
  • the light emission control sub-circuit 2114 In response to the first enable signal, the light emission control sub-circuit 2114 is turned on, and transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1 through the fifth node N5 and the driving sub-circuit 2112 in sequence.
  • the ninth transistor T9 in the light emission control sub-circuit 2114 is turned on under the control of the first enable signal, so that a conductive path is formed between the fifth node N5 and the first voltage signal terminal VDD.
  • the fifth transistor T5 in the third control sub-circuit 2123 is in an alternate state of being on and off, so that the first node N1 and the light emitting device 22 are in a conduction state. On and off alternate states.
  • the seventh transistor T7 in the driving sub-circuit 2112 is turned on to transmit the first voltage signal to the first node N1.
  • the seventh transistor T7 can generate a driving signal according to the voltage value of the data signal written to the sixth node N6 and the voltage value of the first voltage signal, and transmit to the light emitting device 22, so that the light emitting device 22 emits light.
  • the above driving signal may be intermittently transmitted to the light emitting device 22, so that the light emitting device 22 periodically receives the driving signal, Further, the light emitting device 22 is made to emit light periodically. In this way, the total duration of light emission of the light emitting device 22 is shortened, so that a display with a lower gray scale can be realized.
  • the data lines DL in the above display substrate 100 are configured to store data signals.
  • the scan signal terminal Gate is configured to transmit a scan signal after the data line DL stores the data signal in the above-mentioned third stage S3 (that is, the third stage S3a or the third stage S3b), so as to control the data writing sub-circuit 2111 and The compensation sub-circuit 2113 is turned on.
  • the data line DL itself has a parasitic capacitance, and after the data signal is transmitted to the data line DL, the data signal can be stored on the parasitic capacitance of the data line DL.
  • the scanning signal terminal Gate is capable of transmitting a scanning signal, and the scanning signal may come from a corresponding gate line GL.
  • the level of the data signal is low level (that is, active level)
  • the level of the scanning signal is low level (that is, active level)
  • the above-mentioned data signal is received on the data line DL.
  • the scanning signal terminal Gate can transmit the scanning signal, so that the data writing sub-circuit 2111 and the compensation sub-circuit 2113 are turned on, and the data re-stored in the data line DL is received and transmitted. Signal.
  • the data signal stored in the data line DL can be refreshed first to avoid remaining the data signal displayed in the previous frame, and then in the next frame display, after the level of the scanning signal jumps to an active level, it can receive
  • the refreshed data signal avoids that the data signal displayed in the next frame cannot be written normally due to the residual data signal of the previous frame, so that each sub-pixel 2 can display the desired gray scale, and the display effect of the display substrate 100 is improved.
  • the display substrate 100 further includes a multiple output selection circuit 4 .
  • the driving method of the display substrate including the multi-output selection circuit 4 will be schematically described below with reference to the timing diagrams shown in FIG. 14 and FIG. 15 .
  • the selection signals (Mux 1 -Mux 6 ) transmitted by the plurality of selection signal lines Mux are respectively transmitted to the multi-output selection circuit 4 .
  • Each selection transistor group 41 in the multi-channel output selection circuit 4 is respectively turned on under the control of the corresponding selection signal, and the data signal from the data transmission line DTL is time-divisionally transmitted to the corresponding data line DL, and stored in the corresponding data line. on the parasitic capacitance of line DL.
  • the duration of the low level of the first reset signal can be selected and set according to actual needs.
  • the level of the first reset signal jumps to a low level, and after completing the writing of the data signal , and before the second stage S2, the level of the first reset signal transitions to a high level.
  • the level of the first reset signal can jump to a low level. Before the writing of the data signal is completed and before the second stage S2, the level of the first reset signal transitions to a high level. In this way, the duration of the low level of the first reset signal can be increased, which is beneficial to increase the writing duration of the data signal.
  • the transmission process of the data signal is the same as the transmission process of the data signal in the first stage S1
  • the duration of the low level of the second reset signal is
  • the setting method may be the same as the setting method of the low level duration of the first reset signal, which will not be repeated here.
  • the driver chip 200 can be adjusted so that the driver chip 200 can be compatible.
  • the multi-channel output selection circuit 4 completes the time-division writing and writing of the data signal. storage.
  • the present disclosure can reduce the duration of the low level (that is, the active level) of each selection signal, This is beneficial to increase the duration of the low level of the first reset signal, the second reset signal and the scan signal, and further helps to provide more sufficient time for writing the data signal and compensating the seventh transistor T7.
  • the same data line DL is electrically connected to at least two columns of sub-pixels, and one row of sub-pixels is electrically connected to at least two gate lines GL.
  • the driving method of the display substrate is described. Schematic description.
  • the number of first reset signal lines RL1 electrically connected to the first reset signal terminal Res_A of the same row of sub-pixels is also six (RL1 1 -RL1 6 )
  • the number of second reset signal lines RL2 electrically connected to the second reset signal terminals Res_B of the same row of sub-pixels is also six (RL2 1 -RL2 6 ).
  • the connection relationship between the first reset signal line RL1 or the second reset signal line RL2 and the sub-pixels in the same row may be the same as the connection relationship between the gate line GL and the sub-pixels in the same row.
  • the six first reset signal lines respectively transmit the first reset signal (Res_A 1 ⁇ Res_A 6 ) to the corresponding sub- The first reset signal terminal Res_A of the pixel 2 .
  • Active levels of the first reset signals do not coincide with each other, which facilitates time-division writing of data signals in the same data line DL to different sub-pixels 2 .
  • the six second reset signal lines respectively transmit the second reset signal (Res_B 1 ⁇ Res_B 6 ) to the corresponding sub- The second reset signal terminal Res_B of the pixel 2 .
  • Active levels of the second reset signals do not coincide with each other, which facilitates time-division writing of data signals in the same data line DL to different sub-pixels 2 .
  • the six gate lines GL respectively transmit the scanning signals (Gate 1 -Gate 6 ) to the scanning signal terminals Gate of the corresponding sub-pixels.
  • the active levels of the scanning signals do not coincide with each other, which facilitates time-division writing of data signals in the same data line DL to different sub-pixels 2 .
  • the active level (that is, low level) time of the second enable signal is all in the fourth stage S4. That is to say, the level of the second enable signal is in the fourth stage S4 during the transition period from high level to low level.
  • the level of the second enable signal can be kept at an inactive level (ie high level), for example.
  • the third stage S3 in the process of compensating the threshold voltage of the seventh transistor T7, it is possible to avoid causing damage to the data signal written to the gate electrode of the seventh transistor T7 due to the high-frequency pull-down of the second enable signal. Coupling interference prevents the voltage of the control electrode of the seventh transistor T7 from being disturbed, thereby helping to ensure that the sub-pixel 2 can normally display gray scales.
  • the active level time of the second enable signal in the fourth stage S4 it is also possible to avoid setting an anti-interference transistor between the fifth transistor T5 and the first node N1, which is beneficial to simplify the sub-pixel 2
  • the structure improves the yield of the sub-pixel 2 and the display substrate 100 .

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Abstract

一种显示基板（100），包括：沿第一方向（Y）延伸的多条数据线（DL）；以及，多个子像素（2）。子像素（2）包括像素驱动电路（21）及发光器件（22）。像素驱动电路（21）包括：电流控制电路（211），及与电流控制电路（211）、发光器件（22）电连接的时长控制电路（212）。电流控制电路（211）被配置为，生成驱动信号，以驱动发光器件（22）发光；时长控制电路（212）被配置为，生成时长控制信号，以控制电流控制电路（211）和发光器件（22）之间的导通时长。其中，电流控制电路（211）和时长控制电路（212），与同一条数据线电连接。

Description

显示基板及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其驱动方法、显示装置。
背景技术
显示市场目前正在蓬勃发展，并且随着消费者对笔记本电脑、智能手机、电视、平板电脑、智能手表和健身腕带等各类显示产品的需求的持续提升，将来会涌现出更多的新显示产品。
发明内容
一方面，提供一种显示基板。所述显示基板沿第一方向延伸的多条数据线；以及，多个子像素。子像素包括像素驱动电路及发光器。所述像素驱动电路包括：电流控制电路，及与所述电流控制电路、所述发光器件电连接的时长控制电路。所述电流控制电路被配置为，生成驱动信号，以驱动所述发光器件发光；所述时长控制电路被配置为，生成时长控制信号，以控制所述电流控制电路和所述发光器件之间的导通时长。其中，所述电流控制电路和所述时长控制电路，与同一条数据线电连接。
在一些实施例中，所述多个子像素述第二方向排列为多列。同一条数据线与至少一列子像素电连接。
在一些实施例中，任意相邻两条数据线之间，设置有至少一列子像素。
在一些实施例中，所述显示基板，还包括：与所述多条数据线电连接的多路输出选择电路；与所述多路输出选择电路电连接的多条数据传输线；及，与所述多路输出选择电路电连接的多条选择信号线。其中，所述多路输出选择电路被配置为，在所述多条选择信号线所传输的选择信号的控制下，将所述多条数据传输线所传输的数据信号，分时传输至所述多条数据线。
在一些实施例中，所述多条数据线至少包括：多条第一数据线、多条第二数据线和多条第三数据线。所述多条数据传输线至少包括：多条第一数据传输线、多条第二数据传输线和多条第三数据传输线。所述多路输出选择电路包括：多个选择晶体管组；选择晶体管组与选择信号线、第一数据线、第二数据线及第三数据线电连接。其中，第一数据传输线与至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第一数据线电连接。第二数据传输线与所述至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第二数据线电连接。第三数据传输线与所述至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第三数据线电连接。
在一些实施例中，所述第一数据传输线、所述第二数据传输线和所述第三数据传输线呈周期性排布。和/或，所述第一数据线、所述第二数据线和所述第三数据线呈周期性排布。
在一些实施例中，所述选择晶体管组至少包括：第一选择晶体管、第二选择晶体管和第三选择晶体管。所述第一选择晶体管的控制极与所述选择信号线电连接，所述第一选择晶体管的第一极与所述第一数据传输线电连接，所述第一选择晶体管的第二极与所述第一数据线电连接。所述第二选择晶体管的控制极与所述选择信号线电连接，所述第二选择晶体管的第一极与所述第二数据传输线电连接，所述第二选择晶体管的第二极与所述第二数据线电连接。所述第三选择晶体管的控制极与所述选择信号线电连接，所述第三选择晶体管的第一极与所述第三数据传输线电连接，所述第三选择晶体管的第二极与所述第三数据 线电连接。
在一些实施例中，同一条数据线与一列子像素电连接。
在一些实施例中，同一条数据线与至少两列子像素电连接。所述显示基板还包括：沿第一方向延伸的多条栅线；一个子像素与一条栅线电连接。其中，所述多个子像素沿所述第二方向排列为多行；一行子像素与至少两条栅线电连接。所述至少两条栅线被配置为，分别向相应的子像素传输扫描信号，以控制所述一行子像素分时接收所述数据线所传输的数据信号。
在一些实施例中，同一条数据线所电连接的子像素的列数，与同一行子像素所电连接的栅线条数，相等。
在一些实施例中，所述至少两条栅线分别设置在所述一行子像素的相对两侧。
在一些实施例中，同一行子像素中，任意相邻的两个子像素分别与不同栅线电连接。
在一些实施例中，所述显示基板，还包括：衬底；所述多条数据线所述多个子像素设置在所述衬底的一侧；以及，设置在所述衬底边缘的多条连接配线。连接配线的一端与至少一条所述数据线电连接，所述连接配线的另一端延伸至所述衬底的另一侧。在所述显示基板还包括多路输出选择电路、多条数据传输线的情况下，所述连接配线的一端与数据传输线电连接，并通过所述多路输出选择电路与多条数据线电连接。
在一些实施例中，所述电流控制电路至少与扫描信号端、数据信号端、第一使能信号端、第一电压信号端及第一节点电连接；所述电流控制电路被配置为，响应于在所述扫描信号端处接收的扫描信号、在所述数据信号端处接收的数据信号、在所述第一使能信号端处接收的第一使能信号及在所述第一电压信号端处接收的第一电压信号，生成驱动信号。所述时长控制电路至少与所述数据信号端、第一复位信号端、第二复位信号端、所述第一使能信号端、第二使能信号端、所述第一节点及所述发光器件电连接；所述时长控制电路被配置为，响应于所述数据信号和在所述第一复位信号端处接收的第一复位信号，根据在所述第二使能信号端处接收的第二使能信号控制所述第一节点和所述发光器件之间的导通时长；或，响应于所述数据信号和在所述第二复位信号端处接收的第二复位信号，根据在所述第一使能信号，控制所述第一节点和所述发光器件之间的导通时长。其中，所述电流控制电路和所述时长控制电路，均通过所述数据信号端与所述数据线电连接。
在一些实施例中，所述第一复位信号和所述第二复位信号的有效电平时间不重合。所述数据信号中，与所述第一复位信号的有效电平相对应的电平、及与所述第二复位信号的有效电平相对应的电平中的一者，为有效电平。
在一些实施例中，在生成所述驱动信号的阶段，所述数据信号的电平跳变为有效电平的时间，早于所述扫描信号的电平跳变为有效电平的时间。
在一些实施例中，所述时长控制电路包括：第一控制子电路、第二控制子电路及第三控制子电路。第一控制子电路至少与所述数据信号端、所述第一复位信号端、所述第二使能信号端及第二节点电连接。所述第一控制子电路被配置为，响应于所述数据信号和所述第一复位信号，将所述第二使能信号传输至所述第二节点。第二控制子电路至少与所述数据信号端、所述第二复位信号端、所述第一使能信号端及所述第二节点电连接。所述第二控制子电路被配置为，响应于所述数据信号和所述第二复位信号，将所述第一使能信号传输至所述第二节点。第三控制子电路与所述第一节点、所述第二节点及所述发光器件电连接。所述第三控制子电路被配置为，在来自所述第二节点的信号的控制下，控制所述第一 节点和所述发光器件之间的导通时长。
在一些实施例中，所述第一控制子电路包括：第一晶体管、第二晶体管和第一电容器。所述第一晶体管的控制极与所述第一复位信号端电连接，所述第一晶体管的第一极与所述数据信号端电连接，所述第一晶体管的第二极与第三节点电连接。所述第二晶体管的控制极与所述第三节点电连接，所述第二晶体管的第一极与所述第二使能信号端电连接，所述第二晶体管的第二极与所述第二节点电连接。所述第一电容器的第一极与初始信号端电连接，所述第一电容器的第二极与所述第三节点电连接。所述第二控制子电路包括：第三晶体管、第四晶体管和第二电容器。所述第三晶体管的控制极与所述第二复位信号端电连接，所述第三晶体管的第一极与所述数据信号端电连接，所述第三晶体管的第二极与第四节点电连接。所述第四晶体管的控制极与所述第四节点电连接，所述第四晶体管的第一极与所述第一使能信号端电连接，所述第四晶体管的第二极与所述第二节点电连接。所述第二电容器的第一极与所述初始信号端电连接，所述第二电容器的第二极与所述第四节点电连接。所述第三控制子电路包括：第五晶体管。所述第五晶体管的控制极与所述第二节点电连接，所述第五晶体管的第一极与所述第一节点电连接，所述第五晶体管的第二极与所述发光器件电连接。
在一些实施例中，所述电流控制电路包括：数据写入子电路、驱动子电路、补偿子电路以及发光控制子电路。数据写入子电路与所述扫描信号端、所述数据信号端及第五节点电连接；所述数据写入子电路被配置为，在所述扫描信号的控制下，将所述数据信号传输至所述第五节点。驱动子电路至少与所述第一节点、所述第五节点及第六节点电连接；所述驱动子电路被配置为，在所述第六节点的电压的控制下，将来自所述第五节点的信号传输至所述第一节点。补偿子电路与所述扫描信号端、所述第一节点及所述第六节点电连接；所述补偿子电路被配置为，在所述扫描信号的控制下，将来自所述第一节点的信号传输至所述第六节点，以对所述驱动子电路进行阈值电压的补偿。发光控制子电路与所述第一使能信号端、所述第一电压信号端及所述第五节点电连接；所述发光控制子电路被配置为，在所述第一使能信号的控制下，将所述第一电压信号传输至所述第五节点。
在一些实施例中，所述数据写入子电路包括：第六晶体管。所述第六晶体管的控制极与所述扫描信号端电连接，所述第六晶体管的第一极与所述数据信号端电连接，所述第六晶体管的第二极与所述第五节点电连接。所述驱动子电路包括：第七晶体管和第三电容器。所述第七晶体管的控制极与所述第六节点电连接，所述第七晶体管的第一极与所述第五节点电连接，所述第七晶体管的第二极与所述第一节点电连接。所述第三电容器的第一极与所述第六节点电连接，所述第三电容器的第二极与所述第一电压信号端电连接。所述补偿子电路包括：第八晶体管。所述第八晶体管的控制极与所述扫描信号端电连接，所述第八晶体管的第一极与所述第一节点电连接，所述第八晶体管的第二极与所述第六节点电连接。所述发光控制子电路包括：第九晶体管。所述第九晶体管的控制极与所述第一使能信号端电连接，所述第九晶体管的第一极与所述第一电压信号端电连接，所述第九晶体管的第二极与所述第五节点电连接。
在一些实施例中，所述电流控制电路还包括：复位子电路。所述复位子电路与所述第一复位信号端、初始信号端、所述第六节点及所述发光器件电连接；所述复位子电路被配置为，响应于所述第一复位信号，将在所述初始信号端处接收的初始信号传输至所述第六节点及所述发光器件。
在一些实施例中，所述复位子电路包括：第十晶体管和第十一晶体管。所述第十晶体管的控制极与所述第一复位信号端电连接，所述第十晶体管的第一极与所述初始信号端电连接，所述第十晶体管的第二极与所述第六节点电连接。所述第十一晶体管的控制极与所述第一复位信号端电连接，所述第十一晶体管的第一极与所述初始信号端电连接，所述第十一晶体管的第二极与所述发光器件电连接。
另一方面，提供一种显示基板的驱动方法。所述驱动方法用于驱动如上述任一项实施例所述的显示基板。所述驱动方法包括：向所述显示基板的多条数据线传输数据信号，同一子像素的电流控制电路和时长控制电路同时接收所述数据信号。
在一些实施例中，所述电流控制电路包括数据写入子电路、驱动子电路、补偿子电路及发光控制子电路，所述时长控制电路包括第一控制子电路、第二控制子电路及第三控制子电路。在一帧显示阶段，所述驱动方法还包括：第一阶段、第二阶段、第三阶段和第四阶段。在所述显示基板的子像素所显示的灰阶大于或等于阈值灰阶的情况下，在所述第一阶段，响应于在第一复位信号端处接收的第一复位信号和所述数据信号，所述第一控制子电路关断；在所述第二阶段，响应于在第二复位信号端处接收的第二复位信号和所述数据信号，所述第二控制子电路导通，将在第一使能信号端处接收的第一使能信号传输至第二节点。在所述显示基板的子像素所显示的灰阶小于阈值灰阶的情况下，在所述第一阶段，响应于所述第一复位信号和所述数据信号，所述第一控制子电路导通，将在第二使能信号端处接收的第二使能信号传输至所述第二节点；在所述第二阶段，响应于所述第二复位信号和所述数据信号，所述第二控制子电路关断。其中，在所述第三阶段，响应于在扫描信号端处接收的扫描信号，所述数据写入子电路和所述补偿子电路导通，将所述数据信号依次经第五节点、所述驱动子电路、第一节点及所述补偿子电路，传输至第六节点，对所述驱动子电路进行阈值电压的补偿。在所述第四阶段，响应于所述第一使能信号，所述发光控制子电路导通，将在第一电压信号端处接收的第一电压信号依次经第五节点和所述驱动子电路，传输至所述第一节点。
在一些实施例中，数据线被配置为，对所述数据信号进行存储。所述扫描信号端被配置为，在所述第三阶段，在所述数据线存储所述数据信号之后，传输所述扫描信号，以控制所述数据写入子电路和所述补偿子电路导通。
又一方面，提供一种显示装置。所述显示装置，包括：至少一个如上述任一实施例中所述的显示基板。
在一些实施例中，所述显示基板包括衬底及设置在所述衬底边缘的多条连接配线；所述多条连接配线的一端位于所述衬底的一侧，所述多条连接配线的另一端延伸至所述衬底的另一侧。所述显示装置还包括：设置在所述衬底另一侧的驱动芯片。所述驱动芯片与所述多条连接配线的另一端电连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一种实现方式中的一种显示基板的结构图；
图2为根据一种实现方式中的一种对应于图1所示显示基板的时序图；
图3为根据一种实现方式中的另一种对应于图1所示显示基板的时序图；
图4为根据一种实现方式中的又一种对应于图1所示显示基板的时序图；
图5为根据本公开一些实施例中的一种显示基板的结构图；
图6为根据本公开一些实施例中的一种子像素的结构图；
图7为根据本公开一些实施例中的一种子像素的电路图；
图8为根据本公开一些实施例中的一种焊盘及像素驱动电路的分布图；
图9为根据本公开一些实施例中的另一种焊盘及像素驱动电路的分布图；
图10为根据本公开一些实施例中的一种对应于图7所示子像素的时序图；
图11为根据本公开一些实施例中的另一种对应于图7所示子像素的时序图；
图12为根据本公开一些实施例中的另一种显示基板的结构图；
图13为根据本公开一些实施例中的又一种显示基板的结构图；
图14为根据本公开一些实施例中的一种对应于图13所示显示基板的时序图；
图15为根据本公开一些实施例中的另一种对应于图13所示显示基板的时序图；
图16为根据本公开一些实施例中的又一种显示基板的结构图；
图17为根据本公开一些实施例中的又一种显示基板的结构图；
图18为根据本公开一些实施例中的一种对应于图17所示显示基板的时序图；
图19为根据本公开一些实施例中的又一种显示基板的结构图；
图20为根据本公开一些实施例中的又一种显示基板的结构图；
图21为根据本公开一些实施例中的一种显示装置的结构图；
图22为根据本公开一些实施例中的另一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例 时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，各电路所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，“节点”并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例提供的各电路所包括的晶体管，可以均为N型晶体管，也可以均为P型晶体管。或者，各电路所包括的晶体管中的一部分晶体管可以为N型晶体管，另一部分可以为P型晶体管。
在本公开中，“有效电平”指的是，可以使晶体管导通的电平。
下面，在本公开的实施例提供的各电路，以晶体管均为P型晶体管(此时有效电平为 低电平)为例进行说明。需要说明的是，下面提及的各电路中的晶体管采用相同的导通类型，可以简化工艺流程，减少工艺难度，提高产品(例如显示基板100及显示装置1000)的良率。
本公开的一些实施例提供了一种显示基板100、显示基板的驱动方法及显示装置1000，以下对显示基板100、显示基板的驱动方法及显示装置1000分别进行介绍。
本公开的一些实施例提供一种显示装置1000，如图21和图22所示。该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些实施例中，如图21所示，上述显示装置1000可以包括：至少一个显示基板100。也即，显示装置1000可以包括一个显示基板100，也可以包括多个显示基板100。
其中，如图21所示，在显示装置1000包括多个显示基板100的情况下，该多个显示基板100可以相互拼接，使得显示装置1000能够具有较大的屏幕尺寸。此时，上述显示基板100可以称为拼接显示基板，上述显示装置1000可以称为拼接显示装置。
当然，如图22所示，上述显示装置1000例如还可以包括：驱动芯片200以及其他电子配件等。
示例性的，驱动芯片200可以包括但不限于包括：用于提供数据信号的源极驱动电路或用于提供第一电压信号的电源电路等。
在一些实施例中，如图5所示，上述显示基板100可以包括：衬底1、多个子像素2、多条数据线DL及多条栅线GL。
上述衬底1的类型包括多种，可以根据是实际需要选择设置。
示例性的，衬底1可以为刚性衬底。该刚性衬底的材料例如可以包括玻璃、石英或塑料等。
示例性的，衬底1可以为柔性衬底。该柔性衬底的材料例如可以包括PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)或PI(Polyimide，聚酰亚胺)等。
在一些示例中，上述多个子像素2、多条数据线DL及多条栅线GL均设置在衬底1的一侧。其中，该多条数据线DL可以沿第一方向Y延伸，该多条栅线GL可以沿第二方向X延伸。每个子像素2与一条数据线DL及一条栅线GL电连接。
在一些示例中，如图5所示，上述多个子像素2可以沿第二方向X排列为多列，沿第一方向Y排列为多行。其中，任意相邻两列子像素所包括的子像素2的数量可以相等，也可以不相等；任意相邻两行子像素所包括的子像素2的数量可以相等，也可以不相等。
此处，第一方向Y和第二方向X相互交叉。第一方向Y和第二方向X之间的夹角可以根据实际需要选择设置。示例性的，第一方向Y和第二方向X之间的夹角可以为85°、88°、90°、92°或95°等。
示例性的，上述多个子像素2可以包括多种颜色子像素。例如，该多个子像素2可以包括：红色子像素、绿色子像素和蓝色子像素。当然，该多个子像素2例如还可以包括：白色子像素。在该多个子像素2包括红色子像素、绿色子像素和蓝色子像素的情况下，该三种子像素可以采用水平并列、竖直并列或品字型等方式排列。在包括该多个子像素2包括红色子像素、绿色子像素、蓝色子像素和白色子像素的情况下，该四种子像素可以采用水平并列、竖直并列或阵列等方式排列，本公开在此不做限定。
在一些示例中，如图5和图6所示，上述多个子像素2中，每个子像素2可以包括像素驱动电路21及与该像素驱动电路21电连接的发光器件22。像素驱动电路21可以提供驱动信号至发光器件22，驱动发光器件22发光。
此处，根据子像素的颜色类型，发光器件22可以发出不同颜色的光。
例如，红色子像素中的发光器件22可以发出红色光，绿色子像素中的发光器件22可以发出绿色光，蓝色子像素中的发光器件22可以发出蓝色光，白色子像素中的发光器件22可以发出白色光。
又如，红色子像素、绿色子像素、蓝色子像素和白色子像素中的发光器件22均可以发出蓝色光。此时，红色子像素、绿色子像素和白色子像素，可以分别通过配合色转材料(例如量子点、荧光粉等材料)，将蓝色光转换为红色光、绿色光和白色光，实现红、绿、蓝和白等相应颜色的出光。
也就是说，上述子像素2的排列方式，可以指的是，发光器件22的排列方式。
示例性的，上述发光器件22电流型驱动元件。该发光器件22的类型包括多种，可以根据实际需要选择设置。
例如，上述发光器件22可以为：微发光二极管(Micro Light Emitting Diodes，简称Micro LED)、迷你发光二极管(Mini Light Emitting Diodes，简称Mini LED)或发光二极管(Light Emitting Diodes，简称LED)等。
需要说明的是，在上述发光器件22发光的情况下，发光器件22所呈现的亮度，与其所接收的驱动信号(也即电流信号)的电流幅值及所接收的驱动信号的时长相关。
例如，在发光器件22所接收的驱动信号的时长为定值的情况下，驱动信号的电流幅值越大，则发光器件22所呈现的亮度越大，驱动信号的电流幅值越小，则发光器件22所呈现的亮度越小。在发光器件22所接收的驱动信号的电流幅值为定值的情况下，其所接收的驱动信号的时长越长，则所呈现的亮度越大，其所接收的驱动信号的时长越短，则所呈现的亮度越小。
然而，在具有较低电流密度的驱动信号(也即驱动信号的电流幅值较小)的驱动下，上述发光器件22容易出现色坐标漂移、外量子效率较低的情况，进而导致显示基板100出现亮度均一性较差的现象，也就是说，仅通过控制驱动信号的电流幅值大小难以准确显示低灰阶。因此，可以在控制驱动信号的电流幅值的基础上，控制向发光器件22提供的驱动信号的时间长度，来实现准确的低灰阶显示。
在一些示例中，如图5和图6所示，上述像素驱动电路21可以包括：电流控制电路211，及与电流控制电路211、发光器件22电连接的时长控制电路212。其中，电流控制电路211被配置为，生成驱动信号，以驱动发光器件22发光。时长控制电路212被配置为，生成时长控制信号，以控制电流控制电路211和发光器件22之间的导通时长。
示例性的，上述电流控制电路211能够生成驱动信号，发光器件22可以在该驱动信 号的作用下发光。其中，该驱动信号的电流幅值是可变的，相应的，发光器件22所发出的光的亮度也是可变的。通过调整电流控制电路211所生成的驱动信号的电流幅值，可以使得发光器件22显示不同的灰阶。
示例性的，时长控制电路212设置在电流控制电路211和发光器件22之间。时长控制电路212可以控制电流控制电路211和发光器件22之间是否导通。也即，在时长控制电路212未生成时长控制信号的情况下，电流控制电路211和发光器件22之间断开，未导通，即使电流控制电路211生成驱动信号，该驱动信号难以施加至发光器件22。
另外，时长控制电路212所生成的时长控制信号，可以控制电流控制电路211和发光器件22之间的导通时长。也即，在时长控制信号的电平为有效电平的情况下，电流控制电路211和发光器件22之间可以相互电连接，形成通路；在时长控制信号的电平为非有效电平的情况下，电流控制电路211和发光器件22之间断开。此处，时长控制信号的占空比是可变的，也就是说，时长控制信号的电平为有效电平的时长是可变的。通过调整时长控制信号的占空比，可以调整电流控制电路211和发光器件22之间的导通时长，进而可以调整发光器件22的发光时长，使得发光器件22显示不同的灰阶。
也就是说，本公开可以在利用电流控制电路211生成具有较高电流幅值的驱动信号的基础上，利用时长控制电路212生成的时长控制信号控制该驱动信号传输至发光器件22的时长，共同控制发光器件22所呈现的亮度，这样有利于提高显示基板100的亮度均一性，提高显示基板100的显示效果。
此处，上述驱动信号的较高电流幅值范围可以是在，发光器件22工作在发光效率高且稳定、色坐标均一度好且出光主波长稳定的范围内。因此，无论发光器件22所显示的灰阶是较高灰阶还是较低灰阶，驱动信号的电流幅值范围可以是相同的。
在一种实现方式中，如图1所示，子像素中像素驱动电路所电连接的数据信号端包括两类，也即，与电流控制电路电连接的电流数据信号端、及与时长控制电路电连接的时长数据信号端；电流控制电路可以根据电流数据信号端所传输的电流数据线号，控制驱动信号的电流幅值，时长控制电路可以根据时长数据信号端所传输的时长数据信号，选择时长控制信号的占空比。相应的，显示基板所包括的数据线可以包括：与电流数据信号端电连接的电流数据线DI、及与时长数据信号端电连接的时长数据线DT。其中，第i条电流数据线DI i和第i条时长数据线DT i分别位于第i列子像素的相对两侧，第i列子像素和第i+1列子像素之间则设置有两条数据线。该两条数据线例如可以为：第i条时长数据线DT i和第i+1条电流数据线DI i+1、或者第i条电流数据线DI i和第i+1条时长数据线DT i+1。n和i均为正整数。
以第i列子像素和第i+1列子像素之间设置有第i条时长数据线DT i和第i+1条电流数据线DI i+1为例。本公开的发明人发现，在将第i+1列子像素中某个子像素所需的电流数据信号写入至第i+1条电流数据线DI i+1后，第i+1条电流数据线DI i+1会处于浮置状态。在此过程中，写入至第i条时长数据线DT i的时长数据信号的电平可能会发生变化。此时，第i+1条电流数据线DI i+1中的电流数据信号会因该时长数据信号的电平的变化而发生跳变，这样会导致上述第i+1列子像素中某个子像素的电流控制电路所生成的驱动信号发生变化，进而导致上述第i+1列子像素中某个子像素所呈现的亮度发生变化，出现列向亮暗差异不良现象。
例如，写入至第i条时长数据线DT i的时长数据信号的电平，由高电平跳变为低电平， 相应的，第i+1条电流数据线DI i+1中的电流数据信号的电平会被拉低，导致上述第i+1列子像素中某个子像素的电流控制电路所生成的驱动信号的电流幅值增大，进而导致上述第i+1列子像素中某个子像素所呈现的亮度变大，出现列向亮暗差异不良现象。
基于此，在一些示例中，如图5所示，本公开所提供的子像素2中，电流控制电路211和时长控制电路212，与同一条数据线DL电连接。其中，与同一条数据线DL电连接的电流控制电路211和时长控制电路212，属于同一个子像素2的像素驱动电路21。
也即，在本公开中，同一个子像素2与同一条数据线DL电连接，该同一条数据线DL所传输的数据信号可以同时传输至电流控制电路211和时长控制电路212。
示例性的，由于同一个子像素2的电流控制电路211和时长控制电路212，接收相同的数据信号，因此，本公开可以将数据信号的有效电平，分时写入至电流控制电路211和时长控制电路212。
例如，写入至电流控制电路211的数据信号的有效电平可以称为第一有效电平，写入至时长控制电路212的数据信号的有效电平可以称为第二有效电平。在一帧显示阶段，可以先将具有第二有效电平的数据信号写入至时长控制电路212，使得时长控制电路212生成时长控制信号(该时长控制信号的占空比根据子像素2所需显示的灰阶而定)，然后可以将具有第一有效电平的数据信号写入至电流控制电路211，使得电流控制电路211生成驱动信号(该驱动信号的电流幅值根据子像素2所需显示的灰阶而定)。
由于本公开中同一子像素2与同一条数据线DL电连接，并将数据信号的有效电平，分时写入至电流控制电路211和时长控制电路212，这样可以使得与电流控制电路211相对应的写入及补偿阶段，及与时长控制电路212相对应的生成时长控制信号的阶段隔开，无重合，且数据信号的电平在各阶段基本无变化。这样可以有效避免相邻两条数据线DL之间产生信号串扰，避免出现因写入至时长控制电路212的数据信号的电平发生变化而导致写入至电流控制电路211的数据信号的电平发生跳变的情况，进而有利于改善列向亮暗差异不良现象。
由此，本公开的一些实施例所提供的显示基板100，通过将同一子像素2中像素驱动电路21所包括的电流控制电路211和时长控制电路212，与同一条数据线DL电连接，可以将数据信号的有效电平，分时写入至电流控制电路211和时长控制电路212。这样可以使得电流控制电路211生成驱动信号的阶段与时长控制电路212生成时长控制信号的阶段无重合，有利于确保各阶段数据信号的稳定性，避免相邻两条数据线DL之间产生信号串扰，进而避免因写入至时长控制电路212的数据信号的电平发生变化而导致写入至电流控制电路211的数据信号的电平发生跳变，有利于改善列向亮暗差异不良现象，提高显示基板100的显示效果。
另外，由于同一子像素2与同一条数据线DL电连接，这样可以有效减小数据线DL的数量，减小数据线DL所占的空间，增大显示基板100的布线空间。
需要说明的是，上述子像素2中电流控制电路211和时长控制电路212的结构包括多种，本公开以如图6和图7所示的结构进行示意性说明。当然，电流控制电路211和时长控制电路212的结构并不局限于本公开举例的结构。
在一些实施例中，如图6和图7所示，电流控制电路211至少与扫描信号端Gate、数据信号端Data、第一使能信号端EM、第一电压信号端VDD及第一节点N1电连接。其中，电流控制电路211被配置为，响应于在扫描信号端Gate处接收的扫描信号、在数据信号端 Data处接收的数据信号、在第一使能信号端EM处接收的第一使能信号及在第一电压信号端VDD处接收的第一电压信号，生成驱动信号。时长控制电路212至少与数据信号端Data、第一复位信号端Res_A、第二复位信号端Res_B、第一使能信号端EM、第二使能信号端Hf、第一节点N1及发光器件22电连接。其中，时长控制电路212被配置为，响应于数据信号和在第一复位信号端Res_A处接收的第一复位信号，根据在第二使能信号端EM处接收的第二使能信号控制第一节点N1和发光器件22之间的导通时长；或，响应于数据信号和在第二复位信号端Res_B处接收的第二复位信号，根据在第一使能信号，控制第一节点N1和发光器件22之间的导通时长。也即，时长控制信号为第一使能信号或第二使能信号。
在一些示例中，如图6和图7所示，发光器件22的阳极与第一节点N1电连接，发光器件22的阴极与第二电压信号端VSS电连接。
在一些示例中，第一电压信号端VDD被配置为传输直流高电平信号，本文将该直流高电平信号称为第一电压信号。第二电压信号端VSS被配置为传输直流低电平信号，本文将该直流低电平信号称为第二电压信号。本文中的“高电平”和“低电平”是相对而言的，并不因此限定电压值的大小。
在一些示例中，第二使能信号端Hf所传输的第二使能信号为高频脉冲信号。示例性的，在一帧显示阶段内，第二使能信号包括多个脉冲。例如，第二使能信号的频率大于第一使能信号的频率。例如，在单位时间内，第二使能信号中出现有效电平的时间段的次数，大于第一使能信号中出现有效电平的时间段的次数。
示例性的，在传输第二使能信号的过程中，第二使能信号可以同时传输至显示基板100所包括的多个子像素2。第二使能信号的频率例如可以根据显示基板100所包括的子像素行数进行划分。例如，显示基板100的帧频率为60Hz，也即，在1s的时间段内，显示基板100可以显示60帧图像，且每帧图像的显示时长相等。在每帧显示阶段内，例如每隔4行或5行子像素的刷新时间，第二使能信号中出现一次有效电平。
此处，通过控制时长控制信号的频率，可以控制电流控制电路211和发光器件22之间的导通频率，通过控制时长控制信号的占空比，可以控制电流控制电路211和发光器件22之间的导通时长。在一帧显示阶段的发光阶段，控制电流控制电路211和发光器件22之间的导通频率及每次导通时的导通时长，决定了发光器件22发光的总时长(也即多次导通的时长之和)。
在发光器件22所显示的灰阶大于或等于阈值灰阶的情况下，时长控制电路212可以将第一使能信号作为时长控制信号，使得在发光阶段，电流控制电路211和发光器件22之间一直处于导通状态，像素驱动电路21与发光器件22之间一直形成导电通路。此时，电流控制电路211生成的驱动信号可以持续传输至发光器件22，进而可以实现较高灰阶的显示。
在发光器件22所显示的灰阶小于阈值灰阶的情况下，时长控制电路212可以将第二使能信号作为时长控制信号，使得在发光阶段，电流控制电路211和发光器件22之间在第二使能信号的高频脉冲信号的控制下处于导通和截止交替的状态。此时，电流控制电路211生成的驱动信号可以间歇性地传输至发光器件22，使得发光器件22周期性地接收驱动信号。例如，发光器件22接收一段时间驱动信号后停止一段时间，再接收一段时间驱动信号后停止一段时间。这样，像素驱动电路21与发光器件22之间形成导电通路的时间被缩短，驱动信号传输至发光器件22的时间被缩短，发光器件22发光的总时长被缩短， 进而实现较低灰阶的显示。
在本公开的一些示例中，同一子像素2中的电流控制电路211和时长控制电路212，均通过数据信号端Data与同一数据线DL电连接。也即，电流控制电路211和时长控制电路212，均与同一数据信号端Data电连接，并通过该数据信号端Data与同一数据线DL电连接。该数据线DL所传输的数据信号，可以经该数据信号端Data同时传输至电流控制电路211和时长控制电路212。
在上述一种实现方式中，如图1所示，设置有多路输出选择电路4＇，该多路输出选择电路4＇分别与多条电流数据线DI、多条时长数据线DT、第一电流选择信号线DI_MUX 1、第二电流选择信号线DI_MUX 2、第一时长选择信号线DT_MUX 1及第二时长选择信号线DT_MUX 2电连接。其中，多路输出选择电路4＇在第一电流选择信号和第二电流选择信号的控制下，将电流数据信号分时传输至电流数据线DI，并可以在第一时长选择信号和第二时长选择信号的控制下，将时长数据信号传输至时长数据线DT。
在图2中，DI_MUX 2表示为第二电流选择信号，DT_MUX 1表示为第一时长选择信号，Gate表示第n行子像素所接收的扫描信号，DT i(低于阈值灰阶)表示为第n行第i列子像素在显示灰阶小于阈值灰阶的情况下所接收的时长数据信号，DT i(高于阈值灰阶)表示为第n行第i列子像素在显示灰阶大于阈值灰阶的情况下所接收的时长数据信号，DI i+1表示为第n行第i+1列子像素所接收的电流数据信号。
在上述一种实现方式中，电流控制电路和时长控制电路均与扫描信号端电连接。从图2中可以看出，对于同一行子像素中的相邻两个子像素而言，与其中一个子像素的电流控制电路相对应的写入及补偿阶段，及与另一个子像素的时长控制电路相对应的生成时长控制信号的阶段会具有重合。在扫描信号为有效电平(也即低电平)的阶段，电流数据信号随第二电流选择信号写入至第i+1条电流数据线DI i+1后，第二电流选择信号的电平变为非有效电平，使得第i+1条电流数据线DI i+1处于浮置状态。在生成时长控制信号的阶段，第一时长选择信号的电平变为有效电平后，时长数据信号随第一时长选择信号写入至第i条时长数据线DT i。在第n行第i列子像素所显示的灰阶为高于阈值灰阶的情况下，时长数据信号的电平会由高电平跳变为低电平，相应的，第i+1条电流数据线DI i+1中的电流数据信号的电平会被拉低，进而导致上述第n行第i+1列子像素所呈现的亮度变大，出现列向亮暗差异不良现象。
而本公开中，仅将电流控制电路211和扫描信号端Gate电连接，将时长控制电路212与其他的信号端电连接，并将电流控制电路211和时长控制电路212，均与同一数据线DL电连接，可以在分时写入数据信号的有效电平同时，确保与某一子像素2的电流控制电路211相对应的写入及补偿阶段，及与另一子像素2(该子像素2与上述某一子像素2位于同一行且相邻)的时长控制电路212生成时长控制信号的阶段无重合。这样可以进一步避免相邻两条数据线DL之间产生信号串扰，避免出现因写入至某一子像素2的时长控制电路212的数据信号的电平发生变化，而导致写入至另一子像素2的电流控制电路211的数据信号的电平发生跳变的情况，进而有利于改善列向亮暗差异不良现象。
在一些实施例中，如图10和图11所示，上述第一复位信号和第二复位信号的有效电平时间不重合。上述数据信号中，与第一复位信号的有效电平相对应的电平、及与第二复位信号的有效电平相对应的电平中的一者，为有效电平。
也就是说，在第一复位信号的电平为有效电平的阶段，数据信号的电平可以为有效电 平，也可以为非有效电平。在第二复位信号的电平为有效电平的阶段，数据信号的电平可以为有效电平，也可以为非有效电平。但是，在第一复位信号的电平为有效电平的阶段及第二复位信号的电平为有效电平的阶段中，数据信号的电平相反。
相应的，第一复位信号、第二复位信号及数据信号的有效电平之间的关系可以包括两种。其中一种关系为：在第一复位信号的电平为有效电平的阶段，数据信号的电平为有效电平，在第二复位信号的电平为有效电平的阶段，数据信号的电平为非有效电平。另一种关系为：在第一复位信号的电平为有效电平的阶段，数据信号的电平为非有效电平，在第二复位信号的电平为有效电平的阶段，数据信号的电平为有效电平。
需要说明的是，本公开不对第一复位信号的电平为有效电平的阶段及第二复位信号的电平为有效电平的阶段的先后顺序做限定，可以根据实际需要选择设置。
对于同一子像素2，通过采用上述设置方式设置第一复位信号、第二复位信号及数据信号，可以在生成时长控制信号的阶段，使得时长控制电路212仅在数据信号和第一复位信号的共同控制下，将第二使能信号作为时长控制信号，或者仅在数据信号和第二复位信号的共同控制下，将第一使能信号作为时长控制信号。这样有利于确保时长控制电路212的工作性能，确保时长控制电路212能够仅选择第一使能信号和第二使能信号中的一者作为时长控制信号，提高信号选择的稳定性，进而提高对发光器件22所显示灰阶的控制性。
在一些实施例中，如图6所示，时长控制电路212包括：第一控制子电路2121、第二控制子电路2122和第三控制子电路2123。
在一些示例中，如图6所示，第一控制子电路2121至少与数据信号端Data、第一复位信号端Res_A、第二使能信号端Hf及第二节点N2电连接。其中，第一控制子电路2121被配置为，响应于数据信号和第一复位信号，将第二使能信号传输至第二节点N2。
示例性的，在数据信号的电平为有效电平且第一复位信号的电平为有效电平的情况下，第一控制子电路2121可以在数据信号和第一复位信号的控制下，将第二使能信号作为时长控制信号传输至第二节点N2。
在一些示例中，如图6所示，第二控制子电路2122至少与数据信号端Data、第二复位信号端Res_B、第一使能信号端EM及第二节点N2电连接。其中，第二控制子电路2122被配置为，响应于数据信号和第二复位信号，将第一使能信号传输至第二节点N2。
示例性的，在数据信号的电平为有效电平且第二复位信号的电平为有效电平的情况下，第二控制子电路2122可以在数据信号和第二复位信号的控制下，将第一使能信号作为时长控制信号传输至第二节点N2。
在一些示例中，如图6所示，第三控制子电路2123与第一节点N1、第二节点N2及发光器件22电连接。其中，第三控制子电路2123被配置为，在来自第二节点N2的信号的控制下，控制第一节点N1和发光器件22之间的导通时长。
示例性的，在第一控制子电路2121将第二使能信号传输至第二节点N2的情况下，第三控制子电路2123可以在第二使能信号的控制下，将第一节点N1和发光器件22之间的导通。由于第二使能信号为高频脉冲信号，因此，第一节点N1和发光器件22之间会处于导通和截止交替的状态，第一节点N1和发光器件22之间的导通时长则为多次导通状态而定总时长。
在第二控制子电路2122将第一使能信号传输至第二节点N2的情况下，第三控制子电路2123可以在第一使能信号的控制下，将第一节点N1和发光器件22之间的导通。其中， 在发光阶段，第一节点N1和发光器件22之间可以一直导通。
此处，基于第一复位信号、第二复位信号及数据信号之间的有效电平的设置方式，在生成时长控制信号的阶段，可以仅使得第一控制子电路2121和第二控制子电路2122中的一者工作，进而可以实现时长控制信号的选择，避免出现第一控制子电路2121和第二控制子电路2122同时工作、导致发光器件22所显示灰阶异常的情况。
在一些实施例中，如图6所示，电流控制电路211包括：数据写入子电路2111、驱动子电路2112、补偿子电路2113和发光控制子电路2114。
在一些示例中，如图6所示，数据写入子电路2111与扫描信号端Gate、数据信号端Data及第五节点N5电连接。其中，数据写入子电路2111被配置为，在扫描信号的控制下，将数据信号传输至第五节点N5。
示例性的，在扫描信号的电平为有效电平的情况下，数据写入子电路2111可以在扫描信号的控制下导通，接收并传输数据信号至第五节点N5。
在一些示例中，如图6所示，驱动子电路2112至少与第一节点N1、第五节点N5及第六节点N6电连接。其中，驱动子电路2112被配置为，在第六节点N6的电压的控制下，将来自第五节点N5的信号传输至第一节点N1。
示例性的，来自第五节点N5的信号可以为，数据写入子电路2111所传输的数据信号。在第六节点N6的电压为有效电平的情况下，驱动子电路2112可以在第六节点N6的电压的控制下导通，将来自第五节点N5的信号传输至第一节点N1。
在一些示例中，如图6所示，补偿子电路2113与扫描信号端Gate、第一节点N1及第六节点N6电连接。其中，补偿子电路2113被配置为，在扫描信号的控制下，将来自第一节点N1的信号传输至第六节点N6，以对驱动子电路2112进行阈值电压的补偿。
示例性的，来自第一节点N1的信号可以为，数据写入子电路2111所传输的数据信号。在扫描信号的电平为有效电平的情况下，补偿子电路2113可以在扫描信号的控制下导通，将来自第一节点N1的信号传输至第六节点N6，以对驱动子电路2112进行阈值电压的补偿。
由于数据写入子电路2111和补偿子电路2113均与扫描信号端Gate电连接，因此，数据写入子电路2111和补偿子电路2113可以同时在扫描信号的控制下导通。数据信号端Data所传输的数据信号便可以依次经数据写入子电路2111、驱动子电路2112、补偿子电路2113传输至第六节点N6，直至驱动子电路2112截止，完成对驱动子电路2112的阈值电压的补偿。
在一些示例中，如图6所示，发光控制子电路2114与第一使能信号端EM、第一电压信号端VDD及第五节点N5电连接。其中，发光控制子电路2114被配置为，在第一使能信号的控制下，将第一电压信号传输至第五节点N5。
示例性的，在第一使能信号的电平为有效电平的情况下，发光控制子电路2114可以在第一使能信号的控制下导通，接收并传输第一电压信号至第五节点N5。
此处，在时长控制信号控制第一节点N1和发光器件22之间的导通的情况下，驱动子电路2112可以根据来自第五节点N5的第一电压信号及写入至第六节点N6的数据信号，生成驱动信号，并将该驱动信号传输至发光器件22，驱动发光器件22发光。
由于数据信号分时写入至电流控制电路211和时长控制电路212，且数据写入子电路2111与扫描信号端Gate电连接，第一控制子电路2121与第一复位信号端Res_A电连接， 第二控制子电路2122与第二复位信号端Res_B电连接，因此，扫描信号的有效电平时间，与第一复位信号、第二复位信号的有效电平时间均不重合。这样也就可以使得对驱动子电路2112进行阈值电压补偿的阶段，及第一控制子电路2121、第二控制子电路2122选择时长控制信号的阶段不重合，有利于避免相邻两条数据线DL之间产生信号串扰，避免出现因写入至时长控制电路212的数据信号的电平发生变化而导致写入至驱动子电路2112的数据信号的电平发生跳变的情况，进而有利于改善列向亮暗差异不良现象。
在一些实施例中，如图6所示，电流控制电路211还包括：复位子电路2115。
在一些示例中，如图6所示，复位子电路2115与第一复位信号端Res_A、初始信号端Vinit、第六节点N6及发光器件22电连接。其中，复位子电路2115被配置为，响应于第一复位信号，将在初始信号端Vinit处接收的初始信号传输至第六节点N6及发光器件22。
示例性的，复位子电路2115与发光器件22的阳极电连接。初始信号端Vinit所传输的初始信号可以为直流低电平信号。
示例性的，在第一复位信号的电平为有效电平的情况下，复位子电路2115可以在第一复位信号的控制下导通，接收并传输初始信号传输至第六节点N6及发光器件22的阳极，对第六节点N6及发光器件22的阳极进行复位。
通过设置复位子电路2115，可以为第六节点N6及发光器件22的阳极提供基准电压，消除上一帧显示过程中残留的电荷，提高像素驱动电路21的可控性。
下面结合图7对电流控制电路211所包括的各子电路及时长控制电路212所包括的各子电路的结构进行示意性说明，当然，电流控制电路211所包括的各子电路及时长控制电路212所包括的各子电路的结构并不局限于此。
在一些示例中，如图7所示，上述第一控制子电路2121包括：第一晶体管T1、第二晶体管T2和第一电容器C1。
示例性的，如图7所示，第一晶体管T1的控制极与第一复位信号端Res_A电连接，第一晶体管T1的第一极与数据信号端Data电连接，第一晶体管T1的第二极与第三节点N3电连接。
例如，在第一复位信号的电平为有效电平(也即低电平)的情况下，第一晶体管T1可以在第一复位信号的控制下导通，接收并传输数据信号至第三节点N3。
示例性的，如图7所示，第二晶体管T2的控制极与第三节点N3电连接，第二晶体管T2的第一极与第二使能信号端Hf电连接，第二晶体管T2的第二极与第二节点N2电连接。
例如，第三节点N3的电压由数据信号的电平而定。在传输至第三节点N3的数据信号的电平为低电平的情况下，第三节点N3的电压则为低电平，第二晶体管T2可以在第三节点N3的电平的控制下导通，将第二使能信号作为时长控制信号，接收并传输至第二节点N2。
示例性的，如图7所示，第一电容器C1的第一极与初始信号端Vinit电连接，第一电容器C1的第二极与第三节点N3电连接。
第一电容器C1具有存储功能，可以对传输至第三节点N3的数据信号进行存储。
例如，在上述数据信号的电平为非有效电平(也即高电平)的情况下，第三节点N3的电压则为高电平，第二晶体管T2可以在该第三节点N3的电压的控制下关断。在第一晶体管T1关断后，第一电容器C1可以进行放电，使得第三节点N3的电压维持为高电平，进而使得第二晶体管T2保持为关断状态。
又如，在上述数据信号的电平为低电平的情况下，第三节点N3的电压则为低电平，第二晶体管T2可以在该第三节点N3的电压的控制下导通。在第一晶体管T1关断后，第一电容器C1可以进行放电，使得第三节点N3的电压维持为低电平，进而使得第二晶体管T2保持为导通状态，持续传输第二使能信号至第二节点N2。
在一些示例中，如图7所示，第二控制子电路2122包括：第三晶体管T3、第四晶体管T4和第二电容器C2。
示例性的，如图7所示，第三晶体管T3的控制极与第二复位信号端Res_B电连接，第三晶体管T3的第一极与数据信号端Data电连接，第三晶体管T3的第二极与第四节点N4电连接。
例如，在第二复位信号的电平为低电平的情况下，第三晶体管T3可以在第二复位信号的控制下导通，接收并传输数据信号至第四节点N4。
示例性的，如图7所示，第四晶体管T4的控制极与第四节点N4电连接，第四晶体管T4的第一极与第一使能信号端EM电连接，第四晶体管T4的第二极与第二节点N2电连接。
例如，第四节点N4的电压由数据信号的电平而定。在传输至第四节点N4的数据信号的电平为低电平的情况下，第四节点N4的电压则为低电平，第四晶体管T4可以在第四节点N4的电平的控制下导通，将第一使能信号作为时长控制信号，接收并传输至第二节点N2。
示例性的，如图7所示，第二电容器C2的第一极与初始信号端Vinit电连接，第二电容器C2的第二极与第四节点N4电连接。
第二电容器C2具有存储功能，可以对传输至第四节点N4的数据信号进行存储。
例如，在上述数据信号的电平为高电平的情况下，第四节点N4的电压则为高电平，第四晶体管T4可以在该第四节点N4的电压的控制下关断。在第三晶体管T3关断后，第二电容器C2可以进行放电，使得第四节点N4的电压维持为高电平，进而使得第四晶体管T4保持为关断状态。
又如，在上述数据信号的电平为低电平的情况下，第四节点N4的电压则为低电平，第四晶体管T4可以在该第四节点N4的电压的控制下导通。在第三晶体管T3关断后，第二电容器C2可以进行放电，使得第四节点N4的电压维持为低电平，进而使得第四晶体管T4保持为导通状态，持续传输第一使能信号至第二节点N2。
此处，基于第一复位信号、第二复位信号及数据信号之间的有效电平的设置方式，在生成时长控制信号的阶段，可以仅使得第二晶体管T2导通、并将第二使能信号作为时长控制信号传输至第二节点N2，或者仅使得第四晶体管T4导通、并将第一使能信号作为时长控制信号传输至第二节点N2，这样便可以实现时长控制信号的选择，避免出现第二晶体管T2和第四晶体管T4同时导通、导致发光器件22所显示灰阶异常的情况。
在一些示例中，如图7所示，第三控制子电路2123包括：第五晶体管T5。
示例性的，如图7所示，第五晶体管T5的控制极与第二节点N2电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与发光器件22电连接。
例如，在第二晶体管T2将第二使能信号传输至第二节点N2的情况下，由于第二使能信号为高频脉冲信号，因此，第五晶体管T5可以在第二使能信号的控制下，交替地导通、关断，进而使得第一节点N1和发光器件22之间会处于导通和截止交替的状态。
又如，在第四晶体管T4将第一使能信号传输至第二节点N2的情况下，第五晶体管T5可以在第一使能信号的控制下保持持续导通的状态，使得第一节点N1和发光器件22之间可以一直导通。
在一些示例中，如图7所示，数据写入子电路2111包括：第六晶体管T6。
示例性的，如图7所示，第六晶体管T6的控制极与扫描信号端Gate电连接，第六晶体管T6的第一极与数据信号端Date电连接，第六晶体管T6的第二极与第五节点N5电连接。
例如，在扫描信号的电平为低电平的情况下，第六晶体管T6可以在扫描信号的控制下导通，接收并传输数据信号至第五节点N5。
在一些示例中，如图7所示，驱动子电路2112包括：第七晶体管T7和第三电容器C3。
示例性的，如图7所示，第七晶体管T7的控制极与第六节点N6电连接，第七晶体管T7的第一极与第五节点N5电连接，第七晶体管T7的第二极与第一节点N1电连接。
例如，在第六节点N6的电平为低电平的情况下，第七晶体管T7可以在第六节点N6的电压的控制下导通，将来自第五节点N5的数据信号传输至第一节点N1。
示例性的，如图7所示，第三电容器C3的第一极与第六节点N6电连接，第三电容器C3的第二极与第一电压信号端VDD电连接。
例如，第三电容器C3具有存储功能，可以对传输至第六节点N6的信号进行存储，还可以放电维持第六节点N6的电平。
在一些示例中，如图7所示，补偿子电路2113包括：第八晶体管T8。
示例性的，如图7所示，第八晶体管T8的控制极与扫描信号端Gate电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第六节点N6电连接。
例如，在扫描信号的电平为低电平的情况下，第八晶体管T8可以在扫描信号的控制下导通，将来自第一节点N1的数据信号传输至第六节点N6，直至第七晶体管T7截止，完成对第七晶体管T7的阈值电压的补偿。
此处，在第八晶体管T8关断后，第三电容器C3可以进行放电，维持第六节点N6的电压。
在一些示例中，如图7所示，发光控制子电路2114包括：第九晶体管T9。
示例性的，如图7所示，第九晶体管T9的控制极与第一使能信号端EM电连接，第九晶体管T9的第一极与第一电压信号端VDD电连接，第九晶体管T9的第二极与第五节点N5电连接。
例如，在第一使能信号的电平为低电平的情况下，第九晶体管T9可以在第一使能信号的控制下导通，接收并传输第一电压信号至第五节点N5。
在一些示例中，如图7所示，复位子电路2115包括：第十晶体管T10和第十一晶体管T11。
示例性的，如图7所示，第十晶体管T10的控制极与第一复位信号端Res_A电连接，第十晶体管T10的第一极与初始信号端Vinit电连接，第十晶体管T10的第二极与第六节点N6电连接。第十一晶体管T11的控制极与第一复位信号端Res_A电连接，第十一晶体管T11的第一极与初始信号端Vinit电连接，第十一晶体管T11的第二极与发光器件22电连接。
例如，在第一复位信号的电平为低电平的情况下，第十晶体管T10和第十一晶体管T11可以在第一复位信号的控制下同时导通，第十晶体管T10可以接收并传输初始信号至第六节点N6，对第六节点N6进行复位；第十一晶体管T11可以接收并传输初始信号至发光器件22，对发光器件22进行复位。
在一些实施例中，如图8和图9所示，上述显示基板100还可以包括：设置在像素驱动电路21远离衬底1一侧的多个焊盘P。该多个焊盘P包括多个阳极焊盘P1和多个阴极焊盘P2，一个阳极焊盘P1和一个阴极焊盘P2可以构成一个焊盘对。其中，一个像素驱动电路21可以与至少一个焊盘对相对应。
在一些示例中，上述显示基板100还可以包括：多条第二电压信号线。其中，每个焊盘对中，阳极焊盘P1可以与一个像素驱动电路21中的复位子电路2115及第三控制子电路2123的一端电连接，接收复位子电路2115所传输的初始信号及第三控制子电路2123所传输的驱动信号；阴极焊盘P2可以与一条第二电压信号线电连接，接收第二电压信号线所传输的第二电压信号。阴极焊盘P2例如可以作为第二电压信号端VSS。
如图8和图9所示，以一个像素驱动电路21与一个焊盘对相对应、且显示基板100所包括的多个子像素2包括红色子像素、绿色子像素和蓝色子像素为例。其中，一个红色子像素、一个绿色子像素和一个蓝色子像素，例如可以构成一个像素单元(如图8和图9中虚线框所示)。
在一些示例中，与上述像素驱动电路21电连接的发光器件22，可以包括阳极电极引脚和阴极电极引脚。其中，阳极电极引脚可以与该焊盘对中的阳极焊盘P1进行绑定，实现与复位子电路2115及第三控制子电路2123之间的电连接，阴极电极引脚可以与该焊盘对中的阴极焊盘P2进行绑定，实现与第二电压信号端VSS之间的电连接。
示例性的，如图8和图9所示，上述多个焊盘P在衬底1上的正投影，与各像素驱动电路21中第七晶体管T7在衬底1上的正投影，无重叠。这样在将发光器件22与相应的焊盘进行绑定、并施加压力的过程中，可以避免对第七晶体管T7造成不良影响，确保第七晶体管T7具有较好的驱动性能。
示例性的，发光器件22的结构类型包括多种，可以根据实际需要选择设置。例如，发光器件22的结构类型可以为正装结构、垂直结构或者倒装结构。
此处，各焊盘对的排列方式包括多种，能够满足各像素单元(在宏观上可视的像素单元是由像素单元中的发光器件构成)之间的间距要求(此处的间距要求例如指的是，宏观上可视的像素单元之间的间距)及发光器件22与焊盘对之间的绑定能力即可。
示例性的，各焊盘对的排列方式，与各子像素中发光器件22的排列方式相同。
例如，各像素单元中，发光器件22采用品字型的方式排列。相应的，如图8所示，与各像素单元相对应的焊盘对可以采用品字型的方式排列。此时，同一像素单元中，各焊盘对的中心，构成三角形(例如为锐角三角形)。这样有利于确保任意相邻两个焊盘对之间具有较大间距，进而使得任意相邻两个发光器件22之间具有较大间距，既能够满足各像素单元之间的间距要求，又能够降低对发光器件22进行绑定的难度。
又如，各像素单元中，发光器件22采用水平并列的方式排列。相应的，如图9所示，与各像素单元相对应的焊盘对可以采用水平并列的方式排列。
可以理解的是，在本公开的示例中，如图8和图9所示，任意相邻的三行子像素，分别为第2N-1行子像素、第2N行子像素和第2N+1行子像素。第2N-1行子像素和第2N行 子像素之间的区域为第一间隙区域GA1，第2N行子像素和第2N+1行子像素之间的区域为第二间隙区域GA2。其中，第2N-1行子像素和第2N行子像素中，像素驱动电路21更靠近第一间隙区域GA1；第2N行子像素和第2N+1行子像素中，像素驱动电路21更远离第二间隙区域GA2。N为正整数。
例如，第2N-1行子像素和第2N行子像素中，各像素驱动电路21关于第一间隙区域GA1对称设置，且各像素驱动电路21更靠近第一间隙区域GA1，各焊盘对更远离第一间隙区域GA1。第2N行子像素和第2N+1行子像素中，各像素驱动电路21关于第一间隙区域GA2对称设置，且各像素驱动电路21更远离第二间隙区域GA2，各焊盘对更靠近第二间隙区域GA2。
示例性的，沿第一方向Y，第二间隙区域GA2的尺寸大于第一间隙区域GA1的尺寸。
这样可以在满足各像素单元之间的间距要求的前提下，提高各像素单元的分布均匀性，实现像素驱动电路21的紧凑排布，有效利用布线空间。
例如，同一行像素单元中，任意相邻两个像素单元之间的间距相等。同一列像素单元中，任意相邻连个像素单元之间的间距相等。
需要说明的是，本示例仅对各子像素中的像素驱动电路和焊盘对的位置进行了限定，并未对像素驱动电路21中的具体结构是否对称进行限定。由于像素驱动电路21包括多个膜层，在制备该多个膜层的过程中，可能会因为工艺误差等不可避免的原因导致不同像素驱动电路21所包括的膜层尺寸之间具有差异。这样也就不能使得第2N-1行子像素中的像素驱动电路21和第2N行子像素中的像素驱动电路21关于第一间隙区域GA1严格对称设置，不能使得第2N行子像素中的像素驱动电路21和第2N+1行子像素中的像素驱动电路21关于第二间隙区域GA2严格对称设置。
在一些实施例中，如图12、图13、图16和图17所示，同一条数据线DL与至少一列子像素电连接。
在一些示例中，如图12和图13所示，一条数据线DL可以与一列子像素电连接，也即，两者一一对应。数据线DL的条数和子像素的列数相等。此时，各数据线DL所传输的数据信号仅写入至相应的一列子像素。
在另一些示例中，如图16和图17所示，一条数据线DL可以与多列子像素电连接。数据线DL的条数小于子像素的列数。此时，各数据线DL所传输的数据信号可以分时写入至相应的多列子像素。
此处，通过将同一条数据线DL与至少一列子像素电连接，有利于减小数据线DL的数量，减小数据线DL所占的空间，增大显示基板100的布线空间。
在一些实施例中，如图12、图13、图16和图17所示，任意相邻两条数据线DL之间，设置有至少一列子像素。
在一些示例中，如图12和图13所示，任意相邻两条数据线DL之间，设置有一列子像素。相应的，各条数据线DL可以与一列子像素电连接。
在另一些示例中，如图16和图17所示，任意相邻两条数据线DL之间，设置有多列子像素。相应的，各条数据线DL可以与多列子像素电连接。
需要说明的是，在相邻两条数据线DL之间未设置子像素的情况下，需要使得该相邻两条数据线DL之间具有较大的间距，避免在两者之间形成寄生电容。但是，这样容易增大数据线DL在显示基板100中所占据的空间，增大布线难度。
本公开通过在任意相邻两条数据线DL之间设置有至少一列子像素，可以利用该至少一列子像素将任意相邻两条数据线DL隔开。这样不仅有利于减小数据线DL在显示基板100中所占据的空间，降低布线难度，还可以避免相邻两条数据线DL之间产生信号串扰，有利于确保各数据线DL所传输的数据信号的准确性。
在一些实施例中，如图19和图20所示，显示基板100还包括：设置在衬底1的边缘的多条连接配线3。其中，显示基板100所包括的多个子像素2可以设置在衬底1的一侧，显示装置1000所包括的驱动芯片200可以设置在衬底1的另一侧。
在一些示例中，各连接配线3可以呈U型。连接配线3的一端可以位于衬底1的一侧，并与至少一条数据线DL电连接(例如包括直接电连接或间接电连接)，连接配线3的另一端可以延伸至衬底1的另一侧。如图22所示，连接配线3的另一端可以与驱动芯片200电连接。该驱动芯片200例如可提供数据信号至连接配线3，连接配线3可以将该数据信号传输至相应的数据线DL。
示例性的，上述设置方式可以称为侧边走线的方式。
通过采用侧边走线的方式对子像素2和驱动芯片200进行电连接，有利于减小显示基板100的边框的尺寸，便于实现窄边框甚至无边框设计。
另外，在显示装置1000由多个显示基板100拼接而成的情况下，通过采用侧边走线的方式对显示基板100进行拼接，可以有效减小拼缝的尺寸，甚至实现无拼缝拼接，进而有利于实现窄边框甚至无边框设计。
由于本公开提供的显示基板100中具有较少数量的数据线DL，这样可以相应减小连接配线3的数量，进而有利于提高侧边走线的工艺良率，提高显示基板100及显示装置1000的良率。
此外，在一条数据线DL与多列子像素电连接的情况下，可以进一步减小连接配线3的数量，有利于进一步提高侧边走线的工艺良率，进一步提高显示基板100及显示装置1000的良率。
需要说明的是，在采用侧边走线的方式的情况下，有效减小连接配线3的数量的设置方式可以有多种，具体可以根据实际需要选择设置。另外，该多种设置方式包括但不限于本公开举例的方式。
在一种示例性实施例中，如图12和图13所示，上述显示基板100还包括：多路输出选择电路4、多条数据传输线DTL和多条选择信号线Mux。
在一些示例中，上述多路输出选择电路4可以与子像素2位于衬底1的同一侧。该多路输出选择电路4可以与显示基板100所包括的多条数据线DL电连接。
在一些示例中，上述多条数据传输线DTL可以与子像素2位于衬底1的同一侧。该多条数据传输线DTL可以沿第一方向Y延伸，并与上述多路输出选择电路4电连接。当然，每条数据传输线DTL的一部分可以沿第一方向Y延伸，另一部分可以沿第二方向X延伸。
在一些示例中，上述多条选择信号线Mux可以与子像素2位于衬底1的同一侧。该多条选择信号线Mux可以沿第二方向X延伸，并与上述多路输出选择电路4电连接。当然，每条选择信号线Mux的一部分可以沿第一方向Y延伸，另一部分可以沿第二方向X延伸。
在一些示例中，上述多路输出选择电路4被配置为，在上述多条选择信号线Mux所传输的选择信号的控制下，将上述多条数据传输线DTL所传输的数据信号，分时传输至上述多条数据线DL。
需要说明的是，数据传输线DTL的数量少于数据线DL的数量，一条数据传输线DTL与多条数据线DL相对应。上述多路输出选择电路4具有选择功能，在选择控制信号的作用下，多路输出选择电路4可以将每条数据传输线DTL所传输的数据信号，在某一时间段内，仅传输至相对应的多条数据线DL中的某一条数据线DL，然后在下一时间段内，仅传输至相对应的多条数据线DL中的另一条数据线DL。
在此情况下，上述多条数据线DL可以通过上述多条数据传输线DTL，与生成数据信号的源极驱动电路(例如可以为上述驱动芯片200)电连接。由于数据传输线DTL的数量少于数据线DL的数量，因此，可以减小用于与驱动芯片200电连接的引脚的数量，有利于提高与该引脚电连接的良率，提高显示装置1000的良率。
另外，在显示基板100包括连接配线3的情况下，各连接配线3位于衬底1一侧的一端可以与一条数据传输线DTL电连接，从而可以依次通过该数据传输线DTL、多路输出选择电路4与相应的多条数据线DL电连接。
由于数据传输线DTL的数量少于数据线DL的数量，因此，可以减小连接配线3的数量，这样可以有效提高侧边走线的良率。
在一些实施例中，如图12和图13所示，上述多条数据线DL至少包括：多条第一数据线DL 1、多条第二数据线DL 2和多条第三数据线DL 3。上述多条数据传输线DTL至少包括：多条第一数据传输线DTL 1、多条第二数据传输线DTL 2和多条第三数据传输线DTL 3。其中，上述多路输出选择电路4可以包括：多个选择晶体管组41。选择晶体管组41可以与选择信号线Mux、第一数据线DL 1、第二数据线DL 2及第三数据线DL 3电连接。
示例性的，每个选择晶体管组41可以与一条选择信号线Mux、一条第一数据线DL 1、一条第二数据线DL 2及一条第三数据线DL 3电连接。
在一些示例中，如图13所示，第一数据传输线DTL 1与至少两个选择晶体管组41电连接，并通过该至少两个选择晶体管组41与相应的第一数据线DL 1电连接。
由于每个选择晶体管组41可以与一条选择信号线Mux及一条第一数据线DL 1电连接，因此，每条第一数据传输线DTL 1可以与至少两条选择信号线Mux及至少两条第一数据线DL 1相对应。第一数据传输线DTL 1所传输的数据信号，可以在其中一条选择信号线Mux所传输的选择信号的控制下，传输至相应的一条第一数据线DL 1，并在另一条选择信号线Mux所传输的选择信号的控制下，传输至相应的另一条第一数据线DL 1，实现第一数据传输线DTL 1所传输的数据信号的分时写入。
示例性的，第一数据传输线DTL 1可以与两个、三个、四个或六个选择晶体管组41等电连接，相应的，第一数据传输线DTL 1可以与两条、三条、四条或六条第一数据线DL 1等电连接。
在一些示例中，如图13所示，第二数据传输线DTL 2与上述至少两个选择晶体管组41电连接，并通过该至少两个选择晶体管组41与相应的第二数据线DL 2电连接。
由于每个选择晶体管组41可以与一条选择信号线Mux及一条第二数据线DL 2电连接，因此，每条第二数据传输线DTL 2可以与至少两条选择信号线Mux及至少两条第二数据线DL 2相对应。第二数据传输线DTL 2所传输的数据信号，可以在其中一条选择信号线Mux所传输的选择信号的控制下，传输至相应的一条第二数据线DL 2，并在另一条选择信号线Mux所传输的选择信号的控制下，传输至相应的另一条第二数据线DL 2，实现第二数据传输线DTL 2所传输的数据信号的分时写入。
示例性的，第二数据传输线DTL 2可以与两个、三个、四个或六个选择晶体管组41等电连接，相应的，第二数据传输线DTL 2可以与两条、三条、四条或六条第二数据线DL 2等电连接。
在一些示例中，如图13所示，第三数据传输线DTL 3与上述至少两个选择晶体管组41电连接，并通过该至少两个选择晶体管组41与相应的第三数据线DL 3电连接。
由于每个选择晶体管组41可以与一条选择信号线Mux及一条第三数据线DL 3电连接，因此，每条第三数据传输线DTL 3可以与至少两条选择信号线Mux及至少两条第三数据线DL 3相对应。第三数据传输线DTL 3所传输的数据信号，可以在其中一条选择信号线Mux所传输的选择信号的控制下，传输至相应的一条第三数据线DL 3，并在另一条选择信号线Mux所传输的选择信号的控制下，传输至相应的另一条第三数据线DL 3，实现第三数据传输线DTL 3所传输的数据信号的分时写入。
示例性的，第三数据传输线DTL 3可以与两个、三个、四个或六个选择晶体管组41等电连接，相应的，第三数据传输线DTL 3可以与两条、三条、四条或六条第三数据线DL 3等电连接。
可选的，如图13所示，上述多条选择信号线Mux的数量可以为六条，相应的，上述多个选择晶体管组41的数量可以为6i个。此时，第一条选择信号线Mux 1可以与第6i-5个选择晶体管组41电连接，第二条选择信号线Mux 2可以与第6i-4个选择晶体管组41电连接，第三条选择信号线Mux 3可以与第6i-3个选择晶体管组41电连接，第四条选择信号线Mux 4可以与第6i-2个选择晶体管组41电连接，第五条选择信号线Mux 5可以与第6i-1个选择晶体管组41电连接，第六条选择信号线Mux 6可以与第6i个选择晶体管组41电连接。其中，i为正整数。
在此情况下，结合图13，对各选择晶体管组41与数据传输线DTL及数据线DL之间的连接关系进行示意性说明。
示例性的，第i条第一数据传输线DTL 1可以与第6i-5个选择晶体管组41电连接，并通过该第6i-5个选择晶体管组41与第6i-5条第一数据线DL 1电连接；第i条第一数据传输线DTL 1还可以与第6i-4个选择晶体管组41电连接，并通过该第6i-4个选择晶体管组41与第6i-4条第一数据线DL 1电连接；第i条第一数据传输线DTL 1还可以与第6i-3个选择晶体管组41电连接，并通过该第6i-3个选择晶体管组41与第6i-3条第一数据线DL 1电连接；第i条第一数据传输线DTL 1还可以与第6i-2个选择晶体管组41电连接，并通过该第6i-2个选择晶体管组41与第6i-2条第一数据线DL 1电连接；第i条第一数据传输线DTL 1还可以与第6i-1个选择晶体管组41电连接，并通过该第6i-1个选择晶体管组与第6i-1条第一数据线DL 1电连接；第i条第一数据传输线DTL 1还可以与第6i个选择晶体管组电连接，并通过该第6i个选择晶体管组与第6i条第一数据线DL 1电连接。
示例性的，第i条第二数据传输线DTL 2可以与第6i-5个选择晶体管组41电连接，并通过该第6i-5个选择晶体管组与第6i-5条第二数据线DL 2电连接；第i条第二数据传输线DTL 2还可以与第6i-4个选择晶体管组41电连接，并通过该第6i-4个选择晶体管组41与第6i-4条第二数据线DL 2电连接；第i条第二数据传输线DTL 2还可以与所述第6i-3个选择晶体管组41电连接，并通过该第6i-3个选择晶体管组与第6i-3条第二数据线DTL 2电连接；第i条第二数据传输线DTL 2还可以与第6i-2个选择晶体管组41电连接，并通过该第6i-2个选择晶体管组41与第6i-2条第二数据线DL 2电连接；第i条第二数据传输线DTL 2 还可以与第6i-1个选择晶体管组41电连接，并通过该第6i-1个选择晶体管组与第6i-1条第二数据线DL 2电连接；第i条第二数据传输线DTL 2还可以与第6i个选择晶体管组41电连接，并通过该第6i个选择晶体管组与第6i条第二数据线DL 2电连接。
示例性的，第i条第三数据传输线DTL 3可以与第6i-5个选择晶体管组41电连接，并通过该第6i-5个选择晶体管组41与第6i-5条第三数据线DL 3电连接；第i条第三数据传输线DTL 3还可以与第6i-4个选择晶体管组41电连接，并通过该第6i-4个选择晶体管组与第6i-4条第三数据线DL 3电连接；第i条第三数据传输线DTL 3还可以与第6i-3个选择晶体管组41电连接，并通过该第6i-3个选择晶体管组41与第6i-3条第三数据线DL 3电连接；第i条第三数据传输线DTL 3还可以与第6i-2个选择晶体管组41电连接，并通过该第6i-2个选择晶体管组41与第6i-2条第三数据线DL 3电连接；第i条第三数据传输线DTL 3还可以与第6i-1个选择晶体管组41电连接，并通过该第6i-1个选择晶体管组41与第6i-1条第三数据线DL 3电连接；第i条第三数据传输线DTL 3还可以与第6i个选择晶体管组41电连接，并通过该第6i个选择晶体管组41与第6i条第三数据线DL 3电连接。
在一些示例中，如图12和图13所示，上述第一数据传输线DTL 1、第二数据传输线DTL 2和第三数据传输线DTL 3呈周期性排布。也即，第一数据传输线DTL 1、第二数据传输线DTL 2和第三数据传输线DTL 3可以按照一定的排列次序，依次循环排布。
上述排列次序可以包括多种，可以根据实际需要选择设置。
示例性的，如图12和图13所示，一个周期的排列次序可以为：第一数据传输线DTL 1、第二数据传输线DTL 2和第三数据传输线DTL 3；或者，第二数据传输线DTL 2、第一数据传输线DTL 1和第三数据传输线DTL 3；或者，第三数据传输线DTL 3、第一数据传输线DTL 1和第二数据传输线DTL 2等。
在一些示例中，如图12和图13所示，上述第一数据线DL 1、第二数据线DL 2和第三数据线DL 3呈周期性排布。也即，第一数据线DL 1、第二数据线DL 2和第三数据线DL 3可以按照一定的排列次序，依次循环排布。
上述排列次序可以包括多种，可以根据实际需要选择设置。
示例性的，如图12和图13所示，一个周期的排列次序可以为：第一数据线DL 1、第二数据线DL 2和第三数据线DL 3；或者，第二数据线DL 2、第一数据线DL 1和第三数据线DL 3；或者，第三数据线DL 3、第一数据线DL 1和第二数据线DL 2等。
例如，如图12和图13所示，数据传输线DTL的排列次序可以和数据线DL的排列次序相同。这样有利于提高布线的规律性，降低布线的难度。
可选的，与第一数据线DL 1所电连接的子像素2可以均为红色子像素，与第二数据线DL 2所电连接的子像素2可以均为绿色子像素，与第三数据线DL 3所电连接的子像素2可以均为蓝色子像素。
可选的，在子像素2还包括白色子像素的情况下，数据线DL例如可以包括第四数据线DL 4，数据传输线DTL例如可以包括第四数据传输线DTL 4。其中，第四数据线DL 4、第四数据传输线DTL 4与各选择晶体管组41之间的连接关系，可以参照上述一下示例中的说明，此处不再赘述。
在一些实施例中，如图13所示，选择晶体管组41至少包括：第一选择晶体管411、第二选择晶体管412和第三选择晶体管413。
在一些示例中，如图13所示，第一选择晶体管411的控制极与选择信号线Mux电连 接，第一选择晶体管411的第一极与第一数据传输线DTL 1电连接，第一选择晶体管411的第二极与第一数据线DL 1电连接。
示例性的，在选择信号线Mux所传输的选择信号的电平为低电平的情况下，第一选择晶体管411可以在选择信号的控制下导通，将来自第一数据传输线DTL 1的数据信号传输至第一数据线DL 1。
在一些示例中，如图13所示，第二选择晶体管412的控制极与选择信号线Mux电连接，第二选择晶体管412的第一极与第二数据传输线DTL 2电连接，第二选择晶体管412的第二极与第二数据线DL 2电连接。
示例性的，在选择信号线Mux所传输的选择信号的电平为低电平的情况下，第二选择晶体管412可以在选择信号的控制下导通，将来自第二数据传输线DTL 2的数据信号传输至第二数据线DL 2。
在一些示例中，如图13所示，第三选择晶体管413的控制极与选择信号线Mux电连接，第三选择晶体管413的第一极与第三数据传输线DTL 3电连接，第三选择晶体管413的第二极与第三数据线DL 3电连接。
示例性的，在选择信号线Mux所传输的选择信号的电平为低电平的情况下，第三选择晶体管413可以在选择信号的控制下导通，将来自第三数据传输线DTL 3的数据信号传输至第三数据线DL 3。
可选的，如图13所示，以选择信号线Mux的数量为六条，选择晶体管组41的数量为6i个为例。
第i条第一数据传输线DTL 1可以与第6i-5至第6i个选择晶体管组41中的第一选择晶体管411电连接。第i条第一数据传输线DTL 1所传输的数据信号，则可以分别在第一条选择信号线Mux 1所传输的选择信号、第二条选择信号线Mux 2所传输的选择信号、第三条选择信号线Mux 3所传输的选择信号、第四条选择信号线Mux 4所传输的选择信号、第五条选择信号线Mux 5所传输的选择信号、第六条选择信号线Mux 6所传输的选择信号的控制下，分时传输至第6i-5至第6i条第一数据线DL 1，实现数据信号的分时写入。
第i条第二数据传输线DTL 2可以与第6i-5至第6i个选择晶体管组41中的第二选择晶体管412电连接。第i条第二数据传输线DTL 2所传输的数据信号，则可以分别在第一条选择信号线Mux 1所传输的选择信号、第二条选择信号线Mux 2所传输的选择信号、第三条选择信号线Mux 3所传输的选择信号、第四条选择信号线Mux 4所传输的选择信号、第五条选择信号线Mux 5所传输的选择信号、第六条选择信号线Mux 6所传输的选择信号的控制下，分时传输至第6i-5至第6i条第二数据线DL 2，实现数据信号的分时写入。
第i条第三数据传输线DTL 3可以与第6i-5至第6i个选择晶体管组41中的第三选择晶体管413电连接。第i条第三数据传输线DTL 3所传输的数据信号，则可以分别在第一条选择信号线Mux 1所传输的选择信号、第二条选择信号线Mux 2所传输的选择信号、第三条选择信号线Mux 3所传输的选择信号、第四条选择信号线Mux 4所传输的选择信号、第五条选择信号线Mux 5所传输的选择信号、第六条选择信号线Mux 6所传输的选择信号的控制下，分时传输至第6i-5至第6i条第三数据线DL 3，实现数据信号的分时写入。
需要说明的是，在子像素2还包括白色子像素的情况下，选择晶体管组41例如还可以包括第四选择晶体管。其中，第四选择晶体管的电连接关系，可以参照上述一下示例中的说明，此处不再赘述。
在一些示例中，如图12和图13所示，同一条数据线DL可以与一列子像素电连接。也即，数据线DL的条数和子像素的列数相等。
可以理解的是，在本实施例中，同一行子像素可以仅与一条栅线GL电连接。也即，每条栅线GL所传输的扫描信号，可以同时控制同一行子像素中，各数据写入子电路2111和补偿子电路2113的工作情况。
在另一种示例性实施例中，如图16和图17所示，同一条数据线DL与至少两列子像素电连接，且一行子像素与至少两条栅线GL电连接。其中，该至少两条栅线GL被配置为，分别向相应的子像素传输扫描信号，以控制该一行子像素分时接收数据线DL所传输的数据信号。
在一些示例中，由于每个子像素2与一条数据线DL及一条栅线GL电连接，因此，上述至少两条栅线GL中，每条栅线GL仅与同一行子像素中的一部分子像素2电连接；并且，该同一行子像素中，至少两个子像素2同时与一条数据线DL电连接。
示例性的，与同一条数据线DL电连接的至少两个子像素2，分别与不同的栅线GL电连接。该至少两个子像素2所接收的扫描信号的有效电平时间可以不重合，这样该至少两个子像素2便可以在不同的时间工作(例如不同子像素2中的数据写入子电路2111和补偿子电路2113可以在不同的时间导通)，依次接收该数据线DL所传输的数据信号，实现数据信号的分时写入。
需要说明的是，数据线DL的数量少于同一行子像素中子像素2的数量。
采用上述设置方式设置栅线GL和数据线DL，可以有效减少显示基板100所包括的数据线DL的数量，减小数据线DL所占的空间，增大显示基板100的布线空间。
在显示基板100包括连接配线3的情况下，一条数据线DL可以与一条连接配线3电连接。也即，数据线DL的数量和连接配线3的数量可以相等。由于数据线DL的数量少于同一行子像素中子像素2的数量，因此，可以有效减小连接配线3的数量，这样可以有效提高侧边走线的良率。
在一些实施例中，如图16和图17所示，同一行子像素中，任意相邻的两个子像素2分别与不同栅线GL电连接。
这样可以将上述相邻的两个子像素2(甚至相邻近的更多子像素2)与同一条数据线DL电连接，进而有利于将该数据线DL设置在上述相邻的两个子像素2旁边，有利于减小该数据线DL与相应电连接的子像素2之间的间距，降低该数据线DL与相应电连接的子像素2之间的连线复杂度。
在一些实施例中，如图16和图17所示，同一条数据线DL所电连接的子像素2的列数，与同一行子像素所电连接的栅线GL条数，相等。
在一些示例中，同一条数据线DL所电连接的子像素2的列数为n，与同一行子像素所电连接的栅线GL条数为n。其中，同一行子像素中，与同一条数据线DL电连接的n个子像素2，分别与该n条栅线GL一一对应地电连接。
这样便于对同一行子像素进行分组控制，降低布线及对同一行子像素进行控制的难度。
此处，同一条数据线DL所电连接的子像素2的列数，及与同一行子像素所电连接的栅线GL条数，可以根据实际需要选择设置。
示例性的，同一条数据线DL所电连接的子像素2的列数可以为两列、三列、四列或 六列等。相应的，与同一行子像素所电连接的栅线GL条数可以为两条、三条、四条或六条等。
可选的，如图16和图17所示，同一条数据线DL所电连接的子像素2的列数为六列，相应的，与同一行子像素所电连接的栅线GL条数为六条。此时，同一行子像素中，第一条栅线GL 1可以与第6i-5个子像素2电连接，第二条栅线GL 2可以与第6i-4个子像素2电连接，第三条栅线GL 3可以与第6i-3个子像素2电连接，第四条栅线GL 4可以与第6i-2个子像素2电连接，第五条栅线GL 5可以与第6i-1个子像素2电连接，第六条栅线GL 6可以与第6i个子像素电连接。第i条数据线DL可以与第6i-5至第6i列子像素电连接。
例如，如图18所示，上述第一条栅线GL 1所传输的扫描信号Gate 1、第二条栅线GL 2所传输的扫描信号Gate 2、第三条栅线GL 3所传输的扫描信号Gate 3、第四条栅线GL 4所传输的扫描信号Gate 4、第五条栅线GL 5所传输的扫描信号Gate 5及第六条栅线GL 6所传输的扫描信号Gate 6的电平依次跳变为有效电平，且该六个扫描信号中，任意相邻两个扫描信号的有效电平时间不重合。相应的，第6i-5个子像素2、第6i-4个子像素2、第6i-3个子像素2、第6i-2个子像素2、第6i-1个子像素2及第6i个子像素2中的数据写入子电路2111和补偿子电路2113，可以依次接收第i条数据线DL所传输的数据信号，实现数据信号的分时写入。
在一些实施例中，如图16和图17所示，与同一行子像素电连接的至少两条栅线GL分别设置在该一行子像素的相对两侧。也即，该至少两条栅线GL可以分为两部分，其中一部分栅线GL可以设置在该一行子像素的一侧，另一部分栅线GL可以设置在该一行子像素的另一侧。其中，该两部分栅线GL的数量例如可以相等。
示例性的，与同一行子像素电连接的栅线GL的数量为六条。此时，其中三条栅线GL可以设置在该一行子像素的一侧，另外三条栅线GL可以设置在该一行子像素的另一侧。
通过采用上述设置方式设置栅线GL的排布方式，有利于使得不同栅线GL与相应电连接的子像素2之间具有较小的间距，降低不同栅线GL与相应电连接的子像素2之间的连线复杂度。
需要说明的是，在本实施例中，栅线GL的数量较多，相应的，显示基板100中所需设置的移位寄存器(用于生成扫描信号)的数量也会较多。此时，可以将本实施例中对栅线GL及数据线DL的设置方式应用于分辨率较低的显示基板中，避免对显示基板100的分辨率产生不良影响。
在上述一种实现方式中，如图3和图4所示，对于任意一行子像素，均是在扫描信号跳变为有效电平(也即低电平)后，第一电流选择信号、第二电流选择信号、第一时长选择信号及第二时长选择信号均是分时跳变为低电平，以实现电流数据信号及时长数据信号的分时写入。通常，信号和信号之间会增加时间间隔(如图3和图4中双向箭头所示)，以防止信号误写入。
此处，以某个子像素的电流控制电路相对应的写入及补偿阶段为例。在扫描信号跳变为低电平后，电流数据信号写入至相应的电流数据线DI。在上一帧显示后，与该子像素相对应的第一电流选择信号跳变为高电平时，之前写入的电流数据信号会通过电流数据线DI上的寄生电容存储在电流数据线DI上。在这种情况下，在下一帧显示时，电流数据信号可能无法正常写入至电流控制电路中(也即电流控制电路中驱动晶体管的控制极)。
例如，在上一帧显示中，电流数据信号的电平为低电平(其压值为Vdata(n-1))。在 下一帧显示中，在扫描信号跳变为低电平之后、第一电流选择信号的电平发生跳变之前的时间间隔内，存储在电流数据线DI上的电流数据信号会先写入至电流控制电路中。在第一电流选择信号跳变为低电平后，如图3所示，如果下一帧显示中电流数据信号的电平(其压值为Vdata(n))高于上一帧显示中电流数据信号的电平，该数据电流信号可以持续写入至电流控制电路(如图3中Vg所示，Vth为电流控制电路中的阈值电压)；如图4所示，如果下一帧显示中电流数据信号的电平(其压值为Vdata(n))低于上一帧显示中电流数据信号的电平，则会持续上一帧的数据信号的写入(如图4中Vg所示)，导致这一帧显示的数据信号无法正常写入，进而导致电流控制电路中驱动晶体管难以正常开启，进而难以显示所需显示的灰阶。
基于此，如图10和图11所示，在本公开的一些实施例中，在电流控制电路211生成驱动信号的阶段，数据信号的电平跳变为有效电平的时段，早于扫描信号的电平跳变为有效电平的时段。
也即，在生成驱动信号的阶段，数据信号可以在先传输至相应的数据线DL，并存储在相应数据线DL的寄生电容上，然后使得扫描信号的电平跳变为有效电平，使得数据信号依次经数据写入子电路2111、驱动子电路2112和补偿子电路2113，写入至第六节点N6，完成对驱动子电路2112的阈值电压的补偿。
在电流控制电路211生成驱动信号的阶段，通过将数据信号的电平跳变为有效电平的时段，设置为早于扫描信号的电平跳变为有效电平的时段，可以在下一帧显示之前，先将数据线DL中存储的数据信号进行刷新，避免残留有上一帧显示的数据信号，这样在扫描信号的电平跳变为有效电平后，便可以接收刷新后的数据信号，避免因上一帧数据信号的残留导致下一帧显示的数据信号无法正常写入，使得各子像素2能够显示所需显示的灰阶，提高显示基板100的显示效果。
在一些示例中，在显示基板100包括多路输出选择电路4的情况下，在电流控制电路211生成驱动信号的阶段，各选择信号线Mux所传输的选择信号的有效电平的时段，早于扫描信号的电平跳变为有效电平的时段。
这样可以确保在扫描信号的电平跳变为有效电平之前，各选择信号已依次跳变为有效电平，将数据信号分时写入至相应的数据线DL上，并通过数据线DL上的寄生电容，完成对相应数据信号的存储。
在另一些示例中，在同一条数据线DL与至少两列子像素电连接，且一行子像素与至少两条栅线GL电连接的情况下，对于各个子像素2而言，在电流控制电路211生成驱动信号的阶段，数据信号的电平跳变为有效电平的时段，早于扫描信号的电平跳变为有效电平的时段；对于与同一条栅线GL电连接、且与不同数据线DL电连接的不同子像素2而言，扫描信号中可以具有与不同子像素2分别相对应的多个间隔的有效电平，此时，不同数据信号的电平，均在相应的扫描信号的有效电平之前，跳变为有效电平。
本公开的一些实施例提供了一种显示基板的驱动方法。该驱动方法包括：向该显示基板100的多条数据线DL传输数据信号，同一子像素2的电流控制电路211和时长控制电路212同时接收该数据信号。
示例性的，在驱动显示基板100进行显示的过程中，数据信号的有效电平，分时写入至电流控制电路211和时长控制电路212。
这样可以使得与电流控制电路211相对应的写入及补偿阶段，及与时长控制电路212 相对应的生成时长控制信号的阶段隔开，无重合，且数据信号的电平在各阶段基本无变化。这样可以有效避免相邻两条数据线DL之间产生信号串扰，避免出现因写入至时长控制电路212的数据信号的电平发生变化而导致写入至电流控制电路211的数据信号的电平发生跳变的情况，进而有利于改善列向亮暗差异不良现象。
在一些实施例中，如图6和图7所示，上述电流控制电路211包括数据写入子电路2111、驱动子电路2112、补偿子电路2113及发光控制子电路2114，时长控制电路212包括第一控制子电路2121、第二控制子电路2122及第三控制子电路2123。
下面结合图7所示的子像素2的结构，对显示基板100的一帧显示阶段的驱动方法进行示意性说明。
在一些示例中，在一帧显示阶段，上述驱动方法还包括：第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4。其中，在显示基板100的子像素2所显示的灰阶不同的情况下，上述第一阶段S1和第二阶段S2略有不同。下面根据显示基板100的子像素2所显示的灰阶，对驱动方法还所包括的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4进行说明。
示例性的，如图10所示，显示基板100的子像素2所显示的灰阶大于或等于阈值灰阶。此时，像素驱动电路21与发光器件22之间可以一直形成导电通路，相应的，时长控制信号可以为第一使能信号。
在第一阶段S1a，如图10所示，第一复位信号的电平为低电平，第二复位信号的电平为高电平，数据信号的电平为高电平。
响应于在第一复位信号端Res_A处接收的第一复位信号和数据信号，第一控制子电路2121关断。
第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下导通，将数据信号传输至第三节点N3。由于数据信号的电平为高电平，因此，第一控制子电路2121中的第二晶体管T2可以在来自第三节点N3的数据信号的控制下关断，此时，第二使能信号无法传输至第二节点N2。同时，第一控制子电路2121中的第一电容器C1可以对高电平的数据信号进行存储。
第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下关断。
另外，在电流控制电路211还包括复位子电路2115的情况下，复位子电路2115中的第十晶体管T10和第十一晶体管T11，可以在第一复位信号的控制下同时导通，第十晶体管T10可以将初始信号传输至第六节点N6，对第六节点N6进行复位；第十一晶体管T11可以将初始信号传输至发光器件22，对发光器件22进行复位。
在第二阶段S2a，如图10所示，第一复位信号的电平为高电平，第二复位信号的电平为低电平，数据信号的电平为低电平。
响应于在第二复位信号端Res_B处接收的第二复位信号和数据信号，第二控制子电路2122导通，将在第一使能信号端EM处接收的第一使能信号传输至第二节点N2。
第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下导通，将数据信号传输至第四节点N4。由于数据信号的电平为低电平，因此，第二控制子电路2122中的第四晶体管T4可以在来自第四节点N4的数据信号的控制下导通，将第一使能信号传输至第二节点N2。同时，第二控制子电路2122中的第二电容器C2可以对低电平的数据信号进行存储。
另外，第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下关断。此时，第一电容器C1进行放电，使得第三节点N3的电压保持为高电平。
在第三阶段S3a，如图10所示，扫描信号的电平为低电平，数据信号的电平为低电平，第一复位信号的电平为高电平，第二复位信号的电平为高电平。
响应于在扫描信号端Gate处接收的扫描信号，数据写入子电路2111和补偿子电路2113导通，将数据信号依次经第五节点N5、驱动子电路2112、第一节点N1及补偿子电路2113，传输至第六节点N6，对驱动子电路2112进行阈值电压的补偿。
驱动子电路2112中的第七晶体管T7可以在来自第六节点N6的初始信号的控制下导通。
数据写入子电路2111中的第六晶体管T6和补偿子电路2113中的第八晶体管T8，可以在扫描信号的控制下同时导通。第六晶体管T6可以接收数据信号，并依次经第五节点N5、第七晶体管T7、第一节点N1及第八晶体管T8传输至第六节点N6。在此阶段，数据信号可以持续传输至第六节点N6，直至第七晶体管T7截止。此时，完成对第七晶体管T7的阈值电压的补偿。
另外，第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下关断。此时，第一电容器C1进行放电，使得第三节点N3的电压保持为高电平。第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下关断。此时，第二电容器C2开始放电，使得第四节点N4的电压保持为低电平，进而使得第四晶体管T4持续传输第一使能信号至第二节点N2。
在第四阶段中S4a，如图10所示，第一使能信号的电平为低电平，扫描信号的电平为高电平，第一复位信号的电平为高电平，第二复位信号的电平为高电平。
响应于第一使能信号，发光控制子电路2114导通，将在第一电压信号端VDD处接收的第一电压信号依次经第五节点N5和驱动子电路2112，传输至第一节点N1。
发光控制子电路2114中的第九晶体管T9在第一使能信号的控制下导通，使得第五节点N5和第一电压信号端VDD之间形成导电通路。
第三控制子电路2123中的第五晶体管T5在来自第二节点N2的第一使能信号的控制下导通，使得第一节点N1和发光器件22之间形成导电通路。
驱动子电路2112中的第七晶体管T7导通，将第一电压信号传输至第一节点N1。第七晶体管T7可以根据写入至第六节点N6的数据信号的压值及第一电压信号的压值，生成驱动信号。
在此阶段，第一使能信号可以使得第一节点N1和发光器件22之间持续导通。这样能够将驱动信号持续传输至发光器件22，使得发光器件22持续发光，进而能够实现较高灰阶的显示。
示例性的，如图11所示，显示基板100的子像素2所显示的灰阶小于阈值灰阶。此时，像素驱动电路21与发光器件22之间处于导通和截止交替的状态，相应的，时长控制信号可以为第二使能信号。
在第一阶段S1b，如图11所示，第一复位信号的电平为低电平，第二复位信号的电平为高电平，数据信号的电平为低电平。
响应于第一复位信号和数据信号，第一控制子电路2121导通，将在第二使能信号端EM处接收的第二使能信号传输至第二节点N2。
第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下导通，将数据信号传输至第三节点N3。由于数据信号的电平为低电平，因此，第一控制子电路2121中的第二晶体管T2可以在来自第三节点N3的数据信号的控制下导通，将第二使能信号传输至第二节点N2。同时，第一控制子电路2121中的第一电容器C1可以对低电平的数据信号进行存储。
第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下关断。
另外，在电流控制电路211还包括复位子电路2115的情况下，复位子电路2115中的第十晶体管T10和第十一晶体管T11，可以在第一复位信号的控制下同时导通，第十晶体管T10可以将初始信号至第六节点N6，对第六节点N6进行复位；第十一晶体管T11可以将初始信号至发光器件22，对发光器件22进行复位。
在第二阶段S2b，如图11所示，第一复位信号的电平为高电平，第二复位信号的电平为低电平，数据信号的电平为高电平。
响应于第二复位信号和数据信号，第二控制子电路2122关断。
第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下导通，将数据信号传输至第四节点N4。由于数据信号的电平为高电平，因此，第二控制子电路2122中的第四晶体管T4可以在来自第四节点N4的数据信号的控制下关断，此时，第一使能信号无法传输至第二节点N2。同时，第二控制子电路2122中的第二电容器C2可以对高电平的数据信号进行存储。
另外，在此阶段，第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下关断。此时，第一电容器C1进行放电，使得第三节点N3的电压保持为低电平。
在第三阶段S3b，如图11所示，扫描信号的电平为低电平，数据信号的电平为低电平，第一复位信号的电平为高电平，第二复位信号的电平为高电平。
响应于在扫描信号端Gate处接收的扫描信号，数据写入子电路2111和补偿子电路2113导通，将数据信号依次经第五节点N5、驱动子电路2112、第一节点N1及补偿子电路2113，传输至第六节点N6，对驱动子电路2112进行阈值电压的补偿。
驱动子电路2112中的第七晶体管T7可以在来自第六节点N6的初始信号的控制下导通。
数据写入子电路2111中的第六晶体管T6和补偿子电路2113中的第八晶体管T8，可以在扫描信号的控制下同时导通。第六晶体管T6可以接收数据信号，并依次经第五节点N5、第七晶体管T7、第一节点N1及第八晶体管T8传输至第六节点N6。在此阶段，数据信号可以持续传输至第六节点N6，直至第七晶体管T7截止。此时，完成对第七晶体管T7的阈值电压的补偿。
另外，第二控制子电路2122中的第三晶体管T3可以在第二复位信号的控制下关断。此时，第二电容器C2进行放电，使得第四节点N4的电压保持为高电平。第一控制子电路2121中的第一晶体管T1可以在第一复位信号的控制下关断。此时，第一电容器C1开始放电，使得第三节点N3的电压保持为低电平，进而使得第二晶体管T2持续传输第二使能信号至第二节点N2。
在第四阶段S4b，如图11所示，第一使能信号的电平为低电平，第二使能信号为高频脉冲信号，扫描信号的电平为高电平，第一复位信号的电平为高电平，第二复位信号的电平为高电平。
响应于第一使能信号，发光控制子电路2114导通，将在第一电压信号端VDD处接收的第一电压信号依次经第五节点N5和驱动子电路2112，传输至第一节点N1。
发光控制子电路2114中的第九晶体管T9在第一使能信号的控制下导通，使得第五节点N5和第一电压信号端VDD之间形成导电通路。
第三控制子电路2123中的第五晶体管T5在来自第二节点N2的第二使能信号的控制下处于导通和截止交替的状态，进而使得第一节点N1和发光器件22之间处于导通和截止交替的状态。
驱动子电路2112中的第七晶体管T7导通，将第一电压信号传输至第一节点N1。在第一节点N1和发光器件22之间导通的时段，第七晶体管T7可以根据写入至第六节点N6的数据信号的压值及第一电压信号的压值，生成驱动信号，并传输至发光器件22，使得发光器件22发光。
在此阶段，由于第一节点N1和发光器件22之间处于导通和截止交替的状态，因此，上述驱动信号可以间歇性地传输至发光器件22，使得发光器件22周期性地接收驱动信号，进而使得发光器件22周期性的发光。这样发光器件22发光的总时长被缩短，进而能够实现较低灰阶的显示。
需要说明的是，上述显示基板100中的数据线DL被配置为，对数据信号进行存储。扫描信号端Gate被配置为，在上述第三阶段S3(也即第三阶段S3a或第三阶段S3b)，在数据线DL存储数据信号之后，传输扫描信号，以控制数据写入子电路2111和补偿子电路2113导通。
示例性的，数据线DL自身具有寄生电容，在数据信号传输至数据线DL上后，该数据信号可以存储在该数据线DL的寄生电容上。
示例性的，上述扫描信号端Gate能够传输扫描信号，该扫描信号可以来自相应的栅线GL。在上述第三阶段S3，数据信号的电平为低电平(也即有效电平)，扫描信号的电平为低电平(也即有效电平)，在数据线DL接收上述数据信号对自身进行刷新后，可以对该数据信号进行重新存储，之后扫描信号端Gate可以传输扫描信号，使得数据写入子电路2111和补偿子电路2113导通，接收并传输数据线DL中重新存储的数据信号。
这样可以首先对数据线DL中存储的数据信号进行刷新，避免残留有上一帧显示的数据信号，然后在下一帧显示中，在扫描信号的电平跳变为有效电平后，便可以接收刷新后的数据信号，避免因上一帧数据信号的残留导致下一帧显示的数据信号无法正常写入，使得各子像素2能够显示所需显示的灰阶，提高显示基板100的显示效果。
在一些实施例中，如图13所示，显示基板100还包括多路输出选择电路4。下面结合图14和图15所示的时序图，对包括多路输出选择电路4的显示基板的驱动方法进行示意性说明。
在上述第一阶段S1(也即第一阶段S1a或第一阶段S1b)，多条选择信号线Mux所传输的选择信号(Mux 1～Mux 6)分别传输至多路输出选择电路4。多路输出选择电路4中的各选择晶体管组41分别在相应的选择信号的控制下导通，将来自数据传输线DTL的数据信号，分时传输至相应的数据线DL，并存储在相应的数据线DL的寄生电容上。
其中，任意相邻两条选择信号线Mux所传输的选择信号的有效电平(也即低电平)之间具有时间间隔，因此，任意相邻两个晶体管组41的导通具有时间间隔，这样便可以将来自数据传输线DTL的数据信号，分时传输至相应的数据线DL。
在此阶段，第一复位信号的低电平持续时长，可以根据实际需要选择设置。
例如，如图14所示，在多路输出选择电路4将数据信号分时传输至各数据线DL之后，第一复位信号的电平跳变为低电平，并在完成数据信号的写入、及在第二阶段S2之前，第一复位信号的电平跳变为高电平。
又如，如图15所示，在多路输出选择电路4将数据信号分时传输至各数据线DL的同时，第一复位信号的电平便可以跳变为低电平。在完成数据信号的写入、及在第二阶段S2之前，第一复位信号的电平跳变为高电平。这样可以增长第一复位信号的低电平持续时长，有利于增加数据信号的写入时长。
在上述第二阶段S2(也即第二阶段S2a或第二阶段S2b)，数据信号的传输过程与在第一阶段S1中数据信号的传输过程相同，第二复位信号的低电平持续时长的设置方式可以与第一复位信号的低电平持续时长的设置方式相同，此处不再赘述。
需要提及的是，在增长第一复位信号和第二复位信号的持续时长的情况下，会使得第一复位信号、第二复位信号及数据信号的频率不一致。此时，可以对驱动芯片200进行调整，使得驱动芯片200能够进行兼容。
在上述第三阶段S3(也即第三阶段S3a或第三阶段S3b)，在扫描信号的电平跳变为低电平之前，多路输出选择电路4完成对数据信号的分时写入及存储。
可以理解的是，在一帧显示的时长为定值的情况下，上述第一阶段S1、第二阶段S2及第三阶段S3的时长也可以为定值。此时，在确保多路输出选择电路4能够将数据信号分时传输至各数据线DL的前提下，本公开可以减小各选择信号的低电平(也即有效电平)的持续时长，这样有利于增加第一复位信号、第二复位信号及扫描信号的低电平的持续时长，进而有利于为数据信号的写入及对第七晶体管T7的补偿提供更为充分的时间。
在另一些实施例中，如图17所示，同一条数据线DL与至少两列子像素电连接，且一行子像素与至少两条栅线GL电连接。下面结合图18所示的时序图，以同一条数据线DL与六列子像素电连接，且一行子像素与六条栅线(GL 1～GL 6)电连接为例，对显示基板的驱动方法进行示意性说明。
可以理解的是，如图17所示，在本示例中，与同一行子像素的第一复位信号端Res_A电连接的第一复位信号线RL1的数量也为六条(RL1 1～RL1 6)，与同一行子像素的第二复位信号端Res_B电连接的第二复位信号线RL2的数量也为六条(RL2 1～RL2 6)。第一复位信号线RL1或第二复位信号线RL2，与同一行子像素之间的连接关系，可以和栅线GL与同一行子像素之间的连接关系，相同。
在上述第一阶段S1(也即第一阶段S1a或第一阶段S1b)，六条第一复位信号线(RL1 1～RL1 6)分别将第一复位信号(Res_A 1～Res_A 6)传输至相应子像素2的第一复位信号端Res_A。各第一复位信号的有效电平时间不重合，这样便于将同一条数据线DL中的数据信号分时写入至不同的子像素2。
其中，任意相邻两条第一复位信号线RL1所传输的第一复位信号的有效电平(也即低电平)之间具有时间间隔。这样在各第一复位信号的电平跳变为有效电平之前，可以利用该时间间隔会完成各数据线DL的数据信号的刷新及存储。
在上述第二阶段S2(也即第二阶段S2a或第二阶段S2b)，六条第二复位信号线(RL2 1～RL2 6)分别将第二复位信号(Res_B 1～Res_B 6)传输至相应子像素2的第二复位信号端Res_B。各第二复位信号的有效电平时间不重合，这样便于将同一条数据线DL中 的数据信号分时写入至不同的子像素2。
其中，任意相邻两条第二复位信号线RL2所传输的第二复位信号的有效电平(也即低电平)之间具有时间间隔。这样在各第二复位信号的电平跳变为有效电平之前，可以利用该时间间隔会完成各数据线DL的数据信号的刷新及存储。
在上述第三阶段S3(也即第三阶段S3a或第三阶段S3b)，六条栅线GL分别将扫描信号(Gate 1～Gate 6)传输至相应子像素的扫描信号端Gate。各扫描信号的有效电平时间不重合，这样便于将同一条数据线DL中的数据信号分时写入至不同的子像素2。
其中，任意相邻两条第一栅线GL所传输的扫描信号的有效电平之间具有时间间隔。这样在各扫描信号的电平跳变为有效电平之前，可以利用该时间间隔会完成各数据线DL的数据信号的刷新及存储。
在一些实施例中，第二使能信号的有效电平(也即低电平)时间均位于第四阶段S4。也即，第二使能信号的电平在由高电平跳变为低电平的时段，均位于第四阶段S4。在第一阶段S1、第二阶段S2及第三阶段S3，第二使能信号的电平例如可以保持为非有效电平(也即高电平)。
这样在第三阶段S3中，对第七晶体管T7进行阈值电压的补偿的过程中，可以避免因第二使能信号的高频拉低对写入至第七晶体管T7的控制极的数据信号造成耦合干扰，避免第七晶体管T7的控制极的电压产生扰动，进而有利于确保子像素2能够正常显示灰阶。另外，通过将第二使能信号的有效电平时间均设置在第四阶段S4，还可以避免在第五晶体管T5和第一节点N1之间设置防干扰的晶体管，这样有利于简化子像素2的结构，提高子像素2及显示基板100的良率。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示基板，包括：
    沿第一方向延伸的多条数据线；以及，
    多个子像素；子像素包括像素驱动电路及发光器件；
    所述像素驱动电路包括：电流控制电路，及与所述电流控制电路、所述发光器件电连接的时长控制电路；所述电流控制电路被配置为，生成驱动信号，以驱动所述发光器件发光；所述时长控制电路被配置为，生成时长控制信号，以控制所述电流控制电路和所述发光器件之间的导通时长；
    其中，所述电流控制电路和所述时长控制电路，与同一条数据线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述多个子像素沿第二方向排列为多列；
    同一条数据线与至少一列子像素电连接。
  3. 根据权利要求2所述的显示基板，其中，任意相邻两条数据线之间，设置有至少一列子像素。
  4. 根据权利要求2或3所述的显示基板，还包括：
    与所述多条数据线电连接的多路输出选择电路；
    与所述多路输出选择电路电连接的多条数据传输线；及，
    与所述多路输出选择电路电连接的多条选择信号线；
    其中，所述多路输出选择电路被配置为，在所述多条选择信号线所传输的选择信号的控制下，将所述多条数据传输线所传输的数据信号，分时传输至所述多条数据线。
  5. 根据权利要求4所述的显示基板，其中，
    所述多条数据线至少包括：多条第一数据线、多条第二数据线和多条第三数据线；
    所述多条数据传输线至少包括：多条第一数据传输线、多条第二数据传输线和多条第三数据传输线；
    所述多路输出选择电路包括：多个选择晶体管组；选择晶体管组与选择信号线、第一数据线、第二数据线及第三数据线电连接；
    其中，第一数据传输线与至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第一数据线电连接；
    第二数据传输线与所述至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第二数据线电连接；
    第三数据传输线与所述至少两个选择晶体管组电连接，并通过所述至少两个选择晶体管组与相应的第三数据线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一数据传输线、所述第二数据传输线和所述第三数据传输线呈周期性排布；
    和/或，
    所述第一数据线、所述第二数据线和所述第三数据线呈周期性排布。
  7. 根据权利要求5或6所述的显示基板，其中，所述选择晶体管组至少包括：第一选择晶体管、第二选择晶体管和第三选择晶体管；
    所述第一选择晶体管的控制极与所述选择信号线电连接，所述第一选择晶体管的第一极与所述第一数据传输线电连接，所述第一选择晶体管的第二极与所述第一数据线电连接；
    所述第二选择晶体管的控制极与所述选择信号线电连接，所述第二选择晶体管的第一 极与所述第二数据传输线电连接，所述第二选择晶体管的第二极与所述第二数据线电连接；
    所述第三选择晶体管的控制极与所述选择信号线电连接，所述第三选择晶体管的第一极与所述第三数据传输线电连接，所述第三选择晶体管的第二极与所述第三数据线电连接。
  8. 根据权利要求4～7中任一项所述的显示基板，其中，同一条数据线与一列子像素电连接。
  9. 根据权利要求2或3所述的显示基板，其中，同一条数据线与至少两列子像素电连接；
    所述显示基板还包括：沿第二方向延伸的多条栅线；一个子像素与一条栅线电连接；
    其中，所述多个子像素沿所述第一方向排列为多行；一行子像素与至少两条栅线电连接；
    所述至少两条栅线被配置为，分别向相应的子像素传输扫描信号，以控制所述一行子像素分时接收所述数据线所传输的数据信号。
  10. 根据权利要求9所述的显示基板，其中，同一条数据线所电连接的子像素的列数，与同一行子像素所电连接的栅线条数，相等。
  11. 根据权利要求9或10所述的显示基板，其中，所述至少两条栅线分别设置在所述一行子像素的相对两侧。
  12. 根据权利要求9～11中任一项所述的显示基板，其中，同一行子像素中，任意相邻的两个子像素分别与不同栅线电连接。
  13. 根据权利要求2～12中任一项所述的显示基板，还包括：
    衬底；所述多条数据线所述多个子像素设置在所述衬底的一侧；以及，
    设置在所述衬底边缘的多条连接配线；连接配线的一端与至少一条所述数据线电连接，所述连接配线的另一端延伸至所述衬底的另一侧；
    在所述显示基板还包括多路输出选择电路、多条数据传输线的情况下，所述连接配线的一端与数据传输线电连接，并通过所述多路输出选择电路与多条数据线电连接。
  14. 根据权利要求1～13中任一项所述的显示基板，其中，
    所述电流控制电路至少与扫描信号端、数据信号端、第一使能信号端、第一电压信号端及第一节点电连接；所述电流控制电路被配置为，响应于在所述扫描信号端处接收的扫描信号、在所述数据信号端处接收的数据信号、在所述第一使能信号端处接收的第一使能信号及在所述第一电压信号端处接收的第一电压信号，生成驱动信号；
    所述时长控制电路至少与所述数据信号端、第一复位信号端、第二复位信号端、所述第一使能信号端、第二使能信号端、所述第一节点及所述发光器件电连接；所述时长控制电路被配置为，响应于所述数据信号和在所述第一复位信号端处接收的第一复位信号，根据在所述第二使能信号端处接收的第二使能信号控制所述第一节点和所述发光器件之间的导通时长；或，响应于所述数据信号和在所述第二复位信号端处接收的第二复位信号，根据在所述第一使能信号，控制所述第一节点和所述发光器件之间的导通时长；
    其中，所述电流控制电路和所述时长控制电路，均通过所述数据信号端与所述数据线电连接。
  15. 根据权利要求14所述的显示基板，其中，所述第一复位信号和所述第二复位信 号的有效电平时间不重合；
    所述数据信号中，与所述第一复位信号的有效电平相对应的电平、及与所述第二复位信号的有效电平相对应的电平中的一者，为有效电平。
  16. 根据权利要求14或15所述的显示基板，其中，在生成所述驱动信号的阶段，所述数据信号的电平跳变为有效电平的时间，早于所述扫描信号的电平跳变为有效电平的时间。
  17. 根据权利要求14～16中任一项所述的显示基板，其中，所述时长控制电路包括：
    第一控制子电路，至少与所述数据信号端、所述第一复位信号端、所述第二使能信号端及第二节点电连接；所述第一控制子电路被配置为，响应于所述数据信号和所述第一复位信号，将所述第二使能信号传输至所述第二节点；
    第二控制子电路，至少与所述数据信号端、所述第二复位信号端、所述第一使能信号端及所述第二节点电连接；所述第二控制子电路被配置为，响应于所述数据信号和所述第二复位信号，将所述第一使能信号传输至所述第二节点；及，
    第三控制子电路，与所述第一节点、所述第二节点及所述发光器件电连接；所述第三控制子电路被配置为，在来自所述第二节点的信号的控制下，控制所述第一节点和所述发光器件之间的导通时长。
  18. 根据权利要求17所述的显示基板，其中，所述第一控制子电路包括：第一晶体管、第二晶体管和第一电容器；
    所述第一晶体管的控制极与所述第一复位信号端电连接，所述第一晶体管的第一极与所述数据信号端电连接，所述第一晶体管的第二极与第三节点电连接；
    所述第二晶体管的控制极与所述第三节点电连接，所述第二晶体管的第一极与所述第二使能信号端电连接，所述第二晶体管的第二极与所述第二节点电连接；
    所述第一电容器的第一极与初始信号端电连接，所述第一电容器的第二极与所述第三节点电连接；
    所述第二控制子电路包括：第三晶体管、第四晶体管和第二电容器；
    所述第三晶体管的控制极与所述第二复位信号端电连接，所述第三晶体管的第一极与所述数据信号端电连接，所述第三晶体管的第二极与第四节点电连接；
    所述第四晶体管的控制极与所述第四节点电连接，所述第四晶体管的第一极与所述第一使能信号端电连接，所述第四晶体管的第二极与所述第二节点电连接；
    所述第二电容器的第一极与所述初始信号端电连接，所述第二电容器的第二极与所述第四节点电连接；
    所述第三控制子电路包括：第五晶体管；
    所述第五晶体管的控制极与所述第二节点电连接，所述第五晶体管的第一极与所述第一节点电连接，所述第五晶体管的第二极与所述发光器件电连接。
  19. 根据权利要求14～18中任一项所述的显示基板，其中，所述电流控制电路包括：
    数据写入子电路，与所述扫描信号端、所述数据信号端及第五节点电连接；所述数据写入子电路被配置为，在所述扫描信号的控制下，将所述数据信号传输至所述第五节点；
    驱动子电路，至少与所述第一节点、所述第五节点及第六节点电连接；所述驱动子电路被配置为，在所述第六节点的电压的控制下，将来自所述第五节点的信号传输至所述第一节点；
    补偿子电路，与所述扫描信号端、所述第一节点及所述第六节点电连接；所述补偿子电路被配置为，在所述扫描信号的控制下，将来自所述第一节点的信号传输至所述第六节点，以对所述驱动子电路进行阈值电压的补偿；以及，
    发光控制子电路，与所述第一使能信号端、所述第一电压信号端及所述第五节点电连接；所述发光控制子电路被配置为，在所述第一使能信号的控制下，将所述第一电压信号传输至所述第五节点。
  20. 根据权利要求19所述的显示基板，其中，所述数据写入子电路包括：第六晶体管；
    所述第六晶体管的控制极与所述扫描信号端电连接，所述第六晶体管的第一极与所述数据信号端电连接，所述第六晶体管的第二极与所述第五节点电连接；
    所述驱动子电路包括：第七晶体管和第三电容器；
    所述第七晶体管的控制极与所述第六节点电连接，所述第七晶体管的第一极与所述第五节点电连接，所述第七晶体管的第二极与所述第一节点电连接；
    所述第三电容器的第一极与所述第六节点电连接，所述第三电容器的第二极与所述第一电压信号端电连接；
    所述补偿子电路包括：第八晶体管；
    所述第八晶体管的控制极与所述扫描信号端电连接，所述第八晶体管的第一极与所述第一节点电连接，所述第八晶体管的第二极与所述第六节点电连接；
    所述发光控制子电路包括：第九晶体管；
    所述第九晶体管的控制极与所述第一使能信号端电连接，所述第九晶体管的第一极与所述第一电压信号端电连接，所述第九晶体管的第二极与所述第五节点电连接。
  21. 根据权利要求19或20所述的显示基板，其中，所述电流控制电路还包括：复位子电路；
    所述复位子电路与所述第一复位信号端、初始信号端、所述第六节点及所述发光器件电连接；所述复位子电路被配置为，响应于所述第一复位信号，将在所述初始信号端处接收的初始信号传输至所述第六节点及所述发光器件。
  22. 根据权利要求21所述的显示基板，其中，所述复位子电路包括：第十晶体管和第十一晶体管；
    所述第十晶体管的控制极与所述第一复位信号端电连接，所述第十晶体管的第一极与所述初始信号端电连接，所述第十晶体管的第二极与所述第六节点电连接；
    所述第十一晶体管的控制极与所述第一复位信号端电连接，所述第十一晶体管的第一极与所述初始信号端电连接，所述第十一晶体管的第二极与所述发光器件电连接。
  23. 一种显示基板的驱动方法，用于驱动如权利要求1～22中任一项所述的显示基板，所述驱动方法包括：
    向所述显示基板的多条数据线传输数据信号，同一子像素的电流控制电路和时长控制电路同时接收所述数据信号。
  24. 根据权利要求23所述的驱动方法，其中，所述电流控制电路包括数据写入子电路、驱动子电路、补偿子电路及发光控制子电路，所述时长控制电路包括第一控制子电路、第二控制子电路及第三控制子电路；
    在一帧显示阶段，所述驱动方法还包括：第一阶段、第二阶段、第三阶段和第四阶段；
    在所述显示基板的子像素所显示的灰阶大于或等于阈值灰阶的情况下，
    在所述第一阶段，响应于在第一复位信号端处接收的第一复位信号和所述数据信号，所述第一控制子电路关断；
    在所述第二阶段，响应于在第二复位信号端处接收的第二复位信号和所述数据信号，所述第二控制子电路导通，将在第一使能信号端处接收的第一使能信号传输至第二节点；
    在所述显示基板的子像素所显示的灰阶小于阈值灰阶的情况下，
    在所述第一阶段，响应于所述第一复位信号和所述数据信号，所述第一控制子电路导通，将在第二使能信号端处接收的第二使能信号传输至所述第二节点；
    在所述第二阶段，响应于所述第二复位信号和所述数据信号，所述第二控制子电路关断；
    其中，在所述第三阶段，响应于在扫描信号端处接收的扫描信号，所述数据写入子电路和所述补偿子电路导通，将所述数据信号依次经第五节点、所述驱动子电路、第一节点及所述补偿子电路，传输至第六节点，对所述驱动子电路进行阈值电压的补偿；
    在所述第四阶段，响应于所述第一使能信号，所述发光控制子电路导通，将在第一电压信号端处接收的第一电压信号依次经第五节点和所述驱动子电路，传输至所述第一节点。
  25. 根据权利要求24所述的驱动方法，其中，数据线被配置为，对所述数据信号进行存储；
    所述扫描信号端被配置为，在所述第三阶段，在所述数据线存储所述数据信号之后，传输所述扫描信号，以控制所述数据写入子电路和所述补偿子电路导通。
  26. 一种显示装置，包括：至少一个如权利要求1～22中任一项所述的显示基板。
  27. 根据权利要求26所述的显示装置，其中，所述显示基板包括衬底及设置在所述衬底边缘的多条连接配线；所述多条连接配线的一端位于所述衬底的一侧，所述多条连接配线的另一端延伸至所述衬底的另一侧；
    所述显示装置还包括：设置在所述衬底另一侧的驱动芯片；
    所述驱动芯片与所述多条连接配线的另一端电连接。
PCT/CN2021/132874 2021-11-24 2021-11-24 显示基板及其驱动方法、显示装置 WO2023092346A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1750100A (zh) * 2004-09-15 2006-03-22 三星Sdi株式会社 有机发光显示器及驱动方法
CN109801594A (zh) * 2017-11-17 2019-05-24 上海和辉光电有限公司 一种显示面板和显示装置
CN111477165A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 显示装置及其驱动方法
CN112585670A (zh) * 2019-07-18 2021-03-30 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN113096600A (zh) * 2021-03-30 2021-07-09 京东方科技集团股份有限公司 折叠显示面板、装置及其驱动方法、电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1750100A (zh) * 2004-09-15 2006-03-22 三星Sdi株式会社 有机发光显示器及驱动方法
CN109801594A (zh) * 2017-11-17 2019-05-24 上海和辉光电有限公司 一种显示面板和显示装置
CN112585670A (zh) * 2019-07-18 2021-03-30 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN111477165A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 显示装置及其驱动方法
CN113096600A (zh) * 2021-03-30 2021-07-09 京东方科技集团股份有限公司 折叠显示面板、装置及其驱动方法、电子设备

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