WO2022264215A1 - 半導体装置および電力変換装置 - Google Patents
半導体装置および電力変換装置 Download PDFInfo
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- WO2022264215A1 WO2022264215A1 PCT/JP2021/022530 JP2021022530W WO2022264215A1 WO 2022264215 A1 WO2022264215 A1 WO 2022264215A1 JP 2021022530 W JP2021022530 W JP 2021022530W WO 2022264215 A1 WO2022264215 A1 WO 2022264215A1
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- Prior art keywords
- metal foil
- semiconductor device
- semiconductor element
- surface electrode
- power
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 212
- 238000006243 chemical reaction Methods 0.000 title claims description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 230
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Images
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Definitions
- the present disclosure relates to a semiconductor device and a power conversion device having a metal foil partially bonded to a surface electrode.
- a wire material whose main component is aluminum (Al) is wired on the surface electrode of the power semiconductor element to ensure mechanical and electrical connection.
- a high-strength film made of a sintered metal layer is formed on the entire surface of the surface electrode of the power semiconductor element, thereby simplifying the manufacturing process rather than using a film forming method such as plating, and using Cu as the main material.
- a wire material used as a component is joined onto a power semiconductor element without damage (for example, Patent Document 1 and Patent Document 2).
- the present disclosure has been made to solve the above-described problems, and an object of the present disclosure is to provide a semiconductor device having improved reliability by providing a metal foil partially bonded to a surface electrode of a semiconductor element. .
- a semiconductor device includes a semiconductor element having a front surface and a back surface, a surface electrode formed on the surface of the semiconductor element, and a metal foil partially bonded to the upper surface of the surface electrode. It is a semiconductor device.
- the metal foil is partially bonded to the surface electrode of the semiconductor element, the stress generated at the edge of the metal foil can be relaxed, and failure due to cracks on the surface of the semiconductor element can be suppressed. As a result, the reliability of the semiconductor device can be improved.
- FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment
- FIG. 1 is a cross-sectional structural schematic diagram showing a semiconductor device according to a first embodiment
- FIG. 2 is a schematic plan view showing a metal foil of the semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1;
- FIG. 3 is a schematic plan view showing a metal foil of another
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1;
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1;
- FIG. 3 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1;
- FIG. 2 is a cross-sectional structure schematic diagram which shows the outer peripheral part of the conventional semiconductor device.
- FIG. 2 is a cross-sectional structural schematic diagram showing the outer peripheral portion of the semiconductor device in Embodiment 1;
- FIG. 2 is a cross-sectional structural schematic diagram showing the outer peripheral portion of the semiconductor device in Embodiment 1;
- FIG. 2 is a cross-sectional structural schematic diagram showing the outer peripheral portion of the semiconductor device in Embodiment 1;
- FIG. 10 is a schematic plan view showing a semiconductor device according to a second embodiment
- FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment
- FIG. 12 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 3 is applied;
- FIG. 1 is a schematic plan view showing a semiconductor device according to Embodiment 1.
- FIG. 2 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.
- FIG. 2 is a schematic cross-sectional view taken along the dashed-dotted line AA in FIG.
- a semiconductor device 100 includes a power semiconductor element 1 which is a semiconductor element, a surface electrode 2, a metal foil 3, a stirring region 4, a wiring member 5, a solder 6 which is a bonding material, and an insulating substrate 7. , is equipped with
- the back surface of the power semiconductor element 1 is joined to the metal layer 72 on the upper surface side of the insulating substrate 7 via solder 6 .
- a surface electrode 2 is formed on the surface of the power semiconductor element 1 .
- a metal foil 3 is formed on the upper surface of the surface electrode 2 . The surface electrode 2 and the metal foil 3 are partially joined, and the joining area between the surface electrode 2 and the metal foil 3 is the stirring area 4 .
- a wire 5 as a wiring member is formed on the upper surface of the metal foil 3 .
- the semiconductor device 100 has a configuration including one power module having one power semiconductor element 1 and three wires 5 .
- the semiconductor device 100 may have a configuration including a plurality of power modules each having one or more power semiconductor elements 1 and less than three or three or more wires 5 .
- FIG. 1 is a schematic plan view of the semiconductor device 100 viewed from above.
- the outermost solid line is the outer edge of the insulating layer 71 of the insulating substrate 7 .
- a metal layer 72 on the upper surface side of the insulating substrate 7 is arranged inside the outer edge of the insulating layer 71 of the insulating substrate 7 .
- two metal layers 72 are arranged on the upper surface of the insulating layer 71 of the insulating substrate 7 .
- the power semiconductor element 1 is arranged inside the outer edge of the metal layer 72 on the left side of the upper surface of the insulating substrate 7 .
- a surface electrode 2 is arranged inside the outer edge of the surface of the power semiconductor element 1 .
- a metal foil 3 is arranged inside the outer edge of the surface electrode 2 .
- a depression 31 of the metal foil 3 is arranged on the upper surface of the metal foil 3 in a region corresponding to the stirring region 4 which is a bonding region between the surface electrode 2 and the lower surface of the metal foil 3 .
- a wire 5 is arranged on the upper surface of the metal foil 3 .
- the wire 5 is arranged across the gap (spaced portion) between the outer edges of the left metal layer 72 and the right metal layer 72 on the upper surface side of the insulating substrate 7 .
- the wire 5 is arranged inside the outer edge of the power semiconductor element 1 inside the outer edge of the left metal layer 72 on the upper surface side of the insulating substrate 7 and inside the outer edge of the right metal layer 72 .
- FIG. 2 is a schematic cross-sectional view of the semiconductor device 100.
- the back surface of the power semiconductor element 1 is joined to the metal layer 72 on the right side of the upper surface of the insulating substrate 7 via the solder 6 .
- a metal foil 3 is arranged on the upper surface of the surface electrode 2 on the surface of the power semiconductor element 1 .
- the metal foil 3 is partially joined to the lower surface of the metal foil 3 and the surface of the surface electrode 2 via the stirring region 4 .
- the metal foil 3 has an uneven shape (wavy shape) in a cross-sectional view.
- the metal foil 3 is pressed against the upper surface of the surface electrode 2 using a jig. 31.
- the surface electrode 2 is deformed reflecting the shape of the metal foil 3 and is in contact with the area sandwiched between the adjacent recesses 31 .
- the lower surface of metal foil 3 is not joined to the upper surface of surface electrode 2 of power semiconductor element 1 . Therefore, the outer peripheral region of the metal foil 3 can be deformed.
- a wire 5 is connected (bonded) to the upper surface of the metal foil 3 .
- the power semiconductor element 1 is a power semiconductor element for electric power. Silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) can be used as the material of the power semiconductor element 1, for example. Also, the power semiconductor element 1 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), FWD (Free Wheel Diode), and RC-IGBT (Reverse Conducting Power IGBT). However, the type of power semiconductor element 1 is not limited to these. 1 and 2, the number of power semiconductor elements 1 is one, but the number of power semiconductor elements 1 is not limited to this.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- IGBT Insulated Gate Bipolar Transistor
- FWD Free Wheel Diode
- RC-IGBT Reverse Conducting Power IGBT
- the power semiconductor element 1 has a structure in which a front surface electrode 2 is arranged on the front surface of the power semiconductor element 1 and a rear surface electrode (not shown) is arranged on the rear surface of the power semiconductor element 1 .
- the power semiconductor element 1 is bonded to the top surface of the metal layer 72 on the left side of the top surface of the insulating substrate 7 via solder 6 as a bonding portion.
- the front surface electrode 2 of the power semiconductor element 1 is arranged on the opposite side of the center of the power semiconductor element 1 from the rear surface electrode (not shown).
- the surface electrode 2 of the power semiconductor element 1 is partially joined to the metal foil 3 via the stirring region 4 .
- a back electrode of the power semiconductor element 1 (not shown) is joined to the upper surface of the metal layer 72 on the left side of the upper surface of the insulating substrate 7 via the solder 6 .
- the surface electrodes 2 of the power semiconductor element 1 include, for example, control signal electrodes and main electrodes, but the types of the surface electrodes 2 of the power semiconductor element 1 are not limited to these. Either one of the control signal electrode and the main electrode may be provided as the surface electrode 2 of the power semiconductor element 1 .
- the bonding material 6 is arranged between the back electrode (not shown) of the power semiconductor element 1 and the metal layer 72 on the left side of the upper surface of the insulating substrate 7 . Thereby, the back electrode of the power semiconductor element 1 and the metal layer 72 on the left side of the upper surface of the insulating substrate 7 are mechanically and electrically connected.
- the material of the bonding material 6 for example, high-temperature solder containing lead (Pb) and tin (Sn) is used.
- the materials used for the bonding material 6 are not limited to these.
- Ag nanoparticle paste and Cu nanoparticle paste for example, can be used as the material of the bonding material 6 .
- a conductive adhesive containing Ag particles or Cu particles and an epoxy resin or the like can also be used.
- the insulating substrate 7 is a plate-like member.
- the insulating substrate 7 has an upper surface layer, an intermediate layer and a lower surface layer.
- the insulating substrate 7 has an insulating layer 71 as an intermediate layer, a metal layer 72 on the upper surface side of the insulating layer 71 as an upper surface layer, and a metal layer 73 on the lower surface side of the insulating layer 71 as a lower surface layer.
- the insulating substrate 7 is plate-shaped, and when the plate-shaped insulating substrate 7 is viewed from the plane (upper surface) direction, the size of the metal layer 72 on the upper surface side of the insulating layer 71 is smaller than the size of the insulating layer 71 .
- the size of the metal layer 73 on the lower surface side of the insulating layer 71 is smaller than the size of the insulating layer 71 .
- the end of insulating layer 71 protrudes outward beyond the ends of metal layer 72 on the upper surface side of insulating layer 71 and metal layer 73 on the lower surface side of insulating layer 71 .
- the metal layer 72 on the upper surface side of the insulating layer 71 is joined to the metal layer 73 on the lower surface side of the insulating layer 71 and the insulating substrate 7 with the insulating layer 71 interposed therebetween. This is for suppressing (securing creepage distance).
- the metal layer 72 on the upper surface side of the insulating layer 71 may be divided into a plurality of parts depending on the purpose to form a circuit pattern.
- the power semiconductor element 1 and the wire 5 are arranged on the metal layer 72 .
- Materials for the metal layer 72 on the upper surface side and the metal layer 73 on the lower surface side of the insulating substrate 7 include, from the viewpoint of electrical properties, thermal properties and mechanical properties, for example, Al, Cu, Ni, Au, or any of these. An alloy containing any one of them as a main component can be used. However, the materials used for the metal layer 72 on the upper surface side and the metal layer 73 on the lower surface side of the insulating substrate 7 are not limited to these.
- the upper surface side of the insulating substrate 7 is synonymous with the upper surface side of the insulating layer 71
- the lower surface side of the insulating substrate 7 is synonymous with the lower surface side of the insulating layer 71 .
- a ceramic substrate such as aluminum oxide ( Al2O3 ), aluminum nitride ( AlN) or silicon nitride ( Si3N4 ) can be used.
- materials for the ceramic substrate are not limited to these.
- an organic material filled with a ceramics filler As such an organic material, an epoxy resin, a polyimide resin, a cyanate resin, or the like is used.
- the ceramic filler Al 2 O 3 , AlN, boron nitride (BN), or the like can be used.
- a metal layer 72 (circuit pattern board) is joined to the upper surface of the insulating layer 71 using a method such as brazing or direct joining.
- a metal layer 73 (radiating plate) is joined to the lower surface of the insulating layer 71 by using a method such as brazing or direct joining.
- the wire 5 is preferably made of a material with good electrical conductivity, for example, Cu, Al, or an alloy containing at least one of these can be used.
- the wire 5 can be directly bonded to the upper surface of the metal foil 3 by an ultrasonic bonding method.
- the material and bonding method used for the wire 5 are not limited to these.
- the metal foil 3 is a thin plate-like (foil-like) member of metal.
- the metal foil 3 is directly bonded to the surface electrode 2 on the surface of the power semiconductor element 1 via the stirring region 4 .
- the material used for the metal foil 3 is not limited to these.
- the metal foil 3 can be directly bonded onto the surface electrode 2 on the surface of the power semiconductor element 1 by ultrasonic bonding or laser welding without using a bonding material.
- This directly joined area is the stirring area 4 .
- the material of the surface electrode 2 and the material of the metal foil 3 penetrated into the metal foil 3 and the surface electrode 2 at the interface between the lower surface of the metal foil 3 and the upper surface of the surface electrode 2, respectively.
- Agitated regions 4 can be formed which are (interdiffused) junctions.
- the stirring region 4 is not formed over the entire interface between the surface electrode 2 and the metal foil 3, but is formed partially.
- a contact surface protruding portion
- any shape can be formed by irradiating the laser according to the shape of the region where the stirring region 4 is desired to be formed.
- the thickness of the metal foil 3 is preferably in the range of 10 ⁇ m to 200 ⁇ m.
- the thickness of the metal foil 3 is thinner than (less than) 10 ⁇ m, mechanical and thermal energy are likely to propagate to the power semiconductor element 1, and there is concern that the power semiconductor element 1 may be damaged.
- the thickness of the metal foil 3 is thicker than (or more than) 200 ⁇ m, excessive mechanical and thermal energy is required to form the stirring region 4, and there is concern that the power semiconductor element 1 may be damaged. be done. Therefore, in order to suppress the occurrence of damage to the power semiconductor element 1 and to form a good stirring region 4, the thickness of the metal foil 3 should be in the range of 10 ⁇ m to 200 ⁇ m.
- the outer peripheral region (peripheral part) of the metal foil 3 is in a non-bonded state (non-bonded state) with the surface electrode 2 .
- the stress generated between the metal foil 3 and the surface electrode 2 is mainly generated at the outer periphery and corners of the metal foil 3 . Therefore, by leaving the outer peripheral portion of the metal foil 3 and the surface electrode 2 in an unbonded state, it is possible to obtain the effect of relieving the stress generated at the end portion of the metal foil.
- the outer peripheral portion of the metal foil 3 in an unbonded state with the surface electrode 2 is 5 ⁇ m or more from the end (outer edge) of the metal foil 3 .
- the state in which the metal foil 3 is not joined to the upper surface of the surface electrode 2 means that the end 32 of the metal foil 3 is not separated from the upper surface of the surface electrode 2 when stress is generated in the end 32 of the metal foil 3 . It refers to a state in which it is possible to move without moving.
- the surface electrode 2 and the metal foil 3 are joined using a joining material, but this joining process requires heat treatment at a high temperature of about 200 to 300°C. For this reason, thermal damage due to the heat treatment may deteriorate the joint due to remelting of the solder 6 at the joint between the power semiconductor element 1 and the insulating substrate 7 or structural change.
- the metal foil 3 is directly bonded to the surface electrode 2 on the surface of the power semiconductor element 1 without interposing a metal sintered layer or the like, heat treatment becomes unnecessary, and thermal damage to the semiconductor device 100 is suppressed. be able to.
- the wire 5 as the wiring member is bonded onto the upper surface of the metal foil 3, the wiring member such as the wire 5 can be bonded without damaging the power semiconductor element 1 when the wire 5 is bonded.
- the configuration of the semiconductor device 100 is not limited to the configuration described above.
- an insulating sheet is used instead of the insulating substrate 7, and the metal layer on the upper surface side of the insulating sheet constitutes the circuit pattern.
- the semiconductor device 100 includes a sealing member for securing insulation characteristics, a terminal for electrically connecting the semiconductor device 100 to the outside, or a terminal for the semiconductor device 100.
- a housing may be provided.
- FIG. 3 is a schematic plan view showing the metal foil of the semiconductor device according to Embodiment 1.
- FIG. 4 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 5 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 6 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 7 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. FIG. 8 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 9 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 10 is a schematic plan view showing a metal foil of another semiconductor device according to Embodiment 1.
- FIG. 3 to 10 show the shape and arrangement of the stirring region 4, which is the junction between the metal foil 3 and the surface electrode 2.
- FIG. 3 to 10 show
- the recessed portion 31 of the metal foil 3 is a partial joint portion with the upper surface of the surface electrode 2.
- the recessed portion 31 of the metal foil 3 is partially joined to the upper surface of the surface electrode 2 .
- a plurality of depressions 31 of the metal foil 3 are arranged in stripes at predetermined intervals.
- the depressions 31 of the metal foil 3 are arranged in a plurality of divided islands at predetermined intervals, as in FIG.
- the recessed portion 31 of the metal foil 3 is arranged to widen the contact area between the recessed portion 31 in the central region of the power semiconductor element 1 and the surface electrode 2, where the current flows intensively during the operation of the power semiconductor element 1. It is In FIG.
- the recessed portions 31 of the metal foil 3 are arranged by increasing the number of striped recessed portions 31 while maintaining the contact area with the surface electrode 2 in FIG.
- the recessed portions 31 of the metal foil 3 are arranged such that the contact area of the island-shaped recessed portions 31 in the central region of FIG. ing.
- the depressions 31 of the metal foil 3 are arranged by dividing the island-shaped depressions 31 arranged in the central region of FIG.
- the depressions 31 of the metal foil 3 are arranged such that the number of the depressions 31 in the central region of FIG. 8 is increased to reduce the current density in the central region of the metal foil 3 .
- the recessed portion 31 of the metal foil 3 is arranged such that the recessed portion 31 having a large contact area is arranged in the central region, and the periphery of the recessed portion 31 having a large contact area is surrounded by the recessed portion 31 having a small contact area. It's becoming In FIGS. 3 to 10 , the recessed portion 31 is surrounded by a contact area between the surface electrode 2 and the metal foil 3 .
- the size and total area of the bonding region between the metal foil 3 and the surface electrode 2 are not limited, but the size and total area may be appropriately set according to the allowable current (power) of the power semiconductor element 1 to be applied. Just do it. Formation of these recessed portions 31 can be realized, for example, by processing the contact surface of a jig for pressing the metal foil 3 against the surface electrode 2 .
- FIG. 11 is a schematic sectional view showing the outer periphery of a conventional semiconductor device.
- FIG. 12 is a schematic cross-sectional view showing the outer periphery of a conventional semiconductor device.
- FIG. 13 is a schematic cross-sectional view showing the outer peripheral portion of the semiconductor device according to the first embodiment.
- 14 is a schematic cross-sectional view showing the outer peripheral portion of the semiconductor device according to the first embodiment.
- FIG. 11 and 12 relate to a conventional joint structure. 13 and 14 are diagrams showing a joint structure using the metal foil 3.
- the surface electrode 2 and the metal foil 3 are bonded to the entire upper surface of the surface electrode 2 . Therefore, when stress is generated at the end 32 of the metal foil 3, for example, when the stress is generated toward the upper side of the metal foil 3 as indicated by the arrow in FIG. is pulled upwards. As the surface electrode 2 is pulled by the metal foil 3 , force is applied to a weaker portion than the joint between the surface electrode 2 and the metal foil 3 , and the surface electrode 2 is cracked. The generated crack grows toward the central region of power semiconductor element 1 .
- the current flowing through the power semiconductor element 1, which serves as a current path concentrates on the portion that was not separated due to the crack, causing heat generation, etc., and degrading the reliability of the semiconductor device.
- the contact area between the surface electrode 2 and the metal foil 3 decreases, causing an increase in thermal resistance or electrical resistance, which ultimately leads to failure of the semiconductor device. leads to
- the surface electrode 2 and the metal foil 3 are partially joined via the surface electrode 2 and the stirring region 4.
- the surface electrode 2 and the metal foil 3 are not joined at the outer periphery of the metal foil 3 . Therefore, when stress is generated at the end portion 32 of the metal foil 3, for example, when the stress is generated toward the upper side of the metal foil 3 as indicated by the arrow in FIG. is pulled upwards.
- the end portion 32 of the metal foil 3 The generated stress only pulls the unjoined region of the outer peripheral portion of the metal foil 3 .
- the stress does not affect the inside of the unbonded region (the central region of the power semiconductor element 1) of the upper surface of the surface electrode 2 of the metal foil 3, and the stirring region 4 does not peel off. Therefore, unlike the case where the metal foil 3 and the surface electrode are bonded over the entire surface as shown in FIG. 12, cracks do not develop. As a result, partial concentration of current flowing through the power semiconductor element 1 does not occur, and deterioration of the reliability of the semiconductor device can be suppressed.
- the metal foil 3 is joined to the upper surface of the surface electrode 2 via the stirring region 4 in this way, the stress generated at the end portion 32 of the metal foil 3 can be suppressed, and the metal foil can be displaced from the upper surface of the surface electrode 2 . 3 can be suppressed. As a result, reliability of the semiconductor device can be improved. Also, the life of the semiconductor device can be extended.
- the metal foil 3 is directly bonded to the surface electrode 2 on the surface of the power semiconductor element 1 by an ultrasonic bonding method or a laser welding method without using a metal sintered material or the like, heat treatment of the entire semiconductor device is not required, and soldering is not necessary. It is possible to suppress thermal damage to the internal structural members of the semiconductor device such as 6.
- the metal foil 3 is bonded to the upper surface of the surface electrode 2, even when a wire 5 made of a high-strength material such as a Cu wire is bonded to the upper surface of the metal foil 3, the power semiconductor element 1 is not affected by damage.
- a highly reliable semiconductor device can be obtained without
- the main manufacturing processes of the first embodiment are roughly divided into three processes.
- the power semiconductor element 1 and the like are bonded onto the insulating substrate 7 (power semiconductor element mounting step).
- the metal foil 3 is bonded onto the surface electrode of the power semiconductor element 1 (metal foil bonding step).
- the wire 5 is used to perform the answer wiring on the insulating substrate 7 (wiring formation step). Through these steps, the semiconductor device 100 can be manufactured.
- the power semiconductor element 1 is bonded (arranged) to a predetermined position on the metal layer 72 on the left side of the upper surface of the insulating substrate 7 (power semiconductor element mounting process).
- Solder 6 is used as a bonding material for bonding the power semiconductor element 1 .
- the metal foil 3 is bonded to the upper surface of the surface electrode 2 of the power semiconductor element 1 arranged on the upper surface of the metal layer 72 on the upper surface of the insulating substrate 7 (metal foil bonding step).
- metal foil bonding step For bonding the surface electrode 2 on the surface of the power semiconductor element 1 and the metal foil 3, for example, an ultrasonic bonding method is used.
- an ultrasonic bonding method is used for bonding the surface electrode 2 on the surface of the power semiconductor element 1 and the metal foil 3.
- the metal layer 72 to which the power semiconductor element 1 is bonded and the other metal layer 72 forming the circuit pattern are connected using the wire 5 (wiring forming step).
- the bonding position between the upper surface of the metal foil 3 bonded to the surface of the power semiconductor element 1 and the wire 5 can be selected according to the current (power) handled by the power semiconductor element 1, and the current density is high and the bonding area is large. A large area is desirable.
- the semiconductor device 100 can be manufactured.
- the insulating substrate 7 is bonded (placed) on the upper surface of the heat spreader.
- a frame is arranged surrounding the insulating substrate 7 in the outer peripheral region of the upper surface of the heat spreader (mounting process to the heat spreader).
- Solder is usually used for bonding the insulating substrate 7 .
- Adhesives are usually used for adhering (bonding) the frames.
- the insulating substrate 7 is placed, and the sealing member is filled in the area surrounded by the frame and the heat spreader (sealing member filling step). After the sealing member is filled, a lid portion is placed on the upper surface of the frame filled with the sealing member to seal the insulating substrate 7 in the frame (insulating substrate sealing step).
- connection between the heat spreader and the cooling section is performed using bolts (cooling section placement step).
- the semiconductor device 100 having the cooling section can be manufactured.
- the metal foil 3 is provided on the upper surface of the surface electrode 2 via the stirring region 4, the stress generated at the end 32 of the metal foil 3 can be suppressed. It becomes possible to suppress peeling of the metal foil 3 from the upper surface of the surface electrode 2 . As a result, reliability of the semiconductor device can be improved. Also, the life of the semiconductor device can be extended.
- the metal foil 3 is directly bonded to the surface electrode 2 on the surface of the power semiconductor element 1 by an ultrasonic bonding method or a laser welding method without using a metal sintered material or the like, heat treatment of the entire semiconductor device is not required, and soldering is not necessary. It is possible to suppress thermal damage to the internal structural members of the semiconductor device such as 6.
- the metal foil 3 is bonded to the upper surface of the surface electrode, even when a wire 5 made of a high-strength material such as a Cu wire is bonded to the upper surface of the metal foil 3, the power semiconductor element 1 is not affected by damage. , a highly reliable semiconductor device can be obtained.
- Embodiment 2 is different in that the wire 5 which is the wiring member used in the first embodiment is replaced with a plate-like wiring member 8 .
- the metal foil 3 is partially joined to the surface electrode 2 on the surface of the power semiconductor element 1 via the stirring region 4 .
- the stress at the end portion 32 of the surface electrode 2 can be relieved, and the occurrence of cracks in the surface electrode 2 can be suppressed. Since other points are the same as those of the first embodiment, detailed description thereof will be omitted.
- FIG. 15 is a schematic plan view showing the semiconductor device according to the second embodiment.
- FIG. 16 is a cross-sectional schematic diagram showing a semiconductor device according to the second embodiment.
- FIG. 16 is a schematic cross-sectional view taken along dashed-dotted line BB in FIG.
- a semiconductor device 200 includes a power semiconductor element 1 which is a semiconductor element, a surface electrode 2, a metal foil 3, a stirring region 4, a plate wiring member 8 which is a wiring member, and solder 6 which is a bonding material. , and an insulating substrate 7 .
- the back surface of the power semiconductor element 1 is joined to the metal layer 72 on the upper surface side of the insulating substrate 7 via solder 6 .
- a surface electrode 2 is formed on the surface of the power semiconductor element 1 .
- a metal foil 3 is formed on the upper surface of the surface electrode 2 .
- the surface electrode 2 and the metal foil 3 are partially joined, and the joining area is the stirring area 4 .
- a plate-shaped wiring member 8 as a wiring member is formed on the upper surface of the metal foil 3 .
- a recessed portion 31 of the metal foil 3 is indicated by a dotted line.
- the semiconductor device 100 has a configuration including one power module having one power semiconductor element 1 and three wires 5 .
- the semiconductor device 100 may have a configuration including a plurality of power modules each having one or more power semiconductor elements 1 and less than three or three or more wires 5 .
- FIG. 15 is a schematic plan view of the semiconductor device 200 viewed from above.
- the outermost solid line is the outer edge of the insulating layer 71 of the insulating substrate 7 .
- a metal layer 72 on the upper surface side of the insulating substrate 7 is arranged inside the outer edge of the insulating layer 71 of the insulating substrate 7 .
- two metal layers 72 are arranged on the upper surface of the insulating layer 71 of the insulating substrate 7 .
- the power semiconductor element 1 is arranged inside the outer edge of the metal layer 72 on the left side of the upper surface of the insulating substrate 7 .
- a surface electrode 2 is arranged inside the outer edge of the surface of the power semiconductor element 1 .
- a metal foil 3 is arranged inside the outer edge of the surface electrode 2 .
- a recessed portion 31 (dotted line) of the metal foil 3 is arranged in a region corresponding to the stirring region 4 that is the bonding region between the surface electrode 2 and the lower surface of the metal foil 3 .
- a plate-shaped wiring member 8 is arranged on the upper surface of the metal foil 3 .
- the plate-shaped wiring member 8 is arranged across the gap (spaced portion) between the outer edges of the left metal layer 72 and the right metal layer 72 on the upper surface side of the insulating substrate 7 .
- the plate-shaped wiring member 8 is arranged inside the outer edge of the power semiconductor element 1 inside the outer edge of the left metal layer 72 on the upper surface side of the insulating substrate 7 and inside the outer edge of the right metal layer 72 .
- FIG. 16 is a schematic cross-sectional view of the semiconductor device 200.
- the back surface of the power semiconductor element 1 is joined to the metal layer 72 on the left side of the upper surface of the insulating substrate 7 via the solder 6 .
- a metal foil 3 is arranged on the upper surface of the surface electrode 2 on the surface of the power semiconductor element 1 .
- the metal foil 3 is partially joined to the lower surface of the metal foil 3 and the surface of the surface electrode 2 via the stirring region 4 .
- the metal foil 3 has an uneven shape (wavy shape) in a cross-sectional view.
- the surface electrode 2 is deformed reflecting the shape of the metal foil 3 and is in contact with the area sandwiched between the adjacent recesses 31 .
- the lower surface of metal foil 3 is not joined to the upper surface of surface electrode 2 of power semiconductor element 1 . Therefore, the outer peripheral region of the metal foil 3 can be deformed.
- One end of a plate-like wiring member 8 is connected (bonded) to the upper surface of the metal foil 3 via solder 6 as a bonding material.
- the other end of the plate-shaped wiring member 8 is joined to the upper surface of the metal layer 72 on the right side of the insulating substrate 7 via solder 6 .
- the plate-like wiring member 8 is joined to the metal foil 3 and the metal layer 72 on the right side of the insulating substrate 7 via solder 6 as a joining material.
- the plate-shaped wiring member 8 is preferably made of a material having good electrical conductivity, and for example, Cu, Al, or an alloy containing at least one of these can be used. However, the material used for the plate-like wiring member 8 is not limited to these.
- the metal foil 3 is provided on the upper surface of the surface electrode 2 via the stirring region 4 , the stress generated at the end portion 32 of the metal foil 3 can be suppressed, and the metal foil can be dissipated from the upper surface of the surface electrode 2 . 3 can be suppressed. As a result, reliability of the semiconductor device can be improved. Also, the life of the semiconductor device can be extended.
- the plurality of semiconductor devices 200 when processing a plurality of semiconductor devices 200 in the bonding step of the solder 6, the plurality of semiconductor devices 200 can be processed collectively and bonded with the solder 6, and the plate-like wiring members 8 are bonded one by one.
- the manufacturing process is simplified as compared with the case.
- the metal foil 3 is provided on the upper surface of the surface electrode 2 via the stirring region 4, the stress generated at the end 32 of the metal foil 3 can be suppressed. It becomes possible to suppress peeling of the metal foil 3 from the upper surface of the surface electrode 2 . As a result, reliability of the semiconductor device can be improved. Also, the life of the semiconductor device can be extended.
- the plurality of semiconductor devices 200 when processing a plurality of semiconductor devices 200 in the bonding step of the solder 6, the plurality of semiconductor devices 200 can be processed collectively and bonded with the solder 6, and the plate-like wiring members 8 are bonded one by one.
- the manufacturing process is simplified as compared with the case.
- Embodiment 3 a power conversion device to which the semiconductor device described in the first and second embodiments is applied will be described.
- the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a third embodiment.
- FIG. 17 is a block diagram showing the configuration of a power conversion system to which the power converter according to this embodiment is applied.
- the power conversion system shown in FIG. 17 includes a power supply 1000, a power converter 2000, and a load 3000.
- the power supply 1000 is a DC power supply and supplies DC power to the power converter 2000 .
- the power supply 1000 can be composed of various things, for example, it can be composed of a DC system, a solar battery, and a storage battery. Alternatively, it may be composed of a rectifier circuit or an AC/DC converter connected to an AC system. Also, power supply 1000 may be configured with a DC/DC converter that converts DC power output from a DC system into predetermined power.
- the power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, converts the DC power supplied from the power supply 1000 into AC power, and supplies the AC power to the load 3000. As shown in FIG. 17, the power conversion device 2000 includes a main conversion circuit 2001 that converts DC power into AC power and outputs it, and a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the main conversion circuit 2001. and
- a load 3000 is a three-phase electric motor driven by AC power supplied from the power converter 2000 .
- the load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for an air conditioner.
- the main conversion circuit 2001 includes a switching element and a freewheeling diode (not shown). By switching the switching element, DC power supplied from power supply 1000 is converted into AC power and supplied to load 3000 .
- the main conversion circuit 2001 has various specific circuit configurations, the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel.
- each switching element and each freewheeling diode of the main converter circuit 2001 is a switching element or a freewheeling diode included in the semiconductor device 2002 corresponding to the semiconductor device according to at least one of the first to fifth embodiments described above.
- the six switching elements constitute upper and lower arms connected in series for every two switching elements, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
- Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 2001 are connected to the load 3000 .
- the main conversion circuit 2001 includes a drive circuit (not shown) for driving each switching element. may be provided.
- the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies it to the control electrode of the switching element of the main conversion circuit 2001 .
- a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
- the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).
- the control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000 . Specifically, based on the power to be supplied to the load 3000, the time (on time) during which each switching element of the main converter circuit 2001 should be in the ON state is calculated. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) to the drive circuit provided in the main conversion circuit 2001 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state at each time. to output The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
- the semiconductor device according to the first to fifth embodiments is applied as the semiconductor device 2002 that constitutes the main conversion circuit 2001 .
- longitudinal cracks in the solder 6 that joins the power semiconductor element 1 to the insulating substrate 7 can be suppressed.
- the reliability of power converter 2000 can be improved.
- the present disclosure is not limited to this, and can be applied to various power converters.
- a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. Disclosure may apply.
- the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.
- the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used, and furthermore, it can be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.
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Abstract
Description
図1は、実施の形態1における半導体装置を示す平面構造模式図である。図2は、実施の形態1における半導体装置を示す断面構造模式図である。図2は、図1の一点鎖線AAにおける断面構造模式図である。
本実施の形態2においては、実施の形態1で用いた配線部材であるワイヤ5を板状配線部材8に置き換えた点が異なる。このように、配線部材として板状配線部材8を用いた場合においても、金属箔3をパワー半導体素子1の表面の表面電極2と撹拌領域4を介して部分的に接合したので、金属箔3の端部32での応力を緩和することができ、表面電極2のクラックの発生を抑制することができる。なお、その他の点については、実施の形態1と同様であるので、詳しい説明は省略する。
ここでは、上述した実施の形態1~2において説明した半導体装置を適用した電力変換装置について説明する。本開示は特定の電力変換装置に限定されるものではないが、以下、実施の形態3として、三相のインバータに本開示を適用した場合について説明する。
Claims (10)
- 表面と裏面とを有する半導体素子と、
前記半導体素子の表面上に形成された表面電極と、
前記表面電極の上面上に部分的に接合された金属箔と、
を備えた半導体装置。 - 前記金属箔は、前記金属箔の外周領域と前記表面電極の上面とが接合されてない、請求項1に記載の半導体装置。
- 前記表面電極と前記金属箔とは、直接接合された、請求項1または請求項2に記載の半導体装置。
- 前記直接接合された領域には、撹拌領域が形成されている、請求項3に記載の半導体装置。
- 前記金属箔の材料は、アルミニウム、銅、ニッケル、金、モリブデンまたはこれらのいずれかを主成分とする合金である、請求項1から請求項4のいずれか1項に記載の半導体装置。
- 前記金属箔の上面には、配線部材が配置された、請求項1から請求項5のいずれか1項に記載の半導体装置。
- 前記配線部材は、前記金属箔と直接接合された、請求項6に記載の半導体装置。
- 前記配線部材は、接合材を介して前記金属箔の上面と接合された、請求項6に記載の半導体装置。
- 前記配線部材の材料は、銅、アルミニウムまたはこれらのうち少なくとも一方を含む合金である、請求項6から請求項8のいずれか1項に記載の半導体装置。
- 請求項1から請求項9のいずれか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、
を備えた、電力変換装置。
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JPH10261664A (ja) * | 1997-01-17 | 1998-09-29 | Furukawa Electric Co Ltd:The | 半導体素子、突起電極の形成方法およびワイヤボンディング方法 |
JP2006173509A (ja) * | 2004-12-20 | 2006-06-29 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2015142063A (ja) * | 2014-01-30 | 2015-08-03 | 三菱電機株式会社 | パワーモジュール及びパワーモジュールの製造方法 |
WO2016063744A1 (ja) * | 2014-10-20 | 2016-04-28 | 三菱電機株式会社 | パワーモジュール |
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JPH10261664A (ja) * | 1997-01-17 | 1998-09-29 | Furukawa Electric Co Ltd:The | 半導体素子、突起電極の形成方法およびワイヤボンディング方法 |
JP2006173509A (ja) * | 2004-12-20 | 2006-06-29 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2015142063A (ja) * | 2014-01-30 | 2015-08-03 | 三菱電機株式会社 | パワーモジュール及びパワーモジュールの製造方法 |
WO2016063744A1 (ja) * | 2014-10-20 | 2016-04-28 | 三菱電機株式会社 | パワーモジュール |
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