WO2022262272A1 - 一种超细节距半导体互连结构及其成型方法 - Google Patents

一种超细节距半导体互连结构及其成型方法 Download PDF

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WO2022262272A1
WO2022262272A1 PCT/CN2022/072575 CN2022072575W WO2022262272A1 WO 2022262272 A1 WO2022262272 A1 WO 2022262272A1 CN 2022072575 W CN2022072575 W CN 2022072575W WO 2022262272 A1 WO2022262272 A1 WO 2022262272A1
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nano
copper
copper particles
ultra
interconnection structure
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PCT/CN2022/072575
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English (en)
French (fr)
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张昱
童金
崔成强
梁沛林
杨冠南
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广东工业大学
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Priority to US17/897,086 priority Critical patent/US11742316B2/en
Publication of WO2022262272A1 publication Critical patent/WO2022262272A1/zh

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Definitions

  • the invention relates to the field of semiconductor production and manufacturing, in particular to an ultra-fine-pitch semiconductor interconnection structure and a forming method thereof.
  • the feature size of the manufacturing process of integrated circuits has entered the 20/14nm technology node, and the matching flip-chip interconnection bump will be reduced from 40-50 ⁇ m to 5 ⁇ m.
  • the traditional lead-free solder bump technology In order to achieve precise alignment with the solder pads on the circuit board, the traditional lead-free solder bump technology generally has a large distance between solder balls, which limits the total number of I/Os of electronic devices, which severely limits high-density packaging. interconnected development needs.
  • Replacing lead-free solder bumps with copper pillars can avoid problems such as solder ball bridging caused by reflow soldering, and at the same time improve the interconnection strength between the chip and the substrate.
  • the new-generation copper pillar bump interconnection technology has the advantages of good electrical conductivity, thermal conductivity, electromigration resistance, and higher reliability. requirements.
  • Copper pillar bump technology has unique advantages in realizing ultra-fine-pitch package interconnection, but the use of copper pillars will lead to high interconnection temperature, poor positioning of ultra-fine-pitch semiconductors and circuit board pads, etc.
  • the purpose of the present invention is to propose an ultra-fine-pitch semiconductor interconnection structure and its forming method.
  • the ultra-fine-pitch micro-copper pillars are flipped on the nano-copper layer prepared by vapor deposition to realize low-temperature and low-pressure transient
  • the interconnection solves the problem of poor positioning accuracy between the chip and the substrate.
  • a method for forming an ultra-fine-pitch semiconductor interconnection structure comprising the steps of:
  • the vapor deposition device uses the vapor deposition method to prepare nano-copper particles
  • the semi-finished semiconductor interconnection structure after the oxidation treatment is cleaned to remove the residual copper oxide particles, so as to obtain the ultra-fine-pitch semiconductor interconnection structure.
  • the step of bringing the nano-copper particles from the vapor deposition device into the collecting device further includes the following content: bringing the nano-copper particles from the deposition device into the collecting device under the environment of a protective gas and an external electric field.
  • the protective gas used in this process step plays a protective role and can prevent the oxidation of the nano-copper particles during the transfer to the collection device.
  • the vapor deposition device At the same time, if there is no protective gas in the vapor deposition device, the vapor deposition device The gas atmosphere has a great influence on the particle size, shape and appearance of the produced nano-copper particles, making it difficult to accurately control the quality of the transferred nano-copper particles in the vapor deposition device, and it is also difficult to obtain ultra-fine-pitch semiconductor interconnection structures in the future .
  • the protective gas is nitrogen, argon or helium, and the protective gas is doped with a reducing gas with a content of not more than 5%, and the reducing gas is hydrogen, formaldehyde or carbon monoxide; the doping reducing
  • the purpose of the gas is to reduce the produced copper oxide particles while avoiding the oxidation of nano-copper under high temperature conditions.
  • said adjusting the coupling parameters of the vapor deposition device, controlling the initial particle size of the nano-copper particles in the step of producing the initial particle size of the nano-copper particles is less than 20nm; said bringing the nano-copper particles from the vapor deposition device Into the collecting device, and in the step of depositing on the substrate in the deposition area of the collecting device, the gas flow rate of the protective gas flowing into the deposition device is 0.5-5 L/min.
  • the specific value of the flow rate of the shielding gas needs to be determined according to the vapor deposition device used and the particle size of the nano-copper particles to be prepared.
  • the flow rate of the shielding gas in the vapor-phase deposition method has a great influence on the particle size of the prepared nano-copper particles. Excessive gas flow rate will cause a large loss of nano-copper particles, and too small gas flow rate will lead to agglomeration of nano-copper particles, which will affect the quality of subsequent sintering and bonding.
  • the vapor deposition method is: vacuum evaporation PVD, magnetron sputtering PVD, spark burning candle stamping deposition, or ion plating method, etc.
  • the initial particle size of nano-copper prepared according to different vapor deposition methods has certain differences, which can realize chip interconnection with copper pillar I/O output ports of different pitches.
  • the step of hot-pressing and sintering the copper pillars to bond the chip to the substrate also includes the following content: using heat, laser, electromagnetic or ultrasonic existing technology, pressurizing the chip and the substrate through the fixture to fit the existing The sintering process means to bond the chip to the substrate in a short time.
  • the method of oxidizing the nano-copper particles in the remaining region may be: use an oxidizing fluid to contact the nano-copper particles for oxidation , the oxidizing fluid is hot air, oxygen or hydrogen peroxide; it may also be: directly placing the semi-finished semiconductor interconnection structure in an oven for baking and oxidation treatment.
  • the step of cleaning the semi-finished semiconductor interconnection structure after the oxidation treatment and removing the residual copper oxide particles includes the following content: according to the particle size of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, Select dilute sulfuric acid with a concentration of 5%-10% to clean the deposition area of the substrate of the semi-finished semiconductor interconnection structure to remove residual copper oxide, and then use absolute ethanol to clean excess dilute sulfuric acid solution.
  • a complete layer of nano-copper film is formed on the substrate by vapor deposition, and the nano-copper film covers both the interconnection I/O and the positions that do not require interconnection, eliminating the need for conventional mask-assisted methods.
  • the purpose of cleaning is mainly to remove nano-copper particles that do not need to be interconnected. If it is not cleaned, it will lead to conduction between the interconnection position and other positions, which will affect the electrical performance of the chip.
  • the technical difficulty of cleaning is not to damage the interconnection between the substrate and the ultra-fine-pitch micron copper pillars, and at the same time to completely oxidize and remove the excess copper nanoparticles; the above-mentioned technical solution can achieve rapid cleaning of the semi-finished semiconductor interconnection structure, After drying, the ultra-fine-pitch semiconductor interconnection structure can be obtained, so that the forming precision of the ultra-fine-pitch semiconductor is high, and the interconnection structure has better thermoelectric interconnection performance and reliability.
  • An ultra-fine-pitch semiconductor interconnection structure which is prepared according to the molding method described above.
  • the forming method prepares nano-copper particles by vapor deposition, adjusts the coupling parameters in the vapor deposition device to control the size of the generated nano-copper particles, then deposits the prepared nano-copper particles on the substrate, and then deposits the nano-copper particles with I/
  • the chip of the O output port is flip-chip on the substrate, and the bonding of the chip and the substrate is realized by hot pressing and sintering.
  • the nano-copper particles prepared by the vapor deposition device in the forming method have the characteristics of controllable particle size and high purity, avoiding the need for various precursors, solvents or reducing agents and other toxic and environmentally polluting chemical substances in the chemical method preparation, and Organic matter residues affect sintering performance and device reliability, and the molding method can be applied to any conductive material including semiconductors. It is flexible and can avoid problems such as storage and oxidation of nano-copper particles; it can effectively solve ultra-fine pitch chips Problems such as poor positioning with the substrate pad can meet the needs of high-density packaging interconnection.
  • Fig. 1 is a schematic flow chart of the forming method in one embodiment of the present invention.
  • a method for forming an ultra-fine-pitch semiconductor interconnection structure includes the following steps:
  • the vapor deposition device uses the vapor deposition method to prepare nano-copper particles.
  • the nano-copper particles are brought into the collection device from the vapor deposition device, and deposited on the substrate in the deposition area of the collection device.
  • the chip with the copper pillar I/O output port is placed upside down on the deposition area on the substrate, and the copper pillar is hot-pressed and sintered to bond the chip to the substrate to obtain a semi-finished semiconductor interconnection structure.
  • the nanometer copper particles in the residual area in the semi-finished semiconductor interconnection structure are oxidized.
  • the semi-finished semiconductor interconnection structure after the oxidation treatment is cleaned to remove the residual copper oxide particles, so as to obtain the ultra-fine-pitch semiconductor interconnection structure.
  • a method for forming an ultra-fine-pitch semiconductor interconnection structure comprising the following steps:
  • Step 1 using a spark ablation device to prepare nano-copper particles
  • Step 2 setting the voltage and current at both ends of the electrodes of the spark ablation device to 1.2Kv, 10mA, and the airflow velocity to 5L/min to control the initial particle size of the nano-copper particles to 2-5nm;
  • Step 3 Introduce N 2 with a purity of 99.999% into the preparation system. On the one hand, it removes the air in the spark ablation preparation chamber; Copper particles are deposited on the deposition area on the substrate through the stamping system in the collection device until the whole process is completed, the ventilation is stopped, the distance between the stamping nozzle and the substrate is 1 mm, and the thickness of the deposited nano-copper layer is 0.2 ⁇ m;
  • Step 4 absorb and transfer the chip with a copper pillar pitch of 5 ⁇ m through the vacuum pad, and flip it into the deposition area where the nano-copper particles are deposited on the substrate;
  • Step 5 Use a laser with a wavelength of 355nm, a frequency of 150KHz, and a power of 0.16W to scan and heat the connection area between the copper pillar and the substrate at a speed of 100-200mm/s to 180°C, and pressurize the chip to 0.5MPa through the fixture. Ultrasonic for fast bonding;
  • Step 6 after the chip bonding is completed, use hot air/oxygen to oxidize the entire packaging structure
  • Step 7 according to the thickness of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, using the characteristics of the different thicknesses of the prepared and deposited nano-copper particles and the thickness of the copper layer, select a dilute sulfuric acid with a concentration of 5% to 10% to The deposition area attached to nano-copper on the substrate is cleaned to remove residual copper oxide, and then the excess dilute sulfuric acid solution is cleaned with absolute ethanol to achieve the purpose of rapid cleaning. After washing and drying, the interconnected sample is obtained, which has better thermal and electrical interconnection performance and reliability.
  • a method for forming an ultra-fine-pitch semiconductor interconnection structure comprising the following steps:
  • Step 1 using a vacuum evaporation device whose evaporation source is an electron beam to prepare nano-copper particles;
  • Step 2 using an electron beam with a spot diameter of 5um, accelerated by an electric field of 10Kv, and bombarding the target with an inclination angle of 15°, to control the initial size of the nano-copper particles to be 10-20nm;
  • Step 3 Vacuumize the preparation device to ensure that the vacuum degree is ⁇ 10 -6 Pa, and feed N 2 with a purity of 99.999%, so that the gaseous nanoparticles are oriented and transported to the substrate in a linear motion without collision until the entire preparation process End, stop ventilation; control the distance between the evaporation source and the substrate to 20cm, and deposit the thickness of the nano-copper layer to 0.5 ⁇ m;
  • Step 4 attracting and transferring the chip with a copper pillar pitch of 20 ⁇ m by electromagnetic control, and flip-chip it in the deposition area where the nano-copper particles are deposited on the substrate;
  • Step 5 heating the substrate to 120°C with the heat generated by the electromagnetic wave radiation generated by the alternating electric field, and the wavelength of the electromagnetic wave is 10 3 MHz.
  • an alternating current of 220V and 50Hz is passed in the vertical direction of the chip to assist sintering, and the chip is heated with a fixture. Pressure to 1MPa;
  • Step 6 after the chip bonding is completed, use hydrogen peroxide with a concentration of 5% to 8% to oxidize the residual nano-copper in the local area of the packaging structure;
  • Step 7 according to the thickness of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, using the characteristics of the different thicknesses of the prepared and deposited nano-copper particles and the thickness of the copper layer, select a dilute sulfuric acid with a concentration of 5% to 10% to The area attached to the nano-copper on the substrate is cleaned to remove the residual copper oxide, and then the excess dilute sulfuric acid solution is cleaned with absolute ethanol to achieve the purpose of rapid cleaning. After washing and drying, the interconnected sample is obtained, which has good thermal and electrical interconnection performance and reliability.
  • Step 1 using the magnetron sputtering method to prepare nano-copper particles
  • Step 2 Vacuumize the preparation system, the copper target is used as the cathode target, and the substrate is used as the anode, and 0.1-10 Pa of argon gas is introduced into the vacuum chamber so that it is ionized under electron collision to generate Ar + , and the cathode target 1 - Under the action of 3kV DC negative high voltage or 13.56MHz radio frequency voltage, bombard the target with high energy to generate glow discharge, control the initial size of nano-copper particles to 5-10nm, until the thickness of the deposited copper layer meets the requirements, stop the ventilation;
  • Step 3 accelerating the ionized and evaporated nano-copper particles under an electric field of 10Kv to deposit them on the substrate in a directional manner, and the thickness of the deposited nano-copper layer is 0.2um;
  • Step 4 Precisely grasp and transfer the copper pillars with a pitch of 10 ⁇ m by the robotic arm, and flip-chip it in the deposition area where the nano-copper particles are deposited on the substrate;
  • Step 5 heat the substrate to 180°C with an ultrasonic hot-press furnace, pressurize the chip and the substrate to 0.25MPa with an ultrasonic pressure probe, and heat-preserve and sinter for 20 minutes with an ultrasonic power of 210W;
  • Step 6 put the bonded interconnection structure into an oven, set the temperature at 60°C, and oxidize the remaining nano copper in the interconnection structure;
  • Step 7 according to the thickness of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, using the characteristics of the different thicknesses of the prepared and deposited nano-copper particles and the thickness of the copper layer, select a dilute sulfuric acid with a concentration of 5% to 10% to The area attached to the nano-copper on the substrate is cleaned to remove the residual copper oxide, and then the excess dilute sulfuric acid solution is cleaned with absolute ethanol to achieve the purpose of rapid cleaning. After washing and drying, the interconnected sample is obtained, which has good thermal and electrical interconnection performance and reliability.
  • Step 1 using a high-energy laser as a heat source to prepare an evaporated film
  • Step 2 Vacuum the preparation system, feed N 2 with a purity of 99.999%, to prevent the oxidation of the produced nano-copper particles, use a pulsed laser with a wavelength of 308nm, a pulse width of 20ns, a pulse frequency of 20Hz, and a power of 650mJ on copper
  • the target is heat-treated to make it evaporate to generate high-temperature and high-pressure plasma, and the initial size of nano-copper particles is controlled to be 10-20nm;
  • Step 3 the laser continues to process the evaporated plasma after ionization, so that it is directional accelerated under the action of an external electric field of 2Kv, and is emitted and deposited on the substrate at an inclination angle of 30° to form a film, and the thickness of the deposited film is 1um;
  • Step 4 absorb and transfer the chip with a copper pillar spacing of 30 ⁇ m through the vacuum pad, and flip it on the substrate where the nano-copper particles are deposited;
  • Step 5 Use a laser with a wavelength of 355nm, a frequency of 200KHz, and a power of 2.5W to scan and heat the connection area between the copper column and the substrate at a speed of 50-100mm/s to 260°C, pressurize the chip to 1MPa through the fixture, and cooperate with ultrasonic Realize fast bonding;
  • Step 6 after the chip bonding is completed, use hot air/oxygen to oxidize the entire packaging structure
  • Step 7 according to the thickness of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, using the characteristics of the different thicknesses of the prepared and deposited nano-copper particles and the thickness of the copper layer, select a dilute sulfuric acid with a concentration of 5% to 10% to The area attached to the nano-copper on the substrate is cleaned to remove the residual copper oxide, and then the excess dilute sulfuric acid solution is cleaned with absolute ethanol to achieve the purpose of rapid cleaning. After washing and drying, the interconnected sample is obtained, which has good thermal and electrical interconnection performance and reliability.
  • Step 1 using a multi-arc ion plating method to prepare a nano-copper film
  • Step 2 Evacuate the vacuum chamber of the preparation system to a vacuum degree above 4 ⁇ 10 -3 Pa, the copper target is used as the anode, the silicon substrate is used as the cathode, and Ar gas with a purity of 0.1-1 Pa and a purity of 99.999% is introduced into the vacuum chamber , apply a negative voltage of 1-5kV between the anode and the cathode, so that arc discharge occurs between the two electrodes under the argon gas as the medium. Under the action of the discharge electric field, the ionized Ar + is attracted by the cathode negative pressure to bombard the surface of the silicon wafer, and the substrate is removed. Surface dirt, stop feeding gas after the surface of the substrate reaches the cleaning standard;
  • Step 3 Turn on the AC power supply of the evaporation source, vaporize and evaporate the copper target and collide with Ar atoms and ions, control the initial size of the nano-copper particles to 10-20nm, and deposit them on the silicon substrate under the action of a negative high-voltage electric field Form a film on the surface so that the thickness of the nano-copper film is 0.5 ⁇ m;
  • Step 4 Precisely grasp and transfer the chip with a copper column spacing of 15 ⁇ m by the robotic arm, and flip it onto the substrate where copper nanoparticles are deposited;
  • Step 5 heat the substrate to 180°C with an ultrasonic hot-press furnace, pressurize the chip and the substrate to 0.25MPa with an ultrasonic pressure probe, and heat-preserve and sinter for 20 minutes with an ultrasonic power of 210W;
  • Step 6 put the bonded interconnection structure into an oven, set the temperature at 80°C, and oxidize the remaining nano-copper in the interconnection structure;
  • Step 7 according to the thickness of the prepared and deposited nano-copper particles and the thickness of the copper layer formed by sintering, using the characteristics of the different thicknesses of the prepared and deposited nano-copper particles and the thickness of the copper layer, select a dilute sulfuric acid with a concentration of 5% to 10% to The area attached to the nano-copper on the substrate is cleaned to remove the residual copper oxide, and then the excess dilute sulfuric acid solution is cleaned with absolute ethanol to achieve the purpose of rapid cleaning. After washing and drying, the interconnected sample is obtained, which has good thermal and electrical interconnection performance and reliability.
  • An ultrafine semiconductor interconnection structure can be prepared according to any one of the above-mentioned embodiments 1-6.
  • the present application proposes an ultrafine semiconductor interconnection structure and its forming method.
  • the forming method prepares nano-copper particles by vapor deposition, and adjusts the coupling parameters in the vapor-phase deposition device to control the generation of nano-copper particles. Then deposit the prepared nano-copper particles on the substrate, then flip the chip with I/O output port on the substrate, and realize the bonding of the chip and the substrate by hot pressing and sintering.
  • the nano-copper particles prepared by the vapor deposition device in the forming method have the characteristics of controllable particle size and high purity, avoiding the need for various precursors, solvents or reducing agents and other toxic and environmentally polluting chemical substances in the chemical method preparation, and Organic matter residues affect sintering performance and device reliability, and the molding method can be applied to any conductive material including semiconductors. It is flexible and can avoid problems such as storage and oxidation of nano-copper particles; it can effectively solve ultra-fine pitch chips Problems such as poor positioning with the substrate pad can meet the needs of high-density packaging interconnection.

Abstract

本发明涉及半导体生产制造领域，特别是一种超细节距半导体互连结构及其成型方法。所述成型方法通过气相沉积法制备出纳米铜颗粒，调节气相沉积装置中的耦合参数控制生成纳米铜颗粒的大小，将制备的纳米铜颗粒沉积在基板上，并把带有I/O输出端口的芯片倒装在基板上，通过热压烧结实现芯片与基板的键合。所述成型方法中通过气相沉积装置制备出的纳米铜颗粒具有粒径可控，纯度高等特点，避免了化学法制备所带来的多种问题；所述成型方法可应用于包括半导体在内任何导电材料，灵活多高，可避免纳米铜颗粒存贮氧化等问题；能有效解决超细节距芯片与基板焊盘间定位差等问题，可满足高密度封装互连的需要。

Description

一种超细节距半导体互连结构及其成型方法 技术领域
本发明涉及半导体生产制造领域，特别是一种超细节距半导体互连结构及其成型方法。
背景技术
随着电子产品向微型化和智能化方向发展，集成电路的制造工艺特征尺寸进入到20/14nm技术节点，与之匹配倒装互连凸点将由40-50μm缩小到5μm。传统的无铅焊料凸点技术为了实现与线路板上的焊盘精确对准，一般焊球与焊球间距较大，从而限制了电子器件I/O的总数量，这严重限制了高密度封装互连的发展需求。以铜柱代替无铅焊料凸点可以避免由于回流焊中造成的焊球桥连等问题，同时提高芯片与基板间的互连强度。新一代铜柱凸点互连技术由于具有良好的导电、导热、抗电迁移能力、更高的可靠性等优点，目前正成为下一代芯片超细节距互连的关键技术，满足高密度三维封装的要求。
铜柱凸点技术在实现超细节距的封装互连中具有独特的优势，但使用铜柱会导致互连温度很高，超细节距半导体与线路板焊盘定位差等问题。
发明内容
针对上述缺陷，本发明的目的在于提出一种超细节距半导体互连结构及其成型方法，将超细节距微米铜柱倒装在通过气相沉积法制备的纳米铜层上，实现低温低压瞬态互连，解决了芯片与基板间定位精度差的问题。
为达此目的，本发明采用以下技术方案：
一种超细节距半导体互连结构的成型方法，其包括如下步骤：
气相沉积装置使用气相沉积法制备纳米铜颗粒；
调节气相沉积装置的耦合参数，控制生产纳米铜颗粒的初始粒径；
将纳米铜颗粒从气相沉积装置带入收集装置中，并沉积在收集装置沉积区域的基板上；
将带有铜柱I/O输出端口的芯片倒立放置在基板上的沉积区域，对铜柱进行热压烧结，使芯片与基板键合，得到半成品半导体互连结构；
将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理；
对氧化处理后的半成品半导体互连结构进行清洗，除去残余的氧化铜颗粒，得到超细节距半导体互连结构。
更优的，所述将纳米铜颗粒从气相沉积装置带入收集装置中的步骤还包括如下内容：通入保护气体和外加电场的环境下，将纳米铜颗粒从沉积装置带入收集装置中。该工艺步骤中用到的保护气体是起到保护作用，可以起到防止纳米铜颗粒在转移至收集装置的过程中被氧化，同时在气相沉积装置中如果没有保护气体通入，气相沉积装置的气体氛围对产生的纳米铜颗粒粒径、形状样貌都会有很大的影响，使得气相沉积装置中的转移出来的纳米铜颗粒质量难以得到精准控制，后续也难以得到超细节距半导体互连结构。
更优的，所述保护气体为氮气、氩气或氦气，且保护气体中掺杂有含量不超过5％的还原性气体，所述还原性气体为氢气、甲醛或一氧化碳；掺杂还原性气体的目的是还原产生的氧化铜颗粒，同时避免高温条件下纳米铜发生氧化。
更优的，所述调节气相沉积装置的耦合参数，控制生产纳米铜颗粒的初始粒径的步骤中所述纳米铜颗粒的初始粒粒径小于20nm；所述将纳米铜颗粒从气相沉积装置带入收集装置中，并沉积在收集装置沉积区域的基板上的步骤中，所述保护气体通入沉积装置中的气体流速为0.5-5L/min。保护气体的流速具体值需要根据所使用的气相沉积装置及需要制备的纳米铜颗粒的粒径大小决定， 气相沉积法中保护气体的流速对制备的纳米铜颗粒粒径有很大的影响，保护气体的气流速过大会造成纳米铜颗粒的大量损失，气流流速过小会导致纳米铜颗粒的团聚，会影响后续烧结键合的质量。
具体的，所述气相沉积装置使用气相沉积法制备纳米铜颗粒的步骤中，所述气相沉积法为：真空蒸镀PVD、磁控溅射PVD、火花烧烛冲压沉积、或离子镀法等现有工艺；根据不同气相沉积法制备的纳米铜初始颗粒粒径有一定差异，可实现与不同节距的铜柱I/O输出端口的芯片互连。
具体的，所述对铜柱进行热压烧结，使芯片与基板键合的步骤中还包括如下内容：使用热、激光、电磁或超声现有工艺，通过夹具对芯片和基板加压配合现有烧结工艺手段实现短时间内将芯片与基板键合。
具体的，所述将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理的步骤中，对残余区域纳米铜颗粒进行氧化处理的方法可以为：使用氧化性的流体与纳米铜颗粒接触氧化，所述氧化性流体为热空气、氧气或双氧水；也可以为：直接将半成品半导体互连结构放置在烘箱中进行烘烤氧化处理。
更优的，所述对氧化处理后的半成品半导体互连结构进行清洗，除去残余的氧化铜颗粒的步骤中包括如下内容：根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，选用浓度为5％～10％的稀硫酸对半成品半导体互连结构的基板的沉积区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液。通过气相沉积法在基板上形成的是一层完整的纳米铜薄膜，该纳米铜膜将互连I/O处和无需互连的位置都覆盖了，省去了常规掩模版辅助的办法。清洗的目的主要是为了去除无需互连处的纳米铜颗粒。若不清洗会导致互连位置与其他位置导通，影响芯片的电性能。清洗的技术难点在于不能破坏基板与超细节距微米铜柱成型的互连位置，同时要将多余的铜纳米颗粒完全氧化除去； 采用上述技术方案则可以达到快速清洗所述半成品半导体互连结构，再经过烘干即可得到所述超细节距半导体互连结构，使得所述超细节距半导体的成型精度高，互连结构具有较好的热电力互连性能及可靠性。
一种超细节距半导体互连结构，其按照如上所述成型方法制备得到。
本发明的实施例的有益效果：
所述成型方法通过气相沉积法制备出纳米铜颗粒，调节气相沉积装置中的耦合参数，来控制生成纳米铜颗粒的大小，再将制备的纳米铜颗粒沉积在基板上，然后把带有I/O输出端口的芯片倒装在基板上，通过热压烧结实现芯片与基板的键合。所述成型方法中通过气相沉积装置制备出的纳米铜颗粒具有粒径可控，纯度高等特点，避免化学法制备中需要各种前驱体、溶剂或还原剂等有毒、污染环境的化学物质，以及有机物残留影响烧结性能和器件可靠性等问题，且所述成型方法可应用于包括半导体在内任何导电材料，灵活多高，可避免纳米铜颗粒存贮氧化等问题；能有效解决超细节距芯片与基板焊盘间定位差等问题，可满足高密度封装互连的需要。
附图说明
图1是本发明的一个实施例中所述成型方法的流程示意图。
具体实施方式
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
实施例1
如图1所示，一种超细节距半导体互连结构的成型方法，其包括如下步骤：
气相沉积装置使用气相沉积法制备纳米铜颗粒。
调节气相沉积装置的耦合参数，控制生产纳米铜颗粒的初始粒径。
将纳米铜颗粒从气相沉积装置带入收集装置中，并沉积在收集装置沉积区 域的基板上。
将带有铜柱I/O输出端口的芯片倒立放置在基板上的沉积区域，对铜柱进行热压烧结，使芯片与基板键合，得到半成品半导体互连结构。
将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理。
对氧化处理后的半成品半导体互连结构进行清洗，除去残余的氧化铜颗粒，得到超细节距半导体互连结构。
实施例2
一种超细节距半导体互连结构的成型方法,包括以下步骤：
步骤一，使用火花烧蚀装置制备纳米铜颗粒；
步骤二，设置火花烧蚀装置电极两端的电压、电流为1.2Kv、10mA，气流速度为5L/min，来控制纳米铜颗粒的初始粒径为2-5nm；
步骤三，向制备系统中通入纯度为99.999％的N 2，一方面，排除火花烧蚀制备腔室中的空气，另一方面作为介质可降低电极两端的击穿电压，同时将制备的纳米铜颗粒通过收集装置中冲压系统沉积在基板上的沉积区域，直至整个过程完成，停止通气,冲压喷头与基板间的间距为1mm，沉积纳米铜层的厚度为0.2μm；
步骤四，通过真空焊盘吸附并转移铜柱节距为5μm的芯片，将其倒装在基板上沉积了纳米铜颗粒的沉积区域内；
步骤五，选用波长355nm、频率为150KHz、功率0.16W的激光对铜柱与基板间连接区域以100-200mm/s的速度扫描加热至180℃，通过夹具对芯片进行加压至0.5MPa，配合超声实现快速键合；
步骤六，芯片键合完成后，使用热空气/氧气对整个封装结构进行氧化处理；
步骤七，根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，利用 制备、沉积的纳米铜颗粒与铜层厚度不一的特点，选用浓度为5％～10％的稀硫酸对基板上附着纳米铜的沉积区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液达到快速清洗的目的，洗完烘干得到互连样品，具有较好的热电力互连性能及可靠性。
实施例3
一种超细节距半导体互连结构的成型方法,包括以下步骤：
步骤一，使用蒸发源为电子束的真空蒸镀装置制备纳米铜颗粒；
步骤二，使用光斑直径为5um的电子束，经过10Kv的电场加速，以倾角15°轰击靶材，来控制纳米铜颗粒的初始尺寸为10-20nm；
步骤三，对制备装置抽真空处理，保证真空度≤10 -6Pa，通入纯度为99.999％的N 2，使气态纳米粒子以基本无碰撞的直线运动定向传送至基片，直至整个制备过程结束，停止通气；控制蒸发源与基板间的距离为20cm，沉积纳米铜层的厚度为0.5μm；
步骤四，通过电磁控制吸引并转移铜柱节距为20μm芯片，将其倒装在基板上沉积了纳米铜颗粒的沉积区域内；
步骤五，选用交变电场产生的电磁波辐射产生的热量加热基板至120℃，电磁波波长为10 3MHz,同时在芯片垂直方向上通入220V、50Hz的交变电流辅助烧结，用夹具对芯片加压至1MPa；
步骤六，芯片键合完成后，使用浓度为5％～8％的双氧水对封装结构局部区域中残留纳米铜进行氧化处理；
步骤七，根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，利用制备、沉积的纳米铜颗粒与铜层厚度不一的特点，选用浓度为5％～10％的稀硫酸对基板上附着纳米铜的区域进行清洗去除残余的氧化铜，然后使用无水乙醇清 洗多余的稀硫酸溶液达到快速清洗的目的，洗完烘干得到互连样品，具有较好的热电力互连性能及可靠性。
实施例4
一种超细节距半导体互连结构及其成型方法,包括以下步骤：
步骤一，使用磁控溅射法制备纳米铜颗粒；
步骤二，将制备系统抽真空处理，铜靶作为阴极靶，基板作为阳极，向真空腔室中通入0.1-10Pa的氩气，使其在电子碰撞下发生电离产生Ar +，在阴极靶1-3kV直流负高压或13.56MHz的射频电压作用下以高能量轰击靶材产生辉光放电，控制纳米铜颗粒的初始尺寸为5-10nm，直至沉积铜层厚度满足要求，停止通气；
步骤三，将电离后蒸发的纳米铜颗粒在10Kv电场下加速，使其定向沉积在基板上，沉积纳米铜层的厚度为0.2um；
步骤四，通过机械手臂精确抓取并转移铜柱节距为10μm芯片，将其倒装在基板上沉积了纳米铜颗粒的沉积区域内；
步骤五，使用超声热压炉加热基板至180℃，通过超声加压探头对芯片与基板加压为0.25MPa，超声功率为210W，保温烧结20min；
步骤六，将键合后的互连结构放入烘箱中，设定温度为60℃，使互连结构中残留纳米铜氧化；
步骤七，根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，利用制备、沉积的纳米铜颗粒与铜层厚度不一的特点，选用浓度为5％～10％的稀硫酸对基板上附着纳米铜的区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液达到快速清洗的目的，洗完烘干得到互连样品，具有较好的热电力互连性能及可靠性。
实施例5
一种超细节距半导体互连结构及其成型方法,包括以下步骤：
步骤一，使用高能激光作为热源来制备蒸镀薄膜；
步骤二，对制备系统抽取真空，通入纯度为99.999％的N 2，防止产生的纳米铜颗粒氧化，使用波长为308nm，脉宽为20ns，脉冲频率为20Hz，功率为650mJ的脉冲激光器对铜靶材进行热处理使其蒸发产生高温高压等离子体，控制纳米铜颗粒初始尺寸为10-20nm；
步骤三，激光继续处理电离后蒸发的等离子体，使其在2Kv外加电场作用下定向加速并以30°的倾角发射沉积到基底上形成薄膜,沉积薄膜的厚度为1um；
步骤四，通过真空焊盘吸附并转移铜柱间距为30μm的芯片，将其倒装在基板上沉积了纳米铜颗粒的区域内；
步骤五，选用波长355nm、频率为200KHz、功率2.5W的激光对铜柱与基板间连接区域以50-100mm/s的速度扫描加热至260℃，通过夹具对芯片进行加压至1MPa，配合超声实现快速键合；
步骤六，芯片键合完成后，使用热空气/氧气对整个封装结构进行氧化处理；
步骤七，根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，利用制备、沉积的纳米铜颗粒与铜层厚度不一的特点，选用浓度为5％～10％的稀硫酸对基板上附着纳米铜的区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液达到快速清洗的目的，洗完烘干得到互连样品，具有较好的热电力互连性能及可靠性。
实施例6
一种超细节距半导体互连结构及其成型方法,包括以下步骤：
步骤一，使用多弧离子镀法来制备纳米铜薄膜；
步骤二，将制备系统的真空室抽至4×10 -3Pa以上的真空度，铜靶作为阳极，硅基板作为阴极，向真空腔室中通入0.1-1Pa的纯度为99.999％的Ar气，在阳、阴极间施加1-5kV的负电压，使两电极在氩气作为介质下间发生弧光放电，在放电电场作用下，电离的Ar +受阴极负压吸引轰击硅片表面，除去基板表面污物，基板表面达到清洁标准后停止通入气体；
步骤三，接通蒸发源交流电源，使铜靶材气化蒸发后与Ar原子及离子间发生碰撞，控制纳米铜颗粒初始尺寸为10-20nm，同时在负高压电场作用下淀积到硅基板表面成膜，使纳米铜膜的厚度为0.5μm；
步骤四，通过机械手臂精确抓取并转移铜柱间距为15μm的芯片，将其倒装在基板上沉积了纳米铜颗粒的区域内；
步骤五，使用超声热压炉加热基板至180℃，通过超声加压探头对芯片与基板加压为0.25MPa，超声功率为210W，保温烧结20min；
步骤六，将键合后的互连结构放入烘箱中，设定温度为80℃，使互连结构中残留纳米铜氧化；
步骤七，根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，利用制备、沉积的纳米铜颗粒与铜层厚度不一的特点，选用浓度为5％～10％的稀硫酸对基板上附着纳米铜的区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液达到快速清洗的目的，洗完烘干得到互连样品，具有较好的热电力互连性能及可靠性。
一种超细半导体互连结构，可以根据上述实施例1-6中任意个制备得到。
通过上述实施例本申请提出一种超细半导体互连结构及其成型方法，所述成型方法通过气相沉积法制备出纳米铜颗粒，调节气相沉积装置中的耦合参数， 来控制生成纳米铜颗粒的大小，再将制备的纳米铜颗粒沉积在基板上，然后把带有I/O输出端口的芯片倒装在基板上，通过热压烧结实现芯片与基板的键合。所述成型方法中通过气相沉积装置制备出的纳米铜颗粒具有粒径可控，纯度高等特点，避免化学法制备中需要各种前驱体、溶剂或还原剂等有毒、污染环境的化学物质，以及有机物残留影响烧结性能和器件可靠性等问题，且所述成型方法可应用于包括半导体在内任何导电材料，灵活多高，可避免纳米铜颗粒存贮氧化等问题；能有效解决超细节距芯片与基板焊盘间定位差等问题，可满足高密度封装互连的需要。
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明的保护范围之内。

Claims (10)

  1. 一种超细节距半导体互连结构的成型方法，其特征在于，包括如下步骤：
    气相沉积装置使用气相沉积法制备纳米铜颗粒；
    调节气相沉积装置的耦合参数，控制生产纳米铜颗粒的初始粒径；
    将纳米铜颗粒从气相沉积装置带入收集装置中，并沉积在收集装置沉积区域的基板上；
    将带有铜柱I/O输出端口的芯片倒立放置在基板上的沉积区域，对铜柱进行热压烧结，使芯片与基板键合，得到半成品半导体互连结构；
    将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理；
    对氧化处理后的半成品半导体互连结构进行清洗，除去残余的氧化铜颗粒，得到超细节距半导体互连结构。
  2. 根据权利要求1所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述将纳米铜颗粒从气相沉积装置带入收集装置中的步骤还包括如下内容：
    通入保护气体和外加电场的环境下，将纳米铜颗粒从沉积装置带入收集装置中。
  3. 根据权利要求2所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述保护气体为氮气、氩气或氦气，且保护气体中掺杂有含量不超过5％的还原性气体，所述还原性气体为氢气、甲醛或一氧化碳。
  4. 根据权利要求3所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述调节气相沉积装置的耦合参数，控制生产纳米铜颗粒的初始粒径的步骤中还包括如下内容：
    所述纳米铜颗粒的初始粒粒径小于20nm；
    所述将纳米铜颗粒从气相沉积装置带入收集装置中，并沉积在收集装置沉 积区域的基板上的步骤中还包括如下内容：
    所述保护气体通入沉积装置中的气体流速为0.5-5L/min。
  5. 根据权利要求1所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述气相沉积装置使用气相沉积法制备纳米铜颗粒的步骤中还包括如下内容：
    所述气相沉积法为：真空蒸镀PVD、磁控溅射PVD、火花烧烛冲压沉积、或离子镀法。
  6. 根据权利要求1所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述对铜柱进行热压烧结，使芯片与基板键合的步骤中还包括如下内容：使用热、激光、电磁或超声，通过夹具对芯片和基板加压配合烧结工艺手段实现短时间内将芯片与基板键合。
  7. 根据权利要求1所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理的步骤中包括如下内容：
    对残余区域纳米铜颗粒进行氧化处理的方法为：使用氧化性的流体与纳米铜颗粒接触氧化，所述氧化性流体为热空气、氧气或双氧水。
  8. 根据权利要求1所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述将半成品半导体互连结构中残余区域的纳米铜颗粒进行氧化处理的步骤中包括如下内容：
    对残余区域纳米铜颗粒进行氧化处理的方法为：直接将半成品半导体互连结构放置在烘箱中进行烘烤氧化处理。
  9. 根据权利要求7所述的一种超细节距半导体互连结构的成型方法，其特征在于，所述对氧化处理后的半成品半导体互连结构进行清洗，除去残余的氧 化铜颗粒的步骤中包括如下内容：根据制备和沉积的纳米铜颗粒粒径及烧结形成铜层的厚度，选用浓度为5％～10％的稀硫酸对半成品半导体互连结构的基板的沉积区域进行清洗去除残余的氧化铜，然后使用无水乙醇清洗多余的稀硫酸溶液。
  10. 一种超细节距半导体互连结构，其特征在于，按照如权利要求1-9中所述成型方法制备得到。
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