WO2021136222A1 - 一种硅片背面金属化结构及其制造工艺 - Google Patents

一种硅片背面金属化结构及其制造工艺 Download PDF

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WO2021136222A1
WO2021136222A1 PCT/CN2020/140529 CN2020140529W WO2021136222A1 WO 2021136222 A1 WO2021136222 A1 WO 2021136222A1 CN 2020140529 W CN2020140529 W CN 2020140529W WO 2021136222 A1 WO2021136222 A1 WO 2021136222A1
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metal layer
silicon wafer
gold
thickness
hafnium
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PCT/CN2020/140529
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French (fr)
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高瑞峰
周骏贵
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南京市产品质量监督检验院
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Publication of WO2021136222A1 publication Critical patent/WO2021136222A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]

Definitions

  • the invention belongs to the technical field of semiconductor devices and integrated circuit technology, and in particular relates to the back metallization structure and technology of silicon devices.
  • the back metallization system is an important part of the transistor. It has two main functions, one is a larger current path, and the other is a path for transferring and dissipating the large amount of heat generated by the collector of the transistor. Therefore, the back metallization system has a great influence on the performance and reliability of the transistor.
  • a good back metallization system requires low ohmic contact resistance, low contact thermal resistance and good reliability.
  • it is usually required to select: 1) a metal material with a lower Schottky barrier height; 2) a substrate material with a high doping concentration; 3) a substrate with a high recombination center.
  • the back metallization layer of the transistor In order to make the back metallization layer of the transistor have good thermal conductivity and reliability, it is necessary to minimize the thermal stress between the silicon chip and the back metallization layer.
  • the device When the transistor is in an intermittent working state, the device undergoes periodic high and low temperature processes, forming a thermal cycle. Due to the different linear expansion coefficients among the silicon chip, solder, and the materials of the base layers inside the transistor, thermal stress is generated inside the system during the thermal cycle, and the thermal resistance increases, causing the transistor to locally overheat and fail.
  • the silicon chip with a thickness of about 200 ⁇ m is a very thin and brittle material. During ion implantation, the chip has greater stress and is prone to fragmentation. When the linear expansion coefficients of the materials of each layer are not well matched, they will experience multiple heat during use. It may warp, crack and fail after cycling.
  • the structure of the back metallization system currently used in actual devices generally consists of three parts: an ohmic contact layer, a diffusion barrier layer and a conductive layer.
  • the ohmic contact layer is also called the adhesion layer.
  • the metal used in the adhesion layer is generally titanium or vanadium or chromium or gold or gold-arsenic alloy.
  • the metal used in the barrier layer is generally nickel or gold, or copper-tin alloy, or gold-germanium alloy, or gold-germanium-antimony alloy.
  • the metal used for the conductive layer is generally gold or silver.
  • the present invention aims to solve the shortcomings of the prior art, provide a low contact resistance silicon wafer back metallization structure and its manufacturing process, have the advantages of high electrical conductivity, high thermal conductivity, thermal expansion coefficient and good matching with the medium, and improve the product Yield.
  • the technical solution adopted by the present invention is that the structure has at least a first metal layer of hafnium deposited on the surface of the backside substrate silicon wafer in sequence from the nearer to the farthest from the silicon wafer.
  • a second metal layer can be deposited, and the material of the second metal layer is any one of gold, nickel, or gold-germanium alloy.
  • a third metal layer can be deposited, and the material of the third metal layer is any one of silver, gold, gold-germanium alloy, and gold-tin alloy.
  • the thickness of the first metal layer is 30 nm to 300 nm.
  • the thickness of gold used as the second metal layer is 500 nm to 2000 nm
  • the thickness of nickel used as the second metal layer is 100 nm to 600 nm
  • the thickness of gold germanium alloy used as the second metal layer is 100 nm to 500 nm.
  • the thickness of silver used as the third metal layer is 100nm-2000nm
  • the thickness of gold used as the third metal layer is 100nm-1500nm
  • the thickness of gold-germanium alloy or gold-tin alloy used as the third metal layer is 300nm-1500nm .
  • a processing technology for the metallization structure on the back of a silicon wafer which includes the following steps: front protection, back thinning, back polishing, cleaning, magnetron sputtering or electron beam evaporation to prepare the first metal layer, evaporation or sputtering to prepare other metals Floor.
  • the front surface protection is to paste a protective film on the front surface of the silicon wafer.
  • the back side thinning is to thin the back side of the silicon wafer to a desired thickness.
  • the back polishing is to remove the damaged layer produced by the grinding plate.
  • the cleaning is to clean the polished silicon wafer.
  • the first metal layer is prepared by magnetron sputtering or electron beam evaporation, wherein the rate of magnetron sputtering is 5nm/s-15nm/s, and the rate of electron beam evaporation is 0.5nm/s-3nm/s.
  • the second metal layer and the third metal layer are prepared by evaporation or magnetron sputtering, the evaporation rate is 0.5nm/s-3nm/s, and the magnetron sputtering rate is 5nm/s-15nm/s.
  • the electron beam evaporation method is a kind of vacuum evaporation coating, which is a method of directly heating the evaporation material under vacuum conditions by using an electron beam to vaporize the evaporation material and transport it to the substrate, and condense on the substrate to form a thin film.
  • the material to be heated is placed in a water-cooled crucible, which can prevent the evaporation material from reacting with the crucible wall to affect the quality of the film.
  • Electron beam evaporation can evaporate high melting point materials. Compared with general resistance heating evaporation, it has higher thermal efficiency, higher beam current density, and faster evaporation speed; the produced film has the advantages of high purity, good quality, and accurate control of thickness.
  • the magnetron sputtering is a type of physical vapor deposition, and has the advantages of simple equipment, easy control, large coating area and strong adhesion.
  • the technology includes the target, power supply and working mode of the target, and the target is the key among them.
  • the target is connected to a negative potential of 400V ⁇ 600V, the substrate is grounded, and the two constitute a discharge field with the target as the cathode and the substrate as the anode.
  • the cathode target is equipped with a magnetic circuit module, which can be a permanent magnet or an electromagnet, which provides a magnetic flux density of 0.03T ⁇ 0.06T to the target surface.
  • the magnetic field lines are parallel to the target surface and orthogonal to the electric field.
  • the space enclosed by the magnetic field lines and the target surface is the plasma region that produces a binding effect on electrons.
  • the positive Ar ions generated by glow discharge bombard the surface of the target continuously, causing the target atoms to be sputtered out and deposited on the substrate opposite to the target to form a sputtering film.
  • the material of the first metal layer of the present invention is hafnium. Compared with the existing titanium or gold or gold arsenic, the hafnium and the silicon substrate form a better ohmic contact, with lower contact resistance and better adhesion. It also has good electrical conductivity, thermal conductivity and a suitable coefficient of thermal expansion, which effectively improves the yield and reliability of silicon devices during the manufacturing process.
  • the hafnium layer is applied to an n-type silicon substrate, the ohmic contact can be realized without increasing the surface doping concentration of the substrate.
  • the design of the second metal layer and the third metal layer of the present invention effectively increases the stability of the silicon device, can be applied to eutectic welding occasions, and has a wide range of applications.
  • the processing technology of the present invention ensures the realization of the above-mentioned back metallization structure.
  • FIG. 1 is a schematic diagram of the metallization structure on the back of a silicon wafer of the present invention. Among them: 101 silicon wafer; 102 hafnium, the first metal layer of the structure; 103 gold, the second metal layer of the structure.
  • Fig. 2 is a schematic diagram of the metallization structure on the back of the silicon wafer of the present invention. Among them: 201 silicon wafer; 202 hafnium, the first metal layer of the structure; 203 nickel, the second metal layer of the structure; 204 silver or gold, the third metal layer of the structure.
  • FIG. 3 is a schematic diagram of the metallization structure on the back of the silicon wafer of the present invention. Among them: 301 silicon wafer; 302 hafnium, which is the first metal layer of the structure; 303 gold germanium alloy, is the second metal layer of the structure; 304 silver or gold, is the third metal layer of the structure.
  • Fig. 4 is a schematic diagram of the metallization structure on the back of the silicon wafer of the present invention. Among them: 401 silicon wafer; 402 hafnium is the first metal layer of the structure; 403 nickel is the second metal layer of the structure; 404 gold-germanium alloy or gold-tin alloy is the third metal layer of the structure.
  • Fig. 5 is a schematic diagram of the metallization structure on the back of the silicon wafer of the present invention. Among them: 501 silicon wafer; 502 hafnium, the first metal layer of the structure; 503 nickel, the second metal layer of the structure; and 504 gold, the third metal layer of the structure.
  • the metallization structure on the back of the silicon wafer is shown in Figure 1.
  • the first metal layer 102 is hafnium with a thickness of 300 nm
  • the second metal layer 103 is gold with a thickness of 2000 nm.
  • the processing steps are: front protection, back thinning, back polishing, cleaning, magnetron sputtering at a rate of 5 nm/s to prepare a hafnium layer, and evaporation at a rate of 3 nm/s to prepare a gold layer.
  • Example 2 The metallization structure on the back of the silicon wafer is shown in Figure 2.
  • the first metal layer 202 is hafnium with a thickness of 30 nm
  • the second metal layer 203 is nickel with a thickness of 600 nm
  • the third metal layer 204 is silver or gold with a thickness of 2000 nm.
  • the processing steps are: front protection, back thinning, back polishing, cleaning, electron beam evaporation at a rate of 0.5 nm/s to prepare a hafnium layer, and magnetron sputtering at a rate of 15 nm/s to prepare a nickel layer.
  • the gold layer was prepared by magnetron sputtering at a rate of nm/s or the silver layer was prepared by magnetron sputtering at a rate of 15 nm/s.
  • Example 3 The metallization structure on the back of the silicon wafer is shown in Figure 3.
  • the first metal layer 302 is hafnium with a thickness of 200 nm
  • the second metal layer 303 is a gold-germanium alloy with a thickness of 500 nm
  • the third metal layer 304 is silver or gold with a thickness of 100 nm.
  • the processing steps are: front protection, back thinning, back polishing, cleaning, magnetron sputtering at a rate of 15 nm/s to prepare a hafnium layer, and evaporation at a rate of 0.5 nm/s to prepare a gold-germanium layer at 0.5 nm Evaporate at a rate of 3 nm/s to prepare a gold layer or at a rate of 3 nm/s to prepare a silver layer.
  • Example 4 The metallization structure on the back of the silicon wafer is shown in Figure 4.
  • the first metal layer 402 is hafnium with a thickness of 100 nm
  • the second metal layer 403 is nickel with a thickness of 100 nm
  • the third metal layer 404 is a gold-germanium alloy or a gold-tin alloy with a thickness of 1500 nm.
  • the processing steps are: front protection, back thinning, back polishing, cleaning, electron beam evaporation at a rate of 3 nm/s to prepare a hafnium layer, and magnetron sputtering at a rate of 8 nm/s to prepare a nickel layer.
  • a gold-germanium alloy layer or a gold-tin alloy layer is prepared by magnetron sputtering at a rate of nm/s.
  • Example 5 The metallization structure on the back of the silicon wafer is shown in Figure 5.
  • the first metal layer 502 is hafnium with a thickness of 120 nm
  • the second metal layer 503 is nickel with a thickness of 150 nm
  • the third metal layer 504 is gold with a thickness of 1500 nm.
  • the processing steps are: front protection, back thinning, back polishing, cleaning, magnetron sputtering at a rate of 8 nm/s to prepare a hafnium layer, and magnetron sputtering at a rate of 5 nm/s to prepare a nickel layer.
  • the gold layer was prepared by magnetron sputtering at a rate of 5 nm/s.

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Abstract

本发明属于半导体器件和集成电路工艺技术领域，具体涉及硅器件背面金属化结构和工艺。所述结构在背面衬底硅片的表面至少沉积有第一金属层铪，然后沉积其他层。所述工艺包括正面保护、背面减薄、背面抛光、清洗、物理气相沉积等工艺步骤。本发明利用铪与硅形成欧姆接触的特点，在硅片的背面制备一层铪，具有更低的接触电阻和更好的粘附性，同时具有良好的导电性、导热性和合适的热膨胀系数，有效提高硅器件制造过程中的良率和使用中的可靠性。

Description

一种硅片背面金属化结构及其制造工艺 技术领域
本发明属于半导体器件和集成电路工艺技术领域，尤其涉及硅器件背面金属化结构和工艺。
 背景技术
随着大规模和超大规模集成电路的发展，芯片的特征尺寸越来越小，集成度越来越高，电子系统和整机不断朝着小型化、高性能、高密度、高可靠性发展，这对其中的芯片互连材料、元件焊接材料、封装材料提出更高的要求。
背面金属化系统是晶体管的一个重要组成部分。它有两个主要功能，其一是较大的电流通路，其二是对晶体管集电极所产生的大量热量进行传递散热的通路。因此背面金属化系统对晶体管的性能和可靠性有很大的影响。
一个良好的背面金属化系统要求具有欧姆接触电阻小，接触热阻低和可靠性好。为了与硅衬底形成良好的欧姆接触，通常要求选用：1)肖特基势垒高度较低的金属材料；2)高掺杂浓度的衬底材料；3)高复合中心的衬底。
为了使晶体管背面金属化层具有良好的导热性能和可靠性，要尽量减少硅芯片和背面金属化层间的热应力。当晶体管处于间歇工作状态时，器件经历周期性的高温和低温过程，形成了热循环。由于晶体管内部的硅芯片、焊料以及底座各层材料间的线膨胀系数不同，在热循环中，系统内部产生了热应力，热阻增大，使得晶体管局部过热而失效。而且，厚度在200μm左右的硅芯片是很薄的脆性材料，在离子注入时芯片有较大应力、易出现碎片，当各层材料的线膨胀系数匹配不佳时，在使用时经历多次热循环后可能翘曲、开裂而失效。
 技术问题
目前用于实际器件的背面金属化系统，其结构一般由三个部分组成：欧姆接触层、扩散阻挡层和导电层。欧姆接触层，又称粘附层。粘附层采用的金属一般是钛或钒或铬或金或金砷合金。阻挡层采用的金属一般是镍或金、或铜锡合金、或金锗合金、或金锗锑合金。导电层采用的金属一般是金或银。现有的结构和工艺还达不到低成本、高稳定性、高可靠性及与后续封装工艺配合良好的综合要求，还存在与后续封装工艺配合不佳、存在翘曲或碎片、良率较低等问题。
 技术解决方案
本发明旨在解决现有技术的不足，提供一种低接触电阻的硅片背面金属化结构及其制造工艺，具有高导电性、高导热性、热膨胀系数与介质匹配较好的优点，提高产品良率。
为实现上述目的，本发明所采用的技术方案是：所述结构在背面衬底硅片的表面按距离硅片由近及远顺序依次至少沉积有第一金属层铪。优选的，可沉积第二金属层，第二金属层的材质是金、镍或金锗合金中的任一种。优选的，可沉积第三金属层，第三金属层的材质是银、金、金锗合金、金锡合金中的任一种。
优选的，所述第一金属层的厚度为30nm～300nm。
优选的，金用作第二金属层的厚度为500nm～2000nm，镍用作第二金属层的厚度为100nm～600nm，金锗合金用作第二金属层的厚度为100nm～500nm。
优选的，银用作第三金属层的厚度为100nm～2000nm，金用作第三金属层的厚度为100nm～1500nm，金锗合金或金锡合金用作第三金属层的厚度为300nm～1500nm。
一种硅片背面金属化结构的加工工艺，它包括以下步骤：正面保护，背面减薄，背面抛光，清洗，磁控溅射或电子束蒸发制备第一金属层，蒸发或溅射制备其他金属层。所述正面保护，是在硅片的正面贴上一层保护膜。所述背面减薄，是将硅片背面减薄至所需厚度。所述背面抛光，是将磨片产生的损伤层去除。所述清洗，是将抛光后的硅片清洗干净。第一金属层采用磁控溅射或电子束蒸发制备，其中磁控溅射的速率为5nm/s～15nm/s，电子束蒸发的速率为0.5nm/s～3nm/s。第二金属层、第三金属层采用蒸发或磁控溅射制备，蒸发的速率为0.5nm/s～3nm/s，磁控溅射的速率为5nm/s～15nm/s。
所述电子束蒸发法是真空蒸发镀膜的一种，是在真空条件下利用电子束进行直接加热蒸发材料，使蒸发材料气化并向基板输运，在基底上凝结形成薄膜的方法。在电子束加热装置中，被加热的物质放置于水冷的坩埚中，可避免蒸发材料与坩埚壁发生反应从而影响薄膜的质量。电子束蒸发可以蒸发高熔点材料，比一般电阻加热蒸发的热效率高、束流密度大、蒸发速度快；所制成的薄膜具有纯度高、质量好、厚度可被准确控制的优点。
所述磁控溅射是物理气相沉积的一种，具有设备简单、易于控制、镀膜面积大和附着力强等优点。该技术包括靶、电源和靶的工作模式等部分，靶是其中的关键。通常，靶接入400V~600V 的负电位，基片接地，两者构成以靶为阴极、基片为阳极的放电场。阴极靶内装有磁路模块，可以是永磁体或电磁铁，给靶面提供0.03T~0.06T 的磁通密度。磁力线平行于靶表面并与电场正交，被磁力线与靶表面所封闭的空间就是对电子产生束缚效应的等离子区。以通入氩气为例，辉光放电产生的Ar 正离子被加速后，不断地轰击靶材表面，使靶材原子溅射出来沉积到位于靶对面的基片上，形成溅射膜层。
 有益效果
本发明的第一金属层的材质是铪，相较于现有的钛或金或金砷，铪与硅衬底之间形成更好的欧姆接触，具有更低的接触电阻和更好的粘附性，同时具有良好的导电性、导热性和合适的热膨胀系数，有效提高硅器件制造过程中的良率和使用中的可靠性。铪层在应用于n型硅衬底时不需提高衬底的表面掺杂浓度即可实现欧姆接触。同时，本发明的第二金属层和第三金属层的设计有效增加了硅器件的稳定性，可适用于共晶焊场合，适用面广。本发明的加工工艺保证了上述背面金属化结构的实现。
 附图说明
图1为本发明的硅片背面金属化结构的示意图。其中：101硅片；102铪，是该结构的第一金属层；103金，是该结构的第二金属层。
图2为本发明的硅片背面金属化结构的示意图。其中：201硅片；202铪，是该结构的第一金属层；203镍，是该结构的第二金属层；204银或金，是该结构的第三金属层。
图3为本发明的硅片背面金属化结构的示意图。其中：301硅片；302铪，是该结构的第一金属层；303金锗合金，是该结构的第二金属层；304银或金，是该结构的第三金属层。
图4为本发明的硅片背面金属化结构的示意图。其中：401硅片；402铪，是该结构的第一金属层；403镍，是该结构的第二金属层；404金锗合金或金锡合金，是该结构的第三金属层。
图5为本发明的硅片背面金属化结构的示意图。其中：501硅片；502铪，是该结构的第一金属层；503镍，是该结构的第二金属层；504金，是该结构的第三金属层。
 本发明的最佳实施方式
硅片背面金属化结构如图1所示。第一金属层102是厚度为300nm的铪，第二金属层103是厚度为2000nm的金。加工工艺步骤为：正面保护，背面减薄，背面抛光，清洗，以5 nm/s的速率进行磁控溅射制备铪层，以3 nm/s的速率进行蒸发制备金层。
 本发明的实施方式
实施例2。硅片背面金属化结构如图2所示。第一金属层202是厚度为30nm的铪，第二金属层203是厚度为600nm的镍，第三金属层204是厚度为2000nm的银或金。加工工艺步骤为：正面保护，背面减薄，背面抛光，清洗，以0.5 nm/s的速率进行电子束蒸发制备铪层，以15 nm/s的速率进行磁控溅射制备镍层，以10 nm/s的速率进行磁控溅射制备金层或以15 nm/s的速率进行磁控溅射制备银层。
 实施例3。硅片背面金属化结构如图3所示。第一金属层302是厚度为200nm的铪，第二金属层303是厚度为500nm的金锗合金，第三金属层304是厚度为100nm的银或金。加工工艺步骤为：正面保护，背面减薄，背面抛光，清洗，以15 nm/s的速率进行磁控溅射制备铪层，以0.5 nm/s的速率进行蒸发制备金锗层，以0.5 nm/s的速率进行蒸发制备金层或以3 nm/s的速率进行蒸发制备银层。
实施例4。硅片背面金属化结构如图4所示。第一金属层402是厚度为100nm的铪，第二金属层403是厚度为100nm的镍，第三金属层404是厚度为1500nm的金锗合金或金锡合金。加工工艺步骤为：正面保护，背面减薄，背面抛光，清洗，以3 nm/s的速率进行电子束蒸发制备铪层，以8 nm/s的速率进行磁控溅射制备镍层，以15 nm/s的速率进行磁控溅射制备金锗合金层或金锡合金层。
实施例5。硅片背面金属化结构如图5所示。第一金属层502是厚度为120nm的铪，第二金属层503是厚度为150nm的镍，第三金属层504是厚度为1500nm的金。加工工艺步骤为：正面保护，背面减薄，背面抛光，清洗，以8 nm/s的速率进行磁控溅射制备铪层，以5 nm/s的速率进行磁控溅射制备镍层，以5 nm/s的速率进行磁控溅射制备金层。

Claims (8)

  1. 一种硅片背面金属化结构，其特征在于：所述结构在背面衬底硅片的表面按距离硅片由近及远顺序依次至少沉积有第一金属层，第一金属层的材质是铪。
  2. 按照权利要求1所述的一种硅片背面金属化结构，其特征在于：所述结构在背面衬底硅片的表面按距离硅片由近及远顺序依次沉积有第一金属层、第二金属层，第二金属层的材质是金、镍或金锗合金中的任一种。
  3. 按照权利要求1所述的一种硅片背面金属化结构，其特征在于：所述结构在背面衬底硅片的表面按距离硅片由近及远顺序依次沉积有第一金属层、第二金属层、第三金属层，第三金属层的材质是银、金、金锗合金、金锡合金中的任一种。
  4. 按照权利要求1所述的一种硅片背面金属化结构，其特征在于：第一金属层的厚度为30nm～300nm。
  5. 按照权利要求2所述的一种硅片背面金属化结构，其特征在于：金用作第二金属层的厚度为500nm～2000nm，镍用作第二金属层的厚度为100nm～600nm，金锗合金用作第二金属层的厚度为100nm～500nm。
  6. 按照权利要求3所述的一种硅片背面金属化结构，其特征在于：银用作第三金属层的厚度为100nm～2000nm，金用作第三金属层的厚度为100nm～1500nm，金锗合金或金锡合金用作第三金属层的厚度为300nm～1500nm。
  7. 一种制备如权利要求1所述的硅片背面金属化结构的工艺，其特征在于：第一金属层采用磁控溅射或电子束蒸发制备，其中磁控溅射的速率为5nm/s～15nm/s，电子束蒸发的速率为0.5nm/s～3nm/s。
  8. 一种制备如权利要求2或3所述的硅片背面金属化结构的工艺，其特征在于：第二金属层、第三金属层采用蒸发或磁控溅射制备，蒸发的速率为0.5nm/s～3nm/s，磁控溅射的速率为5nm/s～15nm/s。
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