WO2022262017A1 - 一种基于忆阻器的完备非易失布尔逻辑电路及操作方法 - Google Patents

一种基于忆阻器的完备非易失布尔逻辑电路及操作方法 Download PDF

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WO2022262017A1
WO2022262017A1 PCT/CN2021/104578 CN2021104578W WO2022262017A1 WO 2022262017 A1 WO2022262017 A1 WO 2022262017A1 CN 2021104578 W CN2021104578 W CN 2021104578W WO 2022262017 A1 WO2022262017 A1 WO 2022262017A1
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value
voltage
logic
memristor
type
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French (fr)
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王兴晟
吴绮雯
宋玉洁
王成旭
缪向水
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Definitions

  • the invention belongs to the technical field of microelectronic devices, and more specifically relates to a complete non-volatile Boolean logic circuit and an operation method based on a memristor.
  • Modern computers are largely based on the von Neumann architecture.
  • data is fetched from a memory unit, transferred to a processing unit, and after calculations are completed, the data is transferred to the memory unit to be stored.
  • the operating speed of the processor and the memory has reached a very high level, but there is still a big gap in the transmission speed of the bus connecting these two parts.
  • Frequent data transmission consumes most of the time and power consumption in the data processing process. .
  • This rate mismatch which limits the development of modern computers, is known as the memory wall.
  • In-memory computing is a very promising solution. Similar to the human brain, storage and computing coexist in memory computing, which has the advantages of high computing parallelism, low latency, and low power consumption.
  • memristor As a new type of memory device, memristor has become a strong candidate for in-memory computing architecture due to its natural non-volatility that can maintain the resistance state after power off.
  • Memristor-based logic implementations are mainly divided into three categories. In the first category, the input and output are expressed in the form of resistance states of memristors. This type of scheme is conducive to logic cascading but uses a large number of devices. , and the number of devices used and the complexity of operation are increasing with the increase of logic calculation complexity; in the second type of implementation method, the input is applied to both ends of the memristor in the form of voltage, and the output is expressed in the form of resistance.
  • the number of devices used in the scheme is greatly reduced, and the number of operation steps is also less, but the logic cascade must introduce the process of digital-to-analog conversion, which reduces the calculation efficiency;
  • the input is the voltage applied to one end of the memristor and the initial resistance value of the memristor, and the output is expressed in the form of the resistance state of the memristor.
  • This method uses fewer devices, fewer operation steps, and easy logic cascading.
  • this type of logic calculation is a destructive calculation, which is not conducive to Protect the integrity of entered information. Therefore, it is necessary to propose a logic-complete implementation scheme, which can easily implement logic cascading without destroying the integrity of input data while using as few devices and operation steps as possible.
  • the present invention provides a complete non-volatile Boolean logic circuit and operation method based on memristors, which are used to solve the problem that the prior art cannot operate in a small number of devices and operation steps.
  • the present invention provides a complete non-volatile Boolean logic circuit based on a memristor, which is used to perform logical operations on the input logic value P and/or the input logic value Q;
  • the above logic circuit includes: a controller, a memristor M 1 , a memristor M 2 and a resistor;
  • the controller is respectively connected to the positive pole of the memristor M1, the positive pole of the memristor M2 and one end of the resistor ; the negative poles of the memristor M1 and the memristor M2 are connected to the same word line; the other end of the resistor connected to the word line ; the memristor M1 and the memristor M2 are the same;
  • the controller is used to set the memristor M2 to a high-impedance state before performing logic operations; when performing logic operations, apply voltage A to memristor M1, apply voltage B to memristor M2 , and apply voltage C, and read the resistance state of the memristor M2 , which is the result of the logic operation;
  • the controller when the above logic circuit performs an operation related to the logic value Q, the controller is also used to set the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation ;
  • the operation includes the operation of logical operation on logical value P and logical value Q and the operation of logical operation on logical value Q only;
  • the value of voltage A and voltage C is determined by the logic value P and the type of logic operation; the value of voltage B is V p ; V p satisfies V set /2 ⁇ V p ⁇ V set and V p ⁇ 2
  • both the above-mentioned memristor M1 and memristor M2 include a high-resistance state and a low-resistance state; the high-resistance state corresponds to a logic value "0", and the low-resistance state corresponds to a logic value "1".
  • the resistance value of the resistor is between the resistance value of the high resistance state of the memristor M1 or the resistance state of the memristor M2 and the resistance value of the low resistance state; the resistance value of the resistance is Where R H is the resistance value of the high resistance state of the memristor M1 or the memristor M2 , and R L is the resistance value of the low resistance state of the memristor M1 or the memristor M2 .
  • the controller includes a control terminal T1, a control terminal T2 and a control terminal T3 ; the control terminal T1 is connected to the positive pole of the memristor M1, and the control terminal T2 is connected to the positive pole of the memristor M2 , The control terminal T3 is connected to one end of the resistor;
  • the controller When the controller performs logic operations, it applies a voltage A to the memristor M1 through the control terminal T1, applies a voltage B to the memristor M2 through the control terminal T2 , and applies a voltage C to the resistor through the control terminal T3. Taking the resistance state of the memristor M2 is the result of the logic operation.
  • logic operations include: true logic operations, false logic operations, P logic operations, Q logic operations, non-P logic operations, non-Q logic operations, AND logic operations, AND NOT logic operations, or logic operations, or Non-logical operations, substantial implication logical operations, anti-substantial implication logical operations, negative substantial implication logical operations, negative negative substantial implication logical operations, exclusive-or logical operations, and exclusive-or logical operations.
  • the value of voltage A is -V p
  • the value of voltage C is -V p ;
  • V takes a value of 0; when the logical value P is 1, V takes a value of V p .
  • an operation method based on the above-mentioned complete non-volatile Boolean logic circuit includes the following steps:
  • the value of voltage A and voltage C is determined by the logic value P and the type of logic operation; the value of voltage B is V p ; V p satisfies V set /2 ⁇ V p ⁇ V set and V p ⁇ 2
  • the value of voltage A is -V p
  • the value of voltage C is -V p ;
  • V takes a value of 0; when the logical value P is 1, V takes a value of V p .
  • a logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit comprising:
  • the present invention provides a complete non-volatile Boolean logic circuit and operation method based on memristors, which are used to perform logic operations on input logic values P and/or input logic values Q;
  • the logic circuit is mainly composed of memory Composed of resistors and resistors, the structure is simple, the complexity of the circuit is low, and the circuit area is small; wherein, the logic value P is defined in the form of voltage at the voltage input terminal of the memristor M1 and the resistor, and the logic value Q is defined as the memristor
  • the resistance state of M 1 and the resistance state of memristor M 2 are used as output; the complete Boolean logic function can be realized only by setting the state of the memristor and pressurizing the memristor and the resistance.
  • Complete Boolean logic operations are realized with high computing efficiency under the condition of fewer devices and operation steps.
  • the resistance state of the memristor M1 does not change during the operation process of logic calculation, and the entire operation process is non-destructive, which is beneficial to protect the input Integrity of Information.
  • the present invention provides a logic cascading method based on a memristor-based complete non-volatile Boolean logic circuit, which can directly use the result obtained from the logic calculation in the previous step as the input of the logic operation in the next step, that is, save the calculation result in the previous step
  • the memristor M 2 is directly regarded as the input memristor M 1 of the logic calculation in the next step, and the logic cascading is simple and easy, which helps to realize more complex logic functions.
  • FIG. 1 is a schematic structural diagram of a complete non-volatile Boolean logic circuit based on a memristor provided in Embodiment 1 of the present invention
  • FIG. 2 is a test diagram of the resistive I-V characteristic of the memristor provided in Embodiment 1 of the present invention.
  • FIG. 3 is a configuration diagram of the control terminal when performing 16 logic operations provided by Embodiment 1 of the present invention.
  • Embodiment 4 is a flow chart of the operation method based on the complete non-volatile Boolean logic circuit described in Embodiment 1 provided by Embodiment 2 of the present invention
  • FIG. 5 is a circuit diagram of an XOR logic calculation provided by Embodiment 2 of the present invention.
  • Fig. 6 is the truth table of exclusive OR logic operation provided by Embodiment 2 of the present invention.
  • Fig. 7 is a schematic diagram of the comparison results of resistance state changes measured before and after the XOR logic calculation circuit diagram provided by Embodiment 2 of the present invention before and after the operation.
  • a memristor-based complete non-volatile Boolean logic circuit for performing logic operations on an input logic value P and/or an input logic value Q;
  • the above logic circuit includes: a controller, a memristor M1, a memristor M2 and a resistor (a fixed-value resistor is used in this embodiment);
  • the controller is respectively connected to the positive pole of the memristor M1, the positive pole of the memristor M2 and one end of the resistor; the positive poles of the memristor M1 and the memristor M2 are respectively connected to different bit lines, and the negative poles are connected to on the same word line WL; the other end of the resistor is connected to the word line WL; the memristor M 1 and the memristor M 2 are the same; specifically, the controller includes a control terminal T 1 , a control terminal T 2 and a control terminal T 3 ; the control terminal T1 is connected to the positive pole of the memristor M1 through the bit line BL1, the control terminal T2 is connected to the positive pole of the memristor M2 through the bit line BL2 , and the control terminal T3 is connected to one end of the resistor ; It should be noted that the above-mentioned memristor M 1 is the same as the memristor M 2 , both of which include a high-re
  • the test diagram of the resistive IV characteristic of the memristor used is shown in Figure 2. Specifically, when a forward voltage greater than Vset is applied across the memristor, the memristor changes from a high-resistance state to a low-resistance state. At this time, the resistance of the memristor is set to a low-resistance state; when a negative voltage less than V reset is applied across the memristor, the memristor changes from a low-resistance state to a high-resistance state, at this time The resistance of the resistor is set to a high resistance state; the memristor can be switched between a high resistance state and a low resistance state by controlling the voltage across the memristor.
  • the high-resistance state of the memristor corresponds to the logic value "0"
  • the low-resistance state of the memristor corresponds to the logic value "1”
  • V set is the memristor M 1 or the memristor M 2 by the high-resistance
  • V reset is the threshold at which the memristor M 1 or the memristor M 2 changes from the low-resistance state to the high-resistance state.
  • the memristor is limited in current, and the current limit is I cc ; specifically, as shown in FIG. 2 , the implementation Example Set the current limit of the memristor used to 1mA, that is, I cc is 1mA.
  • the controller is used to set the memristor M2 to a high-impedance state before performing logic operations; when performing logic operations, apply voltage A to memristor M1, apply voltage B to memristor M2 , and apply voltage C, and read the resistance state of the memristor M2 , which is the result of the logic operation;
  • the controller when the above logic circuit performs an operation related to the logic value Q, the controller is also used to set the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation ;
  • Operations include operations that perform logical operations on logical values P and logical values Q and operations that perform logical operations on logical values only Q
  • the value of voltage A and voltage C is determined by the logic value P and the type of logic operation; the value of voltage B is V p ; since the electrical signals used in the logic operation process are all voltage pulse signals, in order to meet the requirements of logic operations, V p
  • the voltage amplitude should be between V set /2 and V set , so that when no operation is performed, the memristor in the high-impedance state will not change to the low-impedance state; at the same time, when the two ends of the memristor are connected
  • a memristor whose on-off ratio is greater than or equal to the preset switching threshold is used.
  • the preset switch The threshold value is 100.
  • the resistance value of the resistor is between the resistance value of the high-resistance state and the resistance value of the low-resistance state of the memristor M1 or the memristor M2 ;
  • the resistance value of the fixed-value resistor is Wherein, R H is the resistance value of the high-resistance state of the memristor M1 or the memristor M2 , and R L is the resistance value of the low-resistance state of the memristor M1 or the memristor M2 .
  • the fixed-value resistor mainly plays the role of current limiting in this logic circuit; further, considering that both the high-resistance state and the low-resistance state of the memristor have a certain fluctuation range, the selection of the fixed-value resistor resistance R can be slightly larger than Provide better protection for the reliability of the circuit.
  • logic operations include: true logic operations, false logic operations, P logic operations, Q logic operations, not-P logic operations, not-Q logic operations, AND logic operations, AND NOT logic operations, or logic operations, OR non-logical operations, substantial implication logical operations, anti-substantial implication logical operations, negative substantive implication logical operations, negative negative substantive implication logical operations, exclusive-or logical operations, and exclusive-or logical operations.
  • the invention provides a complete non-volatile Boolean logic circuit.
  • the logic value P input in the logic calculation is defined in the form of voltage at the control terminal T1 and the control terminal T3, and the input logic value Q is defined as the memristor M
  • the resistance state of 1 , the resistance state of the memristor M2 is used as the output.
  • Complete 16 kinds of Boolean logic functions can be realized only by two steps of setting the state of the memristor and applying voltage to the memristor and the resistor. The operation is simple, the components required in the circuit are less, the circuit area is small, and the calculation efficiency is high.
  • An operation method based on the complete non-volatile Boolean logic circuit described in Embodiment 1, as shown in Figure 4, comprises the following steps:
  • the value of voltage A and voltage C is determined by the logic value P and the type of logic operation; the value of voltage B is V p ; V p satisfies V set /2 ⁇ V p ⁇ V set and V p ⁇ 2
  • applying voltage A to memristor M1 means applying voltage A to control terminal T1 , apply a voltage C to the resistor, that is, apply a voltage C to the control terminal T3 )
  • the specific operations are as follows:
  • False logic the value of voltage A is 0, and the value of voltage C is 0; at this time, the control terminals T1 and T3 are grounded, and the resistance state of the memristor M1 is used as the input Q;
  • Not P logic the value of voltage A is VV p , and the value of voltage C is VV p ; at this time, the input P is applied to terminals T1 and T3 in the form of voltage VVP , and the memristor M1 The resistance state is used as the input Q;
  • Not Q logic the value of voltage A is 0, and the value of voltage C is -V p ; at this time, the control terminal T 1 is grounded, and -V P is applied to the control terminal T 3 , the resistance of the memristor M 1 State as input Q;
  • NAND logic NAND: the value of voltage A is VV p , and the value of voltage C is -V p ; at this time, the input P is applied to the terminal T1 in the form of voltage VV p , and -V P is applied to the control terminal T3 , the resistance state of the memristor M1 is used as the input Q;
  • Anti-substantial implication logic the value of voltage A is -V, and the value of voltage C is -V p ; at this time, the input P is applied to the terminal T1 in the form of voltage -V, and -V is applied to the control terminal T3 P , the resistance state of the memristor M 1 is used as the input Q;
  • Negative substantial implication logic the value of voltage A is 0, and the value of voltage C is -V; at this time, the control terminal T1 is grounded, the input P is applied to the terminal T3 in the form of voltage -V, and the memristor M The resistance state of 1 is used as the input Q;
  • Reversed Negative Essential Implication Logic The value of voltage A is VV p , and the value of voltage C is 0; at this time, the input P is applied to terminal T1 in the form of voltage VVP , the control terminal T3 is grounded, and the memristor The resistance state of M 1 is used as input Q;
  • Exclusive OR logic the value of voltage A is VV p , and the value of voltage C is -V; at this time, input P is applied to T 1 terminal in the form of voltage VV p , and input P is applied in the form of voltage -V to Terminal T3, the resistance state of memristor M1 is used as input Q ;
  • Exclusive OR logic the value of voltage A is -V, and the value of voltage C is VV p ; at this time, the input P is applied to the terminal T 1 in the form of voltage -V, and the input P is applied to the terminal in the form of voltage VV p Terminal T3, the resistance state of memristor M1 is used as input Q ;
  • V takes a value of 0; when the logical value P is 1, V takes a value of V p .
  • the initialization state of the memristor M2 is a high-impedance state
  • This embodiment provides the resistance variation measured in the actual circuit for the four input situations of the XOR logic operation, and each input situation has been tested 10 times.
  • the value of the resistor R is 10K ⁇ , and the on-off ratio of the memristor is greater than 100, so that the low-resistance state and the high-resistance state of the memristor and the resistance value of the fixed value resistor R can be clearly distinguished.
  • Figure 5 is the XOR logic calculation circuit diagram
  • Figure 6 is the XOR logic operation truth table
  • Figure 7 is the XOR logic calculation circuit diagram before the XOR logic operation operation and operation
  • the comparison results of the resistance state changes measured after the test wherein, the ordinates corresponding to M 1 and M 2 represent the resistance states of the memristor M 1 and the memristor M 2 before operation, and M 1 ′′ and M 2 ′ correspond to The ordinate represents the resistance state of the memristor M1 and the memristor M2 after the operation.
  • the XOR logic operation operation method provided by the present invention can be effective according to the XOR logic operation truth table Control logic inputs and outputs.
  • the invention operates the logic circuit composed of the memristor and the fixed-value resistor, and realizes 16 kinds of complete logic calculations through the two-step operation of setting the state of the memristor and configuring different operating voltages at the control terminal.
  • the invention has the advantages of less devices used, less operation steps, simple logic cascading and no damage to input information, etc., and can be used as a general logic operation realization method.
  • the output of the logic operation of the previous step is stored in the memristor M2 in the form of resistance, and the result obtained by the logic calculation of the previous step is directly used as the input of the logic operation of the next step, that is, the memory of the calculation result saved in the previous step Resistor M 2 is directly regarded as input memristor M 1 for logic calculation in the next step.
  • the present invention discloses a complete non-volatile Boolean logic circuit and operation method based on memristors.
  • the logic circuit includes two memristors and a fixed-value resistor. , and configure the two control terminals (T1, T3) of the circuit in two steps to realize complete 16 kinds of Boolean logic functions.
  • the positive poles of the memristor M1 and the memristor M2 are connected to different bit lines (BL1, BL2), and the negative poles of the memristor M1 and the memristor M2 are connected to the same word line (WL);
  • One end of the fixed-value resistor is connected to the word line, and the other end is connected to the control terminal T3.
  • one input logic value P is defined in the form of voltage at the control terminals T1 and T3
  • another input logic value Q is defined as the resistance state of the memristor M1
  • the resistance state of the memristor M2 is used as an output.
  • the scheme adopts fewer operation steps and fewer devices, improves calculation efficiency and saves circuit area.
  • the logic implementation method adopted is non-destructive, which is beneficial to protect the integrity of the input information.
  • the logic cascading in this solution is simple and easy to implement, which helps to realize more complex logic functions.

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Abstract

本发明公开了一种基于忆阻器的完备非易失布尔逻辑电路及操作方法，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；其中，电路包括控制器、忆阻器M1、忆阻器M2和电阻；控制器用于在逻辑运算之前，将忆阻器M2置为高阻态；进行逻辑运算时，对忆阻器M1施加电压A，对忆阻器M2施加电压B，对电阻施加电压C，并读取忆阻器M2的阻态，即逻辑运算结果；且当对逻辑值P和逻辑值Q进行逻辑运算或仅对逻辑值Q进行逻辑运算时，控制器还用于在逻辑运算之前，将忆阻器M1置为逻辑值Q所对应的阻态；本发明通过对忆阻器进行置态以及对忆阻器和电阻进行加压两步操作即可实现完备的布尔逻辑功能，且器件数较少、电路面积小、操作步数少、计算效率高。

Description

一种基于忆阻器的完备非易失布尔逻辑电路及操作方法 【技术领域】
本发明属于微电子器件技术领域，更具体地，涉及一种基于忆阻器的完备非易失布尔逻辑电路及操作方法。
【背景技术】
现代计算机主要基于冯·诺依曼体系结构。在这种体系结构中，数据从内存单元中获取，传输到处理单元，计算完成后再将数据传输到要存储的内存单元。如今，处理器和存储器的运行速度均已达到了相当高的水平，但连接这两部分的总线传输速度还有很大差距，频繁的数据传输消耗了数据处理过程中大部分的时间和功耗。这一速率不匹配问题限制了现代计算机的发展，我们将其称为存储墙。内存计算是一种非常有潜力的解决方法。与人脑相类似，内存计算中存储与计算共存，具有高计算并行性、低延时、低功耗等优点。
忆阻器作为一种新型的存储器件，因其在撤电后仍能保持电阻状态这一天然的非易失性，成为存内计算架构的有力候选器件。基于忆阻器的逻辑实现主要分为三类，第一类实现方法中输入和输出均以忆阻器的阻态的形式表示，这类方案有利于进行逻辑级联但使用的器件数较多，并且随着逻辑计算复杂度的增加所使用的器件数与操作复杂度都在增加；第二类实现方法中输入以电压形式加在忆阻器两端，输出以阻态形式表示，这类方案所使用的器件数大大减少，操作步数也较少，但逻辑级联必须引入数模转换的过程，降低了计算效率；第三类实现方法中，输入分别为忆阻器一端所加电压和忆阻器的初始阻值，输出以忆阻器阻态形式表示，这类方法所用器件数少，操作步数较少，逻辑级联容易，但这类逻辑计算为破坏式 计算，不利于保护输入信息的完整性。因此，有需要提出一种逻辑完备的实现方案，在使用尽可能少器件数和操作步数的同时，易实现逻辑级联且不破坏输入数据的完整性。
【发明内容】
针对现有技术的以上缺陷或改进需求，本发明提供了一种基于忆阻器的完备非易失布尔逻辑电路及操作方法，用于解决现有技术无法在较少的器件和操作步数的条件下以较高的计算效率实现完备的布尔逻辑运算的技术问题。
为了实现上述目的，第一方面，本发明提供了一种基于忆阻器的完备非易失布尔逻辑电路，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；
上述逻辑电路包括：控制器、忆阻器M 1、忆阻器M 2和电阻；
控制器分别与忆阻器M 1的正极、忆阻器M 2的正极以及电阻的一端相连；忆阻器M 1和忆阻器M 2的负极连接在同一条字线上；电阻的另一端与该字线相连；忆阻器M 1和忆阻器M 2相同；
控制器用于在进行逻辑运算之前，将忆阻器M 2置为高阻态；进行逻辑运算时，对忆阻器M 1施加电压A，对忆阻器M 2施加电压B，对电阻施加电压C，并读取忆阻器M 2的阻态，即为逻辑运算结果；
其中，当上述逻辑电路执行与逻辑值Q有关的操作时，控制器还用于在进行逻辑运算之前，将忆阻器M 1置为逻辑值Q所对应的阻态；与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
电压A和电压C的取值由逻辑值P以及逻辑运算的类型决定；电压B取值为V p；V p满足V set/2<V p<V set且V p<2|V reset|；V set为忆阻器M 1或忆阻器M 2由高阻态转变为低阻态的阈值；V reset为忆阻器M 1或忆阻器M 2由低阻态 转变为高阻态的阈值。
进一步优选地，上述忆阻器M 1和忆阻器M 2均包括高阻态和低阻态；高阻态对应逻辑值“0”，低阻态对应逻辑值“1”。
进一步优选地，电阻的阻值大小介于忆阻器M 1或忆阻器M 2的高阻态阻值与低阻态阻值之间；电阻的阻值为
Figure PCTCN2021104578-appb-000001
其中R H为忆阻器M 1或忆阻器M 2的高阻态电阻值，R L为忆阻器M 1或忆阻器M 2的低阻态电阻值。
进一步优选地，控制器包括控制端T 1、控制端T 2和控制端T 3；控制端T 1与忆阻器M 1的正极相连，控制端T 2与忆阻器M 2的正极相连，控制端T 3与电阻的一端相连；
控制器在进行逻辑运算时，通过控制端T 1给忆阻器M 1施加电压A，通过控制端T 2给忆阻器M 2施加电压B，通过控制端T 3给电阻施加电压C，读取忆阻器M 2的阻态，即为逻辑运算结果。
进一步优选地，逻辑运算的类型包括：真逻辑运算、假逻辑运算、P逻辑运算、Q逻辑运算、非P逻辑运算、非Q逻辑运算、与逻辑运算、与非逻辑运算、或逻辑运算、或非逻辑运算、实质蕴涵逻辑运算、反实质蕴涵逻辑运算、负实质蕴涵逻辑运算、反负实质蕴涵逻辑运算、异或逻辑运算和同或逻辑运算。
进一步优选地，当逻辑运算的类型为真逻辑运算时，电压A取值为-V p，电压C取值为-V p；
当逻辑运算的类型为假逻辑运算时，电压A取值为0，电压C取值为0；
当逻辑运算的类型为P逻辑运算时，电压A取值为-V，电压C取值为-V；
当逻辑运算的类型为Q逻辑运算时，电压A取值为-V p，电压C取值为0；
当逻辑运算的类型为非P逻辑运算时，电压A取值为V-V p，电压C取值为V-V p；
当逻辑运算的类型为非Q逻辑运算时，电压A取值为0，电压C取值为-V p；
当逻辑运算的类型为与逻辑运算时，电压A取值为-V，电压C取值为0；
当逻辑运算的类型为与非逻辑运算时，电压A取值为V-V p，电压C取值为-V p；
当逻辑运算的类型为或逻辑运算时，电压A取值为-V p，电压C取值为-V；
当逻辑运算的类型为或非逻辑运算时，电压A取值为0，电压C取值为V-V p；
当逻辑运算的类型为实质蕴涵逻辑运算时，电压A取值为-V p，电压C取值为V-V p；
当逻辑运算的类型为反实质蕴涵逻辑运算时，电压A取值为-V，电压C取值为-V p；
当逻辑运算的类型为负实质蕴涵逻辑运算时，电压A取值为0，电压C取值为-V；
当逻辑运算的类型为反负实质蕴涵逻辑运算时，电压A取值为V-V p，电压C取值为0；
当逻辑运算的类型为异或逻辑运算时，电压A取值为V-V p，电压C取值为-V；
当逻辑运算的类型为同或逻辑运算时，电压A取值为-V，电压C取值为V-V p；
其中，当逻辑值P为0时，V取值为0；当逻辑值P为1时，V取值为V p。
第二方面，一种基于上述完备非易失布尔逻辑电路的操作方法，包括以下步骤：
S1、将忆阻器M 2置为高阻态；
S2、判断当前操作是否为与逻辑值Q有关的操作，若是，则将忆阻器M 1置为逻辑值Q所对应的阻态；其中，与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
S3、对忆阻器M 1施加电压A，对忆阻器M 2施加电压B，对电阻施加电压C，并读取忆阻器M 2的阻态，即为逻辑运算结果；
其中，电压A和电压C的取值由逻辑值P以及逻辑运算的类型决定；电压B取值为V p；V p满足V set/2<V p<V set且V p<2|V reset|；V set为忆阻器M 1或忆阻器M 2由高阻态转变为低阻态的阈值；V reset为忆阻器M 1或忆阻器M 2由低阻态转变为高阻态的阈值。
进一步优选地，当逻辑运算的类型为真逻辑运算时，电压A取值为-V p，电压C取值为-V p；
当逻辑运算的类型为假逻辑运算时，电压A取值为0，电压C取值为0；
当逻辑运算的类型为P逻辑运算时，电压A取值为-V，电压C取值为-V；
当逻辑运算的类型为Q逻辑运算时，电压A取值为-V p，电压C取值为0；
当逻辑运算的类型为非P逻辑运算时，电压A取值为V-V p，电压C取值为V-V p；
当逻辑运算的类型为非Q逻辑运算时，电压A取值为0，电压C取值为-V p；
当逻辑运算的类型为与逻辑运算时，电压A取值为-V，电压C取值为0；
当逻辑运算的类型为与非逻辑运算时，电压A取值为V-V p，电压C取 值为-V p；
当逻辑运算的类型为或逻辑运算时，电压A取值为-V p，电压C取值为-V；
当逻辑运算的类型为或非逻辑运算时，电压A取值为0，电压C取值为V-V p；
当逻辑运算的类型为实质蕴涵逻辑运算时，电压A取值为-V p，电压C取值为V-V p；
当逻辑运算的类型为反实质蕴涵逻辑运算时，电压A取值为-V，电压C取值为-V p；
当逻辑运算的类型为负实质蕴涵逻辑运算时，电压A取值为0，电压C取值为-V；
当逻辑运算的类型为反负实质蕴涵逻辑运算时，电压A取值为V-V p，电压C取值为0；
当逻辑运算的类型为异或逻辑运算时，电压A取值为V-V p，电压C取值为-V；
当逻辑运算的类型为同或逻辑运算时，电压A取值为-V，电压C取值为V-V p；
其中，当逻辑值P为0时，V取值为0；当逻辑值P为1时，V取值为V p。
第三方面，一种基于上述完备非易失布尔逻辑电路的逻辑级联方法，包括：
将按照第二方面所述操作方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照第二方面所述操作方法进行操作，从而实现逻辑级联。
总体而言，通过本发明所构思的以上技术方案，能够取得以下有益效果：
1、本发明提供了一种基于忆阻器的完备非易失布尔逻辑电路及操作方法，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；该逻辑电路主要由忆阻器和电阻构成，结构简单，电路的复杂度低，电路面积小；其中，逻辑值P以电压的形式定义在忆阻器M 1和电阻的电压输入端，逻辑值Q定义为忆阻器M 1的阻态，忆阻器M 2的阻态作为输出；只需对忆阻器进行置态以及对忆阻器和电阻进行加压两步操作即可实现完备的布尔逻辑功能，能够在较少的器件和操作步数的条件下以较高的计算效率实现完备的布尔逻辑运算。
2、本发明所提供的完备非易失布尔逻辑电路及操作方法，在逻辑计算的操作过程中，忆阻器M 1的阻态不发生改变，整个操作过程为非破坏式，有利于保护输入信息的完整性。
3、本发明提供了一种基于忆阻器的完备非易失布尔逻辑电路的逻辑级联方法，可以将前一步逻辑计算得到的结果直接作为后一步逻辑操作的输入，即将前一步保存计算结果的忆阻器M 2直接看作后一步逻辑计算的输入忆阻器M 1，逻辑级联简单易行，有助于实现更加复杂的逻辑功能。
【附图说明】
图1为本发明实施例1所提供的基于忆阻器的完备非易失布尔逻辑电路的结构示意图；
图2为本发明实施例1所提供的忆阻器的阻变I-V特性测试图；
图3为本发明实施例1所提供的进行16种逻辑运算时控制端的配置图；
图4为本发明实施例2所提供的基于实施例1所述完备非易失布尔逻辑电路的操作方法流程图；
图5为本发明实施例2所提供的异或逻辑计算电路图；
图6为本发明实施例2所提供的异或逻辑运算真值表；
图7为本发明实施例2所提供的对异或逻辑计算电路图进行异或逻辑 运算操作前和操作后所测得的阻态变化对比结果示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
实施例1、
一种基于忆阻器的完备非易失布尔逻辑电路，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；
如图1所示，上述逻辑电路包括：控制器、忆阻器M 1、忆阻器M 2和电阻(本实施例采用定值电阻)；
控制器分别与忆阻器M 1的正极、忆阻器M 2的正极以及电阻的一端相连；忆阻器M 1和忆阻器M 2的正极分别连接在不同的位线上，负极连接在同一条字线WL上；电阻的另一端与该字线WL相连；忆阻器M 1和忆阻器M 2相同；具体地，控制器包括控制端T 1、控制端T 2和控制端T 3；控制端T 1通过位线BL 1与忆阻器M 1的正极相连，控制端T 2通过位线BL 2与忆阻器M 2的正极相连，控制端T 3与电阻的一端相连；需要说明的是，上述忆阻器M 1和忆阻器M 2相同，均包括高阻态和低阻态；高阻态对应逻辑值“0”，低阻态对应逻辑值“1”。所采用的忆阻器的阻变I-V特性测试图如图2所示，具体地，当在忆阻器的两端施加大于V set的正向电压，忆阻器由高阻态转变为低阻态，此时忆阻器的电阻被设置到低阻态；当在忆阻器的两端施加小于V reset的负向电压时，忆阻器由低阻态转变为高阻态，此时忆阻器的电阻被设置到高阻态；通过控制忆阻器两端的电压，可以使忆阻器在高阻态与低阻态之间转换。其中，定义忆阻器的高阻态对应逻辑值“0”，忆阻 器的低阻态对应逻辑值“1”；其中，V set为忆阻器M 1或忆阻器M 2由高阻态转变为低阻态的阈值；V reset为忆阻器M 1或忆阻器M 2由低阻态转变为高阻态的阈值。需要说明的是，为防止施加的正向电压过大而导致忆阻器被击穿，被击穿的器件将无法通过施加负向的reset电压回到高阻态，在忆阻器的两端施加大于V set的正向电压以使忆阻器由高阻态转变为低阻态时，对忆阻器进行限流，限流大小为I cc；具体地，如图2所示，本实施例将所使用的忆阻器的限流大小设置为1mA，即I cc为1mA。
控制器用于在进行逻辑运算之前，将忆阻器M 2置为高阻态；进行逻辑运算时，对忆阻器M 1施加电压A，对忆阻器M 2施加电压B，对电阻施加电压C，并读取忆阻器M 2的阻态，即为逻辑运算结果；
其中，当上述逻辑电路执行与逻辑值Q有关的操作时，控制器还用于在进行逻辑运算之前，将忆阻器M 1置为逻辑值Q所对应的阻态；与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作
电压A和电压C的取值由逻辑值P以及逻辑运算的类型决定；电压B取值为V p；由于逻辑运算过程中采用的电信号均为电压脉冲信号，为满足逻辑运算要求，V p电压幅值应介于V set/2与V set之间，使得不进行运算操作时，原处于高阻态的忆阻器不会向低阻态变化；同时，当忆阻器两端加上2V p压降时，确保忆阻器发生阻态变化；另外，还需要满足V p<2|V reset|，使得不进行运算操作时，原处于低阻态的忆阻器不会向高阻态变化。故V p需满足V set/2<V p<V set且V p<2|V reset|。
进一步地，为了使忆阻器的低阻态、高阻态和定值电阻的阻值能够明显区分，采用开关比大于或等于预设开关阈值的忆阻器，本实施例中，预设开关阈值取值为100。电阻的阻值大小介于忆阻器M 1或忆阻器M 2的高阻态阻值与低阻态阻值之间；由于忆阻器的高阻态与低阻态之间处于不同的数量级，为了进一步将忆阻器的低阻态、高阻态和定值电阻的阻值明显 区分开，优选地，定值电阻的阻值取值为
Figure PCTCN2021104578-appb-000002
其中，R H为忆阻器M 1或忆阻器M 2的高阻态电阻值，R L为忆阻器M 1或忆阻器M 2的低阻态电阻值。定值电阻在该逻辑电路中主要起到限流的作用；进一步地，考虑到忆阻器的高阻态与低阻态都存在一定的波动范围，定值电阻阻值R的选取可以略大于
Figure PCTCN2021104578-appb-000003
为该电路可靠性提供更好的保障。
需要说明的是，逻辑运算的类型包括：真逻辑运算、假逻辑运算、P逻辑运算、Q逻辑运算、非P逻辑运算、非Q逻辑运算、与逻辑运算、与非逻辑运算、或逻辑运算、或非逻辑运算、实质蕴涵逻辑运算、反实质蕴涵逻辑运算、负实质蕴涵逻辑运算、反负实质蕴涵逻辑运算、异或逻辑运算和同或逻辑运算。如图3所示，当逻辑运算的类型为真逻辑运算时，电压A取值为-V p，电压C取值为-V p；当逻辑运算的类型为假逻辑运算时，电压A取值为0，电压C取值为0；当逻辑运算的类型为P逻辑运算时，电压A取值为-V，电压C取值为-V；当逻辑运算的类型为Q逻辑运算时，电压A取值为-V p，电压C取值为0；当逻辑运算的类型为非P逻辑运算时，电压A取值为V-V p，电压C取值为V-V p；当逻辑运算的类型为非Q逻辑运算时，电压A取值为0，电压C取值为-V p；当逻辑运算的类型为与逻辑运算时，电压A取值为-V，电压C取值为0；当逻辑运算的类型为与非逻辑运算时，电压A取值为V-V p，电压C取值为-V p；当逻辑运算的类型为或逻辑运算时，电压A取值为-V p，电压C取值为-V；当逻辑运算的类型为或非逻辑运算时，电压A取值为0，电压C取值为V-V p；当逻辑运算的类型为实质蕴涵逻辑运算时，电压A取值为-V p，电压C取值为V-V p；当逻辑运算的类型为反实质蕴涵逻辑运算时，电压A取值为-V，电压C取值为-V p；当逻辑运算的类型为负实质蕴涵逻辑运算时，电压A取值为0，电压C取值为-V；当逻辑运算的类型为反负实质蕴涵逻辑运算时，电压A取值为V-V p，电压C取值为0；当逻辑运算的类型为异或逻辑运算时，电压A 取值为V-V p，电压C取值为-V；当逻辑运算的类型为同或逻辑运算时，电压A取值为-V，电压C取值为V-V p；其中，当逻辑值P为0时，V取值为0；当逻辑值P为1时，V取值为V p。
本发明提供了一种完备的非易失布尔逻辑电路，逻辑计算中输入的逻辑值P以电压的形式定义在控制端T 1和控制端T 3，输入的逻辑值Q定义为忆阻器M 1的阻态，忆阻器M 2的阻态作为输出。只需对忆阻器进行置态以及对忆阻器和电阻进行加压两步操作即可实现完备的16种布尔逻辑功能。操作简单、电路中所需的器件较少、电路面积较小、计算效率高。
实施例2、
一种基于实施例1所述完备非易失布尔逻辑电路的操作方法，如图4所示，包括以下步骤：
S1、将忆阻器M 2置为高阻态；
S2、判断当前操作是否为与逻辑值Q有关的操作，若是，则将忆阻器M 1置为逻辑值Q所对应的阻态；其中，与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
S3、对忆阻器M 1施加电压A，对忆阻器M 2施加电压B，对电阻施加电压C，并读取忆阻器M 2的阻态，即为逻辑运算结果；
其中，电压A和电压C的取值由逻辑值P以及逻辑运算的类型决定；电压B取值为V p；V p满足V set/2<V p<V set且V p<2|V reset|；V set为忆阻器M 1或忆阻器M 2由高阻态转变为低阻态的阈值；V reset为忆阻器M 1或忆阻器M 2由低阻态转变为高阻态的阈值。
上述操作方法可以基于两个双极性忆阻器实现16种布尔逻辑功能，对不同的逻辑运算类型(本实施例中，对忆阻器M 1施加电压A即在控制端T 1施加电压A，对电阻施加电压C，即在控制端T 3施加电压C)，具体操作如下：
真逻辑(TRUE)：电压A取值为-V p，电压C取值为-V p；此时，在控 制端T 1和T 3施加-V P，忆阻器M 1的阻态作为输入Q；
假逻辑(FALSE)：电压A取值为0，电压C取值为0；此时，控制端T 1和T 3接地，忆阻器M 1的阻态作为输入Q；
P逻辑(COPY P)：电压A取值为-V，电压C取值为-V；此时，输入P以电压-V的形式施加在T 1和T 3端，忆阻器M 1的阻态作为输入Q；
Q逻辑(COPY Q)：电压A取值为-V p，电压C取值为0；此时，在控制端T 1施加-V P，控制端T 3接地，忆阻器M 1的阻态作为输入Q；
非P逻辑(NOT P)：电压A取值为V-V p，电压C取值为V-V p；此时，输入P以电压V-V P的形式施加在T 1和T 3端，忆阻器M 1的阻态作为输入Q；
非Q逻辑(NOT Q)：电压A取值为0，电压C取值为-V p；此时，控制端T 1接地，在控制端T 3施加-V P，忆阻器M 1的阻态作为输入Q；
与逻辑(AND)：电压A取值为-V，电压C取值为0；此时，输入P以电压-V的形式施加在T 1端，控制端T 3接地，忆阻器M 1的阻态作为输入Q；
与非逻辑(NAND)：电压A取值为V-V p，电压C取值为-V p；此时，输入P以电压V-V p的形式施加在T 1端，在控制端T 3施加-V P，忆阻器M 1的阻态作为输入Q；
或逻辑(OR)：电压A取值为-V p，电压C取值为-V；此时，在控制端T 1施加-V P，输入P以电压-V的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
或非逻辑(NOR)：电压A取值为0，电压C取值为V-V p；此时，控制端T 1接地，输入P以电压V-V p的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
实质蕴涵逻辑(IMP)：电压A取值为-V p，电压C取值为V-V p；此时，在控制端T 1施加-V P，输入P以电压V-V p的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
反实质蕴涵逻辑(RIMP)：电压A取值为-V，电压C取值为-V p；此时，输入P以电压-V的形式施加在T 1端，在控制端T 3施加-V P，忆阻器M 1的阻态作为输入Q；
负实质蕴涵逻辑(NIMP)：电压A取值为0，电压C取值为-V；此时，控制端T 1接地，输入P以电压-V的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
反负实质蕴涵逻辑(RNIMP)：电压A取值为V-V p，电压C取值为0；此时，输入P以电压V-V P的形式施加在T 1端，控制端T 3接地，忆阻器M 1的阻态作为输入Q；
异或逻辑(XOR)：电压A取值为V-V p，电压C取值为-V；此时，输入P以电压V-V p的形式施加在T 1端，输入P以电压-V的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
同或逻辑(XNOR)：电压A取值为-V，电压C取值为V-V p；此时，输入P以电压-V的形式施加在T 1端，输入P以电压V-V p的形式施加在T 3端，忆阻器M 1的阻态作为输入Q；
其中，当逻辑值P为0时，V取值为0；当逻辑值P为1时，V取值为V p。
需要说明的是，对于如P逻辑运算、真逻辑运算的逻辑运算，虽然运算结果与输入Q无关，但Q也参与了运算(参见具体逻辑运算的真值表)，故其同样属于对逻辑值P和逻辑值Q进行逻辑运算的操作。
为了进一步说明本发明所提供的操作方法，下面以异或逻辑运算为例进行详述；具体操作如下：
忆阻器M 2初始化状态为高阻态；
当输入P＝0，Q＝0时，V＝0，忆阻器M 1设置为高阻态，此时忆阻器M 1两端的电压V M1约为-V p，忆阻器M 2两端的电压V M2约为V p，由于V set/2<V p<V set且V p<2|V reset|，故此时忆阻器M 2保持高阻态不变，输出逻辑 值0，即逻辑运算结果为0；
当输入P＝0，Q＝1时，V＝0，忆阻器M 1设置为低阻态，此时忆阻器M 1两端的电压V M1约为0，忆阻器M 2两端的电压V M2约为2V p，此时，忆阻器M 2转变为低阻态，输出逻辑值1，即逻辑运算结果为1；
当输入P＝1，Q＝0时，V＝V p，忆阻器M 1设置为高阻态，此时忆阻器M 1两端的电压V M1约为V p，忆阻器M 2两端的电压V M2约为2V p，忆阻器M 2转变为低阻态，输出逻辑值1，即逻辑运算结果为1；
当输入P＝1，Q＝1时，V＝V p，忆阻器M 1设置为低阻态，此时忆阻器M 1两端的电压V M1约为0，忆阻器M 2两端的电压V M2约为V p，忆阻器M 2保持高阻态不变，输出逻辑值0。
本实施例提供了异或逻辑运算的四种输入情况在实际电路中测得的电阻变化情况，其中每一种输入情况都进行了10次测试。其中，本实施例中电阻R取值为10KΩ，忆阻器的开关比大于100，使得忆阻器的低阻态、高阻态和定值电阻R的阻值能够明显区分。具体地，如图5所示为异或逻辑计算电路图，如图6所示为异或逻辑运算真值表，如图7所示为对异或逻辑计算电路图进行异或逻辑运算操作前和操作后所测得的阻态变化对比结果；其中，M 1和M 2所对应的纵坐标表示操作前忆阻器M 1和忆阻器M 2的阻态，M 1”和M 2’所对应的纵坐标表示操作后忆阻器M 1和忆阻器M 2的阻态。从图中可以看出，本发明所提供的异或逻辑运算操作方法能够按照异或逻辑运算真值表有效的控制逻辑输入和输出。
需要说明的是，其它布尔逻辑运算的操作过程与异或逻辑运算的操作过程类似，这里不做赘述。
本发明对由忆阻器和定值电阻组成的逻辑电路进行操作，通过对忆阻器进行置态以及在控制端配置不同的操作电压两步操作即可实现16种完备逻辑计算。本发明具有使用器件数少、操作步数少、逻辑级联简单且不对输入信息造成破坏等优势，可以作为一种通用逻辑运算实现方法。
实施例3、
一种基于实施例1所述完备非易失布尔逻辑电路的逻辑级联方法，包括：
将按照实施例2所述操作方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照实施例2所述操作方法进行操作，从而实现逻辑级联。
本实施例中，前一步逻辑操作的输出以阻态的形式保存在忆阻器M 2中，将前一步逻辑计算得到的结果直接作为后一步逻辑操作的输入，即将前一步保存计算结果的忆阻器M 2直接看作后一步逻辑计算的输入忆阻器M 1。
综上所述，本发明公开了一种基于忆阻器的完备非易失布尔逻辑电路及操作方法，该逻辑电路包括两个忆阻器与一个定值电阻，通过对忆阻器进行置态，以及对该电路的两个控制端(T1、T3)进行配置两步操作即可实现完备的16种布尔逻辑功能。其中，忆阻器M 1和忆阻器M 2的正极与不同的位线(BL1、BL2)相连，忆阻器M 1和忆阻器M 2的负极与同一条字线(WL)相连；定值电阻的一端与字线相连，另一端与控制端T3相连。逻辑计算中一个输入逻辑值P以电压的形式定义在控制端T1和T3，另一个输入逻辑值Q定义为忆阻器M 1的阻态，忆阻器M 2的阻态作为输出。与现有的逻辑方法相比，本方案采用的操作步数少，器件数较少，提高了计算效率并且节省了电路面积。且所采用的逻辑实现方法为非破坏式，有利于保护输入信息的完整性。另外，本方案逻辑级联简单易行，有助于实现更加复杂的逻辑功能。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种基于忆阻器的完备非易失布尔逻辑电路，其特征在于，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；
    所述逻辑电路包括：控制器、忆阻器M 1、忆阻器M 2和电阻；
    所述控制器分别与所述忆阻器M 1的正极、所述忆阻器M 2的正极以及所述电阻的一端相连；所述忆阻器M 1和所述忆阻器M 2的负极连接在同一条字线上；所述电阻的另一端与所述字线相连；所述忆阻器M 1和所述忆阻器M 2相同；
    所述控制器用于在进行逻辑运算之前，将所述忆阻器M 2置为高阻态；进行逻辑运算时，对所述忆阻器M 1施加电压A，对所述忆阻器M 2施加电压B，对所述电阻施加电压C，并读取所述忆阻器M 2的阻态，即为逻辑运算结果；
    其中，当所述逻辑电路执行与所述逻辑值Q有关的操作时，所述控制器还用于在进行逻辑运算之前，将所述忆阻器M 1置为所述逻辑值Q所对应的阻态；与所述逻辑值Q有关的操作包括对所述逻辑值P和所述逻辑值Q进行逻辑运算的操作和仅对所述逻辑值Q进行逻辑运算的操作；
    所述电压A和所述电压C的取值由所述逻辑值P以及逻辑运算的类型决定；所述电压B取值为V p；所述V p满足V set/2<V p<V set且V p<2|V reset|；V set为所述忆阻器M 1或所述忆阻器M 2由高阻态转变为低阻态的阈值；V reset为所述忆阻器M 1或所述忆阻器M 2由低阻态转变为高阻态的阈值。
  2. 根据权利要求1所述的逻辑电路，其特征在于，所述忆阻器M 1和所述忆阻器M 2均包括高阻态和低阻态；所述高阻态对应逻辑值“0”，所述低阻态对应逻辑值“1”。
  3. 根据权利要求2所述的逻辑电路，其特征在于，所述电阻的阻值大小介于所述忆阻器M 1或所述忆阻器M 2的高阻态阻值与低阻态阻值之间； 所述电阻的阻值为
    Figure PCTCN2021104578-appb-100001
    其中，R H为所述忆阻器M 1或所述忆阻器M 2的高阻态电阻值，R L为所述忆阻器M 1或所述忆阻器M 2的低阻态电阻值。
  4. 根据权利要求2所述的逻辑电路，其特征在于，所述控制器包括控制端T 1、控制端T 2和控制端T 3；所述控制端T 1与所述忆阻器M 1的正极相连，所述控制端T 2与所述忆阻器M 2的正极相连，所述控制端T 3与所述电阻的一端相连；
    所述控制器在进行逻辑运算时，通过所述控制端T 1给所述忆阻器M 1施加电压A，通过所述控制端T 2给所述忆阻器M 2施加电压B，通过所述控制端T 3给所述电阻施加电压C，读取所述忆阻器M 2的阻态，即为逻辑运算结果。
  5. 根据权利要求1-4任意一项所述的逻辑电路，其特征在于，所述逻辑运算的类型包括：真逻辑运算、假逻辑运算、P逻辑运算、Q逻辑运算、非P逻辑运算、非Q逻辑运算、与逻辑运算、与非逻辑运算、或逻辑运算、或非逻辑运算、实质蕴涵逻辑运算、反实质蕴涵逻辑运算、负实质蕴涵逻辑运算、反负实质蕴涵逻辑运算、异或逻辑运算和同或逻辑运算。
  6. 根据权利要求5所述的逻辑电路，其特征在于，当所述逻辑运算的类型为真逻辑运算时，所述电压A取值为-V p，所述电压C取值为-V p；
    当所述逻辑运算的类型为假逻辑运算时，所述电压A取值为0，所述电压C取值为0；
    当所述逻辑运算的类型为P逻辑运算时，所述电压A取值为-V，所述电压C取值为-V；
    当所述逻辑运算的类型为Q逻辑运算时，所述电压A取值为-V p，所述电压C取值为0；
    当所述逻辑运算的类型为非P逻辑运算时，所述电压A取值为V-V p，所述电压C取值为V-V p；
    当所述逻辑运算的类型为非Q逻辑运算时，所述电压A取值为0，所述电压C取值为-V p；
    当所述逻辑运算的类型为与逻辑运算时，所述电压A取值为-V，所述电压C取值为0；
    当所述逻辑运算的类型为与非逻辑运算时，所述电压A取值为V-V p，所述电压C取值为-V p；
    当所述逻辑运算的类型为或逻辑运算时，所述电压A取值为-V p，所述电压C取值为-V；
    当所述逻辑运算的类型为或非逻辑运算时，所述电压A取值为0，所述电压C取值为V-V p；
    当所述逻辑运算的类型为实质蕴涵逻辑运算时，所述电压A取值为-V p，所述电压C取值为V-V p；
    当所述逻辑运算的类型为反实质蕴涵逻辑运算时，所述电压A取值为-V，所述电压C取值为-V p；
    当所述逻辑运算的类型为负实质蕴涵逻辑运算时，所述电压A取值为0，所述电压C取值为-V；
    当所述逻辑运算的类型为反负实质蕴涵逻辑运算时，所述电压A取值为V-V p，所述电压C取值为0；
    当所述逻辑运算的类型为异或逻辑运算时，所述电压A取值为V-V p，所述电压C取值为-V；
    当所述逻辑运算的类型为同或逻辑运算时，所述电压A取值为-V，所述电压C取值为V-V p；
    其中，当所述逻辑值P为0时，V取值为0；当所述逻辑值P为1时，V取值为V p。
  7. 一种基于权利要求1-6任意一项所述逻辑电路的操作方法，其特征在于，包括以下步骤：
    S1、将忆阻器M 2置为高阻态；
    S2、判断当前操作是否为与逻辑值Q有关的操作，若是，则将忆阻器M 1置为逻辑值Q所对应的阻态；所述与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
    S3、对忆阻器M 1施加电压A，对忆阻器M 2施加电压B，对电阻施加电压C，并读取忆阻器M 2的阻态，即为逻辑运算结果；
    其中，所述电压A和所述电压C的取值由所述逻辑值P以及所述逻辑运算的类型决定；所述电压B取值为V p；V p满足V set/2<V p<V set且V p<2|V reset|；所述V set为忆阻器M 1或忆阻器M 2由高阻态转变为低阻态的阈值；所述V reset为忆阻器M 1或忆阻器M 2由低阻态转变为高阻态的阈值。
  8. 根据权利要求7所述的操作方法，其特征在于，当所述逻辑运算的类型为真逻辑运算时，所述电压A取值为-V p，所述电压C取值为-V p；
    当所述逻辑运算的类型为假逻辑运算时，所述电压A取值为0，所述电压C取值为0；
    当所述逻辑运算的类型为P逻辑运算时，所述电压A取值为-V，所述电压C取值为-V；
    当所述逻辑运算的类型为Q逻辑运算时，所述电压A取值为-V p，所述电压C取值为0；
    当所述逻辑运算的类型为非P逻辑运算时，所述电压A取值为V-V p，所述电压C取值为V-V p；
    当所述逻辑运算的类型为非Q逻辑运算时，所述电压A取值为0，所述电压C取值为-V p；
    当所述逻辑运算的类型为与逻辑运算时，所述电压A取值为-V，所述电压C取值为0；
    当所述逻辑运算的类型为与非逻辑运算时，所述电压A取值为V-V p，所述电压C取值为-V p；
    当所述逻辑运算的类型为或逻辑运算时，所述电压A取值为-V p，所述电压C取值为-V；
    当所述逻辑运算的类型为或非逻辑运算时，所述电压A取值为0，所述电压C取值为V-V p；
    当所述逻辑运算的类型为实质蕴涵逻辑运算时，所述电压A取值为-V p，所述电压C取值为V-V p；
    当所述逻辑运算的类型为反实质蕴涵逻辑运算时，所述电压A取值为-V，所述电压C取值为-V p；
    当所述逻辑运算的类型为负实质蕴涵逻辑运算时，所述电压A取值为0，所述电压C取值为-V；
    当所述逻辑运算的类型为反负实质蕴涵逻辑运算时，所述电压A取值为V-V p，所述电压C取值为0；
    当所述逻辑运算的类型为异或逻辑运算时，所述电压A取值为V-V p，所述电压C取值为-V；
    当所述逻辑运算的类型为同或逻辑运算时，所述电压A取值为-V，所述电压C取值为V-V p；
    其中，当所述逻辑值P为0时，V取值为0；当所述逻辑值P为1时，V取值为V p。
  9. 一种基于权利要求1-6任意一项所述逻辑电路的逻辑级联方法，其特征在于，包括：
    将按照权利要求7或8所述操作方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照权利要求7或8所述操作方法进行操作，从而实现逻辑级联。
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