WO2022261951A1 - 显示基板及其制备方法、显示装置、掩膜版 - Google Patents

显示基板及其制备方法、显示装置、掩膜版 Download PDF

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Publication number
WO2022261951A1
WO2022261951A1 PCT/CN2021/100959 CN2021100959W WO2022261951A1 WO 2022261951 A1 WO2022261951 A1 WO 2022261951A1 CN 2021100959 W CN2021100959 W CN 2021100959W WO 2022261951 A1 WO2022261951 A1 WO 2022261951A1
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Prior art keywords
edge
slit
display substrate
pixel electrode
included angle
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PCT/CN2021/100959
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English (en)
French (fr)
Inventor
张吉亮
刘晓那
马禹
陈维涛
王骁
陈玉琼
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/100959 priority Critical patent/WO2022261951A1/zh
Priority to US17/779,571 priority patent/US20240168347A1/en
Priority to CN202180001562.6A priority patent/CN115885212A/zh
Publication of WO2022261951A1 publication Critical patent/WO2022261951A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, and specifically relate to a display substrate and a manufacturing method thereof, a display device, and a mask.
  • the liquid crystal display panel has the advantages of low power consumption, small size, and low radiation.
  • liquid crystal display panels in the horizontal electric field mode include In-Plane Switching (IPS) mode LCD panels and Advanced Super Dimension Switching (ADS) mode LCD panels.
  • IPS In-Plane Switching
  • ADS Advanced Super Dimension Switching
  • the ADS type display mode is widely used in the display field due to its wide viewing angle, high resolution, low power consumption and other characteristics.
  • pixel electrodes are covered within the range of data signal lines.
  • an embodiment of the present disclosure provides a display substrate, including a base and a pixel electrode disposed on one side of the base; the pixel electrode includes at least two strip electrodes, and among the at least two strip electrodes There are slits between adjacent strip electrodes, the slits at least include a first corner end located at at least one end of the slit, the first corner end includes a first side and a second side oppositely arranged, and A first transition side connecting the end of the first side and the end of the second side, the first transition side is in the shape of an arc protruding away from the first corner end; the first transition side A first angle is formed between one side and the second side, and the first angle is greater than or equal to 0° and less than or equal to 13°.
  • the first included angle is 9° to 11°.
  • the first included angle is 9.5°, 10° or 10.5°.
  • a gate line disposed on the side of the substrate close to the pixel electrode and extending along a first direction; a first insulating layer disposed on a side of the gate line away from the substrate ; a data line disposed on a side of the first insulating layer away from the base and extending along a second direction; a second insulating layer disposed on a side of the data line away from the base; disposed on the second a common electrode on the side of the insulating layer away from the base; a third insulating layer disposed on the side of the common electrode away from the base; the pixel electrode is disposed on a side of the third insulating layer away from the base; The first direction is different from the second direction.
  • it further includes a gate line disposed on a side of the substrate close to the pixel electrode and extending along a first direction, the first side forms a second angle with the first direction, so The second included angle is 40° to 50°; and/or, the second side forms a third included angle with the first direction, and the third included angle is 40° to 50°.
  • the second included angle is the same as the third included angle.
  • the length H of the orthographic projection of the first corner end in a direction perpendicular to the first direction is greater than or equal to 3 um and less than or equal to 9 um.
  • the slit further includes a first body portion extending along a third direction, a second body portion extending along a fourth direction; and combining the first body portion and the second body portion
  • the connection part connecting the main parts is V-shaped, and the third direction is different from the fourth direction.
  • the slits include a first slit, a second slit, and a third slit located between the first slit and the second slit, the third slit.
  • the length of the orthographic projection of the first corner end of the second slit in the direction perpendicular to the first direction is greater than the length of the orthographic projection of the first corner end of the second slit in the direction perpendicular to the first direction
  • the second The length of the orthographic projection of the first corner end of the slit in the direction perpendicular to the first direction is greater than the length of the orthographic projection of the first corner end of the first slit in the direction perpendicular to the first direction.
  • the width of the third slit is greater than the width of the second slit; and/or, the width of the third slit is greater than the width of the first slit; and/or , the width of the first slit is equal to the width of the second slit.
  • a touch signal line is further included, and the orthographic projection of the touch signal line on the base is at least partially located in the orthographic projection of the third slit on the base.
  • the orthographic projection of the slit on the base does not overlap with the orthographic projection of the data line on the base.
  • a touch signal line is further included, and the touch signal line is arranged on the same layer as the data line.
  • a shielding layer is further included, the shielding layer including at least one first portion extending along the second direction.
  • the shielding layer further includes a second portion extending along the first direction, the second portion being connected to the at least one first portion.
  • it further includes a touch signal line, the second part is connected to the common electrode through a first via hole, and the at least one first part is connected to the touch signal line through a second via hole .
  • the light-shielding layer includes two oppositely disposed first parts and a second part, one end of the second part is connected to one end of the two oppositely disposed first parts, and the other end of the second part One end is disconnected or connected to the other of the two oppositely disposed first parts.
  • the distance from the first side edge of the common electrode to the first side edge of the light shielding layer is the same as the distance from the second side edge of the common electrode to the second side edge of the light shielding layer; and /or, the distance from the first side edge of the common electrode to the first side edge of the data line is the same as the distance from the second side edge of the common electrode to the second side edge of the data line; and/or, the The distance from the first side edge of the common electrode to the first side edge of the pixel electrode is the same as the distance from the second side edge of the common electrode to the second side edge of the pixel electrode.
  • the distance from the edge on the first side of the pixel electrode to the edge on the first side of the light-shielding layer is the same as the distance from the edge on the second side of the pixel electrode to the edge on the second side of the light-shielding layer or, the distance from the edge on the first side of the pixel electrode to the edge on the first side of the light-shielding layer is different from the distance from the edge on the second side of the pixel electrode to the edge on the second side of the light-shielding layer.
  • an embodiment of the present disclosure further provides a display device, including the aforementioned display substrate.
  • the embodiment of the present disclosure also provides a method for preparing a display substrate, including:
  • a pixel electrode is formed on one side of the substrate; wherein, the pixel electrode includes at least two strip-shaped electrodes, and there is a slit between adjacent strip-shaped electrodes in the at least two strip-shaped electrodes, and the slit It includes at least a first corner end located at at least one end of the slit, the first corner end includes a first side and a second side that are oppositely arranged, and the end of the first side is connected to the second side of the second side.
  • a first transition edge connected at the ends, the first transition edge is in the shape of an arc protruding away from the first corner end; a first angle is formed between the first edge and the second edge, The first included angle is 0° to 13°.
  • an embodiment of the present disclosure further provides a mask, including a pattern area, the pattern area includes at least one mask pattern, and the mask pattern includes at least a second mask pattern located at at least one end of the mask pattern.
  • the corner end, the second corner end includes a third side and a fourth side oppositely arranged, and a second transition side connecting the end of the third side and the end of the fourth side, the first
  • the two transition sides are circular arcs protruding away from the second corner end; the third side and/or the fourth side are straight lines, and the distance between the third side and the fourth side is A fifth included angle is formed between them, and the fifth included angle is 0° to 5°.
  • FIG. 1 is a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2a is a first structural schematic diagram of a pixel in a display substrate according to an embodiment of the present disclosure
  • FIG. 2b is a second structural schematic diagram of a pixel in a display substrate according to an embodiment of the present disclosure
  • Fig. 3 a is the sectional view one of A-A ' direction among Fig. 2 a;
  • Fig. 3 b is the sectional view of A-A ' direction among Fig. 2 b;
  • FIG. 4 is a schematic structural diagram showing a pixel electrode in a substrate according to an embodiment of the present disclosure
  • Fig. 5 is a partial enlarged view of place a in Fig. 4;
  • FIG. 6 is a schematic diagram showing the size of the first corner end of the substrate according to an embodiment of the present disclosure
  • Fig. 7 is a partial enlarged view of place b in Fig. 4;
  • FIG. 8 is a schematic diagram showing the structure of a light-shielding layer in a substrate according to an embodiment of the present disclosure
  • Fig. 9 is a partial cross-sectional view at c in Fig. 2a;
  • Fig. 10 is a second cross-sectional view along A-A' direction in Fig. 2a.
  • FIG. 11 is a cross-sectional view of a display device according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a mask according to an embodiment of the present disclosure.
  • Fig. 13 is an enlarged view at point d in Fig. 12 .
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate of the embodiment of the present disclosure may include a display area 100 for displaying images and a peripheral area 200 disposed around the display area 100 .
  • the display area 100 of the display substrate in the embodiment of the present disclosure may include a plurality of gate lines 300 , a plurality of data lines 400 ; and pixels 500 connected to the plurality of gate lines 300 and the plurality of data lines 400 .
  • the gate line 300 is used to transmit gate electrical signals
  • the data line 400 is used to transmit data electrical signals.
  • the plurality of gate lines 300 extend along a first direction (eg, a horizontal direction), and the plurality of gate lines 300 may be parallel to each other.
  • the plurality of data lines 400 extend along a second direction (eg, a vertical direction), and the plurality of data lines 400 may be parallel to each other.
  • the first direction is different from the second direction.
  • the first direction is perpendicular to the second direction.
  • the pixel 500 may include a thin film transistor (TFT), a pixel electrode and a common electrode, the pixel electrode is connected to the drain electrode of the thin film transistor (TFT), at least one of the multiple data lines 400 is connected to the thin film transistor (TFT) and at least one of the plurality of gate lines 300 is connected to a gate of a thin film transistor (TFT).
  • the thin film transistor can be turned on or off by a gate electric signal applied by the gate line 300 connected thereto, and can be transmitted to the pixel electrode by a data electric signal provided by the data line 400 connected thereto.
  • the pixel 500 may display an image according to a data electrical signal applied to the pixel electrode.
  • the peripheral area 200 may be a part of the non-display area where the display substrate does not display an image.
  • the peripheral area 200 can be arranged around the display area 100 ; or, the peripheral area 200 can be extended along the side of the display substrate.
  • the gate lines 300 and the data lines 400 in the display area 100 may partially extend to the peripheral area 200 .
  • the peripheral area 200 may include a common voltage line (not shown in the drawing).
  • the common voltage line is connected to the common electrodes in the display area 100 for transmitting the common voltage Vcom to the common electrodes in the display area 100 .
  • FIG. 2 a is a first structural schematic diagram of a pixel in a display substrate according to an embodiment of the present disclosure.
  • Fig. 3a is a cross-sectional view along A-A' direction in Fig. 2a.
  • the embodiment of the present disclosure shows that the substrate may be a TFT array substrate.
  • the substrate may include a base 10 , a gate line 300 extending along a first direction on one side of the base 10 ; a first insulating layer disposed on a side of the gate line 300 away from the base 10 and covering the gate line 300 20; the data line 400 disposed on the side of the first insulating layer 20 away from the base 10 and extending along the second direction; the second insulating layer 30 disposed on the side of the data line 400 away from the base 10 and covering the data line 400; setting The common electrode 40 on the side of the second insulating layer 30 away from the substrate 10; the third insulating layer 50 arranged on the side of the common electrode 40 away from the substrate 10 and covering the common electrode 40; arranged on the side of the third insulating layer 50 away from the substrate 10
  • the pixel electrode 60 wherein, the first direction is different from the second direction. For example, the first direction is perpendicular to the second direction.
  • the substrate 10 may be an insulating substrate.
  • the substrate 10 may include a glass substrate, a quartz substrate, or a resin substrate, or the like.
  • the gate line 300 may be disposed on the same layer as the gate of the thin film transistor (to be described later), and manufactured by using the same material through the same process. In some embodiments, the gate line 300 may be integrally formed with the gate.
  • the gate line 300 may extend in a first direction (eg, a horizontal direction) of the substrate 10 and may be connected to a gate of the thin film transistor.
  • the material of the grid line 300 may include aluminum-based metals such as aluminum or aluminum alloys, silver-based metals such as silver or silver alloys, copper-based metals such as copper or copper alloys, molybdenum-based metals such as molybdenum or molybdenum alloys.
  • the first insulating layer 20 may be a gate insulating layer covering the gate line 300 and the gate of the thin film transistor.
  • the material of the first insulating layer 20 may include silicon oxide or silicon nitride.
  • the data line 400 may be disposed on the same layer as the source level (to be described later) of the thin film transistor, and manufactured by using the same material through the same process.
  • the data line 400 may extend in a second direction (eg, a vertical direction) of the substrate 10 and may be connected to the source of the thin film transistor.
  • the data lines 400 may be arranged across the gate lines 300 to define a plurality of pixel areas, and each pixel area corresponds to a pixel.
  • the data line 400 may not extend completely along the second direction.
  • the data line 400 may have a bent portion, and the extending direction of the data line 400 may deviate from the second direction, but the data line 400 as a whole may be regarded as extending along the second direction.
  • the second insulating layer 30 covers the data line 400 and the source and drain electrodes in the thin film transistor.
  • the material of the second insulating layer 30 may include silicon oxide or silicon nitride.
  • the plurality of common electrodes 40 corresponds to the plurality of common electrodes 40 of a plurality of pixel regions.
  • the orthographic projection of the common electrode 40 on the substrate 10 may not overlap with the orthographic projection of the data line 400 on the substrate 10 .
  • the material of the common electrode 40 may be a transparent conductive material.
  • the material of the common electrode 40 may be ITO, IZO, indium tin zinc oxide (ITZO) or aluminum doped zinc oxide (AZO).
  • the third insulating layer 50 covers the common electrode 40 .
  • the material of the third insulating layer 50 may include silicon oxide or silicon nitride or the like.
  • the pixel electrode 60 may be connected to a drain (to be described later) of a thin film transistor.
  • the orthographic projection of the pixel electrode 60 on the substrate 10 may not overlap with the orthographic projection of the data line 400 on the substrate 10 .
  • the material of the pixel electrode 60 may be a transparent conductive material.
  • the material of the pixel electrode 60 may be ITO, IZO, indium tin zinc oxide (ITZO) or aluminum doped zinc oxide (AZO).
  • the embodiment of the present disclosure shows that the pixel electrode 60 in the substrate includes at least two strip electrodes 601, and the adjacent strip electrodes 601 of the at least two strip electrodes 601 have
  • the slot 602 includes at least a first corner end 603 at at least one end of the slot 602 .
  • the embodiment of the present disclosure shows that the first corner end 603 in the substrate can reduce the problem of trace mura (uneven marks) of the liquid crystal display substrate.
  • the corner end of the present disclosure is described as an example where the bending direction of the corner end is the same as the bending direction of the middle part of the slit, as shown in Figure 2, the corner end is bent to the right; the actual product can adopt the bending direction of the corner end
  • the bending direction is different from the bending direction in the middle of the slit, or the bending direction is different at the corner ends located at the two ends of the same slit.
  • the inventors of the present disclosure found that the first corner end 603 of the pixel electrode in the display substrate will cause the arrangement of the liquid crystal in the end area of the pixel electrode 60 to be disordered under the action of finger pressing, resulting in problems such as scratches and trailing, and slow recovery time.
  • FIG. 4 is a schematic diagram showing the structure of a pixel electrode in a substrate according to an embodiment of the present disclosure.
  • Fig. 5 is a partial enlarged view of a in Fig. 4 .
  • the embodiment of the present disclosure shows that the end of the first corner end 603 of the pixel electrode 60 in the substrate is arc-shaped protruding along the direction away from the first corner end 603 .
  • the embodiment of the present disclosure shows that the arc-shaped end of the first corner end 603 in the substrate can improve the problem of liquid crystal arrangement disorder under the action of external force, so that the liquid crystal arrangement can recover faster, and reduce the Trace mura (uneven marks) of the liquid crystal display substrate )The problem.
  • the first corner end 603 includes a first side 6031 and a second side 6032 oppositely disposed, and connects the end of the first side 6031 and the end of the second side 6032 The first transition edge 6033 of .
  • Both the first side 6031 and the second side 6032 can be curved or straight.
  • a first angle a1 is formed between the first side 6031 and the second side 6032, and the first angle a1 may be 0° to 13°.
  • the first included angle a1 may be 9° to 11°.
  • the first included angle a1 may be 9.5°, 10° or 10.5°.
  • the angle between the two sides is the angle at the intersection point of the extension lines of the two sides; if the first side 6031 and the second side 6032 are both curved, the second side An included angle a1 is the included angle of the tangent line at the intersection of the first side 6031 and the second side 6032 and the same straight line in the first direction. It should be noted that the angle ranges listed in the present disclosure include end values. For example, the first included angle a1 may be 0° to 13°, and the third included angle a3 may be 0° or 13°.
  • the embodiment of the present disclosure shows that the first angle a1 formed between the first side 6031 and the second side 6032 in the substrate can improve the problem of liquid crystal arrangement disorder, enable the liquid crystal arrangement to recover faster, and reduce the Trace of the liquid crystal display substrate.
  • the problem of mura (uneven marks).
  • the first side 6031 forms a second included angle a2 with the first direction, and the second included angle a2 may be 35° to 55°.
  • the second side 6032 forms a third included angle a3 with the first direction, and the third included angle a3 may be 35° to 55°.
  • the second included angle a2 may be the same as the third included angle a3.
  • both the second included angle a2 and the third included angle a3 may be 45°.
  • the second included angle a2 is the included angle between the tangent at an end point of the first side 6031 close to the interior of the pixel and the first direction
  • the third The included angle a3 is the included angle between the tangent line at an end point of the second side 6032 close to the interior of the pixel and the first direction.
  • the angle ranges listed in the present disclosure include end values.
  • the third included angle a3 may be 35° to 55°
  • the third included angle a3 may be 35° or 55°.
  • the first transition edge 6033 is located at the end of the first corner end 603 .
  • the first transition edge 6033 is in the shape of an arc protruding away from the first corner end 603 .
  • the arc-shaped first transition edge 6033 can improve the disorder of liquid crystal arrangement under the action of external force.
  • FIG. 6 is a schematic diagram showing the dimensions of the first corner end of the substrate according to an embodiment of the present disclosure.
  • the length H of the orthographic projection of the first corner end in a direction perpendicular to the first direction is greater than or equal to 3 um and less than or equal to 9 um.
  • examples 1 to 8 of the display substrates of the embodiments of the present disclosure were tested to test the liquid crystal arrangement recovery time and Trace mura (uneven marks) improvement effect of examples 1 to 8. The results are shown in Table 1.
  • FIG. 7 is a partially enlarged view at point b in FIG. 4 .
  • the slit 602 further includes a first body portion 604 extending along a third direction, a second body portion 605 extending along a fourth direction, and the first body portion 604
  • the connection part 606 connected with the second main body part 605 .
  • the connecting portion 606 is V-shaped.
  • the first corner end 603 is located at an end of at least one of the first body portion 604 and the second body portion 605 . Wherein, the first direction, the second direction, the third direction and the fourth direction are all different.
  • the slit 602 includes a first slit 607 , a second slit 608 , and a third slit 609 located between two adjacent second slits 608 .
  • the first corner end 603 of the first slit 607 has a first orthographic projection h1 in a direction perpendicular to the first direction
  • the first corner end 602 of the second slit 608 has a first orthographic projection h1 in a direction perpendicular to the first direction.
  • the first corner end 602 of the third slit 609 has a third orthographic length h3 in a direction perpendicular to the first direction, wherein h3>h2>h1.
  • the first slit 607 has a first width w1
  • the second slit 608 has a second width w2
  • the third slit 609 has a third width w3 .
  • w3>w2 w1.
  • the first width w1 is 5.1 ⁇ 1 ⁇ m
  • the second width w2 is 5.1 ⁇ 1 ⁇ m
  • the third width w3 is 10.8 ⁇ 2 ⁇ m.
  • the inventors of the present disclosure found that, in the related art, the slit in the pixel extends along the second direction, and the extending direction of the slit is different from the extending direction of the data line. Since the slit is formed on the data line near the data line, the slit The climbing at the data line will lead to the Rubbing Shadow area, which needs to be blocked by the BM layer, resulting in a loss of about 3% of the pixel aperture ratio.
  • the embodiment of the present disclosure shows that the orthographic projection of the substrate slit 602 on the substrate 10 does not overlap with the orthographic projection of the data line on the substrate 10 .
  • the slit 602 may extend along the second direction and be arranged parallel to the data line. Avoiding the intersection of the slit 602 and the extending direction of the data line to generate a Rubbing Shadow area, and increasing the pixel aperture ratio.
  • the display substrate of the embodiment of the present disclosure further includes a touch signal line 70 , and the orthographic projection of the touch signal line 70 on the substrate 10 is at least partially located in the third slit on the substrate. 10 in the orthographic projection.
  • the touch signal line 70 passes through the opening area of the pixel 500 .
  • the opening area refers to the light-transmitting area in the pixel 500 except for components such as gate lines, data lines, and thin film transistors.
  • the touch signal line 70 may be connected to the common electrode 40 .
  • the touch signal line 70 can provide a common voltage signal for the common electrode. Receive induction signal.
  • the touch stage when a touch occurs, the finger forms a capacitance with the common electrode, the voltage on the common electrode at the touch position changes, and the touch position is determined by detecting the voltage change on the common electrode.
  • a capacitance is formed between the common electrode and the pixel electrode, and the liquid crystal in the liquid crystal layer (not shown in the figure) is driven to deflect to realize image display.
  • the distance between the edge of the first side of the touch signal line 70 and the edge of the first side of the pixel electrode 60 is the same as the distance between the edge of the second side of the touch signal line 70 and the second side of the pixel electrode 60
  • the edges are at the same distance.
  • the first side of the touch signal line 70 and the first side of the pixel electrode 60 are located on the same side of the display substrate, and the second side of the touch signal line 70 and the second side of the pixel electrode 60 are located on the same side of the display substrate.
  • first side of the touch signal line 70 and the second side of the touch signal line 70 are respectively located on opposite sides of the touch signal line 70 along the first direction, the first side of the pixel electrode 60 and the second side of the pixel electrode 60 The two sides are respectively located on opposite sides of the pixel electrode 60 along the first direction.
  • the inventors of the present disclosure found that when the preparation process of the pixel electrode 60 fluctuates, the pixel electrodes 60 located on both sides of the touch signal line 70 are offset, resulting in inconsistent distances between the two sides of the touch signal line 70 and the pixel electrode 60 , making the touch control
  • the electric fields on both sides of the signal line 70 are asymmetrical, resulting in deviations in left and right transmittance (Trans), and fluctuations in transmittance lead to visually different light and dark, resulting in poor stains.
  • the touch signal line 70 and the data line 400 may be disposed on the same layer, and manufactured from the same material through the same process.
  • a common electrode 40 is disposed between the touch signal line 70 and the pixel electrode 60 .
  • the orthographic projection of the common electrode 40 on the substrate 10 covers the orthographic projection of the touch signal line 70 below the common electrode 40 on the substrate 10 .
  • the common electrode 40 can function as a shielding layer to shield the process fluctuation of the pixel electrode 60 , solve the problem of transmittance fluctuation caused by the asymmetry of the electric field on both sides of the touch signal line 70 , and solve the problem of stains.
  • FIG. 8 is a schematic diagram showing the structure of a light-shielding layer in a substrate according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure shows that the substrate further includes a light-shielding layer 80.
  • the light-shielding layer 80 at least includes at least one first portion 801 extending along the second direction.
  • the first portion 801 is adjacent to
  • the data lines 400 are arranged parallel to the data lines 400 .
  • the light shielding layer 80 can be used to shield the data line 400 from light.
  • the shielding layer 80 may be a conductor having light shielding properties, for example, the shielding layer may be an opaque metal.
  • the opaque metal can be aluminum-based metal, molybdenum-based metal, titanium-based metal, silver-based metal or copper-based metal, etc.
  • the light shielding layer 80 further includes a second portion 802 extending along the first direction, and the second portion 802 is connected to at least one first portion 801 .
  • the second part 802 is connected to the common electrode 40 through the first via hole 90 .
  • At least one first portion 801 is connected to the touch signal line 70 through the second via hole 100 .
  • the light-shielding layer 80 reduces the load of the touch signal line 70 and improves the touch sensitivity of the touch signal line 70 .
  • the light-shielding layer 80 includes two opposite first portions 801 and one second portion 802, one end of the second portion 802 is connected to one of the two opposite first portions 801 The ends are connected, and the other end of the second part 802 is disconnected or connected with the other of the two opposite first parts 801 .
  • the embodiment of the present invention shows that the substrate can realize the connection or disconnection of adjacent common electrodes 40 through the light shielding layer 80 .
  • connecting or disconnecting the first portion 801 of the adjacent light shielding layer 80 can realize the connection or disconnection of the adjacent common electrodes 40 in the first direction; connecting or disconnecting the second portion 802 of the adjacent light shielding layer 80, Connection or disconnection of common electrodes 40 adjacent in the second direction may be achieved.
  • the embodiment of the present invention shows that the distance between the edge of the first side of the pixel electrode 60 and the edge of the first side of the light-shielding layer 80 in the substrate is the same as the distance between the edge of the second side of the pixel electrode 60 and the edge of the second side of the light-shielding layer 80 the same distance.
  • the first side of the pixel electrode 60 and the first side of the light shielding layer 80 are located on the same side of the display substrate, and the second side of the pixel electrode 60 and the second side of the light shielding layer 80 are located on the same side of the display substrate.
  • first side of the pixel electrode 60 and the second side of the pixel electrode 60 are respectively located on opposite sides of the pixel electrode 60 along the first direction
  • first side of the light shielding layer 80 and the second side of the light shielding layer 80 are respectively located in the light shielding layer. 80 along opposite sides of the first direction.
  • Fig. 10 is a second cross-sectional view along A-A' direction in Fig. 2a.
  • the distance from the edge of the first side of the pixel electrode 60 to the edge of the first side of the light shielding layer 80 is different from the distance from the second side of the pixel electrode 60
  • the distances from the edge to the second side edge of the light-shielding layer 80 are different.
  • the distance L1 from the edge of the first side of the pixel electrode 60 to the edge of the first side of the light shielding layer 80 is 0.5 ⁇ m
  • the distance L2 from the edge of the second side of the pixel electrode 60 to the edge of the second side of the light shielding layer 80 is 2.7 ⁇ m.
  • the embodiment of the present invention shows that the distance from the edge of the first side 401 of the common electrode 40 of the substrate to the edge of the first side 804 of the light-shielding layer 80 and the second side of the common electrode 40
  • the distance from the edge 402 to the edge of the second side 805 of the light shielding layer 80 may be the same.
  • the first side 401 of the common electrode 40 and the first side 804 of the light-shielding layer 80 are located on the same side of the display substrate
  • the second side 402 of the common electrode 40 and the second side 805 of the light-shielding layer 80 are located on the same side of the display substrate.
  • first side 401 of the common electrode 40 and the second side 402 of the common electrode 40 are respectively located on opposite sides of the common electrode 40 along the first direction, the first side 804 of the light shielding layer 80 and the second side 805 of the light shielding layer 80 respectively located on opposite sides of the light shielding layer 80 along the first direction.
  • the orthographic projection of the first side 401 of the common electrode 40 on the substrate 10 and the orthographic projection of the first side 804 of the light shielding layer 80 on the substrate 10 may overlap, and the common electrode 40
  • the orthographic projection of the second side 402 on the base 10 and the orthographic projection of the second side 805 of the light shielding layer 80 on the base 10 may overlap.
  • Fig. 2b is a second structural schematic diagram of a pixel in a display substrate according to an embodiment of the present disclosure
  • Fig. 3b is a cross-sectional view along the direction A-A' in Fig. 2b.
  • the embodiment of the present invention shows that the distance from the edge of the first side 401 of the common electrode 40 of the substrate to the edge of the first side 804 of the light shielding layer 80 is the same as the distance from the edge of the second side 402 of the common electrode 40 to the edge of the light shielding layer 80.
  • the distance between the edges of the two sides 805 may be different.
  • first side 401 of the common electrode 40 and the first side 804 of the light-shielding layer 80 are located on the same side of the display substrate, and the second side 402 of the common electrode 40 and the second side 805 of the light-shielding layer 80 are located on the same side of the display substrate.
  • first side 401 of the common electrode 40 and the second side 402 of the common electrode 40 are respectively located on opposite sides of the common electrode 40 along the first direction, the first side 804 of the light shielding layer 80 and the second side 805 of the light shielding layer 80 respectively located on opposite sides of the light shielding layer 80 along the first direction.
  • the orthographic projection of the first side 401 of the common electrode 40 on the substrate 10 and the orthographic projection of the first side 804 of the light shielding layer 80 on the substrate 10 may overlap, and the common electrode 40
  • the orthographic projection of the second side 402 on the base 10 may not overlap with the orthographic projection of the second side 805 of the light shielding layer 80 on the base 10 .
  • the embodiment of the present invention shows that the distance from the edge of the first side of the common electrode to the edge of the first side of the data line of the substrate is the same as the distance from the edge of the second side of the common electrode to the edge of the second side of the data line.
  • the first side of the common electrode and the first side of the data line are located on the same side of the display substrate, and the second side of the common electrode and the second side of the data line are located on the same side of the display substrate.
  • the first side of the common electrode and the second side of the common electrode are respectively located on opposite sides of the common electrode along the first direction, and the first side of the data line and the second side of the data line are respectively located on the opposite sides of the data line along the first direction. opposite sides of the .
  • the embodiment of the present invention shows that the distance from the edge of the first side of the common electrode to the edge of the first side of the pixel electrode is the same as the distance from the edge of the second side of the common electrode to the edge of the second side of the pixel electrode.
  • the first side of the common electrode and the first side of the pixel electrode are located on the same side of the display substrate, and the second side of the common electrode and the second side of the pixel electrode are located on the same side of the display substrate.
  • the first side of the common electrode and the second side of the common electrode are respectively located on opposite sides of the common electrode along the first direction, and the first side of the pixel electrode and the second side of the pixel electrode are respectively located on the data line along the first direction. opposite sides of the .
  • FIG. 9 is a partial cross-sectional view at point c in FIG. 2 .
  • the embodiment of the present invention shows that the substrate further includes a thin film transistor 110, and the thin film transistor 110 includes a gate 120 disposed on the substrate 10; An insulating layer 20; the active layer 130 disposed on the side of the first insulating layer 20 away from the base 10; the source 140 and the drain 150 disposed on the side of the active layer 130 away from the base 10; disposed on the source 140 and the drain
  • the electrode 150 is away from the side of the substrate 10 and covers the second insulating layer 30 of the source electrode 140 and the drain electrode 150; the common electrode 40 is arranged on the side of the second insulating layer 30 away from the substrate 10; the common electrode 40 is arranged on the side away from the substrate 10 And the third insulating layer 50 covering the common electrode 40 ; the pixel electrode 60 disposed on the side of the third insulating layer 50 away from the substrate 10 .
  • the first insulating layer 20 , the second insulating layer 30 and the third insulating layer 50 are provided with via holes communicating with each other to form the third via hole 160 .
  • the third via hole 160 includes a side wall and a bottom wall, the side wall of the third via hole 160 exposes the drain electrode 150 , and the pixel electrode 60 is connected to the drain electrode 150 through the third via hole 160 .
  • Materials of the source 140 and the drain 150 may include aluminum-based metals such as aluminum or aluminum alloys, silver-based metals such as silver or silver alloys, copper-based metals such as copper or copper alloys, molybdenum-based metals such as molybdenum or molybdenum alloys.
  • the gate 120 of the thin film transistor 110 is connected to the gate line, and the gate 120 and the gate line may be arranged in the same layer and manufactured by using the same material through the same process.
  • the material of the gate 120 may include aluminum-based metals such as aluminum or aluminum alloys, silver-based metals such as silver or silver alloys, copper-based metals such as copper or copper alloys, molybdenum-based metals such as molybdenum or molybdenum alloys.
  • the source electrode 140 of the thin film transistor 110 is connected to the data line, and the source electrode 140 and the data line may be arranged on the same layer and manufactured from the same material through the same process.
  • the technical solution of this embodiment will be further described below by showing the preparation process of the substrate in this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which is a mature preparation process in related technologies.
  • the "photolithography process” mentioned in this embodiment includes film coating, mask exposure and development, which is a mature preparation process in the related art.
  • Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition
  • coating can use known coating processes
  • etching can use known methods, which are not specifically limited here.
  • a “thin film” refers to a thin film produced by depositing or coating a certain material on a substrate. If the "thin film” does not require a patterning process or a photolithography process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” still needs a patterning process or a photolithography process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the "layer” after patterning or photolithography includes at least one "pattern”.
  • a gate pattern is formed on a substrate.
  • Forming the gate pattern on the substrate includes: firstly depositing a buffer film on the substrate 10 to form a buffer layer pattern covering the entire substrate 10 .
  • the first metal film, the light-shielding material layer and the first insulating film are sequentially deposited, and the first metal film is patterned by a patterning process to form the gate 120 and the gate line arranged on the buffer layer (not shown in FIG. 9 ).
  • the light-shielding material layer is patterned by a patterning process to form a light-shielding layer (not shown in FIG.
  • the first insulating layer 20 of the line and the light-shielding layer is shown in FIG. 9 .
  • the material of the gate 120 may include multiple layers of stacked metal.
  • the material of the gate 120 may be a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer stacked in sequence, the thickness of the first molybdenum metal layer may be 150 angstroms, and the thickness of the aluminum metal layer may be 3000 angstroms. , the thickness of the second molybdenum metal layer may be 800 angstroms.
  • the material of the first insulating layer 20 may be SiNx, and the thickness of the first insulating layer 20 may be 4000 angstroms.
  • Forming the active layer pattern includes: depositing an active layer thin film on the first insulating layer 20 on the substrate 10 forming the above structure, and patterning the active layer thin film through a patterning process to form the active layer thin film disposed on the first insulating layer 20.
  • the pattern of the active layer 130 is as shown in FIG. 9 . Wherein, the thickness of the active layer 130 may be 1700 angstroms.
  • Form patterns of source electrodes, drain electrodes, data lines and touch signal lines includes: on the substrate 10 forming the above-mentioned structure, depositing a second metal film and a second insulating film in sequence on the active layer 130, patterning the second metal film through a patterning process, Form source 140, drain 150, data lines (not shown in FIG. 9 ) and touch signal lines (not shown in FIG. 9 ) patterns, wherein both source 140 and drain 150 are connected to active layer 130 .
  • the second insulating film is patterned by a patterning process, so that the second insulating film forms the second insulating layer 30 covering the source electrode 140, the drain electrode 150, the data line and the touch signal line, and a first insulating layer is opened in the second insulating layer 30.
  • the first opening includes a side wall and a bottom wall, and the side wall of the first opening exposes the drain electrode 150 , as shown in FIG. 9 .
  • the material of the source electrode 140 and the drain electrode 150 may include a multi-layer stacked metal.
  • the material of the source electrode 140 and the drain electrode 150 can be a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer stacked in sequence, the thickness of the first molybdenum metal layer can be 150 angstroms, and the thickness of the aluminum metal layer It may be 3000 angstroms, and the thickness of the second molybdenum metal layer may be 800 angstroms.
  • the material of the second insulating layer 30 may be SiNx, and the thickness of the second insulating layer 30 may be 2500 angstroms.
  • Forming the common electrode pattern includes: on the substrate 10 forming the above structure, depositing a third metal film and a third insulating film in sequence on the second insulating layer 30, patterning the third metal film through a patterning process, forming The common electrode 40 pattern on the insulating layer 30; the common electrode 40 is connected to the light-shielding layer through the first via hole, and the common electrode 40 is connected to the touch signal line through the second via hole; the third insulating film is patterned by a patterning process to form The third insulating layer 50 covering the common electrode 40 is provided with a second opening on the third insulating layer 50, the second opening communicates with the first opening to form a third via hole 160, and the third via hole 160 exposes the drain electrode 150, As shown in Figure 9. Wherein, the material of the common electrode 40 may be ITO, and the thickness of the common electrode 40 may be 700 angstroms.
  • Forming the pixel electrode pattern includes: depositing a fourth metal thin film on the third insulating layer 50 on the substrate 10 with the above-mentioned structure, and patterning the fourth metal thin film through a patterning process to form a pixel disposed on the third insulating layer 50
  • the pattern of the electrode 60 ; the pixel electrode 60 is connected to the drain 150 through the third via hole 160 .
  • the material of the pixel electrode 60 may be ITO, and the thickness of the pixel electrode 60 may be 700 angstroms.
  • the pixel electrode 60 includes at least two strip electrodes 601, and there is a slit 602 between adjacent strip electrodes 601 in the at least two strip electrodes 601, and the slit 602 includes at least a first The corner end 603 , the first corner end 603 includes a first side 6031 , a second side 6032 opposite to each other, and a first transition side 6033 connecting the end of the first side 6031 and the end of the second side 6032 . Both the first side 6031 and the second side 6032 can be curved or straight.
  • a first angle a1 is formed between the first side 6031 and the second side 6032, and the first angle a1 may be 0° to 13°.
  • the first included angle a1 may be 9° to 11°.
  • the first included angle a1 may be 9.5°, 10° or 10.5°.
  • FIG. 11 is a cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in FIG. 11 , an embodiment of the present disclosure also provides a display device.
  • the display device may include the aforementioned display substrate 1 , the opposite substrate 2 , and a liquid crystal disposed between the display substrate 1 and the opposite substrate 2 . Layer 3. Wherein, the display substrate 1 may be the aforementioned display substrate.
  • the liquid crystal layer 3 may include a plurality of liquid crystal molecules having dielectric anisotropy. An electric field is formed between the display substrate 1 and the opposite substrate 2, so that the liquid crystal molecules can rotate between the display substrate 1 and the opposite substrate 2 in a predetermined direction, thereby allowing or blocking the transmission of light.
  • the display device of the embodiment of the present disclosure further includes a black matrix 4 , and the black matrix 4 is disposed on the display substrate 1 side of the counter substrate 2 .
  • the black matrix 4 covers at least part of the data lines 400 and the light-shielding layer 80 in the display substrate 1 through the positive projection of the base 10 in the display substrate 1 , and the black matrix 4 is used to block the data lines 400 from light.
  • the central axis of the orthographic projection of the black matrix 4 on the base 10 in the display substrate 1 overlaps with the central axis of the orthographic projection of the common electrode 40 in the display substrate 1 on the base 10 in the display substrate 1 .
  • the central axis of the orthographic projection of the base 10 of the black matrix 4 in the display substrate 1 is the central axis extending in a direction perpendicular to the first direction; The direction extends perpendicular to the central axis.
  • An embodiment of the present disclosure also provides a method for preparing a display substrate, including:
  • a pixel electrode is formed on one side of the substrate; wherein, the pixel electrode includes at least two strip-shaped electrodes, and there is a slit between adjacent strip-shaped electrodes in the at least two strip-shaped electrodes, and the slit It includes at least a first corner end located at at least one end of the slit, the first corner end includes a first side and a second side that are oppositely arranged, and the end of the first side is connected to the second side of the second side.
  • a first transition edge connected at the ends, the first transition edge is in the shape of an arc protruding away from the first corner end; a first angle is formed between the first edge and the second edge, The first included angle is 0° to 13°.
  • FIG. 12 is a schematic structural diagram of a mask according to an embodiment of the present disclosure
  • FIG. 13 is an enlarged view at point d in FIG. 12
  • the embodiment of the present disclosure also provides a mask, including a pattern area 1000 and a non-pattern area 1100 surrounding the pattern area 1000.
  • the pattern area 1000 includes at least one mask pattern 1200.
  • the film patterns 1200 are periodically distributed in the pattern area 1000 .
  • the mask pattern 1200 is an opening structure, and the mask pattern 1200 allows the light emitted by the exposure light source to pass through.
  • the non-pattern area 1100 is completely closed without openings, and the non-pattern area 1100 does not allow the light emitted by the exposure light source to pass through.
  • the mask pattern 1200 at least includes a second corner end 1300 located at at least one end of the mask pattern 1200, the second corner end 1300 includes a third side 1400 and a fourth side 1500 oppositely arranged, and the end of the third side 1400 is connected to the second side.
  • the ends of the four sides 1500 are connected to the second transition side 1600, the second transition side 1600 is in the shape of a circular arc protruding away from the second corner end 1300; the third side 1400 and/or the fourth side 1500 are straight lines, A fifth included angle is formed between the third side 1400 and the fourth side 1500, and the fifth included angle is greater than or equal to 0° and less than or equal to 5°.
  • the fourth side 1500 forms a fourth angle a4 with the first direction, and the fourth angle a4 may be 35° to 55°.
  • the third side 1400 forms a fifth included angle a5 with the first direction, and the fifth included angle a5 may be 35° to 55°.
  • the fifth included angle a5 may be the same as the fourth included angle a4.
  • both the fifth included angle a5 and the fourth included angle a4 may be 45°.
  • the angle ranges listed in the present disclosure include end values.
  • the fifth included angle a5 may be 35° to 55°
  • the fifth included angle a5 may be 35° or 55°.
  • the length H' of the orthographic projection of the second corner end 1300 in a direction perpendicular to the first direction is greater than or equal to 3um and less than or equal to 9um.
  • the mask pattern 1200 includes a first pattern 1201 , a second pattern 1202 and a third pattern 1203 located between two adjacent second patterns 1202 .
  • the second corner end 1300 of the first pattern 1201 has a first orthographic projection h'1 in a direction perpendicular to the first direction
  • the second corner end 1300 of the second pattern 1202 has a first orthographic projection h'1 in a direction perpendicular to the first direction.
  • the second orthographic length h'2 on , the second corner end 1300 of the third pattern 1203 has a third orthographic length h'3 in the direction perpendicular to the first direction, wherein h'3>h '2>h'1.
  • the first pattern 1201 has a first width w'1
  • the second pattern 1202 has a second width w'2
  • the third pattern 1203 has a third width w'3.
  • w'3>w'2 w'1.
  • the first width w'1 is 5.1 ⁇ 1 ⁇ m
  • the second width w'2 is 5.1 ⁇ 1 ⁇ m
  • the third width w'3 is 10.8 ⁇ 2 ⁇ m.
  • the mask plate of the embodiment of the present disclosure may be applied to form the pixel electrode in the display substrate of the embodiment of the present disclosure.

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Abstract

一种显示基板及其制备方法、显示装置、掩膜版，该显示基板包括基底以及设置在所述基底一侧的像素电极；所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为大于等于0°小于等于13°。

Description

显示基板及其制备方法、显示装置、掩膜版 技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及显示基板及其制备方法、显示装置、掩膜版。
背景技术
液晶显示面板作为目前主流的显示屏，具有耗电量低、体积小、辐射低等优势。
目前常用水平电场模式的液晶显示面板包括平面转换(In-Plane Switching，简称IPS)模式液晶显示面板及高级超维场转换(Advanced Super Dimension Switch，简称ADS)模式液晶显示面板。
其中，ADS型显示模式由于其宽视角，高分辨率、低功耗等特点广泛应用于显示领域。目前大尺寸及超大尺寸显示装置为了达到高透过率的效果，将像素电极覆盖到数据信号线的范围之内。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括基底以及设置在所述基底一侧的像素电极；所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为大于等于0°小于等于13°。
在示例性实施方式中，所述第一夹角为9°至11°。
在示例性实施方式中，所述第一夹角为9.5°、10°或10.5°。
在示例性实施方式中，还包括，设置在所述基底靠近所述像素电极一侧且沿着第一方向延伸的栅线；设置于所述栅线远离所述基底一侧的第一绝缘层；设置于所述第一绝缘层远离所述基底一侧且沿着第二方向延伸的数据线；设置于所述数据线远离所述基底一侧的第二绝缘层；设置于所述第二绝缘层远离所述基底一侧的公共电极；以设置于所述公共电极远离所述基底一侧的第三绝缘层；所述像素电极设置于所述第三绝缘层远离所述基底一侧；所述第一方向与所述第二方向不同。
在示例性实施方式中，还包括设置在所述基底靠近所述像素电极一侧且沿着第一方向延伸的栅线，所述第一边与所述第一方向形成第二夹角，所述第二夹角为40°至50°；和/或，所述第二边与所述第一方向形成第三夹角，所述第三夹角为40°至50°。
在示例性实施方式中，所述第二夹角与所述第三夹角相同。
在示例性实施方式中，所述第一拐角端在与所述第一方向相垂直的方向上的正投影长度H为大于等于3um小于等于9um。
在示例性实施方式中，所述狭缝还包括沿着第三方向延伸的第一主体部、沿着第四方向延伸的第二主体部；以及将所述第一主体部和所述第二主体部连接的连接部，所述连接部为V字形，所述第三方向与所述第四方向不相同。
在示例性实施方式中，所述狭缝包括第一狭缝、第二狭缝以及位于所述第一狭缝、所述第二狭缝之间的第三狭缝，所述第三狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度大于所述第二狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度，所述第二狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度大于所述第一狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度。
在示例性实施方式中，所述第三狭缝的宽度大于所述第二狭缝的宽度；和/或，所述第三狭缝的宽度大于所述第一狭缝的宽度；和/或，所述第一狭缝的宽度等于所述第二狭缝的宽度。
在示例性实施方式中，还包括触控信号线，所述触控信号线在所述基底 的正投影至少部分位于所述第三狭缝在所述基底的正投影中。
在示例性实施方式中，所述狭缝在所述基底的正投影与所述数据线在所述基底的正投影不交叠。
在示例性实施方式中，还包括触控信号线，所述触控信号线与所述数据线同层设置。
在示例性实施方式中，所述触控信号线第一侧边缘至所述像素电极第一侧边缘的距离与所述触控信号线第二侧边缘至所述像素电极第二侧边缘的距离相同。
在示例性实施方式中，还包括遮挡层，所述遮挡层至少包括沿着第二方向延伸的至少一个第一部分。
在示例性实施方式中，所述遮挡层还包括沿着第一方向延伸的第二部分，所述第二部分与所述至少一个第一部分连接。
在示例性实施方式中，还包括触控信号线，所述第二部分通过第一过孔与所述公共电极连接，所述至少一个第一部分通过第二过孔与所述触控信号线连接。
在示例性实施方式中，所述遮光层包括两个相对设置的第一部分以及一个第二部分，第二部分的一端与两个相对设置的第一部分中的一个端部连接，第二部分的另一端与两个相对设置的第一部分中的另一个断开或连接。
在示例性实施方式中，所述公共电极第一侧的边缘至所述遮光层第一侧边缘的距离与所述公共电极第二侧边缘至所述遮光层第二侧边缘的距离相同；和/或，所述公共电极第一侧边缘至所述数据线第一侧边缘的距离与所述公共电极第二侧边缘至所述数据线第二侧边缘的距离相同；和/或，所述公共电极第一侧边缘至所述像素电极第一侧边缘的距离与所述公共电极第二侧边缘至所述像素电极第二侧边缘的距离相同。
在示例性实施方式中，所述像素电极第一侧的边缘至所述遮光层第一侧的边缘的距离与所述像素电极第二侧的边缘至所述遮光层第二侧边缘的距离相同；或者，所述像素电极第一侧的边缘至所述遮光层第一侧的边缘的距离与所述像素电极第二侧的边缘至所述遮光层第二侧边缘的距离不相同。
第二方面，本公开实施例还提供了一种显示装置，包括前述的显示基板。
第三方面，本公开实施例还提供了一种显示基板的制备方法，包括：
在所述基底的一侧形成像素电极；其中，所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为0°至13°。
第四方面，本公开实施例还提供了一种掩膜版，包括图案区，所述图案区包括至少一个掩膜图案，所述掩膜图案至少包括位于所述掩膜图案至少一端的第二拐角端，所述第二拐角端包括相对设置的第三边、第四边，以及将所述第三边的端部和所述第四边的端部连接的第二过渡边，所述第二过渡边为沿着远离所述第二拐角端方向凸出的圆弧状；所述第三边和/或所述第四边为直线状，所述第三边与所述第四边之间形成第五夹角，所述第五夹角为0°至5°。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为本公开实施例显示基板的结构示意图；
图2a为本公开实施例显示基板中像素的结构示意图一；
图2b为本公开实施例显示基板中像素的结构示意图二；
图3a为图2a中A-A’方向的剖视图一；
图3b为图2b中A-A’方向的剖视图；
图4为本公开实施例显示基板中像素电极的结构示意图；
图5为图4中a处的局部放大图；
图6为本公开实施例显示基板中第一拐角端的尺寸示意图；
图7为图4中b处的局部放大图；
图8为本公开实施例显示基板中遮光层的结构示意图；
图9为图2a中c处的局部剖视图；
图10为图2a中A-A’方向的剖视图二。
图11为本公开实施例显示装置的剖视图；
图12为本公开实施例掩膜版的结构示意图；
图13为图12中d处的放大图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为本公开实施例显示基板的结构示意图。如图1所示，本公开实施例的显示基板可以包括用于显示图像的显示区域100以及设置于显示区域100周边的外围区域200。本公开实施例显示基板的显示区域100可以包括多个栅线300、多个数据线400；以及与多个栅线300和多个数据线400连接的像素500。栅线300用于传送栅极电信号，数据线400用于传送数据电信号。多个栅线300沿着第一方向(例如水平方向)延伸，且多个栅线300可以彼此平行。多个数据线400沿着第二方向(例如垂直方向)延伸，且多个数据线400可以彼此平行。其中，第一方向与第二方向不同。比如，第一方向与第二方向垂直。
如图1所示，像素500可以包括薄膜晶体管(TFT)、像素电极以及公共电极，像素电极与薄膜晶体管(TFT)的漏电极连接，多个数据线400中的至少一个与薄膜晶体管(TFT)的源电极连接，多个栅线300中的至少一个与薄膜晶体管(TFT)的栅极连接。薄膜晶体管可以通过由与其连接的栅线300施加的栅极电信号而导通或截止，并可以由与其连接的数据线400提供的数据电信号传送到像素电极。像素500可以根据施加到像素电极的数据电信号显示图像。
如图1所示，外围区域200可以是显示基板不显示图像的非显示区域的一部分。外围区域200可以围绕显示区域100的四周设置；或者，外围区域200可以沿着显示基板的侧部延伸设置。
如图1所示，显示区域100中的栅线300和数据线400可以部分延伸到外围区域200。外围区域200可以包括公共电压线(图中未示出)。公共电压线与显示区域100中的公共电极连接，用于传送公共电压Vcom到显示区域100中的公共电极。
图2a为本公开实施例显示基板中像素的结构示意图一。图3a为图2a中A-A’方向的剖视图一。如图2和图3所示，本公开实施例显示基板可以是TFT阵列基板。本公开实施例显示基板可以包括基底10、在基底10的一侧且沿着第一方向延伸的栅线300；设置于栅线300远离基底10一侧、且覆盖栅线300的第一绝缘层20；设置于第一绝缘层20远离基底10一侧且沿着第二方向延伸的数据线400；设置于数据线400远离基底10一侧、且覆盖数据 线400的第二绝缘层30；设置于第二绝缘层30远离基底10一侧的公共电极40；设置于公共电极40远离基底10一侧且覆盖公共电极40的第三绝缘层50；设置于第三绝缘层50远离基底10一侧的像素电极60。其中，第一方向与第二方向不同。比如，第一方向与第二方向垂直。
在示例性实施方式中，基底10可以是绝缘基底。例如，基底10可以包括玻璃基底、石英基底或树脂基底等。
在示例性实施方式中，栅线300可以与薄膜晶体管的栅极(后面将描述)同层设置，采用相同的材料通过同一工艺制备而成。在一些实施例中，栅线300可以与栅极一体形成。栅线300可以在基底10的第一方向(例如水平方向)延伸，并且可以与薄膜晶体管的栅极连接。栅线300的材料可以包括铝基金属诸如铝或铝合金、银基金属诸如银或银合金、铜基金属诸如铜或铜合金、钼基金属诸如钼或钼合金等金属。
在示例性实施方式中，第一绝缘层20可以为栅绝缘层，覆盖栅线300和薄膜晶体管的栅极。第一绝缘层20的材料可以包括氧化硅或氮化硅等。
在示例性实施方式中，数据线400可以与薄膜晶体管的源级(后面将描述)同层设置，采用相同的材料通过同一工艺制备而成。数据线400可以在基底10的第二方向(例如垂直方向)延伸，并且可以与薄膜晶体管的源极连接。数据线400可以与栅线300交叉设置，限定多个像素区域，每个像素区域对应一个像素。
在示例性实施方式中，数据线400可以不完全沿着第二方向延伸。例如，数据线400可以具有弯折部分，数据线400的延伸方向可以偏离第二方向，但是可以将数据线400整体看作沿着第二方向延伸。
在示例性实施方式中，第二绝缘层30覆盖数据线400以及薄膜晶体管中的源级和漏极。第二绝缘层30的材料可以包括氧化硅或氮化硅等。
在示例性实施方式中，多个公共电极40对应于多个像素区域的多个公共电极40。公共电极40可以在基底10的正投影与数据线400在基底10的正投影不交叠。公共电极40的材料可以为透明导电材料。例如，公共电极40的材料可以为ITO、IZO、铟锡锌氧化物(ITZO)或者铝掺杂的锌氧化物(AZO)。
在示例性实施方式中，第三绝缘层50覆盖公共电极40。第三绝缘层50的材料可以包括氧化硅或氮化硅等。
在示例性实施方式中，像素电极60可以与薄膜晶体管的漏级(后面将描述)连接。像素电极60可以在基底10的正投影与数据线400在基底10的正投影不交叠。像素电极60的材料可以为透明导电材料。例如，像素电极60的材料可以为ITO、IZO、铟锡锌氧化物(ITZO)或者铝掺杂的锌氧化物(AZO)。
在示例性实施方式中，如图2所示，本公开实施例显示基板中像素电极60包括至少两个条状电极601，至少两个条状电极601中相邻的条状电极601之间具有狭缝602，狭缝602至少包括位于狭缝602至少一端的第一拐角端603。本公开实施例显示基板中的第一拐角端603能够减小液晶显示基板Trace mura(痕迹不均)的问题。需要说明的是，本公开的拐角端以拐角端的弯折方向和狭缝中部的弯折方向相同为例描述的，如图2所示拐角端向右弯折；实际产品可以采用拐角端的弯折方向和狭缝中部的弯折方向不相同，或者，位于同一狭缝两端的拐角端的弯折方向不相同。
本公开的发明人发现，显示基板中像素电极的第一拐角端603会造成像素电极60末端区域的液晶在手指按压作用下排布絮乱，产生划痕拖尾、恢复时间慢等问题。
图4为本公开实施例显示基板中像素电极的结构示意图。图5为图4中a处的局部放大图。在示例性实施方式中，如图4和图5所示，本公开实施例显示基板中像素电极60的第一拐角端603的末端为沿着远离第一拐角端603方向凸出的弧状。本公开实施例显示基板中第一拐角端603弧状的末端在外力作用下，能够改善液晶排布紊乱的问题，使液晶排布能够更快的恢复，减小液晶显示基板Trace mura(痕迹不均)的问题。
在示例性实施方式中，如图5所示，第一拐角端603包括相对设置的第一边6031、第二边6032，以及将第一边6031的端部和第二边6032的端部连接的第一过渡边6033。第一边6031和第二边6032均可以为曲线状或直线状。第一边6031和第二边6032之间形成第一夹角a1，第一夹角a1可以为0°至13°。示例的，第一夹角a1可以为9°至11°。例如，第一夹角a1可以为9.5°、10°或10.5°。需要说明的是，如果两条边不存在交叉，则两条边的 夹角为两条边延长线交叉点处的夹角；如果第一边6031和第二边6032均为曲线状时，第一夹角a1为第一边6031和第二边6032与第一方向上同一直线交叉点处的切线的夹角。需要说明的是，本公开所列举的角度范围包括端值，例如第一夹角a1的角度可以为0°至13°，则第三夹角a3可以为0°或13°。
本公开实施例显示基板中第一边6031和第二边6032之间形成的第一夹角a1能够改善液晶排布紊乱的问题，使液晶排布能够更快的恢复，减小液晶显示基板Trace mura(痕迹不均)的问题。
在示例性实施方式中，如图5所示，第一边6031与第一方向形成第二夹角a2，第二夹角a2的角度可以为35°至55°。第二边6032与第一方向形成第三夹角a3，第三夹角a3的角度可以为35°至55°。其中，第二夹角a2可以与第三夹角a3相同。比如，第二夹角a2可以与第三夹角a3均为45°。需要说明的是，如果第一边6031和第二边6032均为曲线状时，第二夹角a2为第一边6031靠近像素内部的一端点处的切线和第一方向的夹角，第三夹角a3为第二边6032靠近像素内部的一端点处的切线和第一方向的夹角。需要说明的是，本公开所列举的角度范围包括端值，例如第三夹角a3的角度可以为35°至55°，则第三夹角a3可以为35°或55°。
在示例性实施方式中，如图5所示，第一过渡边6033位于第一拐角端603的末端。第一过渡边6033为沿着远离第一拐角端603方向凸出的弧状。该弧状第一过渡边6033能够在外力作用下改善液晶排布紊乱的问题。
图6为本公开实施例显示基板中第一拐角端的尺寸示意图。在示例性实施方式中，如图6所示，第一拐角端在与第一方向相垂直的方向上的正投影长度H为大于等于3um小于等于9um。
在外力作用下，对本公开实施例显示基板的示例1至示例8进行测试，以测试示例1至示例8液晶排布恢复时间以及Trace mura(痕迹不均)改善效果，结果如表1所示。
表1本公开实施例显示基板的测试结果
Figure PCTCN2021100959-appb-000001
Figure PCTCN2021100959-appb-000002
由表1可知，当第一拐角端在与第一方向相垂直的方向上的正投影长度H为6um，第二夹角a2与第三夹角a3相同，且第二夹角a2与第三夹角a3均为45度时，在外力作用下，液晶排布恢复时间最短，Trace mura(痕迹不均)改善效果最佳。其中，Trace mura(痕迹不均)改善效果5星为最佳，1星为最差。
图7为图4中b处的局部放大图。在示例性实施方式中，如图7所示，狭缝602还包括沿着第三方向延伸的第一主体部604、沿着第四方向延伸的第二主体部605以及将第一主体部604和第二主体部605连接的连接部606。连接部606为V字形。第一拐角端603位于第一主体部604和第二主体部605中至少一个的端部。其中，第一方向、第二方向、第三方向和第四方向均不相同。
在示例性实施方式中，如图4所示，狭缝602包括第一狭缝607、第二狭缝608以及位于相邻两个第二狭缝608之间的第三狭缝609。第一狭缝607的第一拐角端603具有在与第一方向相垂直的方向上的第一正投影h1，第二狭缝608的第一拐角端602具有在与第一方向相垂直的方向上的第二正投影长度h2，第三狭缝609的第一拐角端602具有在与第一方向相垂直的方向上的第三正投影长度为h3，其中，h3>h2>h1。
在示例性实施方式中，如图4所示，第一狭缝607具有第一宽度w1，第二狭缝608具有第二宽度w2，第三狭缝609具有第三宽度w3。其中，w3>w2＝w1。例如，第一宽度w1为5.1±1μm；第二宽度w2为5.1±1μm；第三宽度w3为10.8±2μm。
本公开发明人发现，在相关技术中，像素中的狭缝沿着第二方向延伸，狭缝的延伸方向与数据线的延伸方向不同，在数据线附近由于狭缝形成于数 据线上，狭缝在数据线处的爬坡会导致Rubbing Shadow区域，需要使用BM层来遮挡，使得像素开口率损失3％左右。
在示例性实施方式中，本公开实施例显示基板的狭缝602在基底10的正投影与数据线在基底10的正投影不交叠。例如，狭缝602可以沿着第二方向延伸，与数据线平行设置。避免狭缝602与数据线延伸方向交叉产生Rubbing Shadow区域，增大像素开口率。
在示例性实施方式中，如图2和图3所示，本公开实施例显示基板还包括触控信号线70，触控信号线70在基底10的正投影至少部分位于第三狭缝在基底10的正投影中。触控信号线70穿过像素500的开口区域。所述开口区域是指像素500中除栅线、数据线、薄膜晶体管等部件之外的透光区域。
在示例性实施方式中，触控信号线70可以与公共电极40连接。在显示阶段，触控信号线70可以为公共电极提供公共电压信号，在触控阶段，公共电极作为触控电极，触控信号线70为触控电极(即公共电极)提供触控驱动信号并接收感应信号。具体的，在触控阶段，发生触控时，手指与公共电极形成电容，触控位置处的公共电极上的电压发生变化，通过检测公共电极上的电压变化确定触控位置。在显示阶段，公共电极与像素电极之间形成电容，驱动液晶层(图中未示出)中液晶发生偏转，实现图像显示。
在示例性实施方式中，如图3所示，触控信号线70第一侧的边缘至像素电极60第一侧边缘的距离与触控信号线70第二侧边缘至像素电极60第二侧边缘的距离相同。其中，触控信号线70的第一侧与像素电极60的第一侧位于显示基板的同侧，触控信号线70的第二侧与像素电极60的第二侧位于显示基板的同侧。且触控信号线70的第一侧和触控信号线70的第二侧分别位于触控信号线70沿着第一方向的相对两侧，像素电极60的第一侧和像素电极60的第二侧分别位于像素电极60沿着第一方向的相对两侧。
本公开发明人发现，当像素电极60的制备工艺波动时，位于触控信号线70两侧的像素电极60偏移，导致触控信号线70两侧与像素电极60的距离不一致，使触控信号线70两侧电场不对称，导致左右透过率(Trans)偏差，透过率波动导致视觉上亮暗不一，从而导致污渍不良。
在示例性实施方式中，如图3所示，触控信号线70可以与数据线400 同层设置，采用相同的材料通过同一工艺制备而成。触控信号线70与像素电极60之间设置有公共电极40。公共电极40在基底10的正投影覆盖公共电极40下方触控信号线70在基底10的正投影。公共电极40可以起到屏蔽层的作用，屏蔽像素电极60工艺波动，解决触控信号线70两侧电场不对称引起的透过率波动的问题，解决污渍的不良。
图8为本公开实施例显示基板中遮光层的结构示意图。在示例性实施方式中，如图3和图8所示，本公开实施例显示基板还包括遮光层80，遮光层80至少包括沿着第二方向延伸的至少一个第一部分801，第一部分801紧邻数据线400并与数据线400平行排布。遮光层80能够用于对数据线400进行挡光。
在示例性实施方式中，遮挡层80可以为具有光屏蔽性能的导体，例如，遮挡层可以为不透明金属。不透明金属可以为铝基金属、钼基金属、钛基金属、银基金属或铜基金属等。
在示例性实施方式中，如图3和图8所示，遮光层80还包括沿着第一方向延伸的第二部分802，第二部分802与至少一个第一部分801连接。第二部分802通过第一过孔90与公共电极40连接。至少一个第一部分801通过第二过孔100与触控信号线70连接。遮光层80减小触控信号线70的负载，提升触控信号线70的触控灵敏度。
在示例性实施方式中，如图8所示，遮光层80包括两个相对设置的第一部分801以及一个第二部分802，第二部分802的一端与两个相对设置的第一部分801中的一个端部连接，第二部分802的另一端与两个相对设置的第一部分801中的另一个断开或连接。
在示例性实施方式中，本发明实施例显示基板可以通过遮光层80实现相邻公共电极40的连接或断开。例如，将相邻遮光层80的第一部分801连接或断开，可以实现第一方向相邻的公共电极40的连接或断开；将相邻遮光层80的第二部分802连接或断开，可以实现第二方向相邻的公共电极40的连接或断开。
在示例性实施方式中，本发明实施例显示基板中像素电极60第一侧的边缘至遮光层80第一侧的边缘的距离与像素电极60第二侧的边缘至遮光层80 第二侧边缘的距离相同。其中，像素电极60的第一侧与遮光层80的第一侧位于显示基板的同侧，像素电极60的第二侧与遮光层80的第二侧位于显示基板的同侧。且像素电极60的第一侧和像素电极60的第二侧分别位于像素电极60沿着第一方向的相对两侧，遮光层80的第一侧和遮光层80的第二侧分别位于遮光层80沿着第一方向的相对两侧。
图10为图2a中A-A’方向的剖视图二。在示例性实施方式中，如图10所示，当像素电极60的制备工艺波动时，像素电极60第一侧的边缘至遮光层80第一侧的边缘的距离与像素电极60第二侧的边缘至遮光层80第二侧边缘的距离不相同。例如，像素电极60第一侧的边缘至遮光层80第一侧的边缘的距离L1为0.5μm，像素电极60第二侧的边缘至遮光层80第二侧的边缘的距离L2为2.7μm。
在示例性实施方式中，如图2a和图3a所示，本发明实施例显示基板的公共电极40第一侧401的边缘至遮光层80第一侧804边缘的距离与公共电极40第二侧402边缘至遮光层80第二侧805边缘的距离可以相同。其中，公共电极40的第一侧401与遮光层80的第一侧804位于显示基板的同侧，公共电极40的第二侧402与遮光层80的第二侧805位于显示基板的同侧。且公共电极40的第一侧401和公共电极40的第二侧402分别位于公共电极40沿着第一方向的相对两侧，遮光层80的第一侧804和遮光层80的第二侧805分别位于遮光层80沿着第一方向的相对两侧。
在示例性实施方式中，如图2a和图3a所示，公共电极40第一侧401在基底10的正投影与遮光层80第一侧804在基底10的正投影可以交叠，公共电极40第二侧402在基底10的正投影与遮光层80第二侧805在基底10的正投影可以交叠。
图2b为本公开实施例显示基板中像素的结构示意图二；图3b为图2b中A-A’方向的剖视图。如图2b和图3b所示，本发明实施例显示基板的公共电极40第一侧401的边缘至遮光层80第一侧804边缘的距离与公共电极40第二侧402边缘至遮光层80第二侧805边缘的距离可以不相同。其中，公共电极40的第一侧401与遮光层80的第一侧804位于显示基板的同侧，公共电极40的第二侧402与遮光层80的第二侧805位于显示基板的同侧。 且公共电极40的第一侧401和公共电极40的第二侧402分别位于公共电极40沿着第一方向的相对两侧，遮光层80的第一侧804和遮光层80的第二侧805分别位于遮光层80沿着第一方向的相对两侧。
在示例性实施方式中，如图2b和图3b所示，公共电极40第一侧401在基底10的正投影与遮光层80第一侧804在基底10的正投影可以交叠，公共电极40第二侧402在基底10的正投影与遮光层80第二侧805在基底10的正投影可以不交叠。
在示例性实施方式中，本发明实施例显示基板的公共电极第一侧的边缘至数据线第一侧边缘的距离与公共电极第二侧的边缘至数据线第二侧边缘的距离相同。其中，公共电极的第一侧与数据线的第一侧位于显示基板的同侧，公共电极的第二侧与数据线的第二侧位于显示基板的同侧。且公共电极的第一侧和公共电极的第二侧分别位于公共电极沿着第一方向的相对两侧，数据线的第一侧和数据线的第二侧分别位于数据线沿着第一方向的相对两侧。
在示例性实施方式中，本发明实施例显示基板的公共电极第一侧的边缘至像素电极第一侧边缘的距离与公共电极第二侧的边缘至像素电极第二侧边缘的距离相同。其中，公共电极的第一侧与像素电极的第一侧位于显示基板的同侧，公共电极的第二侧与像素电极的第二侧位于显示基板的同侧。且公共电极的第一侧和公共电极的第二侧分别位于公共电极沿着第一方向的相对两侧，像素电极的第一侧和像素电极的第二侧分别位于数据线沿着第一方向的相对两侧。
图9为图2中c处的局部剖视图。在示例性实施方式中，本发明实施例显示基板还包括薄膜晶体管110，薄膜晶体管110包括设置于基底10上的栅极120；设置于栅极120远离基底10一侧并覆盖栅极120的第一绝缘层20；设置于第一绝缘层20远离基底10一侧的有源层130；设置于有源层130远离基底10一侧的源极140和漏极150；设置于源极140和漏极150远离基底10一侧并覆盖源极140和漏极150的第二绝缘层30；设置于第二绝缘层30远离基底10一侧的公共电极40；设置于公共电极40远离基底10一侧且覆盖公共电极40的第三绝缘层50；设置于第三绝缘层50远离基底10一侧的像素电极60。其中，第一绝缘层20、第二绝缘层30以及第三绝缘层50开设 有互相连通的过孔，形成第三过孔160。第三过孔160包括侧壁以及底壁，第三过孔160的侧壁暴露漏极150，像素电极60通过第三过孔160与漏极150连接。源极140和漏极150的材料可以包括铝基金属诸如铝或铝合金、银基金属诸如银或银合金、铜基金属诸如铜或铜合金、钼基金属诸如钼或钼合金等金属。
在示例性实施方式中，薄膜晶体管110的栅极120与栅线连接，栅极120可以与栅线同层设置，采用相同的材料通过同一工艺制备而成。栅极120的材料可以包括铝基金属诸如铝或铝合金、银基金属诸如银或银合金、铜基金属诸如铜或铜合金、钼基金属诸如钼或钼合金等金属。
在示例性实施方式中，薄膜晶体管110的源极140与数据线连接，源极140可以与数据线同层设置，采用相同的材料通过同一工艺制备而成。
下面通过本实施例显示基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在衬底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
本发明实施例显示基板制备过程包括：
(1)在基底上形成栅极图案。在基底上形成栅极图案包括：先在基底10上沉积一层缓冲薄膜，形成覆盖整个基底10的缓冲层图案。随后在缓冲层上依次沉积第一金属薄膜、遮光材料层和第一绝缘薄膜，通过构图工艺对第一金属薄膜进行构图，形成设置在缓冲层上的栅极120以及栅线(图9中未示出)，通过构图工艺对遮光材料层进行构图，形成设置在缓冲层上的遮光层(图9中未示出)；通过构图工艺对第一绝缘薄膜进行构图，形成覆盖 栅极120、栅线以及遮光层的第一绝缘层20，如图9所示。其中，栅极120的材料可以包括多层层叠设置的金属。例如，栅极120的材料可以为依次层叠设置的第一钼金属层、铝金属层以及第二钼金属层，第一钼金属层的厚度可以为150埃，铝金属层的厚度可以为3000埃，第二钼金属层的厚度可以为800埃。第一绝缘层20的材料可以为SiNx，第一绝缘层20的厚度可以为4000埃。
(2)形成有源层图案。形成有源层图案包括：在形成上述结构的基底10上，在第一绝缘层20上沉积有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成设置在第一绝缘层20上的有源层130图案，如图9所示。其中，有源层130的厚度可以为1700埃。
(3)形成源极、漏极、数据线以及触控信号线图案。形成源极、漏极以及数据线图案包括：在形成上述结构的基底10上，在有源层130上依次沉积第二金属薄膜和第二绝缘薄膜，通过构图工艺对第二金属薄膜进行构图，形成源极140、漏极150、数据线(图9中未示出)以及触控信号线(图9中未示出)图案，其中，源极140和漏极150均与有源层130连接。通过构图工艺对第二绝缘薄膜进行构图，使第二绝缘薄膜形成覆盖源极140、漏极150、数据线以及触控信号线的第二绝缘层30，在第二绝缘层30中开设第一过孔(图9中未示出)、第二过孔(图9中未示出)以及第一开口，第一过孔将遮光层暴露，第二过孔将触控信号线暴露。第一开口包括侧壁以及底壁，第一开口的侧壁将漏极150暴露，如图9所示。其中，源极140和漏极150的材料可以包括多层层叠设置的金属。例如，源极140和漏极150的材料可以为依次层叠设置的第一钼金属层、铝金属层以及第二钼金属层，第一钼金属层的厚度可以为150埃，铝金属层的厚度可以为3000埃，第二钼金属层的厚度可以为800埃。第二绝缘层30的材料可以为SiNx，第二绝缘层30的厚度可以为2500埃。
(4)形成公共电极图案。形成公共电极图案包括：在形成上述结构的基底10上，在第二绝缘层30上依次沉积第三金属薄膜和第三绝缘薄膜，通过构图工艺对第三金属薄膜进行构图，形成设置在第二绝缘层30上的公共电极40图案；公共电极40通过第一过孔与遮光层连接，公共电极40通过第二过 孔与触控信号线连接；通过构图工艺对第三绝缘薄膜进行构图，形成覆盖公共电极40的第三绝缘层50，在第三绝缘层50上开设第二开口，第二开口与第一开口连通，形成第三过孔160，第三过孔160将漏极150暴露，如图9所示。其中，公共电极40的材料可以为ITO，公共电极40的厚度可以为700埃。
(5)形成像素电极图案。形成像素电极图案包括：在形成上述结构的基底10上，在第三绝缘层50上沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，形成设置在第三绝缘层50上的像素电极60图案；像素电极60通过第三过孔160与漏极150连接。其中，像素电极60的材料可以为ITO，像素电极60的厚度可以为700埃。其中，像素电极60包括至少两个条状电极601，至少两个条状电极601中相邻的条状电极601之间具有狭缝602，狭缝602至少包括位于狭缝602至少一端的第一拐角端603，第一拐角端603包括相对设置的第一边6031、第二边6032，以及将第一边6031的端部和第二边6032的端部连接的第一过渡边6033。第一边6031和第二边6032均可以为曲线状或直线状。第一边6031和第二边6032之间形成第一夹角a1，第一夹角a1可以为0°至13°。示例的，第一夹角a1可以为9°至11°。例如，第一夹角a1可以为9.5°、10°或10.5°。
图11为本公开实施例显示装置的剖视图。如图11所示，本公开实施例还提供了一种显示装置，显示装置可以包括相对设置的前述的显示基板1、对向基板2以及设置于显示基板1与对向基板2之间的液晶层3。其中，显示基板1可以为前述显示基板。
液晶层3可以包括具有介电各向异性的多个液晶分子。显示基板1与对向基板2之间形成电场，使液晶分子可以在显示基板1与对向基板2之间、在预定方向上旋转，从而允许或阻挡光的透射。
在示例性实施方式中，如图11所示，本公开实施例显示装置还包括黑矩阵4，黑矩阵4设置于对向基板2显示基板1一侧。黑矩阵4在显示基板1中基底10正投影覆盖显示基板1中数据线400以及遮光层80的至少部分，黑矩阵4用于对数据线400进行挡光。
在示例性实施方式中，如图11所示，黑矩阵4在显示基板1中基底10 正投影的中心轴与显示基板1中公共电极40在显示基板1中基底10正投影的中心轴交叠。其中，黑矩阵4在显示基板1中基底10正投影的中心轴为与第一方向相垂直的方向延伸的中心轴；公共电极40在显示基板1中基底10正投影的中心轴为与第一方向相垂直的方向延伸的中心轴。
本公开实施例还提供了一种显示基板的制备方法，包括：
在所述基底的一侧形成像素电极；其中，所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为0°至13°。
图12为本公开实施例掩膜版的结构示意图；图13为图12中d处的放大图。如图12和图13所示，本公开实施例还提供了一种掩膜版，包括图案区1000以及围绕图案区1000四周的非图案区1100，图案区1000包括至少一个掩膜图案1200，掩膜图案1200在图案区1000中周期分布。掩膜图案1200为开口结构，掩膜图案1200允许曝光光源发出的光通过。非图案区1100完全封闭而没有开口，非图案区1100不允许曝光光源发出的光通过。掩膜图案1200至少包括位于掩膜图案1200至少一端的第二拐角端1300，第二拐角端1300包括相对设置的第三边1400、第四边1500，以及将第三边1400的端部和第四边1500的端部连接的第二过渡边1600，第二过渡边1600为沿着远离第二拐角端1300方向凸出的圆弧状；第三边1400和/第四边1500为直线状，第三边1400与第四边1500之间形成第五夹角，第五夹角为大于等于0°小于等于5°。
在示例性实施方式中，如图13所示，第四边1500与第一方向形成第四夹角a4，第四夹角a4的角度可以为35°至55°。第三边1400与第一方向形成第五夹角a5，第五夹角a5的角度可以为35°至55°。其中，第五夹角a5可以与第四夹角a4相同。比如，第五夹角a5可以与第四夹角a4均为45°。需要说明的是，本公开所列举的角度范围包括端值，例如第五夹角a5的角度可以为35°至55°，则第五夹角a5可以为35°或55°。
在示例性实施方式中，如图13所示，第二拐角端1300在与第一方向相垂直的方向上的正投影长度H’为大于等于3um小于等于9um。
在示例性实施方式中，如图12所示，掩膜图案1200包括第一图案1201、第二图案1202以及位于相邻两个第二图案1202之间的第三图案1203。第一图案1201的第二拐角端1300具有在与第一方向相垂直的方向上的第一正投影h’1，第二图案1202的第二拐角端1300具有在与第一方向相垂直的方向上的第二正投影长度h’2，第三图案1203的第二拐角端1300具有在与第一方向相垂直的方向上的第三正投影长度为h’3，其中，h’3>h’2>h’1。
在示例性实施方式中，如图12所示，第一图案1201具有第一宽度w’1，第二图案1202具有第二宽度w’2，第三图案1203具有第三宽度w’3。其中，w’3>w’2＝w’1。例如，第一宽度w’1为5.1±1μm；第二宽度w’2为5.1±1μm；第三宽度w’3为10.8±2μm。
在示例性实施方式中，本公开实施例掩膜版可以应用于形成本公开实施例显示基板中的像素电极。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (23)

  1. 一种显示基板，包括基底以及设置在所述基底一侧的像素电极；所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为大于等于0°小于等于13°。
  2. 根据权利要求1所述的显示基板，其中，所述第一夹角为大于等于9°小于等于11°。
  3. 根据权利要求2所述的显示基板，其中，所述第一夹角为9.5°、10°或10.5°。
  4. 根据权利要求1所述的显示基板，还包括设置在所述基底靠近所述像素电极一侧且沿着第一方向延伸的栅线；设置于所述栅线远离所述基底一侧的第一绝缘层；设置于所述第一绝缘层远离所述基底一侧且沿着第二方向延伸的数据线；设置于所述数据线远离所述基底一侧的第二绝缘层；设置于所述第二绝缘层远离所述基底一侧的公共电极；以设置于所述公共电极远离所述基底一侧的第三绝缘层；所述像素电极设置于所述第三绝缘层远离所述基底一侧；所述第一方向与所述第二方向不同。
  5. 根据权利要求1-4任一所述的显示基板，还包括设置在所述基底靠近所述像素电极一侧且沿着第一方向延伸的栅线，所述第一边与所述第一方向形成第二夹角，所述第二夹角为40°至50°；和/或，所述第二边与所述第一方向形成第三夹角，所述第三夹角为40°至50°。
  6. 根据权利要求5所述的显示基板，其中，所述第二夹角与所述第三夹角相同。
  7. 根据权利要求1所述的显示基板，其中，所述第一拐角端在与所述第一方向相垂直的方向上的正投影长度H为大于等于3um小于等于9um。
  8. 根据权利要求1所述的显示基板，其中，所述狭缝还包括沿着第三方向延伸的第一主体部、沿着第四方向延伸的第二主体部；以及将所述第一主体部和所述第二主体部连接的连接部，所述连接部为V字形，所述第三方向与所述第四方向不相同。
  9. 根据权利要求1所述的显示基板，其中，所述狭缝包括第一狭缝、第二狭缝以及位于所述第一狭缝、所述第二狭缝之间的第三狭缝，所述第三狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度大于所述第二狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度，所述第二狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度大于所述第一狭缝的第一拐角端在与第一方向相垂直的方向上的正投影长度。
  10. 根据权利要求9所述的显示基板，其中，所述第三狭缝的宽度大于所述第二狭缝的宽度；和/或，所述第三狭缝的宽度大于所述第一狭缝的宽度；和/或，所述第一狭缝的宽度等于所述第二狭缝的宽度。
  11. 根据权利要求9所述的显示基板，还包括触控信号线，所述触控信号线在所述基底的正投影至少部分位于所述第三狭缝在所述基底的正投影中。
  12. 根据权利要求4所述的显示基板，其中，所述狭缝在所述基底的正投影与所述数据线在所述基底的正投影不交叠。
  13. 根据权利要求1所述的显示基板，还包括触控信号线，所述触控信号线与所述数据线同层设置。
  14. 根据权利要求13所述的显示基板，其中，所述触控信号线第一侧的边缘至所述第三狭缝第一侧边缘的距离与所述触控信号线第二侧边缘至所述第三狭缝第二侧边缘的距离相同。
  15. 根据权利要求4所述的显示基板，还包括遮挡层，所述遮挡层至少包括沿着第二方向延伸的至少一个第一部分。
  16. 根据权利要求15所述的显示基板，其中，所述遮挡层还包括沿着第一方向延伸的第二部分，所述第二部分与所述至少一个第一部分连接。
  17. 根据权利要求16所述的显示基板，还包括触控信号线，所述第二部 分通过第一过孔与所述公共电极连接，所述至少一个第一部分通过第二过孔与所述触控信号线连接。
  18. 根据权利要求16所述的显示基板，其中，所述遮光层包括两个相对设置的第一部分以及一个第二部分，第二部分的一端与两个相对设置的第一部分中的一个的端部连接，第二部分的另一端与两个相对设置的第一部分中的另一个断开或连接。
  19. 根据权利要求18所述的显示基板，其中，所述公共电极第一侧的边缘至所述遮光层第一侧边缘的距离与所述公共电极第二侧边缘至所述遮光层第二侧边缘的距离相同；和/或，所述公共电极第一侧的边缘至所述数据线第一侧边缘的距离与所述公共电极第二侧的边缘至所述数据线第二侧边缘的距离相同；和/或，所述公共电极第一侧的边缘至所述像素电极第一侧边缘的距离与所述公共电极第二侧的边缘至所述像素电极第二侧边缘的距离相同。
  20. 根据权利要求18所述的显示基板，其中，所述像素电极第一侧的边缘至所述遮光层第一侧的边缘的距离与所述像素电极第二侧的边缘至所述遮光层第二侧边缘的距离相同；或者，所述像素电极第一侧的边缘至所述遮光层第一侧的边缘的距离与所述像素电极第二侧的边缘至所述遮光层第二侧边缘的距离不相同。
  21. 一种显示装置，包括权利要求1至20任一所述的显示基板。
  22. 一种显示基板的制备方法，包括：
    在所述基底的一侧形成像素电极；其中，所述像素电极包括至少两个条状电极，所述至少两个条状电极中相邻的条状电极之间具有狭缝，所述狭缝至少包括位于所述狭缝至少一端的第一拐角端，所述第一拐角端包括相对设置的第一边、第二边，以及将所述第一边的端部和所述第二边的端部连接的第一过渡边，所述第一过渡边为沿着远离所述第一拐角端方向凸出的弧状；所述第一边与所述第二边之间形成第一夹角，所述第一夹角为大于等于0°小于等于13°。
  23. 一种掩膜版，其中，包括图案区，所述图案区包括至少一个掩膜图案，所述掩膜图案至少包括位于所述掩膜图案至少一端的第二拐角端，所述 第二拐角端包括相对设置的第三边、第四边，以及将所述第三边的端部和所述第四边的端部连接的第二过渡边，所述第二过渡边为沿着远离所述第二拐角端方向凸出的圆弧状；所述第三边与所述第四边之间形成第五夹角，所述第五夹角为大于等于0°小于等于5°。
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