WO2022261812A1 - Emballage par empilement tridimensionnel et son procédé de fabrication - Google Patents

Emballage par empilement tridimensionnel et son procédé de fabrication Download PDF

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Publication number
WO2022261812A1
WO2022261812A1 PCT/CN2021/100028 CN2021100028W WO2022261812A1 WO 2022261812 A1 WO2022261812 A1 WO 2022261812A1 CN 2021100028 W CN2021100028 W CN 2021100028W WO 2022261812 A1 WO2022261812 A1 WO 2022261812A1
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Prior art keywords
semiconductor chip
module
chip
metal layer
oxide layer
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PCT/CN2021/100028
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English (en)
Chinese (zh)
Inventor
张日清
张宏英
雷电
朱继锋
朱靖华
王腾
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华为技术有限公司
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Priority to PCT/CN2021/100028 priority Critical patent/WO2022261812A1/fr
Priority to CN202180098310.XA priority patent/CN117337489A/zh
Publication of WO2022261812A1 publication Critical patent/WO2022261812A1/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a three-dimensional stack package and a manufacturing method of the three-dimensional stack package.
  • an existing three-dimensional integrated circuit (Three-Dimensional Integrated Circuits, 3DIC) structure is to stack memory chips on an application processor (Application processor, AP)
  • Application processor Application processor
  • the AP chip and the memory chip are vertically interconnected in three dimensions, and through-silicon vias (Through-Si-Via, TSV) are made in the lower AP chip for signal interconnection between the upper memory chip and the lower AP chip.
  • TSV through-silicon vias
  • the power supply of the upper storage chip needs to be realized through the TSV in the lower AP chip.
  • AP chips continue to use the most advanced manufacturing technology in the industry (such as the current 5nm chip and 7nm chip).
  • the AP chip uses advanced manufacturing technology, on the one hand the TSV The rate is low, and the stability of chip performance is poor, resulting in high manufacturing costs.
  • the large number of TSVs occupies a large area, and the modules of the AP chip will be divided into fragments, resulting in a decrease in the computing performance of the chip.
  • the present application provides a three-dimensional stack package and a three-dimensional stack package manufacturing method to solve the problems of low TSV process yield and chip computing performance degradation when AP chips use advanced manufacturing processes.
  • the present application provides a three-dimensional stack package, which includes: a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip;
  • the first semiconductor chip and the second semiconductor chip are arranged on the same horizontal plane, the third semiconductor chip is stacked on one side of the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip The process level of the second semiconductor chip is lower than the process level of the second semiconductor chip;
  • the first semiconductor chip includes a first through silicon via forming an electrical connection between the first semiconductor chip and the third semiconductor chip.
  • the third semiconductor chip is stacked on the side of the first semiconductor chip and the second semiconductor chip, and is formed by making the first through-silicon via in the first semiconductor chip with a low process level.
  • the through-silicon vias are not made in the second semiconductor chip with a high process level, and the yield and performance of the through-silicon holes in the semiconductor with a low process level are higher than those in the process.
  • the first semiconductor chip may include one or more of a bluetooth module, a universal serial bus USB module, a high-speed serial computer expansion bus standard PCIE module, and a global positioning system GPS module
  • the The second semiconductor chip includes one or more of a central processing unit CPU module, a graphics processing unit GPU module, a natural processing unit NPU, a modem, and a double-rate synchronous dynamic random access memory (DDR).
  • the first semiconductor chip where one or more of the Bluetooth module, the USB module, the PCIE module, and the GPS module are located can use a low-level process, and the CPU module, the GPU module, the NPU, the modem 1.
  • the second semiconductor chip where one or more of the DDRs are located can use a high-level process, so that the through-silicon vias can be made in the first semiconductor chip with a low process level, and not in the second semiconductor chip with a high process level.
  • the yield and performance of TSVs in semiconductors with low process levels are superior to those in semiconductors with high process levels.
  • the yield rate is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, it can ensure that the second semiconductor chip achieves higher computing performance, realizes high integration of semiconductor chips, higher signal transmission rate, and larger bandwidth.
  • the first semiconductor chip may include one or more of a serial peripheral interface SPI module, a universal serial bus USB module, a boundary scan test JTAG module, and a clock module
  • the second The semiconductor chip includes at least one of a serializer and deserializer SerDes module or a DDR.
  • the first semiconductor chip where one or more of the SPI module, USB module, JTAG module, and clock module are located can use a low-level process, and at least one of the SerDes module or DDR is located.
  • the second semiconductor chip can use a high-level process, so that the through-silicon vias can be made in the first semiconductor chip with a low process level, but not in the second semiconductor chip with a high process level.
  • the yield and performance of low-grade semiconductors are superior to those of high-grade semiconductors. The yield is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, the second semiconductor chip can be guaranteed Achieve higher computing performance, high integration of semiconductor chips, higher signal transmission rate, and larger bandwidth.
  • the active surface of the third semiconductor chip faces the passive surfaces of the first semiconductor chip and the second semiconductor chip.
  • the three-dimensional stack package further includes:
  • a first oxide layer and a second oxide layer, the first oxide layer and the second oxide layer are arranged between the third semiconductor chip and the first semiconductor chip and between the third semiconductor chip and the second semiconductor chip Between the semiconductor chips, the first oxide layer and the second oxide layer are bonded together;
  • a first metal layer and a second metal layer, the first metal layer and the second metal layer are arranged between the third semiconductor chip and the first semiconductor chip, the first metal layer and the The second metal layer is bonded together.
  • the three-dimensional stack package further includes:
  • the three-dimensional stack package further includes:
  • the third semiconductor chip includes a second through silicon via forming an electrical connection between the third semiconductor chip and the fourth semiconductor chip.
  • the entire three-dimensional stack package On the basis of the beneficial effects of the three-dimensional stack package provided in the first aspect, since at least one fourth semiconductor chip is stacked on the third semiconductor chip, the entire three-dimensional stack package The integration level becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • the three-dimensional stack package further includes:
  • the second redistribution layer and the third redistribution layer wherein the second redistribution layer is disposed on the side of the third semiconductor chip away from the first semiconductor chip, and the third redistribution layer is disposed on the the first semiconductor chip is on the same side as the second semiconductor chip;
  • a fifth semiconductor chip, the fifth semiconductor chip is electrically connected to the second redistribution layer through solder balls of the fifth semiconductor chip.
  • the three-dimensional stack package provided by this embodiment has a higher integration degree of the entire three-dimensional stack package, higher signal transmission rate, and larger bandwidth.
  • the three-dimensional stack package further includes:
  • a first substrate and a second substrate wherein the first substrate is arranged on a side of the third semiconductor chip away from the first semiconductor chip, and the second substrate is arranged on the first semiconductor chip and the first semiconductor chip.
  • a fifth semiconductor chip, the fifth semiconductor chip is electrically connected to the first substrate through solder balls of the fifth semiconductor chip.
  • the three-dimensional stack package provided by this embodiment has a higher integration degree of the entire three-dimensional stack package, higher signal transmission rate, and larger bandwidth.
  • the present application provides a method for manufacturing a three-dimensional stack package, the method comprising:
  • the first semiconductor chip and the second semiconductor chip are stacked on the third semiconductor chip, the first semiconductor chip and the second semiconductor chip are arranged on the same level, and the process level of the first semiconductor chip is lower than the process level of the second semiconductor chip;
  • a first through-silicon via is formed in the first semiconductor chip, and the first through-silicon via forms an electrical connection between the first semiconductor chip and the third semiconductor chip.
  • the first through-silicon via is made in the first semiconductor chip with a low process level.
  • Higher semiconductors have advantages, higher yield rate and more stable performance, which can save manufacturing costs and ensure the stability of chip performance, so it can ensure that the second semiconductor chip achieves higher computing performance and realizes high integration of semiconductor chips.
  • the signal transmission rate is higher and the bandwidth is larger.
  • the first semiconductor chip includes one or more of a Bluetooth module, a universal serial bus USB module, a high-speed serial computer expansion bus standard PCIE module, and a global positioning system GPS module.
  • the second semiconductor chip includes one or more of a central processing unit CPU module, a graphics processing unit GPU module, a natural processing unit NPU, a modem, and a double-rate synchronous dynamic random access memory (DDR).
  • DDR double-rate synchronous dynamic random access memory
  • the first semiconductor chip where one or more of the Bluetooth module, the USB module, the PCIE module, and the GPS module are located can use a low-level process, and the CPU module, the GPU module, the NPU, the modem 1.
  • the second semiconductor chip where one or more of the DDRs are located can use a high-level process, so that the through-silicon vias can be made in the first semiconductor chip with a low process level, and not in the second semiconductor chip with a high process level.
  • the yield and performance of TSVs in semiconductors with low process levels are superior to those in semiconductors with high process levels.
  • the yield rate is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, it can ensure that the second semiconductor chip achieves higher computing performance, realizes high integration of semiconductor chips, higher signal transmission rate, and larger bandwidth.
  • the first semiconductor chip includes one or more of a serial peripheral interface SPI module, a universal serial bus USB module, a boundary scan test JTAG module, and a clock module.
  • the chip includes at least one of a serializer and deserializer SerDes module or a DDR.
  • the first semiconductor chip where one or more of the SPI module, USB module, JTAG module, and clock module are located can use a low-level process, and at least one of the SerDes module or DDR is located.
  • the second semiconductor chip can use a high-level process, so that the through-silicon vias can be made in the first semiconductor chip with a low process level, but not in the second semiconductor chip with a high process level.
  • the yield and performance of low-grade semiconductors are superior to those of high-grade semiconductors. The yield is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, the second semiconductor chip can be guaranteed Achieve higher computing performance, high integration of semiconductor chips, higher signal transmission rate, and larger bandwidth.
  • the active surface of the third semiconductor chip faces the first semiconductor chip and the The passive side of the second semiconductor chip.
  • the method also includes:
  • a first oxide layer and a second oxide layer are provided between the third semiconductor chip and the first semiconductor chip and between the third semiconductor chip and the second semiconductor chip, and the first oxide layer bonded to the second oxide layer;
  • a first metal layer and a second metal layer are arranged between the third semiconductor chip and the first semiconductor chip, and the first metal layer and the second metal layer are bonded together.
  • the method also includes:
  • a first redistribution layer or substrate electrically connected to the pad is provided.
  • the method also includes:
  • a second through-silicon via is formed in the third semiconductor chip, and the second through-silicon via forms an electrical connection between the third semiconductor chip and the fourth semiconductor chip.
  • the entire The integration level of the three-dimensional stack package becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • the method also includes:
  • the solder balls of the fifth semiconductor chip are electrically connected to the second redistribution layer.
  • the integration degree of the entire three-dimensional stack package becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • the method also includes:
  • the solder balls of the fifth semiconductor chip are electrically connected to the first substrate.
  • the integration degree of the entire three-dimensional stack package becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • FIG. 1 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application
  • FIG. 2 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • FIG. 3 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • FIG. 4 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • FIG. 5 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • FIG. 6 is a flow chart of a three-dimensional stack package manufacturing method provided by the present application.
  • FIG. 7 is a flow chart of a three-dimensional stack package manufacturing method provided by the present application.
  • FIG. 8 is a flow chart of a three-dimensional stack package manufacturing method provided by the present application.
  • FIG. 9 is a schematic diagram of stacking four wafers.
  • FIG. 10 is a schematic diagram of stacking a semiconductor chip with a low process level and a semiconductor chip with a high process level on a fourth wafer;
  • FIG. 11 is a schematic diagram of making TSVs on the first semiconductor chip
  • Fig. 12 is a structural schematic diagram of completing plastic packaging
  • FIG. 13 is a schematic diagram of forming a redistribution layer on the surface of a semiconductor chip with a low process level and a semiconductor chip with a high process level;
  • Figure 14 is a schematic diagram after removing the carrier board
  • Figure 15 is a schematic diagram of completed ball planting.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations, and any embodiment or solution described as “exemplary” or “for example” in the embodiments of the present application It should not be construed as preferred or advantageous over other embodiments or aspects. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • the memory chip is stacked on the AP chip, and the TSV in the AP chip is used for signal interconnection between the upper layer memory chip and the lower layer AP chip and power supply for the upper layer memory chip.
  • AP chips continue to use the most advanced manufacturing technology in the industry. If TSV is reserved in AP chips produced by the most advanced manufacturing technology, on the one hand, the yield rate of TSV process is low, and the stability of chip performance is relatively low. Poor, resulting in higher manufacturing costs. On the other hand, the large number of TSVs occupies a large area, and the modules of the AP chip will be divided into fragments, resulting in a decrease in the computing performance of the chip.
  • the present application provides a three-dimensional stacked package and a manufacturing method of the three-dimensional stacked package.
  • the three-dimensional stacked package of the present application includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip, and the third semiconductor chip is stacked on the On one side of a semiconductor chip and the second semiconductor chip, the process level of the first semiconductor chip is lower than that of the second semiconductor chip, and the first through-silicon via is formed in the first semiconductor chip with a lower process level
  • the electrical connection and communication connection between the first semiconductor chip and the third semiconductor chip do not make through-silicon vias in the second semiconductor chip with a high process level.
  • FIG. 1 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • the three-dimensional stack package of this embodiment may include a first semiconductor chip 110, a second semiconductor chip 120 and a third semiconductor chip 100 , wherein the first semiconductor chip 110 and the second semiconductor chip 120 are arranged on the same horizontal plane, and the third semiconductor chip 100 is stacked on the side of the first semiconductor chip 110 and the second semiconductor chip 120 .
  • the process level of the first semiconductor chip 110 is lower than that of the second semiconductor chip 120, for example, the process level of the second semiconductor chip 120 is 5nm or 7nm, and the process level of the first semiconductor chip 110 is 10nm.
  • the first semiconductor chip 110 includes a first TSV 111 , and the first TSV 111 forms an electrical connection between the first semiconductor chip 110 and the third semiconductor chip 100 .
  • the first semiconductor chip includes a Bluetooth module, a Universal Serial Bus (Universal Serial Bus, USB) module, a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) module and a global positioning system One or more of the (Global Positioning System, GPS) modules
  • the second semiconductor chip includes a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphic Processing Unit, GPU), a natural processing unit (Natural Processing Unit, One or more of NPU), modem (Modem) and double-rate synchronous dynamic random access memory (Double Data Rate, DDR).
  • the first semiconductor chip where one or more of the Bluetooth module, the USB module, the PCIE module, and the GPS module are located can use a low-level process, and one of the CPU module, the GPU module, the NPU, the modem, and the DDR
  • One or more of the second semiconductor chips can use a high-level process, so that the through-silicon vias can be made in the first semiconductor chip with a low process level, but not in the second semiconductor chip with a high process level.
  • the yield and performance of through holes in semiconductors with low process levels are superior to those in semiconductors with high process levels.
  • the yield rate is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, it can guarantee
  • the second semiconductor chip achieves higher computing performance, high integration of semiconductor chips, higher signal transmission rate, and greater bandwidth.
  • the first semiconductor chip includes a serial peripheral interface (Serial Peripheral Interface, SPI) module, a USB module, a boundary scan test (Joint Test Action Group, JTAG) module and a clock (CLK) module
  • SPI Serial Peripheral Interface
  • USB Universal Serial Bus
  • JTAG boundary scan test
  • CLK clock
  • One or more of the second semiconductor chip includes at least one of a serializer and deserializer SerDes module or a DDR.
  • the first semiconductor chip where one or more of the SPI module, USB module, JTAG module, and clock module are located can use a low-level process
  • the second semiconductor chip where at least one of the SerDes module or DDR is located A high-level process can be used, so that the through-silicon via can be made in the first semiconductor chip with a low process level, and not in the second semiconductor chip with a high process level, and the through-silicon hole can be made in the semiconductor with a low process level
  • Both the yield rate and performance have advantages over semiconductors with high process grades. The yield rate is higher and the performance is more stable, which can save manufacturing costs and ensure the stability of chip performance. Therefore, it can ensure that the second semiconductor chip can achieve higher computing power. Performance, realize high integration of semiconductor chips, higher signal transmission rate, and larger bandwidth.
  • the first semiconductor chip 110 may include a wireless network (WI-FI) module, a Bluetooth module, a USB module, a PCIE module, a GPS module, and a Universal Flash Storage (Universal Flash Storage, UFS) modules
  • the second semiconductor chip 120 includes one or more of CPU, GPU, NPU, modem, DDR and media (Media) modules.
  • the first semiconductor chip where one or more of the WI-FI module, the Bluetooth module, the USB module, the PCIE module, the GPS module and the UFS module are located can use a low-level process, and the CPU, GPU, NPU,
  • the second semiconductor chip on which one or more of the modem, DDR, and media module are located can use a high-grade process, so that the through-silicon vias can be fabricated in the first semiconductor chip with a low process level, and not in the high-level process.
  • the yield and performance of TSVs in semiconductors with low process levels are superior to those in semiconductors with high process levels.
  • the first semiconductor chip 110 may include an SPI module, a USB module, a Universal Asynchronous Receiver/Transmitter (UART) module, a JTAG module, a clock module, and a power management bus (Power Management Bus, PMBUS) module
  • the second semiconductor chip 120 can include at least one of a serializer (Serializer) and a deserializer (Deserializer) SerDes module or DDR, that is, the second semiconductor chip 120 can include a SerDes The module, or DDR, or the second semiconductor chip 120 may include a SerDes module and a DDR.
  • the first semiconductor chip where one or more of the SPI module, USB module, UART module, JTAG module, clock module and PMBUS module is located can use a low-level process, and at least one of the SerDes module or DDR
  • the second semiconductor chip where it is located can use a high-level process, so that the through-silicon vias can be fabricated in the first semiconductor chip with a low process level, but not in the second semiconductor chip with a high process level.
  • the yield and performance of semiconductors with low process grades have advantages over semiconductors with high process grades.
  • the active surface of the third semiconductor chip 100 faces the first semiconductor chip 110 and the second semiconductor chip. 120 passive faces.
  • the three-dimensional stack package of this embodiment may further include a first oxide layer 101, a second oxide layer 103, a first metal layer 102, and a second metal layer 104, wherein the first oxide layer 101 and the second
  • the oxide layer 103 is disposed between the third semiconductor chip 100 and the first semiconductor chip 110 and between the third semiconductor chip 100 and the second semiconductor chip 120 , and the first oxide layer 101 and the second oxide layer 103 are bonded together.
  • the first metal layer 102 and the second metal layer 104 are disposed between the third semiconductor chip 100 and the first semiconductor chip 110 , and the first metal layer 102 and the second metal layer 104 are bonded together.
  • the three-dimensional stack package of this embodiment may also include pads 113 arranged on the active surface of the first semiconductor chip 110 and a dielectric layer 112 , and may also include pads 113 arranged on the active surface of the second semiconductor chip 120.
  • the third semiconductor chip 100 and the first semiconductor chip 110 are connected to solder balls through the first metal layer 102, the second metal layer 104, the first through-silicon via, the pad 113 and the first redistribution layer or substrate (140 and 141).
  • the second semiconductor chip 120 is connected to the solder ball 150 through the pad 115, the first redistribution layer or the substrate (140 and 141), so as to realize the communication between the first semiconductor chip 110, the second semiconductor chip 120 and the third semiconductor chip 100 Interconnection, including electrical connections and signal connections.
  • the second semiconductor chip 120 in this embodiment may be a partial functional module including an AP chip
  • the first semiconductor chip 110 may be a partial functional module including an AP chip
  • the third semiconductor chip 100 may be a Memory chips, logic chips, or any other functional chips.
  • the third semiconductor chip is stacked on the side of the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip is formed by making a first through-silicon via in the first semiconductor chip with a low process level.
  • the electrical connection between the chip and the third semiconductor chip does not make TSVs in the second semiconductor chip with a high process level.
  • the yield and performance of TSVs in semiconductors with low process levels are higher than those in semiconductors with high process levels. It has advantages, higher yield rate and more stable performance, which can save manufacturing costs and ensure the stability of chip performance, so it can ensure that the second semiconductor chip achieves higher computing performance, realizes high integration of semiconductor chips, and higher signal transmission rate Higher, greater bandwidth.
  • Fig. 2 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • the three-dimensional stack package of this embodiment is based on the three-dimensional stack package structure shown in Fig. 1, further, it can also Including a fourth semiconductor chip 160 stacked on the third semiconductor chip 100, when stacked, the active surface of the fourth semiconductor chip may face the passive surface of the third semiconductor chip, in this embodiment, the third semiconductor chip 100 includes The second TSV 121 forms an electrical connection between the third semiconductor chip 100 and the fourth semiconductor chip 160 .
  • the three-dimensional stacked package of this embodiment also includes a third oxide layer 105 and a fourth oxide layer 106, and the third oxide layer 105 and the fourth oxide layer 106 are arranged on the fourth semiconductor chip 160 and the third semiconductor chip. 100, the third oxide layer 105 and the fourth oxide layer 106 are bonded together. And the first metal layer 107 and the second metal layer 108, the first metal layer 107 and the second metal layer 108 are arranged between the fourth semiconductor chip 160 and the third semiconductor chip 100, the first metal layer 107 and the second metal layer 108 bonds together.
  • the fourth semiconductor chip 160 in this embodiment may be a memory chip, a logic chip or any other functional chip.
  • the active surface of the semiconductor chip on the upper layer may face the passive surface of the semiconductor chip on the next layer.
  • the description will be made by taking three semiconductor chips stacked on the third semiconductor chip 100 as an example.
  • Fig. 3 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • the three-dimensional stack package of this embodiment is based on the three-dimensional stack package structure shown in Fig. 1, further, it can also Including the fourth semiconductor chip 160, the sixth semiconductor chip 170 and the seventh semiconductor chip 180 stacked on the third semiconductor chip 100, the third semiconductor chip 100 includes the second through silicon via 121, the fourth semiconductor chip 160 includes the third silicon Through holes 131, the sixth semiconductor chip 170 includes a fourth through silicon via 151, the third through silicon via 131 forms an electrical connection between the fourth semiconductor chip 160 and the fifth semiconductor chip 170, and the fourth through silicon via 151 forms a sixth through silicon via 151. Electrical connection between the semiconductor chip 170 and the seventh semiconductor chip 180 .
  • the fifth oxide layer 203 and the sixth oxide layer 204, as well as the fifth metal layer 201 and the sixth metal layer 202 are arranged between the fourth semiconductor chip 160 and the sixth semiconductor chip 170, and the fifth oxide layer 203 and the sixth oxide layer
  • the layers 204 are bonded together, and the fifth metal layer 201 and the sixth metal layer 202 are bonded together.
  • a seventh oxide layer 205 and an eighth oxide layer 206, a seventh metal layer 207 and an eighth metal layer 208 are arranged between the sixth semiconductor chip 170 and the seventh semiconductor chip 180, and the seventh oxide layer 205 and the eighth oxide layer 206 bonded together, the seventh metal layer 207 and the eighth metal layer 208 are bonded together.
  • the fourth semiconductor chip 160 , the sixth conductor chip 170 and the seventh semiconductor chip 180 in this embodiment may be memory chips, logic chips or any other functional chips.
  • a semiconductor chip can also be added on top of the three-dimensional stack package to form a package-on-package (Package-On-Package, POP) ) structure to realize communication between the top semiconductor chip and the semiconductor chip in the lower three-dimensional stack package.
  • POP Package-On-Package
  • FIG. 4 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • the three-dimensional stack package of this embodiment may include: a first semiconductor chip 110.
  • the second semiconductor chip 120 and the third semiconductor chip 100 wherein the first semiconductor chip 110 and the second semiconductor chip 120 are arranged on the same level, and the third semiconductor chip 100 is stacked between the first semiconductor chip 110 and the second semiconductor chip 120 side.
  • the process level of the first semiconductor chip 110 is lower than that of the second semiconductor chip 120, for example, the process level of the second semiconductor chip 120 is 5nm or 7nm, and the process level of the first semiconductor chip 110 is 10nm.
  • the first semiconductor chip 110 includes a first TSV 111 , and the first TSV 111 forms an electrical connection between the first semiconductor chip 110 and the third semiconductor chip 100 .
  • the modules that may be included in the first semiconductor chip 110 and the second semiconductor chip 120 may refer to the description in the embodiment shown in FIG. 1 , and will not be repeated here.
  • the active surface of the third semiconductor chip 100 faces the first semiconductor chip 110 and the passive surface of the second semiconductor chip 120 .
  • the three-dimensional stack package of this embodiment may further include a first oxide layer 101, a second oxide layer 103, a first metal layer 102, and a second metal layer 104, wherein the first oxide layer 101 and the second
  • the oxide layer 103 is disposed between the third semiconductor chip 100 and the first semiconductor chip 110 and between the third semiconductor chip 100 and the second semiconductor chip 120 , and the first oxide layer 101 and the second oxide layer 103 are bonded together.
  • the first metal layer 102 and the second metal layer 104 are disposed between the third semiconductor chip 100 and the first semiconductor chip 110 , and the first metal layer 102 and the second metal layer 104 are bonded together.
  • the three-dimensional stacked package of this embodiment may also include a bonding pad 113 arranged on the active surface of the first semiconductor chip 110, and a dielectric layer 112, and may also include a pad 113 arranged on the active surface of the second semiconductor chip 120. Pad 115, and dielectric layer 114.
  • the three-dimensional stacked package of this embodiment may further include a second redistribution layer 411, a third redistribution layer 440, and a fifth semiconductor chip 400, wherein the second redistribution layer 411 is disposed on the third semiconductor chip 100 is away from the side of the first semiconductor chip 110 , and the third redistribution layer 440 is disposed on the same side of the first semiconductor chip 110 and the second semiconductor chip 120 .
  • the periphery of the chip structure formed by the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 100 is a plastic package 414, and a hole is opened in the plastic package 414, and copper plating forms a hole through the plastic sealant (Through Molding Via, TMV) 412, the second rewiring layer 411 is arranged on the top of TMV412, the pad position of welding ball 404 is reserved on the dielectric layer 410, the fifth semiconductor chip 400 passes through the solder ball 404 of the fifth semiconductor chip 400 To be electrically connected to the second redistribution layer 411 , specifically, the solder balls 404 of the fifth semiconductor chip 400 may be soldered to the reserved solder ball positions on the lower dielectric layer 410 to form a POP structure.
  • the three-dimensional stacked package structure in this embodiment also includes solder balls 441 planted under the third redistribution layer 440, finally realizing the fifth semiconductor chip 400, the third semiconductor chip 100, the first semiconductor chip 110 and the second semiconductor chip 120 communication interconnection
  • the second redistribution layer 411 shown in FIG. 4 may also be the first substrate
  • the third redistribution layer 440 may also be the second substrate
  • the fifth semiconductor chip 400 passes through the fifth semiconductor
  • the solder balls 404 of the chip 400 are electrically connected to the first substrate.
  • the fifth semiconductor chip 400 may be a memory chip, a logic chip or any other functional chip.
  • FIG. 5 is a schematic structural diagram of an embodiment of a three-dimensional stack package provided by the present application.
  • FIG. 5 shows a possible structure of a fifth semiconductor chip 400.
  • the first semiconductor chip 400 includes an eighth semiconductor chip 400A and a ninth semiconductor chip 400B, a third substrate 403 and solder balls 404, and the eighth semiconductor chip 400A and the ninth semiconductor chip 400B realize on-chip input through metal bonding (wire bonding) 401.
  • the output (IO) Pad and the power ground Pad are connected to the third substrate 403 , and the plastic package 402 protects the chip and the gold wire 401 .
  • the integration degree of the entire three-dimensional stack package becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • FIG. 6 is a flow chart of a three-dimensional stack package manufacturing method provided by the present application. As shown in FIG. 6, the manufacturing method of this embodiment may include:
  • the first semiconductor chip includes one or more of a Bluetooth module, a USB module, a PCIE module, and a GPS module
  • the second semiconductor chip includes one or more of a CPU, a GPU, an NPU, a modem, and a DDR Multiple.
  • the first semiconductor chip includes one or more of an SPI module, a USB module, a JTAG module, and a clock module
  • the second semiconductor chip includes a serializer and deserializer SerDes module or a DDR module. at least one of the .
  • the first semiconductor chip may include one or more of a WI-FI module, a Bluetooth module, a USB module, a PCIE module, a GPS module, and a UFS module
  • the second semiconductor chip 120 includes one or more of a CPU, GPU, NPU, modem, DDR, and media modules.
  • the first semiconductor chip may include one or more of an SPI module, a USB module, a UART module, a JTAG module, a clock module, and a PMBUS module
  • the second semiconductor chip may include a SerDes module or a DDR at least one of the
  • the active surface of the third semiconductor chip faces the passive surface of the first semiconductor chip and the second semiconductor chip. noodle.
  • Pads are provided on the active surfaces of the first semiconductor chip and the second semiconductor chip, and a first redistribution layer or substrate electrically connected to the pads is provided.
  • the three-dimensional stack package manufacturing method provided in this embodiment is formed by stacking the third semiconductor chip on the side of the first semiconductor chip and the second semiconductor chip, and making the first through-silicon via in the first semiconductor chip with a low process level.
  • the electrical connection between the first semiconductor chip and the third semiconductor chip does not make through-silicon holes in the second semiconductor chip with a high process level.
  • the yield and performance of through-silicon holes in semiconductors with low process levels are higher than those in process levels.
  • FIG. 7 is a flow chart of a three-dimensional stack package manufacturing method provided by the present application. As shown in FIG. 7, the method of this embodiment may include:
  • S206 Stack a fourth semiconductor chip on the third semiconductor chip, and form a second through-silicon via on the third semiconductor chip.
  • the second through-silicon via forms an electrical connection between the third semiconductor chip and the fourth semiconductor chip.
  • the three-dimensional stack package manufacturing method provided in this embodiment is based on the beneficial effects of the three-dimensional stack package manufacturing method shown in FIG.
  • the integration level becomes higher, the signal transmission rate increases, and the bandwidth becomes larger.
  • the method of this embodiment may include:
  • S306 may also be: setting the first substrate on the side of the third semiconductor chip away from the first semiconductor chip, setting the second substrate on the side of the first semiconductor chip and the second semiconductor chip, and connecting the solder balls of the fifth semiconductor chip to the The first substrate is electrically connected.
  • the three-dimensional stack package manufacturing method provided in this embodiment has a higher integration degree of the entire three-dimensional stack package, higher signal transmission rate, and larger bandwidth.
  • 9 to 15 are cross-sectional views of the process steps of the three-dimensional stack package manufacturing method provided in the present application.
  • FIG. 9 is a schematic diagram of stacking four wafers. As shown in FIG. 9, firstly, the first wafer 301 is stacked on the carrier 320, the active side of the first wafer 301 is upward, and the passive side of the second wafer 302 is downward. According to actual needs, select a suitable bonding method, bond the metal layer 308_1 and the metal layer 308_2 together, bond the oxide layer 312_1 and the oxide layer 312_2 together, and then make the through silicon via 315, and complete the first wafer 301 and the A stack of second wafers 302 .
  • the passive surface of the third wafer 303 is stacked with the active surface of the second wafer 302, the metal layer 307_1 is bonded to the metal layer 307_2, and the oxide layer 311_1 is bonded to the oxide layer 311_2.
  • TSVs 314 are fabricated to complete the stacking of the second wafer 302 and the third wafer 303 .
  • the passive surface of the fourth wafer 304 is stacked with the active surface of the third wafer 303, the metal layer 306_1 is bonded to the metal layer 306_2, and the oxide layer 310_1 is bonded to the oxide layer 310_2 , and then make TSVs 313 to complete the stacking of the fourth wafer 304 and the third wafer 303 .
  • This step completes the stacking process of multi-layer wafers.
  • FIG. 10 is a schematic diagram of stacking semiconductor chips with a low process level and semiconductor chips with a high process level on the fourth wafer.
  • the semiconductor chip with a low process level and the semiconductor chip with a high process level are two The process level of the two chips is relatively relative, the passive surface of the semiconductor chip 340 with a low process level is stacked on the active surface of the fourth wafer 304, and the metal layer 305_1 is bonded to the metal layer 305_2 Together, the oxide layer 309_1 and the oxide layer 309_2 are bonded together.
  • the passive surface of the semiconductor chip 330 with a high process level is stacked on the active surface of the fourth wafer 304 , and the oxide layer 309_1 and the oxide layer 309_2 are bonded together.
  • FIG. 11 is a schematic diagram of making TSVs on the first semiconductor chip.
  • TSVs 316 are made on a semiconductor chip 340 with a low process level, and the semiconductor chip with a low process level is used to stack the fourth semiconductor chip.
  • FIG. 12 is a schematic diagram of the structure of the completed plastic package. Referring to FIG. 12 , for the overall chip structure that has been stacked, a plastic package 350 is made to protect the chip.
  • FIG. 13 is a schematic diagram of forming a redistribution layer on the surface of a semiconductor chip with a low process level and a semiconductor chip with a high process level.
  • a pad 360 and a dielectric layer 331 are formed on a semiconductor chip 330 with a high process level.
  • a pad 380 and a dielectric layer 341 are formed on a semiconductor chip 340 with a low process level, and then one or more redistribution layers 361 and a dielectric layer 362 are formed on the dielectric layer 341 and the dielectric layer 331 .
  • FIG. 14 is a schematic diagram after removing the carrier board. Referring to FIG. 14 , the carrier board 320 is removed.
  • FIG. 15 is a schematic diagram of completing ball planting. Referring to FIG. 15 , ball planting 370 is completed, and finally a complete chip stack is formed to realize communication interconnection.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un emballage par empilement tridimensionnel et son procédé de fabrication. L'emballage par empilement tridimensionnel comprend une première puce semi-conductrice, une deuxième puce semi-conductrice et une troisième puce semi-conductrice. La première puce semi-conductrice et la deuxième puce semi-conductrice sont disposées sur un même plan horizontal, et la troisième puce semi-conductrice est empilée sur un côté de la première puce semi-conductrice et de la deuxième puce semi-conductrice. Le niveau de traitement de la première puce semi-conductrice est inférieur au niveau de traitement de la deuxième puce semi-conductrice. La première puce semi-conductrice comprend un premier trou d'interconnexion traversant le silicium, et le premier trou d'interconnexion traversant le silicium forme une connexion électrique entre la première puce semi-conductrice et la troisième puce semi-conductrice. Ainsi, les coûts de fabrication peuvent être réduits et la stabilité des performances de la puce est assurée. Par conséquent, les performances de calcul de la deuxième puce semi-conductrice sont plus élevées, l'intégration de la puce semi-conductrice est plus poussée, la vitesse de transmission du signal est plus rapide et la bande passante est plus importante.
PCT/CN2021/100028 2021-06-15 2021-06-15 Emballage par empilement tridimensionnel et son procédé de fabrication WO2022261812A1 (fr)

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PCT/CN2021/100028 WO2022261812A1 (fr) 2021-06-15 2021-06-15 Emballage par empilement tridimensionnel et son procédé de fabrication
CN202180098310.XA CN117337489A (zh) 2021-06-15 2021-06-15 三维堆叠封装及三维堆叠封装制造方法

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733463A (zh) * 2013-12-18 2015-06-24 瑞萨电子株式会社 半导体器件
CN205039151U (zh) * 2015-09-24 2016-02-17 中芯长电半导体(江阴)有限公司 一种堆叠型芯片封装结构
CN109003963A (zh) * 2017-06-07 2018-12-14 三星电子株式会社 半导体封装及制造其的方法
US20200243422A1 (en) * 2019-01-25 2020-07-30 SK Hynix Inc. Semiconductor packages including bridge die
CN111613605A (zh) * 2019-02-22 2020-09-01 爱思开海力士有限公司 包括桥接管芯的系统级封装

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733463A (zh) * 2013-12-18 2015-06-24 瑞萨电子株式会社 半导体器件
CN205039151U (zh) * 2015-09-24 2016-02-17 中芯长电半导体(江阴)有限公司 一种堆叠型芯片封装结构
CN109003963A (zh) * 2017-06-07 2018-12-14 三星电子株式会社 半导体封装及制造其的方法
US20200243422A1 (en) * 2019-01-25 2020-07-30 SK Hynix Inc. Semiconductor packages including bridge die
CN111613605A (zh) * 2019-02-22 2020-09-01 爱思开海力士有限公司 包括桥接管芯的系统级封装

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