WO2012021310A1 - Ensemble de puces semi-conductrices divisées et technique d'encapsulation - Google Patents

Ensemble de puces semi-conductrices divisées et technique d'encapsulation Download PDF

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Publication number
WO2012021310A1
WO2012021310A1 PCT/US2011/045920 US2011045920W WO2012021310A1 WO 2012021310 A1 WO2012021310 A1 WO 2012021310A1 US 2011045920 W US2011045920 W US 2011045920W WO 2012021310 A1 WO2012021310 A1 WO 2012021310A1
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Prior art keywords
semiconductor
chip
semiconductor chip
memory
contacts
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PCT/US2011/045920
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English (en)
Inventor
Scott C. Best
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Rambus Inc.
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Publication of WO2012021310A1 publication Critical patent/WO2012021310A1/fr

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Definitions

  • the disclosure herein relates to semiconductors, and more particularly to semiconductor packages employing multiple integrated circuit chips.
  • Integrated circuit chips often aggregate logic and storage circuitry that carry out separate but complementary functions.
  • a memory core may employ arrays of specialized storage elements (including, for example, transistors, capacitors, etc.) optimized for data storage functions.
  • the same memory device usually includes an I/O interface circuit that has various logic gates optimized to handle a variety of logic-related functions relating to data transfers between the memory core and an external memory controller. Aggregating logic and memory circuits into one chip often involves compromises in power and performance.
  • Figure 1 A illustrates a side view of a semiconductor package including a disaggregated semiconductor die subassembly according to an embodiment
  • Figure IB illustrates a top plan view of the semiconductor package along line IB- IB of Figure 1A;
  • Figure 1C illustrates a partial detailed view of area 1C shown in Figure 1A;
  • Figure 2 illustrates a side view of a semiconductor package including a memory stack and an interface chip according to a further embodiment
  • Figure 3 illustrates a side view of a semiconductor package including a memory stack and multiple disaggregated interface chips according to further embodiments.
  • Figure 4 illustrates a side view of a semiconductor package including a memory stack and an interface chip according to yet another embodiment.
  • Embodiments of semiconductor packages including disaggregated memory devices are disclosed herein.
  • One embodiment of the package comprises a substrate having terminals for external connections and respective first and second semiconductor chips.
  • the first semiconductor chip has pads coupled to respective ones of the terminals and includes a metal layer.
  • the second semiconductor chip has pads coupled to respective ones of the terminals and includes a metal layer.
  • the semiconductor chip is attached to the first semiconductor chip and has first contacts electrically coupled to respective ones of the pads through the metal layer.
  • the second semiconductor chip overlies an area of the first semiconductor chip that is less than a surface area occupied by the pads. In this manner, significant cost advantages may be realized through the reduced-in-size second semiconductor chip.
  • a semiconductor memory device comprising a substrate having terminals for external connections.
  • the device includes a first memory chip having pads coupled to respective ones of the terminals and including a metal layer, and an interface chip including contacts.
  • the interface chip is configured as an interface circuit for the first memory chip and attached to the first memory chip.
  • the interface chip electrically couples to the substrate via the first memory chip metal layer.
  • a semiconductor package comprising a plurality of semiconductor memory devices disposed in a stack. Each of the memory devices is formed with sets of through-silicon vias to define communication paths within the stack.
  • the package further includes at least two semiconductor logic devices bonded to one of the plurality of semiconductor memory devices, each of the logic devices electrically coupled to a respective set of through-silicon vias.
  • a method of manufacturing a semiconductor package comprises forming a metal layer on a first semiconductor chip, the metal layer defining a pad region for coupling to a substrate.
  • the pad region defines a pad surface area.
  • a second semiconductor chip is bonded to the first semiconductor chip such that contacts on the second semiconductor chip electrically engage the metal layer.
  • the second semiconductor chip is formed with a footprint surface area that is less than the pad surface area.
  • Figure 1A illustrates a semiconductor package, generally designated 100, that includes a substrate 102 that mounts a disaggregated die subassembly 120 (in phantom).
  • the substrate 102 has two opposing surfaces 104 and 106 and comprises at least one routing layer.
  • the routing layer generally includes metal traces 108 that may be formed on a dielectric material.
  • the substrate 102 may further comprise conductive vias, such as via 110, formed to enable electrical connections between routing layers (where multiple routing layers are employed).
  • the substrate may be formed from materials such as conventional FR4 laminate, ceramic, organic, coreless, or the like depending on the application.
  • the substrate surfaces 104 and 106 respectively employ terminals or metal contact pads 112 for engaging conductive bumps or balls, such as ball grid array (BGA) contacts 114 or C4 bumps 116.
  • BGA contacts 114 render the substrate 102 suitable for mounting and electrically coupling to external counterpart landings on a daughterboard (not shown) or motherboard (e.g., a memory module, blade, or motherboard of a data processing system, including various consumer electronics devices such as gaming consoles, mobile telephones, personal digital assistants (PDAs), cameras, audio and video rendering devices, etc.) and thus allow coupling of the semiconductor package 100 to a larger electronics system.
  • This capability places certain requirements on the relative spacing or pitch between the BGA contacts 114, e.g., on the order of approximately one millimeter. Physical and mechanical constraints often dictate the pitch.
  • the substrate 102 also serves as a space transformer, in that the relatively wide pitch of the BGA contacts 114 and corresponding pads on the BGA side 106 of the substrate 102 may be tunneled and routed into a smaller area on the opposite side 104 of the substrate 102.
  • the substrate 102 employs the narrower-pitched C4 bumps 116 on the device side 104 that require a smaller pad area for mounting the disaggregated die subassembly 120.
  • C4 pad sizes may be spaced at an approximate pitch of one -hundred- fifty to two-hundred microns (center-to- center), with the corresponding pad metal for each pad measuring approximately sixty to ninety microns in diameter.
  • the disaggregated die subassembly 120 employs respective integrated circuit chips or dice 122 and 124 to, for example, provide storage and logic functions, respectively.
  • a dynamic random access memory (DRAM) device is one example of an application suitable for this architecture.
  • the storage chip 122 otherwise referred to as a "memory die", includes active circuitry 139 in the form of core storage circuitry and is manufactured predominantly in accordance with a process technology that balances low cost, memory cell density, and data retention.
  • the logic or "interface die” 124 includes active circuitry 135 in the form of interface circuitry and is formed predominantly in accordance with a process technology that yields high mobility, lower-gate-capacitance transistors.
  • active circuitry 135 in the form of interface circuitry and is formed predominantly in accordance with a process technology that yields high mobility, lower-gate-capacitance transistors.
  • the interface chip's 124 active circuitry 135 is capable of, among other things, performing interface functions for the memory die or chip 122, including processing command and data signals to carry out data storage and retrieval operations for the memory die or chip 122.
  • the minimum silicon die size necessary to implement the required logic gates to carry out the interface function would be a fraction of the memory die size. Minimizing die size is important since die silicon area has a direct bearing on cost (the smaller the die size, the larger the chip yield from a given wafer to amortize individual chip costs).
  • the memory die 122 and the interface die 124 need to be able to communicate signals via the appropriate contact pads 112 on the substrate 102 with a remotely disposed memory controller (not shown).
  • Typical memory devices may employ up to a few hundred pins or more.
  • the interface die size may be minimized, thereby significantly reducing cost for the semiconductor package 100.
  • the memory die 122 has a bulk substrate side 121 and an active side 123.
  • the active side 123 includes the active circuitry 139 and peripheral C4 pads
  • micro-contacts 126 at a pitch PI of about one-hundred- fifty to two-hundred microns that corresponds to the substrate C4 pitch described above
  • fine-pitch micro-contacts 128A/B The micro-contacts
  • first group of micro-contacts 128A may be employed for routing signals between the core storage circuitry 139 in the memory die 122 and the interface die 124.
  • the memory die 128B may be used for routing signals between the interface die 124 and electronic devices (not shown) external to the package, such as an external memory controller (not shown).
  • 122 includes a metal layer or redistribution layer (RDL), which includes conductive traces 125.
  • the traces 125 route signals between the C4 pads 126 and the second group of micro-contacts 128B.
  • RDL may be formed subsequent to standard die processing, which form the active circuitry 139 on the memory die and the die metal layers interconnecting the active circuitry.
  • the RDL may be formed during wafer or die testing and/or packaging (TAP) operations.
  • the memory die 122 communicates data and command signals with the interface die via the first group of micro-contacts 128 A, while power and ground connections may be by way of some of the second group of micro-contacts 128B, which are coupled to the C4 pads via the conductive traces
  • power and ground connections for the memory die 122 are routed directly via some of the C4 pads so the conductive traces 125 route signals solely between the interface die 124 and the substrate 102.
  • write data or command signals from an external memory controller are routed from respective BGA balls 114 to respective C4 balls 116 via respective traces and vias in the substrate 102, then to respective ones of the second group of micro contacts 128 A via the RDL layer.
  • the interface chip 124 includes active interface circuitry 135, which receives and processes the data and command signals before sending corresponding signals to the memory die 122 via the first group of micro contacts 128 A.
  • read data are fetched from the memory chip 122 and transferred via the first group of micro contacts 128A to the interface chip 124, which includes the active interface circuitry 135 to form corresponding read data signals and drive them out via the second group of micro contacts 128B.
  • the read data signals are thereafter routed via the RDL layer 125 on the memory device 122 to respective C4 pads 126 without going into any of the active circuitry 139 on the memory device 122. From the C4 pads 126, the read data signals are further routed to the memory controller via respective traces 108 and vias 110 in the substrate 102 and respective BGA balls 114.
  • the C4 pads 126 together form a pad region 130 (bounded by concentric phantom rectangles 150 and 151 surrounding the C4 pads 126) on the memory die 122 for flip-chip mounting to the substrate 102.
  • the area A underlying the interface chip 124 i.e., the area of the phantom rectangle 124 in FIG. IB
  • the area A is smaller than a total surface area of the C4 pads 126 on the memory die 122 (i.e., the sum of the surface areas covered by individual C4 pads 126), or
  • A is the area underlying the interface die
  • a k is the surface area covered by the k th C4 pad 126
  • n is the total number of the C4 pads 126, as illustrated in FIG. 1A.
  • the interface die 124 includes a bulk substrate surface 127 and an active surface 129, similar to the memory die 122. Further, micro- contacts 128A/B are formed on the interface die 124 and exhibit a pattern and pitch P2
  • thermo-compression metal-to-metal bonding process facilitates bonding of the interface die active surface 129 to the memory die active surface 123 in a face-to-face or confronting relationship.
  • the active surface 129 of the interface die 124 bonds directly to the active side or surface 123 of the memory die 122.
  • a realizable die size, shown in Figure IB at 124 (sufficient to support the contact pitch) is approximately 0.25 mm 2 (assuming a 12x12 array of contacts at a forty micron pitch, although only a 7x7 array is shown for purposes of illustration). This reflects a significant size reduction compared to, for example, the memory die size (represented in Figure IB by block 122) required to support one-hundred- forty-four C4 pad connections
  • the resulting interface die size (in terms of the active surface area) is less than the memory die pad region 130 surface area.
  • the disaggregated die subassembly 120 flip-chip mounts to the substrate C4 pads 112 in a straightforward manner such that the interface die 124 nests within a windowed array of C4 balls or bumps 1 16.
  • the interface die 124 may be thinned to ensure a thickness less than the height of a connected C4 bump.
  • Other embodiments may account for an unthinned interface die by incorporating an opening (not shown) in the substrate 102 sufficient to receive a portion of the interface die 124 if its height exceeds the height of a C4 ball 116.
  • the semiconductor package 100 may act like a discrete memory device (e.g., DRAM or flash).
  • the interface die 124 forms the I/O interface of the device by receiving command and address signals from a memory controller (not shown) and appropriately transferring data between the core storage circuitry 139 of the memory die 122 and the memory controller. From the perspective of the memory controller, the disaggregated memory device appears like any typical, "aggregated", single-die memory device.
  • line 133 represents a data flow routed along the channel during, for example, read data transmissions.
  • the data signals DATA are routed from the core circuitry 139 in the memory die 122 to the interface die 124 via the first group (e.g., group 128A as illustrated in FIG. 1A) of micro-contacts 128A/B.
  • the signals after being processed by active circuitry 135 disposed in the interface die 124, are sent off the die via a path formed collectively by one micro-contact from the second group (e.g., group 128B) of micro-contacts 128, the conductive traces 125, at least one of the C4 pads 126, bump 116, substrate pad 112, trace 108, via 110, and a BGA contact 114.
  • the path described identifies a singular collection of components to cooperatively form the path, multiple paths may route data in parallel, involving multiple micro-contacts, interconnections, etc.
  • Write operations generally involve a data flow along the described routing path opposite that of the flow described above.
  • the transmission line structure described above contributes to reduced power dissipation during operation.
  • power dissipation along a given memory channel may be categorized in terms of transmission line power (i.e., power which is approximately constant independent of transmission line length) and capacitive power (i.e., power that varies approximately linearly with trace length).
  • transmission line power i.e., power which is approximately constant independent of transmission line length
  • capacitive power i.e., power that varies approximately linearly with trace length.
  • the capacitive portion of the overall channel can be reduced while the transmission line is slightly lengthened, resulting in an overall reduction in device power.
  • Manufacture of the semiconductor package 100 involves straightforward packaging processes. As annunciated above, a manufacturer dices the interface die 124 from a wafer fabricated in accordance with a process technology optimized for high mobility, lower-gate-capacitance transistors. A process technology optimized for low cost, memory cell density, and data retention (such as DRAM or flash) is employed to make the memory die 122.
  • the memory die may employ a standard metal layer and connection pad structures, including the C4 pads 126 and micro-contacts 128A/B, or a subsequently formed redistribution layer (RDL) formed over a standard metal layer to redistribute connections from the standard metal layer to the C4 array and micro-contact structures.
  • RDL redistribution layer
  • the interface die 124 is directly bonded in a confronting relationship to the memory die 122.
  • the bonding may be carried out by any bonding technology appropriate for face-to-face chip bonding, including but not limited to thermo-compression metal-to-metal bonding, epoxy bonding, thermosonic bonding, or ultrasonic bonding techniques.
  • face-to-face bonding involves applying sufficient energy and pressure to form a metallurgic bond between the corresponding micro-contacts 128A/B of both dice.
  • the resulting subassembly 120 may then be flip-chip mounted to the substrate 102 using
  • a non-conductive housing e.g., a plastic over-mold, not shown
  • a BGA metallization process may be disposed over the substrate to cover the disaggregated subassembly, followed by a BGA metallization process to form the BGA area array.
  • FIG. 2 illustrates a further embodiment of a semiconductor package, generally designated 200.
  • the package employs a substrate 202 similar to that described in the embodiment illustrated in Figure 1A, with one side 203 incorporating an array of BGA contacts 204 that electrically interface to C4 contacts 206 disposed on an opposite side 205 via conductive paths 208 formed through the substrate.
  • the C4 contacts 206 bond to a disaggregated device 210 (in phantom) including an interface die 212 bonded to a first memory die 214a.
  • the first memory die 214a includes active circuitry 209, pads 216, conductive traces 217, and micro-contacts 228 formed from a metal layer (or subsequently applied redistribution layer RDL) to route signals between the C4 bumps 206 and the interface die 212.
  • the conductive traces 217, C4 pads 216, active circuitry 209, and micro-contacts 228 may be formed similar to the arrangements shown in Figure IB, although not limited solely to the arrangements shown.
  • the interface die 212 may be formed similar to that described in the previous embodiment, with active circuitry 229 and micro- contacts 230 for engaging the micro-contacts 228.
  • additional memory dies 214b through 214d are disposed over the first memory die 214a in a stacked configuration and electrically interconnected through multiple intra-stack busses 218 (in phantom) formed by through-silicon via (TSV) interconnect.
  • TSV bus 218 includes interconnected through-silicon vias 220 formed in each memory die, and connectors 222 in the form of TSV bonds that, when the memory dies are stacked, align with the vias 220 to form each path within the overall intra-stack TSV bus 218.
  • respective layers 224 of underfill material may be applied between the respective memory dies 214a- d at thicknesses matching the TSV connector 222 thickness.
  • the interface to TSV bus 218 aligns with micro-contacts 230 formed on the interface die 212 such that when bonded together, appropriate connections are formed between the interface die 212 and the first memory die 214a's interface to the TSV bus 218 (note that since the first memory die 214a includes TSV's that allow it to be interconnected from either the front or back side, the interface die 212 may be bonded to it in either a face-to-face or face-to-back arrangement).
  • one or more of the memory dies 214a-d are thinned in an effort to constrain the overall device height.
  • a non-conductive housing e.g., a plastic over-mold, not shown
  • the interface die 212 cooperates with the memory dice 214a-d to effect memory read and write operations. For example, during a read operation to access and transfer data from the memory core circuitry 209 in the memory die 214a-d and deliver it to an external memory controller (not shown), data may be routed along the path followed by line 232. This involves retrieving data DATA from respective cores of the memory devices 214a-d, and routing the data through an intra-stack bus 218 created by one or more TSV paths, which connect via micro-contacts 230 to the interface die 212.
  • the signals after being processed (via the interface circuitry 229) by the interface die 212, are sent off the die back to the first memory die 214a, where the data is received by micro-contacts 228 and routed by conductive traces 217 to one or more C4 pads 216.
  • the data further flows from the C4 pad 216, through C4 ball 206, and along trace 208 on the substrate 202 before exiting BGA contact 204. It should be understood that several paths may be routing data in parallel during the respective read and/or write operations, thus involving multiple contacts, pads, etc.
  • the semiconductor package 200 enjoys many of the benefits described with respect to the semiconductor package 100 shown in Figures 1A and IB, described previously. For example, routing signals between the interface die 212 and the C4 balls 206 along the conductive traces 217 formed on the first memory die 214a enables the interface die 212 to avoid being pad- limited, and thus significantly smaller in size. As explained above, this dramatically reduces costs. Further, in a through- silicon via context, disaggregating the interface die 212 from the memory dice 214a-214d, and employing conductive traces 217 from the interface die 212 to the C4 balls via the metal layer or RDL enables the interface die 212 to avoid having its own integrally formed TSVs.
  • TSV fabrication adds cost both in the manufacturing and attachment process.
  • TSV formation induces stresses on the chip during processing.
  • Manufacture of the semiconductor package 200 of Figure 2 involves similar process steps described with respect to the previous package 100 of Figure 1A, namely, fabrication of process technology-specific interface and memory dies 212 and 214a-214d, and flip-chip bonding of the disaggregated subassembly 210 to the substrate 202.
  • Three of the four memory dies may undergo additional processing to form the through-silicon vias 220 (memory die 214d is shown as slightly thicker than 214a-214c to imply this).
  • Through-silicon- vias are typically formed using vertical metal interconnects (e.g., copper or tungsten) resulting from chemical etching or laser drilling, followed by a metal deposition process.
  • a wafer-thinning process follows metal deposition to fully expose the TSVs. Further details regarding TSV formation are known to those skilled in the art and warrant no further disclosure herein.
  • the various TSV connectors 222 and underfill layers 224 are applied to properly stack and electrically interconnect the dice to form the TSV busses 218.
  • FIG 3 illustrates yet another embodiment of a semiconductor package, generally designated 300.
  • the package includes a substrate 302 having substrate C4 pads 303 constructed similarly to previous embodiments, and stacked memory dies 304a-304d with multiple intra- stack TSV busses 312 similar to the TSV busses 218 shown in Figure 2.
  • the multiple TSV busses are distributed across the memory dies 304a-304d, and are terminated at multiple interface dies 308 and 310.
  • Each interface die is formed similar to those described in the embodiments illustrated by Figures 1 A, IB, and 2.
  • the bottom-most memory device 304a employs conductive traces 307, micro-contacts 309, and C4 pads 311 along a metal layer or redistribution layer for routing signals between the substrate 302 and the interface dice 308 and 310.
  • active circuitry formed in both the interface dice 308, 310 and the memory dice 304a-d are not illustrated in the Figures, although understood to be formed similar to the embodiments shown in Figures 1A, 1C, and 2.
  • TSV busses 312 across the memory dies 304a-d minimizes horizontal wire routing lengths between core circuitry on each memory die and each TSV bus 312. This is apparent when considering line 313 as one data flow path in the event of a read operation.
  • Transmitted read data enters respective portions of the TSV bus 312 from the core circuitry disposed in the respective memory devices 304a-d to the interface die 308, and back to the lower-most memory die 304a via the micro-contacts 309, conductive traces 307, and C4 pads 311.
  • individual wire lengths for each TSV bus 312 are minimized. Consistent with the previous discussion concerning capacitive power, minimizing horizontal wire lengths along the memory dies 304a-d correspondingly reduces capacitive power dissipation resulting from the wires, thus reducing overall power consumption.
  • TSV busses 312 may be used to "cap" the respective TSV busses 312 that are smaller in aggregate than a single interface die required to cover all of the TSV busses.
  • the distributed TSV configuration described above is especially useful for graphics applications, where capacitive power is of utmost concern (due to the very high on-chip data bandwidth in the memory core).
  • additional metal layer connections and paths may be routed between the dies 308 and 310 along the metal layer disposed on the bottom-most memory die 304a.
  • paths 319 may be provided on the substrate 302 to connect adjacent C4 bumps, such as those at 320 and 322.
  • the connections may include command, control and other coordination signal paths defining one or more communication busses.
  • FIG. 4 illustrates yet another embodiment of a semiconductor package, generally designated 400, employing a disaggregated chip subassembly 402 (in phantom) supported by a common substrate 406.
  • the substrate 406 is optimized for package-on-package (POP) applications, including, for example, a 2-layer substrate configuration with POP BGA contacts 408 disposed on an area array side 410, and wirebond pads 412 formed on the other side of the substrate 406.
  • POP package-on-package
  • the disaggregated chip subassembly 402 includes a stack of memory dies 404a-404d. Unlike the stacked die configurations described earlier with respect to embodiments illustrated in Figures 2 and 3, the stack of Figure 4 is oriented such that the active surface of interface die 418 faces downwards, towards the substrate 406, while the active surface of a stacked memory device without TSV's (e.g., memory device 404a, shown as slightly thicker than memory devices 404b-d in Figure 4 to imply this) faces upwards, away from the substrate (note that memory dies 404b-d, which are processed with TSV's, may face either upwards or downwards, as their TSV's allow them to be interconnected from either side).
  • a stacked memory device without TSV's e.g., memory device 404a, shown as slightly thicker than memory devices 404b-d in Figure 4 to imply this
  • memory dies 404b-d which are processed with TSV's, may face either upwards or downwards,
  • TSV busses 416 are formed through the memory dies 404a-d in a top-down configuration to define TSV busses that are accessible by an interface chip 418 through direct bonding to the top-most die of the memory stack.
  • active circuitry formed in both the interface die 418 and the memory dice 404a-d are not illustrated in the Figures, although understood to be formed similar to the embodiments shown in Figures 1 A, IB, and 2.
  • the interface die 418 is bonded to the top-most memory die 404d in the stack using, for example, thermo-compression metal-to -metal bonding technology (note that since the top-most memory die 404d includes TSV's that allow it to be interconnected from either the front or back side, the interface die 418 may be bonded to it in either a face-to-face or face-to-back arrangement).
  • the top-most memory die 404d in the stack employs conductive traces 420 along a metal layer or RDL for routing signals between wirebond pads 422 of the topmost memory die and the interface die 418.
  • Micro-contact connections and bonds formed between the interface die 418 and the memory die 404d are similar to those described in the previous embodiments and for purposes of brevity, are not described further.
  • the wirebond pads 422 formed in the metal layer provide landings for wirebond connections between the subassembly 402 and the substrate 406.
  • the wirebond structures provide a packaging alternative to using C4 bumps that, depending on the application, may provide a lower cost assembly process.
  • data accessed from respective memory cores in the memory dice 404a-d is routed to one or more TSV busses 416, as shown by data flow line 430.
  • the data routes to the interface die 418, and after being appropriately processed by the interface die 418, exits back to the top-most memory die 404d.
  • Conductive traces 420 route the data along the top-most memory die to the wirebond pads 422, and down to the substrate 406 via wirebond wires 411. At the substrate level, the data routes along substrate trace 413 and eventually out to BGA contacts 408.
  • Such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits.
  • a processing entity e.g., one or more processors
  • Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
  • signals described or depicted as having active-high or active- low logic levels may have opposite logic levels in alternative embodiments.
  • Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented.
  • MOS metal oxide semiconductor
  • a signal is said to be "asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition.
  • a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition).
  • a signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits.
  • a signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted.
  • the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state).
  • a line over a signal name e.g., ' ⁇ signal name > ' is also used to indicate an active low signal.
  • the term "coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures.
  • Integrated circuit device "programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device.
  • a one-time programming operation e.g., blowing fuses within a configuration circuit during device production
  • reference voltage lines also referred to as strapping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un boîtier de semi-conducteurs. Le boîtier comprend un substrat comportant des bornes pour des connexions extérieures et des première et seconde puces semi-conductrices respectives. La première puce semi-conductrice possède des plages de connexion couplées aux bornes respectives et comprend une couche de métal. La seconde puce semi-conductrice est attachée à la première puce semi-conductrice et possède des premiers contacts couplés électriquement aux plages de connexion respectives par l'intermédiaire de la couche de métal. La seconde puce semi-conductrice recouvre une surface de la première puce semi-conductrice qui est inférieure à une surface occupée par les plages de connexion.
PCT/US2011/045920 2010-08-09 2011-07-29 Ensemble de puces semi-conductrices divisées et technique d'encapsulation WO2012021310A1 (fr)

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WO2016077488A1 (fr) * 2014-11-11 2016-05-19 Texas Instruments Incorporated Boîtier pour système électronique comportant des puces de semi-conducteur
CN112151527A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括分叉存储器模块的高容量半导体器件

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US6008542A (en) * 1997-08-27 1999-12-28 Nec Corporation Semiconductor device having long pads and short pads alternated for fine pitch without sacrifice of probing
US20050199991A1 (en) * 2004-03-12 2005-09-15 Shin-Hua Chao Multi-chip package structure
US20050218518A1 (en) * 2002-01-07 2005-10-06 Tongbi Jiang Semiconductor device assemblies and packages including multiple semiconductor device components
US20100091537A1 (en) * 2006-12-14 2010-04-15 Best Scott C Multi-die memory device
US20100164094A1 (en) * 2008-12-26 2010-07-01 Chung Hoe-Ju Multi-Chip Package Memory Device

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US6008542A (en) * 1997-08-27 1999-12-28 Nec Corporation Semiconductor device having long pads and short pads alternated for fine pitch without sacrifice of probing
US20050218518A1 (en) * 2002-01-07 2005-10-06 Tongbi Jiang Semiconductor device assemblies and packages including multiple semiconductor device components
US20050199991A1 (en) * 2004-03-12 2005-09-15 Shin-Hua Chao Multi-chip package structure
US20100091537A1 (en) * 2006-12-14 2010-04-15 Best Scott C Multi-die memory device
US20100164094A1 (en) * 2008-12-26 2010-07-01 Chung Hoe-Ju Multi-Chip Package Memory Device

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Publication number Priority date Publication date Assignee Title
WO2016077488A1 (fr) * 2014-11-11 2016-05-19 Texas Instruments Incorporated Boîtier pour système électronique comportant des puces de semi-conducteur
US10109614B2 (en) 2014-11-11 2018-10-23 Texas Instruments Incorporated Silicon package for embedded electronic system having stacked semiconductor chips
CN112151527A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括分叉存储器模块的高容量半导体器件

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