WO2022259327A1 - Procédé de fabrication de composants semi-conducteurs, et tranche composite - Google Patents

Procédé de fabrication de composants semi-conducteurs, et tranche composite Download PDF

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Publication number
WO2022259327A1
WO2022259327A1 PCT/JP2021/021612 JP2021021612W WO2022259327A1 WO 2022259327 A1 WO2022259327 A1 WO 2022259327A1 JP 2021021612 W JP2021021612 W JP 2021021612W WO 2022259327 A1 WO2022259327 A1 WO 2022259327A1
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Prior art keywords
wafer
semiconductor
chip
semiconductor chip
support wafer
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PCT/JP2021/021612
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English (en)
Japanese (ja)
Inventor
耕平 瀬山
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株式会社新川
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Priority to PCT/JP2021/021612 priority Critical patent/WO2022259327A1/fr
Publication of WO2022259327A1 publication Critical patent/WO2022259327A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Definitions

  • the present invention relates to a semiconductor component manufacturing method and a composite wafer.
  • Patent Literature 1 discloses a technique for manufacturing a semiconductor component in which a plurality of semiconductor chips are stacked. The semiconductor chips are bonded together by a thermosetting bonding member. However, when the number of laminated semiconductor chips increases, a temperature difference occurs between a bonding member arranged at a position close to a heating point and a bonding member arranged at a position far from the heating point. Focusing on such a problem, Patent Document 1 discloses a technique capable of appropriately mounting a plurality of semiconductor chips even when the number of stacked semiconductor chips is large.
  • a load may be applied to the semiconductor chip.
  • Heat may be provided to the semiconductor chip when the semiconductor chip is mounted on the semiconductor substrate.
  • the semiconductor chips arranged around the semiconductor chip to be processed may also be affected by the process.
  • the influence on semiconductor chips that are not to be processed may cause defects in semiconductor components. As a result, a semiconductor component that may cause a malfunction is manufactured, resulting in a decrease in yield.
  • An object of the present invention is to provide a semiconductor component manufacturing method and a composite wafer that can suppress a decrease in yield.
  • a semiconductor component manufacturing method is a composite wafer comprising a base wafer including a plurality of arrangement regions to which semiconductor chips are bonded, and a support wafer detachably bonded to the base wafer.
  • the thickness of the support wafer is greater than the thickness of the base wafer, and the support wafer includes a thermal barrier portion formed to surround the placement region in plan view; preparing a composite wafer; and mounting a semiconductor chip in the placement region using a chip bonding member.
  • the base wafer is bonded to the support wafer.
  • the support wafer includes a thermal barrier formed to surround the placement area of the base wafer.
  • the thermal barrier section prevents the heat from affecting another arrangement area adjacent to the arrangement area. suppress As a result, unintended thermal hardening of the chip bonding member is suppressed. Therefore, each semiconductor chip can be mounted in a desired manner. Therefore, a decrease in yield can be suppressed.
  • the support wafer may have a support wafer bonding surface to which the base wafer is detachably bonded, and a support wafer rear surface opposite to the support wafer bonding surface.
  • the thermal barrier portion may extend from the back surface of the support wafer toward the support wafer bonding surface. According to this configuration, the flatness of the support wafer bonding surface can be maintained.
  • the thermal barrier section may be composed of a groove having an opening on the back surface of the support wafer and a molding material filled in the groove.
  • the thermal barrier portion may be a gap formed by a groove having an opening on the back surface of the support wafer. According to this configuration, a heat shielding effect can be obtained with a simple structure.
  • the step of mounting a semiconductor chip may include a step of placing a chip bonding member on a base wafer bonding surface of a base wafer on which a plurality of placement regions are set. According to this step, it is possible to suppress the occurrence of unintended thermal hardening of another chip bonding member adjacent to the chip bonding member that is being thermally cured.
  • the step of mounting a semiconductor chip includes a step of arranging a chip bonding member, and after mounting the semiconductor chip on the chip bonding member, pressing the semiconductor chip toward the composite wafer while pressing the semiconductor chip through the semiconductor chip. and applying heat to the joining member.
  • the chip bonding members can be collectively arranged on the base mounting surface.
  • the step of mounting a semiconductor chip includes the step of providing a chip bonding member on the chip bonding surface of the semiconductor chip facing the base wafer bonding surface, and the step of arranging the chip bonding member.
  • a step of placing a semiconductor chip provided with a chip bonding member on a substrate, and a step of applying heat to the chip bonding member through the semiconductor chip while pressing the semiconductor chip provided with the chip bonding member toward the composite wafer; may include According to these steps, a chip bonding member can be arranged for each semiconductor chip.
  • one semiconductor chip provided with a chip bonding member may be placed in one placement area. According to this process, a semiconductor component with a simple structure can be manufactured.
  • a plurality of semiconductor chips provided with chip bonding members may be stacked in one placement area. According to this process, a laminated semiconductor component can be manufactured.
  • a composite wafer which is another aspect of the present invention, comprises a base wafer including a plurality of arrangement regions to which semiconductor chips are bonded, and a support wafer detachably bonded to the base wafer.
  • the thickness of the support wafer is greater than the thickness of the base wafer.
  • the support wafer includes a thermal barrier formed to surround the arrangement area in plan view.
  • the support wafer includes a thermal barrier formed to surround the placement area of the base wafer.
  • the thermal barrier section prevents the heat from affecting another arrangement area adjacent to the arrangement area. suppress As a result, unintended thermal hardening of the chip bonding member is suppressed.
  • each semiconductor chip can be mounted in a desired manner. Therefore, it is possible to reduce the number of semiconductor components that may malfunction. Therefore, a decrease in yield can be suppressed.
  • a semiconductor component manufacturing method and a composite wafer capable of suppressing a decrease in yield are provided.
  • FIG. 1 is a schematic diagram showing a bonding apparatus used in a method of manufacturing a semiconductor device.
  • FIG. 2 is a perspective view of the composite wafer viewed from the base wafer side.
  • FIG. 3 is a perspective view of the composite wafer viewed from the support wafer side.
  • FIG. 4 is a plan view showing an enlarged part of the support wafer of the composite wafer.
  • FIG. 5 is a cross-sectional view taken along line V-V in FIG. 6(a), 6(b) and 6(c) are diagrams showing steps of preparing a composite wafer included in the method of manufacturing a semiconductor component according to the first embodiment.
  • FIG. 7(a) is a diagram showing a step of preparing a composite wafer following FIG. 6(c).
  • FIG. 7(b) and 7(c) are diagrams showing the process of mounting the semiconductor chip subsequent to FIG. 7(a).
  • 8(a), 8(b) and 8(c) are diagrams showing the process of mounting the semiconductor chip subsequent to FIG. 7(c).
  • 9(a) and 9(b) are diagrams showing the process of cutting into semiconductor components.
  • 10(a), 10(b) and 10(c) are diagrams showing the step of cutting into semiconductor components following FIG. 9(b).
  • FIG. 11(a) is an enlarged perspective view for explaining the effect of the composite wafer of the comparative example.
  • FIG. 11(b) is an enlarged perspective view for explaining the effects of the composite wafer of the embodiment.
  • FIG. 12(a) and 12(b) are diagrams showing steps of mounting a semiconductor chip in the method of manufacturing a semiconductor component according to the second embodiment.
  • FIG. 13 is a diagram showing the process of mounting the semiconductor chip following FIG. 12(b).
  • 14(a) and 14(b) are diagrams showing steps of mounting a semiconductor chip included in the method of manufacturing a semiconductor component according to the third embodiment.
  • 15(a) and 15(b) are diagrams showing the process of mounting the semiconductor chip subsequent to FIG. 14(b).
  • a bonding apparatus 100 mounts a semiconductor chip 30, which is an example of an electronic component, on a composite wafer 1.
  • a semiconductor component 90 (see FIG. 10(c)) including a portion of the composite wafer 1 and the semiconductor chip 30 is obtained.
  • the mutually orthogonal X-axis and Y-axis are directions parallel to the main surface of the semiconductor chip 30 .
  • the plane defined by the mutually orthogonal X-axis and Y-axis may be the main surface of either stage.
  • the Z-axis is perpendicular to the X-axis and also perpendicular to the Y-axis.
  • the bonding apparatus 100 will be explained. As shown in FIG. 1, the bonding apparatus 100 has a chip stage 101, an intermediate stage 102, a bonding stage 103, a bonding unit 104, an XY stage 105, and a bonding controller.
  • the bonding controller is simply referred to as "controller 106" in the following description.
  • a wafer 110 including a plurality of semiconductor chips 30 is temporarily placed on the chip stage 101 .
  • a wafer 110 is fixed to the chip stage 101 with an adhesive film (not shown).
  • a semiconductor chip 30 is temporarily placed on the intermediate stage 102 .
  • the intermediate stage 102 detachably holds the semiconductor chip 30 with an adhesive film (not shown).
  • Intermediate stage 102 is arranged between chip stage 101 and bonding stage 103 .
  • the intermediate stage 102 is configured to be movable in the X-axis direction and the Y-axis direction by a driving mechanism such as a linear motor (not shown).
  • a composite wafer 1 is placed on the bonding stage 103 .
  • the composite wafer 1 will be explained later in detail.
  • the bonding stage 103 detachably holds the composite wafer 1 with an adhesive film (not shown).
  • the bonding stage 103 can move the composite wafer 1 in the X-axis direction and/or the Y-axis direction by a drive mechanism (not shown) including guide rails.
  • the bonding stage 103 may have a heater for heating the composite wafer 1 .
  • the bonding stage 103 may have a light source 103a for irradiating the composite wafer 1 with ultraviolet light.
  • the bonding unit 104 has a bonding head 104a, a bonding tool 104b, a Z-axis driving mechanism 104c, and an imaging section 104d.
  • the bonding head 104 a is attached to the XY stage 105 .
  • the bonding head 104a is movable in the X-axis direction and the Y-axis direction.
  • a bonding tool 104b is attached to the bonding head 104a via a Z-axis drive mechanism 104c.
  • the bonding tool 104b has an air vacuum function.
  • the bonding tool 104b can suck the semiconductor chip 30 by the air vacuum function.
  • the bonding tool 104b has an air blow function.
  • the bonding tool 104b can separate the semiconductor chip 30 by the air blow function.
  • the imaging unit 104d is also attached to the bonding head 104a.
  • the bonding head 104a is moved by the XY stage 105, the bonding tool 104b attached to the bonding head 104a and the imaging section 104d are also moved.
  • the imaging unit 104d is separated from the bonding tool 104b by a predetermined distance in the Y-axis direction.
  • the imaging unit 104 d images the semiconductor chip 30 placed on the intermediate stage 102 .
  • the imaging unit 104 d images the semiconductor chip 30 placed on the bonding stage 103 .
  • the imaging unit 104d may not be fixed to the bonding head 104a.
  • the imaging unit 104d may be movable separately from the bonding tool 104b.
  • a composite wafer 1 is a composite semiconductor wafer including two semiconductor wafers. Specifically, composite wafer 1 includes base wafer 10 and support wafer 20 . Note that the composite wafer 1 may include a wafer formed of a material different from that of the semiconductor wafer. For example, composite wafer 1 may include a glass wafer.
  • FIG. 2 is a perspective view of the composite wafer 1 viewed from the base wafer 10 side.
  • the base wafer 10 is, for example, a silicon thin film wafer.
  • the base wafer 10 is separated into individual pieces in a later process to form semiconductor components 90 together with the semiconductor chips 30 .
  • the base wafer 10 includes a circuit forming surface 10a to which semiconductor chips 30 are bonded, and a base wafer bonding surface 10b (see FIG. 5) to which the support wafer 20 is bonded.
  • a plurality of arrangement regions P arranged two-dimensionally are set on the circuit forming surface 10a.
  • One or a plurality of semiconductor chips 30 are mounted in one placement region P.
  • the thickness of the base wafer 10 is, for example, approximately 100 ⁇ m.
  • a support wafer 20 is bonded to the base wafer 10 to facilitate handling during transportation.
  • FIG. 3 is a perspective view of the composite wafer 1 viewed from the support wafer 20 side.
  • Support wafer 20 defines the stiffness of composite wafer 1 .
  • the stiffness of the support wafer 20 is greater than the stiffness of the base wafer 10 .
  • the rigidity of support wafer 20 is provided by the thickness of support wafer 20 .
  • the thickness of support wafer 20 is greater than the thickness of base wafer 10 .
  • the thickness of the support wafer 20 is approximately 500 ⁇ m.
  • Support wafer 20 may be made of the same material as base wafer 10 . According to this configuration, the coefficient of thermal expansion of the base wafer 10 and the coefficient of thermal expansion of the support wafer 20 are the same.
  • the support wafer 20 is made of silicon.
  • the material of support wafer 20 may be different than the material of base wafer 10 .
  • glass may be used as the material of the support wafer 20 .
  • the shape of the support wafer 20 is the same as that of the base wafer 10 except that the thickness of the support wafer 20 is different from that of the base wafer 10 .
  • the support wafer 20 has a support wafer bonding surface 20a (see FIG. 5) and a support wafer back surface 20b.
  • a base wafer 10 is bonded to the support wafer bonding surface 20a.
  • the support wafer 20 does not constitute a semiconductor component 90 .
  • the support wafer 20 is removed at a certain point in the process of manufacturing the semiconductor component 90 (step S10: see FIG. 9B, etc.). Therefore, a bonding member whose bonding strength can be controlled is used for bonding the support wafer 20 and the base wafer 10 .
  • the bonding member whose bonding strength can be controlled for example, a resin material whose bonding strength can be weakened by being irradiated with ultraviolet rays is used.
  • the support wafer 20 transmits light having a predetermined wavelength.
  • the support wafer 20 has a thermal barrier portion 21 formed therein.
  • the thermal barrier section 21 includes a plurality of barriers 22 arranged in a grid. Barrier 22 impedes heat transfer in the diametrical direction of support wafer 20 .
  • a grid formed by the plurality of barriers 22 corresponds to the arrangement region P described above.
  • One grid corresponds to one placement area P.
  • FIG. The thermal barrier portion 21 is formed so as to surround the semiconductor chip 30 when the composite wafer 1 is viewed from above.
  • FIG. 4 is a plan view showing an enlarged peripheral portion of the back surface 20b of the support wafer.
  • the edge of each barrier 22 does not reach the outer edge 20 e of the support wafer 20 .
  • a wallless region 25 in which the barrier 22 is not formed is formed around the outer circumference of the support wafer 20 .
  • the support wafer 20 includes a region with walls 26 in which a plurality of barriers 22 are formed and a region without walls 25 in which no barriers 22 are formed.
  • the non-walled region 25 is formed in a ring shape so as to surround the walled region 26 .
  • the wallless region 25 allows the stiffness of the support wafer 20 to be less affected by the formation of the barrier 22 . Therefore, deterioration in rigidity of the support wafer 20 can be suppressed.
  • the barriers 22 are formed in regions corresponding to gaps between the semiconductor chips 30 adjacent to each other. Semiconductor chip 30 is not placed above barrier 22 .
  • the width of the barrier 22 may be larger than the interval between the semiconductor chips 30 .
  • the width of the barrier 22 may be smaller than the spacing between the semiconductor chips 30 .
  • the width of the barrier 22 may be substantially the same as the spacing between the semiconductor chips 30 .
  • the barrier 22 includes a portion that does not completely surround the outermost arrangement area P.
  • the placement region P1 is surrounded by barriers 22 on four sides.
  • the barriers 22 surrounding the placement region P1 are connected to each other.
  • a barrier 22 is also formed around the placement region P2. Barriers 22 are formed near some sides of the arrangement region P2.
  • “surrounding the placement region” means not only the case where the barriers 22 are formed near all four sides like the placement region P1, but It also includes the case where the barrier 22 is formed in the vicinity of some sides.
  • the barrier 22 surrounding the placement region P2 includes non-connected portions 27 that are not connected to each other. Such unconnected portions 27 are formed by protrusions 28 of barrier 22 .
  • the heat path from one arrangement area P2 to the other arrangement area P2 can be lengthened. Therefore, heat applied to one semiconductor chip 30 can be suppressed from being transferred to the other semiconductor chip 30 .
  • the non-connecting portion 27 is formed on the side where the semiconductor chip 30 does not exist next to it. Such a non-connecting portion 27 avoids the formation of the groove 23 in the region near the outer peripheral edge 20e of the support wafer 20, which causes a decrease in rigidity. Therefore, deterioration in rigidity of the support wafer 20 can be suppressed.
  • the barrier 22 is composed of a groove 23 and a molding material 24.
  • the groove 23 includes an opening 23a provided on the support wafer rear surface 20b and a bottom surface 23b formed on the support wafer bonding surface 20a side.
  • the groove 23 does not reach the support wafer bonding surface 20a.
  • the depth of the groove 23 is defined by the distance from the back surface 20b of the support wafer to the bottom surface 23b.
  • the depth of groove 23 is deeper than about half the thickness of support wafer 20 .
  • the depth of groove 23 may be about half the thickness of support wafer 20 .
  • the depth of groove 23 may be less than half the thickness of support wafer 20 .
  • the grooves 23 are filled with a molding material 24 such as resin.
  • the molding material 24 compensates for the stiffness of the support wafer 20 which is reduced due to the formation of the grooves 23 .
  • the molding material 24 constitutes a thermal resistance portion in the diametrical direction of the support wafer 20 .
  • the thermal conductivity of molding material 24 is significantly lower than that of support wafer 20 .
  • the coefficient of thermal expansion of the molding material 24 is preferably close to that of the support wafer 20 .
  • a composite wafer 1 is prepared (steps S1 to S4).
  • a wafer 20S is prepared (step S1: FIG. 6A).
  • cuts are formed in the back surface 20b of the support wafer (step S2: FIG. 6B).
  • the molding material 24 is poured into the grooves 23 (step S3: FIG. 6(c)).
  • the support wafer 20 including the thermal barrier portion 21 is obtained.
  • a wafer bonding member 42 is applied to the support wafer bonding surface 20a.
  • the base wafer 10 is bonded to the support wafer 20 (step S4: FIG. 7(a)).
  • a composite wafer 1 is obtained through the above steps S1 to S4.
  • a semiconductor chip is mounted (steps S5 to S8).
  • the composite wafer 1 is placed on the bonding stage 103 (step S5: FIG. 7(b)).
  • a film-like chip bonding member 41 is arranged on the circuit forming surface 10a of the base wafer 10 (step S6: FIG. 7(c)).
  • the chip bonding member 41 is, for example, a non-conductive film material called NCF (Non Conductive Film). After being sandwiched between the semiconductor chip 30 and the base wafer 10, the chip bonding member 41 is cured by heat.
  • the chip bonding member 41 has a softening start temperature and a hardening start temperature.
  • the curing initiation temperature is higher than the softening initiation temperature.
  • the tip joining member 41 does not exhibit fluidity.
  • the chip bonding member 41 maintains a film-like shape, for example.
  • the tip joining member 41 exhibits fluidity. In a fluid state, the chip joining member 41 is easily deformed by external force. Therefore, it is possible to fill the gap between the semiconductor chip 30 and the base wafer 10 without gaps.
  • the temperature of the chip bonding member 41 is higher than the curing start temperature, the chip bonding member 41 is gradually cured.
  • the semiconductor chip 30 is joined (steps S7 and S8).
  • the bonding apparatus 100 picks up the semiconductor chip 30 from the intermediate stage 102 by the bonding tool 104b.
  • the bonding apparatus 100 mounts the semiconductor chip 30 on a predetermined placement area P (step S7: FIG. 8A).
  • the bonding apparatus 100 continuously performs the next process (step S8) without separating the semiconductor chip 30 from the bonding tool 104b.
  • the bonding apparatus 100 raises the temperature of the bonding tool 104b. As the temperature of the bonding tool 104b rises, the temperature of the chip bonding member 41 becomes higher than the softening starting point, and the chip bonding member 41 exhibits fluidity.
  • the bonding apparatus 100 presses the bonding tool 104b against the composite wafer 1 side. As a result, the chip bonding member 41 exhibiting fluidity completely fills the gap between the semiconductor chip 30 and the base wafer 10 .
  • the load applied to the semiconductor chip 30 by the bonding tool 104b is set such that the softened chip bonding member 41 is pushed aside and the bumps 33 come into contact with the electrode terminals 11 and the bumps 33 are not significantly deformed.
  • the bonding tool 104b When the temperature of the bonding tool 104b further rises and the temperature of the chip bonding member 41 becomes higher than the curing start temperature, the chip bonding member 41 exhibiting fluidity starts to be cured. When the temperature of the bonding tool 104b further increases and the temperature of the bumps 33 becomes higher than the melting temperature, the bumps 33 melt. The melted chip joining member 41 adheres to the electrode terminal 11 . As a result, the bumps 33 are electrically joined to the electrode terminals 11 . After that, the bonding tool 104 b is separated from the semiconductor chip 30 .
  • the heat provided from the bonding head 104a is transmitted through the inside of the composite wafer 1 and tries to diffuse to the surroundings. Heat diffusion is suppressed by the barrier 22 in the diameter direction of the composite wafer 1 . In other words, heat is less likely to move to another placement region P adjacent to the placement region P where the semiconductor chip 30 is bonded. As a result, an increase in the temperature of the chip bonding member 41 in the adjacent arrangement region P is suppressed, so that unintended thermal hardening of the chip bonding member 41 is suppressed.
  • This suppression effect is particularly effective when the temperature of the bonding tool 104b is higher than the hardening start temperature of the chip bonding member 41 . It is also effective when the temperature of the bonding tool 104 b is higher than the melting temperature of the bumps 33 .
  • the action of the thermal barrier section 21 will be described later in detail.
  • the semiconductor chips 30 are bonded one by one. As a result, a plurality of semiconductor chips 30 are mechanically and electrically bonded to the base wafer 10 (see FIG. 8(c)).
  • the semiconductor component 90 is cut into pieces (steps S9 to S11).
  • a buried region 302 is formed (step S9: FIG. 9A).
  • a buried region 302 is formed so as to cover the circuit formation surface 10 a of the base wafer 10 and the semiconductor chip 30 .
  • the embedded region 302 may be made of, for example, a resin material.
  • the base wafer 10 is removed from the support wafer 20.
  • the back surface 20b of the support wafer 20 is irradiated with ultraviolet rays L (step S10: FIG. 9B). As a result, the bonding strength of the wafer bonding member 42 is lowered.
  • the base wafer 10 can be removed from the support wafer 20 (see FIG. 10(a)).
  • a dicing cutter 301 or the like is used to cut the semiconductor component 90 (step S11: FIG. 10B).
  • a plurality of individualized semiconductor components 90 are obtained (see FIG. 10(c)).
  • the semiconductor component manufacturing method uses a composite wafer 1 including a base wafer 10 including a plurality of placement regions P to which semiconductor chips 30 are bonded, and a support wafer 20 detachably bonded to the base wafer 10 .
  • the thickness of support wafer 20 is greater than the thickness of base wafer 10 .
  • the support wafer 20 includes a thermal barrier portion 21 formed to surround the placement region P in plan view.
  • the method for manufacturing the semiconductor component 90 includes steps of preparing the composite wafer 1 (steps S1 to S4) and steps of mounting the semiconductor chips 30 in the arrangement region P using the thermosetting chip bonding member 41 (steps S5 to S8). ) and
  • the base wafer 10 is bonded to the support wafer 20.
  • the support wafer 20 includes a thermal barrier section 21 formed so as to surround the placement region P of the base wafer 10 .
  • the thermal barrier section 21 is formed in another arrangement area adjacent to the certain arrangement area P. suppress the effect of heat on P;
  • FIG. 11(a) is a perspective view showing an enlarged part of the composite wafer 1E of the comparative example.
  • a composite wafer 1 ⁇ /b>E of the comparative example does not have the thermal barrier section 21 .
  • a region R1 is a heat input surface that receives heat from the bonding tool 104b.
  • the heat tries to diffuse inside the base wafer 10 and the support wafer 20E.
  • attention is paid to the direction from a region R1 to the adjacent region R2.
  • the movement of heat H is expressed by equation (1) when the amount of heat flowing per unit area (q: heat flux) is defined.
  • q Q/A (1)
  • heat flux Q heat quantity A: area
  • Equation (3) is obtained from equations (1) and (2).
  • Q - ⁇ dT/dx ⁇ A (3) That is, the amount of heat transferred (Q) is proportional to the area and the temperature gradient.
  • a plane N1 positioned between a region R1 and an adjacent region R2 is defined.
  • Surface N1 includes base wafer 10 and support wafer 20 .
  • the entire surface N1 can be defined as contributing to heat transfer.
  • the amount of heat (Q) transferred from one region R1 to the adjacent region R2 increases.
  • unintended thermal hardening of the chip bonding member 41 may occur in part of the adjacent region R2.
  • the intended bonded state may not be formed.
  • the semiconductor chip 30 may be tilted. If the semiconductor chip 30 is tilted, contact failure between the bumps 33 and the electrode terminals 11 may occur.
  • FIG. 11(b) is a perspective view showing an enlarged part of the composite wafer 1 of the embodiment.
  • a plane N2 positioned between a region R1 and an adjacent region R2 is defined.
  • Surface N2 includes barrier 22 in addition to base wafer 10 and support wafer 20 .
  • the partial region N2a of the surface N2 can be defined as contributing to heat transfer.
  • the barrier 22 since the barrier 22 has higher thermal resistance than the base wafer 10 and the support wafer 20, it can be considered that it does not substantially contribute to heat transfer. Then, the area contributing to heat transfer in the composite wafer 1 of the embodiment becomes smaller than that of the composite wafer 1 of the comparative example due to the barrier 22 . Therefore, as the area decreases, the amount of heat transferred (Q) also decreases.
  • the heat barrier section 21 makes it difficult for heat to move from the placement region P where heat is provided. Heat tends to stay in the area surrounded by the barrier 22 . As a result, the semiconductor chip 30 and the chip bonding member 41 can be suitably heated. Specifically, the temperature difference that can occur between the semiconductor chip 30 and the chip bonding member 41 can be reduced. This effect is particularly effective when stacking a plurality of semiconductor chips 30 manufactured in the third embodiment described later.
  • the support wafer 20 has a support wafer bonding surface 20a to which the base wafer 10 is detachably bonded, and a support wafer rear surface 20b opposite to the support wafer bonding surface 20a.
  • the thermal barrier portion 21 extends from the support wafer rear surface 20b toward the support wafer bonding surface 20a. With this configuration, the flatness of the support wafer bonding surface 20a can be maintained.
  • the thermal barrier section 21 is composed of a groove 23 having an opening 23a on the back surface 20b of the support wafer and a mold material 24 filled in the groove 23. As shown in FIG. According to this configuration, it is possible to enhance the heat shielding effect of the heat barrier portion 21 and suppress a decrease in rigidity of the support wafer 20 .
  • the method for manufacturing a semiconductor component according to the second embodiment differs from the method for manufacturing a semiconductor component according to the first embodiment in details of the step of mounting the semiconductor chip 30 .
  • different steps will be described in detail, and descriptions of steps similar to those of the first embodiment will be omitted as appropriate.
  • a composite wafer 1 is prepared (steps S1 to S4). Steps S1 to S4 are the same as in the first embodiment.
  • the semiconductor chip 30 is mounted (steps S21 to S23).
  • the semiconductor chips 30 are arranged on the base wafer 10 after the chip bonding members 41 are provided on the base wafer 10 .
  • the chip bonding member 41 is provided on the semiconductor chip 30 .
  • the semiconductor chip 30 having the chip bonding member 41 is placed on the base wafer 10 .
  • the chip bonding member 41 is provided on the chip bonding surface 31b (step S21: FIG. 12(a)). Through step S21, the semiconductor chip 30 having the chip bonding member 41 is obtained. Next, the semiconductor chips 30 having the chip bonding members 41 are sequentially arranged on the base wafer 10 (step S22: FIG. 12(b)). At this time, the semiconductor chip 30 is temporarily bonded to the base wafer 10 .
  • Temporary bonding refers to a process of heating the temperature of the chip bonding member 41 to a temperature higher than the softening start temperature and lower than the hardening start temperature. Step S22 is repeatedly performed until all the planned placement of the semiconductor chips 30 is completed.
  • step S23 the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature.
  • the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature.
  • the semiconductor chip 30 there is another semiconductor chip 30 adjacent to the semiconductor chip 30 being bonded.
  • an uncured chip bonding member 41 exists in the adjacent placement region P.
  • the composite wafer 1 is provided with the thermal barrier portion 21, the influence of heat on the chip bonding members 41 existing in the adjacent placement region P is suppressed.
  • unintended thermal hardening of the chip bonding member 41 in the adjacent semiconductor chip 30 is suppressed.
  • the same effects as those of the first embodiment can also be obtained by the method of manufacturing the semiconductor component 90 of the second embodiment.
  • the composite wafer 1 can be effectively applied when heat curing treatment of the chip bonding member 41 is performed and another chip bonding member 41 exists in the arrangement region P adjacent to the processing object.
  • the configuration of the semiconductor component 90 to be manufactured is different from that of the semiconductor component 90 manufactured by the method of the first embodiment. Therefore, part of the process of mounting the semiconductor chip 30 in the third embodiment is different from the process of mounting the semiconductor chip 30 in the first embodiment.
  • different steps will be described in detail, and descriptions of steps similar to those of the first embodiment will be omitted as appropriate.
  • a composite wafer 1 is prepared (steps S1 to S4). Steps S1 to S4 are the same as in the first embodiment.
  • a semiconductor component 90 manufactured by the method of the third embodiment is a chip stack in which a plurality of semiconductor chips 30 are stacked. In the third embodiment, a so-called collective bonding method is adopted.
  • a plurality of semiconductor chips 30 are stacked in a certain placement area P (step S31: see FIG. 14(a)).
  • the first semiconductor chip 30 is temporarily bonded to the arrangement region P, as shown in FIG.
  • the second semiconductor chip 30 is temporarily bonded onto the first semiconductor chip 30 .
  • the third semiconductor chip 30 is temporarily bonded onto the second semiconductor chip 30.
  • a temporarily laminated chip 50 in which a plurality of semiconductor chips 30 are temporarily bonded is obtained. Step S31 is performed for each placement region P.
  • FIG. 14(a) a temporarily laminated chip 50 in which a plurality of semiconductor chips 30 are temporarily bonded
  • step S32 The final joining is performed (step S32: FIG. 15(b)).
  • the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature.
  • Steps S9 to S11 are the same as in the first embodiment.
  • the method for manufacturing a semiconductor component is not limited to the above embodiments and may be implemented in various forms.
  • the thermal barrier section 21 may be a gap formed only by the grooves 23 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

La présente invention concerne un procédé de fabrication de composants semi-conducteurs qui fait appel à une tranche composite 1 comprenant une tranche de base 10 qui comprend une pluralité de régions de placement P auxquelles des puces semi-conductrices 30 sont liées, et une tranche de support 20 liée de manière amovible à la tranche de base 10. L'épaisseur de la tranche de support 20 est supérieure à l'épaisseur de la tranche de base 10. La tranche de support 20 comprend une unité de barrière thermique 21 formée de façon à entourer la région de placement P dans une vue en plan. Le procédé de fabrication de composants semi-conducteurs comprend les étapes S1 à S4 consistant à préparer la tranche composite 1, et les étapes S5 à S8 consistant à monter la puce semi-conductrice 30 sur la région de placement P à l'aide d'un élément de liaison de puce thermodurcissable 41.
PCT/JP2021/021612 2021-06-07 2021-06-07 Procédé de fabrication de composants semi-conducteurs, et tranche composite WO2022259327A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016162920A (ja) * 2015-03-03 2016-09-05 東レエンジニアリング株式会社 実装装置および実装方法
WO2018066462A1 (fr) * 2016-10-06 2018-04-12 株式会社新川 Dispositif de montage de puce à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016162920A (ja) * 2015-03-03 2016-09-05 東レエンジニアリング株式会社 実装装置および実装方法
WO2018066462A1 (fr) * 2016-10-06 2018-04-12 株式会社新川 Dispositif de montage de puce à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

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