WO2022252142A1 - 驱动电路、显示基板和显示装置 - Google Patents

驱动电路、显示基板和显示装置 Download PDF

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Publication number
WO2022252142A1
WO2022252142A1 PCT/CN2021/097860 CN2021097860W WO2022252142A1 WO 2022252142 A1 WO2022252142 A1 WO 2022252142A1 CN 2021097860 W CN2021097860 W CN 2021097860W WO 2022252142 A1 WO2022252142 A1 WO 2022252142A1
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Prior art keywords
node
transistor
electrically connected
control
clock signal
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PCT/CN2021/097860
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English (en)
French (fr)
Inventor
李孟
承天一
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001411.0A priority Critical patent/CN115735242A/zh
Priority to PCT/CN2021/097860 priority patent/WO2022252142A1/zh
Publication of WO2022252142A1 publication Critical patent/WO2022252142A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a display substrate and a display device.
  • N-type drive circuit refers to a drive circuit that outputs an active high-level drive signal
  • N-type drive circuit refers to a drive circuit that outputs an active high-level drive signal
  • an embodiment of the present disclosure provides a driving circuit, including an output circuit, a first node reset circuit, and a second node control capacitor;
  • the output circuit is used to control the drive signal terminal to output a drive signal under the control of the potential of the first node
  • the first node reset circuit is used to control the reset of the first node under the control of the potential of the second node
  • the second node control capacitor is electrically connected to the second node
  • the width-to-length ratio of the output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; and/or, the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio aspect ratio; and/or, the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;
  • the value range of the first predetermined aspect ratio is greater than or equal to 150/3.8 and less than or equal to 230/3.8, and the value range of the second predetermined aspect ratio is greater than or equal to 4/4.9 and less than or equal to 6/4.9; the value range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF.
  • the first predetermined width-to-length ratio is 210/3.8
  • the second predetermined width-to-length ratio is 5/4.9
  • the predetermined capacitance value is 243fF.
  • control electrode of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the first clock signal line, and the second electrode of the output transistor is electrically connected to the driving signal terminal. connect;
  • the control pole of the first node reset transistor is electrically connected to the second node, the first pole of the first node reset transistor is electrically connected to the first node, and the second pole of the first node reset transistor is electrically connected to the second node.
  • a clock signal line is electrically connected.
  • the drive circuit further includes a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit and an output reset circuit;
  • the third node control circuit is electrically connected to the second clock signal line, the first voltage line and the third node, and is used to control the first voltage line to writing the provided first voltage signal into the third node;
  • the fourth node control circuit is respectively electrically connected to the sixth node, the third clock signal line and the fourth node, and is used to control the third clock signal line to transmit the third clock signal under the control of the potential of the sixth node. write into the fourth node, and control the potential of the fourth node according to the potential of the sixth node;
  • the fifth node control circuit is electrically connected to the second clock signal line, the first clock signal line, the input terminal, and the fifth node, respectively, for the second clock signal and the first clock signal provided on the second clock signal line Under the control of the first clock signal provided by the signal line, control the input terminal to provide an input signal to the fifth node;
  • the second node control circuit is electrically connected to the third node, the seventh node, the second voltage line, the second node and the third clock signal line, and is used to control the seventh node under the control of the potential of the third node. communicate with the second voltage line, and control the communication between the seventh node and the third clock signal line under the control of the potential of the second node;
  • the first plate of the second node control capacitor is electrically connected to the seventh node, and the second plate of the second node control capacitor is electrically connected to the second node;
  • the first node control circuit is electrically connected to the fourth node, the third clock signal line and the first node, and is used to control the fourth node and the first node under the control of the third clock signal provided by the third clock signal line.
  • the first nodes are connected;
  • the output reset circuit is electrically connected to the second node, the driving signal terminal and the first voltage line, and is used to control the driving signal terminal and the first voltage line under the control of the potential of the second node. A connection between the voltage lines.
  • the third node and the sixth node are the same node; or,
  • the drive circuit also includes a first conduction control circuit; the first conduction control circuit is used to control the third node and the sixth node under the control of the first voltage signal provided by the first voltage line connected between.
  • the fifth node and the second node are the same node; or,
  • the drive circuit also includes a second conduction control circuit; the second conduction control circuit is used to control the fifth node and the second node under the control of the first voltage signal provided by the first voltage line. connected between.
  • the third node control circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the second clock signal line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the The third node is electrically connected;
  • the control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal line, and the second electrode of the second transistor is electrically connected to the third node;
  • the fourth node control circuit includes a third transistor and a first capacitor
  • the control electrode of the third transistor is electrically connected to the sixth node, the first electrode of the third transistor is electrically connected to the third clock signal line, and the second electrode of the third transistor is electrically connected to the first Four-node electrical connection;
  • the first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node;
  • the fifth node control circuit includes a fourth transistor and a fifth transistor
  • the control electrode of the fourth transistor is electrically connected to the first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;
  • the control pole of the fifth transistor is electrically connected to the second clock signal line, the first pole of the fifth transistor is electrically connected to the second pole of the fourth transistor, and the second pole of the fifth transistor electrically connected to the fifth node;
  • the second node control circuit includes a sixth transistor and a seventh transistor
  • the control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the seventh node. connect;
  • the control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the third clock signal line, and the second electrode of the seventh transistor is electrically connected to the first clock signal line. Seven-node electrical connection;
  • the first node control circuit includes an eighth transistor and a second capacitor
  • the control electrode of the eighth transistor is electrically connected to the third clock signal line, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first One node electrical connection;
  • the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first clock signal line;
  • the output reset circuit includes a ninth transistor
  • the control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the driving signal electrical connection.
  • the embodiment of the present disclosure further provides a display substrate including the above driving circuit disposed on the substrate.
  • the drive circuit includes an output circuit; the output circuit includes an output transistor;
  • the active layer of the output transistor includes at least one first channel portion extending along a first direction
  • a sum of widths of the at least one first channel portion along the first direction is less than or equal to a first predetermined width, so that an aspect ratio of the output transistor is less than or equal to the first predetermined width to length ratio.
  • the drive circuit includes a first node reset circuit; the first node reset circuit includes a first node reset transistor;
  • the active layer of the first node reset transistor includes at least one second channel portion
  • the sum of the widths of the at least one second channel portion along the second direction is greater than or equal to a second predetermined width, so that the width-to-length ratio of the first node reset transistor is greater than or equal to the second predetermined width-to-length ratio;
  • the first direction and the second direction intersect.
  • the display substrate according to at least one embodiment of the present disclosure further includes gate lines and data lines disposed in the display area;
  • the gate line includes a portion extending in the first direction, and the data line includes a portion extending in the second direction.
  • the drive circuit includes a second node control capacitor;
  • the second node control capacitor includes a first pole plate and a second pole plate arranged in different layers; the first pole plate and the second pole plate provided with an insulating layer;
  • the orthographic projection of the first pole plate on the base at least partially overlaps the orthographic projection of the second pole plate on the base, and the orthographic projection of the first pole plate on the base overlaps with the orthographic projection of the second pole plate on the base
  • the overlapping area between the orthographic projections of the second plate on the base is greater than or equal to a predetermined area, so that the capacitance value of the second node control capacitor is greater than or equal to the predetermined capacitance value.
  • an embodiment of the present disclosure provides a display device, including a display substrate.
  • the display device further includes a voltage supply circuit; the first voltage signal is a low voltage signal, and the second voltage signal is a high voltage signal;
  • the voltage supply circuit is used to provide a first voltage signal and a second voltage signal, and control the difference between the second voltage value and the first voltage value to be greater than a predetermined difference;
  • the second voltage value is the voltage value of the second voltage signal
  • the first voltage value is the voltage value of the first voltage signal
  • the voltage value of the clock signal is a first voltage value
  • the voltage value of the clock signal is the second voltage value.
  • FIG. 1 is a structural diagram of a driving circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 4 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • 5-9 are simulation waveform diagrams of the driving circuit described in at least one embodiment of the present disclosure.
  • Fig. 10 is on the basis of Fig. 4, marks the schematic diagram of the gate of each transistor and the pole plate of each capacitor;
  • Fig. 11 is a schematic layout diagram of a driving circuit provided by at least one embodiment of the present disclosure.
  • Fig. 12 is a schematic diagram of the active layer in Fig. 11;
  • FIG. 13 is a schematic diagram of the first gate metal layer in FIG. 11;
  • FIG. 14 is a schematic diagram of a second gate metal layer in FIG. 11;
  • Figure 15 shows a plurality of via holes provided on the substrate provided with the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the first interlayer dielectric layer schematic diagram;
  • Fig. 16 is a schematic diagram of setting the conductive connection part L1 on the basis of Fig. 15;
  • FIG. 17 is a schematic diagram of the first source-drain metal layer in FIG. 11;
  • FIG. 18 is a superimposed schematic diagram of the active layer, the first gate metal layer, the second gate metal layer, the third gate metal layer and the first source-drain metal layer in FIG. 11;
  • FIG. 19 is a schematic diagram of a second source-drain metal layer in FIG. 11;
  • FIG. 20 is a superimposed schematic diagram of the first source-drain metal layer and the second source-drain metal layer.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or, the The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the driving circuit described in the embodiment of the present disclosure includes an output circuit, a first node reset circuit and a second node control capacitor;
  • the output circuit is used to control the drive signal terminal to output the drive signal under the control of the potential of the first node
  • the first node reset circuit is used to control the reset of the first node under the control of the potential of the second node
  • the second node control capacitor is electrically connected to the second node
  • the width-to-length ratio of the output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; and/or, the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio aspect ratio; and/or, the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;
  • the value range of the first predetermined aspect ratio is greater than or equal to 150/3.8 and less than or equal to 230/3.8, and the value range of the second predetermined aspect ratio is greater than or equal to 4/4.9 and less than or equal to 6/4.9; the value range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF.
  • the driving circuit described in the embodiments of the present disclosure controls the width-to-length ratio of the output transistor to be less than or equal to the first predetermined width-to-length ratio through optimized design, and/or controls the width-to-length ratio of the first node reset transistor to be greater than or equal to the second predetermined width-to-length ratio. aspect ratio, and/or, controlling the capacitance value of the second node control capacitor to be greater than or equal to the predetermined capacitance value, so that the waveform of the driving signal output by the driving circuit is normal.
  • the output circuit includes an output transistor with a width-to-length ratio less than or equal to a first predetermined width-to-length ratio
  • the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio
  • the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value.
  • the output circuit includes output transistors having a width-to-length ratio less than or equal to a first predetermined width-to-length ratio; or,
  • the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; or,
  • the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value
  • the width-to-length ratio of the output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; or,
  • the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value; or,
  • the width-to-length ratio of the output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; the capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value; or,
  • the width-to-length ratio of the output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; the width-to-length ratio of the first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; The capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value.
  • the driving circuit described in the embodiment of the present disclosure includes an output circuit 11 and a first node reset circuit 12;
  • the output circuit 11 is electrically connected to N1 and the driving signal terminal O1 respectively, and is used to control the driving signal terminal O1 to output a driving signal under the control of the potential of the first node N1;
  • the first node reset circuit 12 is electrically connected to the second node N2 and the first node N1 respectively, and is used to control the reset of the first node N1 under the control of the potential of the second node N2;
  • the aspect ratio of the output transistor included in the output circuit 11 is less than or equal to the first predetermined aspect ratio; and/or, the aspect ratio of the first node reset transistor included in the first node reset circuit 12 is greater than or equal to the first predetermined aspect ratio. 2. Predetermined aspect ratio.
  • the driving circuit described in the embodiments of the present disclosure controls the width-to-length ratio of the output transistor to be less than or equal to the first predetermined width-to-length ratio through optimized design, and/or controls the width-to-length ratio of the first node reset transistor to be greater than or equal to the second predetermined width-to-length ratio.
  • the width-to-length ratio makes the waveform of the driving signal output by the driving circuit normal.
  • the driving circuit may be a gate driving circuit or a light emitting control signal generating circuit, but not limited thereto.
  • the value range of the first predetermined aspect ratio may be greater than or equal to 150/3.8 and less than or equal to 230/3.8, and the value range of the second predetermined aspect ratio may be is greater than or equal to 4/4.9 and less than or equal to 6/4.9.
  • the first predetermined width-to-length ratio is 210/3.8
  • the second predetermined width-to-length ratio is 5/4.9, but not limited thereto.
  • the inter-electrode capacitance of the output transistor is reduced by setting the width-to-length ratio of the output transistor to be small, so that the response time of the output transistor is fast, and it can be turned on or off quickly;
  • the width-to-length ratio of the reset transistor at the first node is set to be larger, so that there are more instantaneous carriers in the reset transistor at the first node, so that the voltage response speed is fast, and the output transistor can be controlled to be turned on or off instantaneously.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a second node control capacitor C0;
  • the second node control capacitor C0 is electrically connected to the second node N2, and the capacitance value of the second node control capacitor C0 is greater than or equal to a predetermined capacitance value, so that the waveform of the driving signal output by the driving circuit is normal.
  • the value range of the predetermined capacitance value may be greater than or equal to 143fF and less than or equal to 243fF.
  • the predetermined capacitance value is 243fF, but not limited thereto.
  • the optimal match of the width-to-length ratio of the output transistor, the width-to-length ratio of the first node reset transistor, and the capacitance value of the second node control capacitor may be: the output transistor The aspect ratio is 210/3.8, the aspect ratio of the first node reset transistor is 6/4.9, and the capacitance value of the second node control capacitor is 243fF.
  • control electrode of the output transistor is electrically connected to the first node, the first electrode of the output transistor is electrically connected to the first clock signal line, and the second electrode of the output transistor is electrically connected to the The drive signal end is electrically connected;
  • the control pole of the first node reset transistor is electrically connected to the second node, the first pole of the first node reset transistor is electrically connected to the first node, and the second pole of the first node reset transistor is electrically connected to the second node.
  • a clock signal line is electrically connected.
  • the drive circuit may further include a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit, and an output reset circuit;
  • the third node control circuit is electrically connected to the second clock signal line, the first voltage line and the third node, and is used to control the first voltage line to writing the provided first voltage signal into the third node;
  • the fourth node control circuit is respectively electrically connected to the sixth node, the third clock signal line and the fourth node, and is used to control the third clock signal line to transmit the third clock signal under the control of the potential of the sixth node. write into the fourth node, and control the potential of the fourth node according to the potential of the sixth node;
  • the fifth node control circuit is electrically connected to the second clock signal line, the first clock signal line, the input terminal, and the fifth node, respectively, for the second clock signal and the first clock signal provided on the second clock signal line Under the control of the first clock signal provided by the signal line, control the input terminal to provide an input signal to the fifth node;
  • the second node control circuit is electrically connected to the third node, the seventh node, the second voltage line, the second node N2 and the third clock signal line, and is used to control the seventh node under the control of the potential of the third node.
  • the node communicates with the second voltage line, and under the control of the potential of the second node, controls the communication between the seventh node and the third clock signal line;
  • the first plate of the second node control capacitor is electrically connected to the seventh node, and the second plate of the second node control capacitor is electrically connected to the second node;
  • the first node control circuit is electrically connected to the fourth node, the third clock signal line and the first node, and is used to control the fourth node and the first node under the control of the third clock signal provided by the third clock signal line.
  • the first nodes are connected;
  • the output reset circuit is electrically connected to the second node, the driving signal terminal and the first voltage line, and is used to control the driving signal terminal and the first voltage line under the control of the potential of the second node. A connection between the voltage lines.
  • the third node and the sixth node are the same node; or,
  • the drive circuit also includes a first conduction control circuit; the first conduction control circuit is used to control the third node and the sixth node under the control of the first voltage signal provided by the first voltage line connected between.
  • the fifth node and the second node are the same node; or,
  • the drive circuit also includes a second conduction control circuit; the second conduction control circuit is used to control the fifth node and the second node under the control of the first voltage signal provided by the first voltage line. connected between.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third node control circuit 31, a fourth node control circuit 32, Node control circuit 33, second node control circuit 34, first node control circuit 35, output reset circuit 36, first conduction control circuit 41 and second conduction control circuit 42;
  • the output circuit 11 is also electrically connected to the first clock signal line K1, and is used to control the first clock signal line K1 to provide a first clock signal to the driving signal terminal under the control of the potential of the first node N1;
  • the first node reset circuit 12 is also electrically connected to the first clock signal line K1, and is used to control the voltage between the first node N1 and the first clock signal line K1 under the control of the potential of the second node N2. connected;
  • the third node control circuit 31 is electrically connected to the second clock signal line K2, the first voltage line V1 and the third node N3 respectively, and is used to control the second clock signal provided by the second clock signal line K2. writing the first voltage signal provided by the first voltage line V1 into the third node N3;
  • the fourth node control circuit 32 is electrically connected to the sixth node N6, the third clock signal line K3, and the fourth node N4, respectively, and is used to control the third clock signal line under the control of the potential of the sixth node N6.
  • K3 writes the third clock signal into the fourth node N4, and controls the potential of the fourth node N4 according to the potential of the sixth node N6;
  • the fifth node control circuit 33 is electrically connected to the second clock signal line K2, the first clock signal line K1, the input terminal I1 and the fifth node N5, respectively, for the second clock signal line K2 provided Under the control of the clock signal and the first clock signal provided by the first clock signal line K1, control the input terminal I1 to provide an input signal to the fifth node N5;
  • the second node control circuit 34 is respectively electrically connected to the third node N3, the seventh node N7, the second voltage line V2, the second node N2 and the third clock signal line K3, and is used to adjust the potential of the third node N3 Under control, controlling the communication between the seventh node N7 and the second voltage line V2, and controlling the communication between the seventh node N7 and the third clock signal line K3 under the control of the potential of the second node N2;
  • the first plate of the second node control capacitor C0 is electrically connected to the seventh node N7, and the second plate of the second node control capacitor is electrically connected to the second node N2;
  • the first node control circuit 35 is electrically connected to the fourth node N4, the third clock signal line K3 and the first node N1 respectively, and is used to control all nodes under the control of the third clock signal provided by the third clock signal line K3.
  • the output reset circuit 36 is electrically connected to the second node N2, the driving signal terminal O1 and the first voltage line V1, and is used to control the driving signal under the control of the potential of the second node N2.
  • the terminal O1 is connected with the first voltage line V1;
  • the first conduction control circuit 41 is respectively electrically connected to the first voltage line V1, the third node N3 and the sixth node N6, and is used to control the first voltage signal provided by the first voltage line V1 to control the
  • the third node N3 is connected to the sixth node N6;
  • the second conduction control circuit 42 is respectively electrically connected to the first voltage line V1, the fifth node N5 and the second node N2, and is used to control the first voltage signal provided by the first voltage line V1 to control the The fifth node N5 communicates with the second node N2.
  • the fifth node control circuit 33 controls the potential of the fifth node N5, and the third node control circuit 31 controls the potential of the third node N3.
  • the second node control circuit 34 controls the potential of the second node N2
  • the fourth node control circuit 32 controls the potential of the fourth node N4
  • the first node control circuit 35 controls the potential of the first node N1, so
  • the first node reset circuit 12 controls the potential of the first node N1 under the control of the potential of the second node N2
  • the output circuit 11 controls the drive signal terminal under the control of the potential of the first node N1 O1 outputs the first clock signal
  • the output reset circuit 36 controls the driving signal terminal O1 to output the first voltage signal under the control of the potential of the second node N2.
  • a first conduction control circuit 41 is provided between the third node N3 and the sixth node N6, A second conduction control circuit 42 is provided between them.
  • the third node control circuit includes a first transistor and a second transistor
  • the control electrode of the first transistor is electrically connected to the second clock signal line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the The third node is electrically connected;
  • the control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the second clock signal line, and the second electrode of the second transistor is electrically connected to the third node;
  • the fourth node control circuit includes a third transistor and a first capacitor
  • the control electrode of the third transistor is electrically connected to the sixth node, the first electrode of the third transistor is electrically connected to the third clock signal line, and the second electrode of the third transistor is electrically connected to the first Four-node electrical connection;
  • the first plate of the first capacitor is electrically connected to the sixth node, and the second plate of the first capacitor is electrically connected to the fourth node;
  • the fifth node control circuit includes a fourth transistor and a fifth transistor
  • the control electrode of the fourth transistor is electrically connected to the first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;
  • the control pole of the fifth transistor is electrically connected to the second clock signal line, the first pole of the fifth transistor is electrically connected to the second pole of the fourth transistor, and the second pole of the fifth transistor electrically connected to the fifth node;
  • the second node control circuit includes a sixth transistor and a seventh transistor
  • the control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second voltage line, and the second electrode of the sixth transistor is electrically connected to the seventh node. connect;
  • the control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the third clock signal line, and the second electrode of the seventh transistor is electrically connected to the first clock signal line. Seven-node electrical connection;
  • the first node control circuit includes an eighth transistor and a second capacitor
  • the control electrode of the eighth transistor is electrically connected to the third clock signal line, the first electrode of the eighth transistor is electrically connected to the fourth node, and the second electrode of the eighth transistor is electrically connected to the first One node electrical connection;
  • the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first clock signal line;
  • the output reset circuit includes a ninth transistor
  • the control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the driving signal electrical connection.
  • the first voltage line is a low voltage end
  • the second voltage line is a high voltage end
  • the output circuit 11 includes an output transistor T01
  • the first node reset circuit 12 includes a first node reset transistor T02;
  • the gate of the output transistor T01 is electrically connected to the first node N1, the source of the output transistor T01 is electrically connected to the first clock signal line K1, and the drain of the output transistor T01 is electrically connected to the driving signal terminal O1. connect;
  • the gate of the first node reset transistor T02 is electrically connected to the second node N2, the source of the first node reset transistor T02 is electrically connected to the first node N1, and the drain of the first node reset transistor T02 The pole is electrically connected to the first clock signal line K1;
  • the first plate of the second node control capacitor C0 is electrically connected to the seventh node N7, and the second plate of the second node control capacitor C0 is electrically connected to the second node N2;
  • the third node control circuit 31 may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the second clock signal line K2, the source of the first transistor T1 is electrically connected to the low voltage terminal, and the drain of the first transistor T1 is electrically connected to the second clock signal line K2.
  • the three nodes N3 are electrically connected; the low voltage terminal is used to provide a low voltage signal VGL;
  • the gate of the second transistor T2 is electrically connected to the fifth node N5, the source of the second transistor T2 is electrically connected to the second clock signal line K2, and the drain of the second transistor T2 is electrically connected to the third node N3 electrical connection;
  • the fourth node control circuit 32 may include a third transistor T3 and a first capacitor C1;
  • the gate of the third transistor T3 is electrically connected to the sixth node N6, the source of the third transistor T3 is electrically connected to the third clock signal line K3, and the drain of the third transistor T3 is electrically connected to the sixth node N6.
  • the fourth node N4 is electrically connected;
  • the first plate of the first capacitor C1 is electrically connected to the sixth node N6, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4;
  • the fifth node control circuit 33 may include a fourth transistor T4 and a fifth transistor T5;
  • the gate of the fourth transistor T4 is electrically connected to the first clock signal line K1, and the source of the fourth transistor T4 is electrically connected to the input terminal I1;
  • the gate of the fifth transistor T5 is electrically connected to the second clock signal line K2, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the fifth transistor T5 The drain is electrically connected to the fifth node N5;
  • the second node control circuit 34 may include a sixth transistor T6 and a seventh transistor T7;
  • the gate of the sixth transistor T6 is electrically connected to the third node N3, the source of the sixth transistor T6 is electrically connected to the high voltage terminal, and the drain of the sixth transistor T6 is electrically connected to the seventh node N7 is electrically connected; the high voltage terminal is used to provide a high voltage signal VGH;
  • the gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the third clock signal line K3, and the drain of the seventh transistor T7 is electrically connected to the second node N2.
  • the seventh node N7 is electrically connected;
  • the first node control circuit 35 may include an eighth transistor T8 and a second capacitor C2;
  • the gate of the eighth transistor T8 is electrically connected to the third clock signal line K3, the source of the eighth transistor T8 is electrically connected to the fourth node N4, and the drain of the eighth transistor T8 is electrically connected to the fourth node N4.
  • the first node N1 is electrically connected;
  • a first plate of the second capacitor C2 is electrically connected to the first node N1, and a second plate of the second capacitor C2 is electrically connected to the first clock signal line K1;
  • the output reset circuit 36 may include a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the second node N2, the source of the ninth transistor T9 is electrically connected to the low voltage terminal, and the drain of the ninth transistor T9 is electrically connected to the drive
  • the signal terminal O1 is electrically connected;
  • the first conduction control circuit 41 includes a tenth transistor T10, and the second conduction control circuit 42 includes an eleventh transistor T11;
  • the gate of the tenth transistor T10 is electrically connected to the low voltage terminal, the source of the tenth transistor T10 is electrically connected to the third node N3, and the drain of the tenth transistor T10 is electrically connected to the sixth node N6 electrical connection;
  • the gate of the eleventh transistor T11 is electrically connected to the low voltage terminal, the source of the eleventh transistor T11 is electrically connected to the fifth node N5, and the drain of the eleventh transistor T11 is electrically connected to the The second node N2 is electrically connected.
  • all transistors can be p-type thin film transistors, but not limited thereto.
  • T10 and T11 may be normally-on transistors. At least one embodiment of the present disclosure can stabilize the potential of N6 by setting T10, and can stabilize the potential of N2 by setting T11.
  • the waveform from top to bottom (the waveform of the driving signal provided by the driving signal terminal) is in turn: when the channel width of T01 is 100um and the channel length of T01 is 3.8um, the waveform of the driving signal; when When the channel width of T01 is 150um and the channel length of T01 is 3.8um, the waveform of the driving signal; when the channel width of T01 is 210um and the channel length of T01 is 3.8um, the waveform of the driving signal; The waveform of the driving signal when the channel width is 250um and the channel length of T01 is 3.8um.
  • At least one embodiment of the driving circuit shown in FIG. 4 is simulated.
  • the CV of T01 remains constant at 400fF, as shown in FIG. 6, when the width-length ratio of T02 is greater than or equal to 5/4.9, the driving signal terminal O1 The output drive signal is normal.
  • the waveform from top to bottom is: when the channel width of T02 is 3um, and the channel length of T02 is 4.9um, the waveform of the driving signal; when When the channel width of T02 is 4um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 5um and the channel length of T02 is 4.9um, the waveform of the driving signal; When the channel width is 6um and the channel length of T02 is 4.9um, the waveform of the driving signal; when the channel width of T02 is 7um and the channel length of T02 is 4.9um, the waveform of the driving signal.
  • At least one embodiment of the driving circuit shown in Figure 4 is simulated, when the CV of T01 remains unchanged at 400fF, as shown in Figure 7, when the capacitance value of C0 is greater than or equal to 143fF, the driving signal output by the driving signal terminal O1 The signal is normal.
  • the waveforms from top to bottom are: when the capacitance value of C0 is 93fF, the waveform of the driving signal; when the capacitance value of C0 is 143fF, the driving signal When the capacitance value of C0 is 193fF, the waveform of the driving signal; when the capacitance value of C0 is 243fF, the waveform of the driving signal; when the capacitance value of C0 is 293fF, the waveform of the driving signal.
  • the waveforms from top to bottom are: when the capacitance value of C2 is 146fF, the waveform of the driving signal; when the capacitance value of C2 is 196fF, the driving signal
  • the capacitance value of C2 is 246fF, the waveform of the driving signal
  • the capacitance value of C2 is 296fF
  • the waveform of the driving signal when the capacitance value of C2 is 346fF, the waveform of the driving signal. It can be known from the waveform in Figure 9 that adjusting the capacitance of C2 will not improve the waveform of the driving signal.
  • the display substrate described in the embodiment of the present disclosure includes the above-mentioned driving circuit disposed on the substrate.
  • the driving circuit includes an output circuit; the output circuit includes an output transistor;
  • the active layer of the output transistor includes at least one first channel portion extending along a first direction
  • a sum of widths of the at least one first channel portion along the first direction is less than or equal to a first predetermined width, so that an aspect ratio of the output transistor is less than or equal to the first predetermined width to length ratio.
  • the width of the first channel portion along the first direction is the channel width of the output transistor.
  • the first direction may be substantially the same as the extending direction of the gate lines disposed in the display area.
  • the value range of the first predetermined aspect ratio may be greater than or equal to 150/3.8 and less than or equal to 230/3.8, and the value range of the second predetermined aspect ratio may be is greater than or equal to 4/4.9 and less than or equal to 6/4.9.
  • the first predetermined width-to-length ratio is 210/3.8, but not limited thereto.
  • the first predetermined width may be 210um.
  • the driving circuit includes a first node reset circuit; the first node reset circuit includes a first node reset transistor;
  • the active layer of the first node reset transistor includes at least one second channel portion
  • a sum of widths of the at least one second channel portion along the first direction is greater than or equal to a second predetermined width, so that a width-to-length ratio of the first node reset transistor is greater than or equal to the second predetermined width-to-length ratio.
  • the width of the second channel portion along the second direction is the first the width of the channel of the node reset transistor
  • the first direction intersects the second direction.
  • the second direction may be substantially the same as the extending direction of the data lines arranged in the display area.
  • the second predetermined width-to-length ratio is 5/4.9, but not limited thereto.
  • the second predetermined width may be 5um.
  • the display substrate according to at least one embodiment of the present disclosure further includes gate lines and data lines disposed in the display area;
  • the gate line includes a portion extending in the first direction, and the data line includes a portion extending in the second direction.
  • the display substrate according to at least one embodiment of the present disclosure may further include multiple rows of gate lines and multiple columns of data lines disposed in the display area;
  • the gate line includes a portion extending along the first direction
  • the data line includes a portion extending along the second direction
  • the driving circuit may be disposed on the first edge region of the display substrate and/or on the display substrate Second edge area.
  • the first edge area may be disposed on the left side of the display area
  • the second edge area may be disposed on the right side of the display area.
  • the drive circuit includes a second node control capacitor;
  • the second node control capacitor includes a first plate and a second plate arranged in different layers; the first plate and the The second pole plate is provided with an insulating layer;
  • the orthographic projection of the first pole plate on the base at least partially overlaps the orthographic projection of the second pole plate on the base, and the orthographic projection of the first pole plate on the base overlaps with the orthographic projection of the second pole plate on the base
  • the overlapping area between the orthographic projections of the second plate on the base is greater than or equal to a predetermined area, so that the capacitance value of the second node control capacitor is greater than or equal to the predetermined capacitance value.
  • the value range of the predetermined capacitance value may be greater than or equal to 143fF and less than or equal to 243fF.
  • the predetermined capacitance value may be 243fF, but not limited thereto.
  • FIG. 10 is a schematic diagram on the basis of FIG. 4 , marking the gates of each transistor and the plates of each capacitor.
  • the grid labeled G1 is the grid of T1
  • the grid labeled G2 is the grid of T2
  • the grid labeled G3 is the grid of T3
  • the grid labeled G4 is the grid of T4
  • the grid labeled G5 is The gate of T5, the gate marked G6 is the gate of T6, the gate marked G7 is the gate of T7, the gate marked G8 is the gate of T8, and the gate marked G9 is the gate of T9.
  • the gate labeled G10 is the grid of T10
  • the grid labeled G11 is the grid of T11
  • the grid labeled G01 is the grid of T01
  • the grid labeled G02 is the grid of T02
  • the grid labeled C0a is the first plate of C0
  • the one marked C1a is the first plate of C1
  • the one marked C2a is the first plate of C2
  • the one marked C1b is the second plate of C1
  • the one marked C2b is the second plate of C2.
  • FIG. 11 is a schematic layout diagram of a driving circuit provided by at least one embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of the active layer in FIG. 11
  • FIG. 13 is a schematic diagram of the first gate metal layer in FIG. 11
  • FIG. 14 is
  • FIG. 11 is a schematic diagram of the second gate metal layer
  • FIG. 17 is a schematic diagram of the first source-drain metal layer in FIG. 11
  • FIG. 19 is a schematic diagram of the second source-drain metal layer in FIG. 11 .
  • the first direction D1 may be a vertical direction
  • the second direction D2 may be a horizontal direction.
  • the active layer of the output transistor T01 includes a first first channel portion 111, a second first channel portion 112, a third first channel portion 113, a fourth first channel portion A channel portion 114, a fifth first channel portion 115 and a sixth first channel portion 116; the first first channel portion 111, the second first channel portion 112, The third first channel portion 113, the fourth first channel portion 114, the fifth first channel portion 115, and the sixth first channel portion 116 are all along the first extend in one direction;
  • the active layer of the ninth transistor T9 includes a first third channel portion 211 extending along the first direction and a second third channel portion 212 extending along the first direction;
  • the width of the first first channel portion 111 along the first direction, the width of the second first channel portion 112 along the first direction, and the width of the third first channel portion 113 along the first direction direction, the width of the fourth first channel portion 114 along the first direction, the width of the fifth first channel portion 115 along the first direction, and the sixth first channel The sum of the widths of the channel portions 116 along the first direction is the channel width of the output transistor T01.
  • the active layer of the first node reset transistor T02 includes a second channel portion 121 ; the width of the channel of T02 is the width of the second channel portion 121 along the second direction.
  • the active layer of T01 and the active layer of T9 are formed by a first semiconductor layer 10 and a second semiconductor layer 20; the first semiconductor layer 10 and the second semiconductor layer
  • the layers 20 are independent of each other (in order to prevent the influence of the heating effect on the characteristics of the transistor due to the large area of the continuous active layer of the transistor caused by the operation of the transistor, the first semiconductor layer 10 and the second semiconductor layer 20 can be arranged are independent of each other).
  • the active layer of the output transistor T01 and the active layer of the ninth transistor T9 may also be formed by a continuous semiconductor layer.
  • the first output reset gate pattern included in the gate of T9 labeled G91, the second output reset gate pattern included in the gate of T9 labeled G92, the gate of G01 includes the first output reset gate pattern An output gate pattern G011, a second output gate pattern G012, a third output gate pattern G013, a fourth output gate pattern G014, a fifth output gate pattern G015 and a sixth output gate pattern G016;
  • the gate labeled G1 is the gate of T1
  • the gate of T2 includes the first gate pattern G21 and the second gate pattern G22
  • the gate labeled G3 is the gate of T3
  • the gate labeled G4 is the gate of T4
  • the gate labeled G4 is T4.
  • the gate of G5 is the gate of T5
  • the gate of G6 is the gate of T6
  • the gate of G7 is the gate of T7
  • the gate of G8 is the gate of T8
  • the gate of G10 is the gate of T10.
  • the gate of G11 is T11
  • the gate of G02 is T02
  • the first plate of C0a is C0
  • the first plate of C1 is C1a
  • the first plate of C2a is C2. first plate.
  • the label C0b is the second pole plate of C0
  • the label C1b is the second pole plate C1
  • the label C2b is the second pole plate C2.
  • the orthographic projection of C0b on the base is within the orthographic projection of C0a on the base; C0a and C0b can be parallel to the base, and the area of the orthographic projection of C0b on the base is greater than or is equal to the predetermined area, so that the capacitance value of C0 is greater than or equal to the predetermined capacitance value.
  • the first gate insulating layer, the first gate metal layer, the second gate insulating layer and the second gate metal layer are sequentially arranged on the substrate, after the second gate metal layer faces away from the second gate insulating
  • a first interlayer dielectric layer is provided on one side of the layer, and a via hole penetrating through the first interlayer dielectric layer is provided.
  • the black dots shown in FIG. 15 indicate via holes penetrating through the first interlayer dielectric layer.
  • a third gate metal layer is provided on the side of the first interlayer dielectric layer facing away from the second gate metal layer; as shown in FIG. 16 , a patterning process is performed on the third gate metal layer to form a conductive connection part L1 .
  • a second interlayer dielectric layer is provided on the side of the third gate metal layer facing away from the first interlayer dielectric layer, and a via hole penetrating through the second interlayer dielectric layer is provided, so that the The conductive connecting portion L1 is electrically connected to the sources of K1 and T01 respectively (as shown in FIG. 18 ).
  • the one labeled V02 is the high voltage line that provides the high voltage signal VGH
  • the one labeled V01 is the low voltage line that provides the low voltage signal VGL
  • the one labeled K1 is the first clock signal line
  • the one labeled K2 is is the second clock signal line
  • the one labeled K3 is the third clock signal line
  • the one labeled K4 is the fourth clock signal line.
  • the source labeled S9 is the source of T9
  • the drain of T01 includes the first drain pattern D011 and the second drain pattern D012
  • the source of T01 includes the first source pattern S011 and the second source Figure S012: D011 is multiplexed as the drain of T9.
  • Fig. 20 is a laminated diagram of the first source-drain metal layer and the second source-drain metal layer, and a passivation layer and a second source-drain metal layer may be sequentially arranged between the first source-drain metal layer and the second source-drain metal layer.
  • a semiconductor material layer is provided on the substrate, and a patterning process is performed on the semiconductor material layer to form the active layer of each transistor; on the back of the active layer forming a first gate insulating layer on one side of the substrate; forming a first gate metal layer on the side of the first gate insulating layer facing away from the active layer, and performing a patterning process on the first gate metal layer, The gates of each transistor and the first plate of each capacitor in the driving circuit are formed.
  • each transistor Using the gate of each transistor as a mask, doping the part of the active layer not covered by the gate, so that the part of the active layer not covered by the gate forms a conductive part, and the active A portion of the layer covered by the gate is formed as a channel portion; the conductive portion serves as a source or a drain; or, the conductive portion is coupled to the source or the drain.
  • a second gate insulating layer is formed on the side of the first gate metal layer facing away from the active layer, and a second gate metal layer is arranged on the side of the second gate insulating layer facing away from the first gate metal layer;
  • a patterning process is performed on the second gate metal layer to form the second plate and the connecting conductive part of each capacitor in the drive circuit; the second gate metal layer is provided on the side facing away from the second gate insulating layer An intermediary layer.
  • a plurality of via holes are arranged on the substrate provided with the active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer and the first interlayer dielectric layer.
  • a third gate metal layer is disposed on a side of the first interlayer dielectric layer facing away from the second gate metal layer.
  • a patterning process is performed on the third gate metal layer to form a conductive connection portion L1.
  • a second interlayer dielectric layer is disposed on a side of the third gate metal layer facing away from the first interlayer dielectric layer.
  • a first source-drain metal layer is provided on the side of the second interlayer dielectric layer facing away from the third gate metal layer, and a patterning process is performed on the first source-drain metal layer to form clock signal lines and voltage lines , connecting the conductive part, the source of T9, the source of T01, and the drain of T01.
  • a passivation layer and a planarization layer are sequentially disposed on a side of the first source-drain metal layer facing away from the second interlayer dielectric layer.
  • the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, the first interlayer dielectric layer, the third gate metal layer, and the second interlayer dielectric layer are formed on the substrate.
  • a second source-drain metal layer is disposed on a side of the flat layer facing away from the first source-drain metal layer.
  • a patterning process is performed on the second source-drain metal layer to form a connecting conductive part.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.
  • the display device further includes a voltage supply circuit; the first voltage signal is a low voltage signal VGL, and the second voltage signal is a high voltage signal VGH;
  • the voltage supply circuit is used to provide a first voltage signal and a second voltage signal, and control the difference between the second voltage value and the first voltage value to be greater than a predetermined difference;
  • the second voltage value is the voltage value of the second voltage signal
  • the first voltage value is the voltage value of the first voltage signal
  • the voltage value of the clock signal is a first voltage value
  • the voltage value of the clock signal is a second voltage value.
  • the embodiment of the present disclosure increases the voltage difference between the voltage value of VGH and the voltage value of VGL, so that when T01 needs to be turned off, the gate potential of T01 can turn off T01, so as to achieve the normal output of the driving circuit and make the screen display normal.
  • the predetermined difference may be 14V, but not limited thereto.
  • T02 when at least one embodiment of the driving circuit shown in FIG. 4 is in operation, when the potential of N2 is a low voltage, T02 is turned on, so that N1 is connected to the first clock signal provided by K1, then when the first clock signal When the potential of is a high voltage, by increasing the voltage difference between the voltage value of the high voltage signal and the voltage value of the low voltage signal, T01 can be controlled to be turned off better.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

本公开提供一种驱动电路、显示基板和显示装置。驱动电路，其特征在于，包括输出电路、第一节点复位电路和第二节点控制电容；所述输出电路用于在第一节点的电位的控制下，控制驱动信号端输出驱动信号；所述第一节点复位电路用于在第二节点的电位的控制下，控制对第一节点进行复位；所述第二节点控制电容与所述第二节点电连接；所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；和/或，所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；和/或，所述第二节点控制电容的电容值大于或等于预定电容值。本公开通过优化设计，使得驱动电路输出的驱动信号的波形正常。

Description

驱动电路、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、显示基板和显示装置。
背景技术
在相关技术中，N型驱动电路(N型驱动电路指的是输出高电平有效的驱动信号的驱动电路)在工作时，当晶体管和存储电容的性能不匹配时，会出现N型驱动电路输出异常，进而造成显示异常的现象。
公开内容
在一个方面中，本公开实施例提供了一种驱动电路，包括输出电路、第一节点复位电路和第二节点控制电容；
所述输出电路用于在第一节点的电位的控制下，控制驱动信号端输出驱动信号；
所述第一节点复位电路用于在第二节点的电位的控制下，控制对第一节点进行复位；
所述第二节点控制电容与所述第二节点电连接；
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；和/或，所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；和/或，所述第二节点控制电容的电容值大于或等于预定电容值；
所述第一预定宽长比的取值范围为大于或等于150/3.8而小于或等于230/3.8，所述第二预定宽长比的取值范围为大于或等于4/4.9而小于或等于6/4.9；所述预定电容值的取值范围为大于或等于143fF而小于或等于243fF。
可选的，所述第一预定宽长比为210/3.8，所述第二预定宽长比为5/4.9，所述预定电容值为243fF。
可选的，所述输出晶体管的控制极与第一节点电连接，所述输出晶体管 的第一极与第一时钟信号线电连接，所述输出晶体管的第二极与所述驱动信号端电连接；
所述第一节点复位晶体管的控制极与所述第二节点电连接，所述第一节点复位晶体管的第一极与第一节点电连接，所述第一节点复位晶体管的第二极与第一时钟信号线电连接。
可选的，所述驱动电路还包括第三节点控制电路、第四节点控制电路、第五节点控制电路、第二节点控制电路、第一节点控制电路和输出复位电路；
所述第三节点控制电路分别与第二时钟信号线、第一电压线和第三节点电连接，用于在第二时钟信号线提供的第二时钟信号的控制下，控制将第一电压线提供的第一电压信号写入第三节点；
所述第四节点控制电路分别与第六节点、第三时钟信号线和第四节点电连接，用于在所述第六节点的电位的控制下，控制第三时钟信号线将第三时钟信号写入第四节点，并根据第六节点的电位控制第四节点的电位；
所述第五节点控制电路分别与第二时钟信号线、第一时钟信号线、输入端和第五节点电连接，用于在所述第二时钟信号线提供的第二时钟信号和第一时钟信号线提供的第一时钟信号的控制下，控制所述输入端提供输入信号至第五节点；
所述第二节点控制电路分别与第三节点、第七节点、第二电压线、第二节点和第三时钟信号线电连接，用于在第三节点的电位的控制下，控制第七节点与第二电压线之间连通，并在所述第二节点的电位的控制下，控制所述第七节点与第三时钟信号线之间连通；
所述第二节点控制电容的第一极板与所述第七节点电连接，所述第二节点控制电容的第二极板与所述第二节点电连接；
所述第一节点控制电路分别与第四节点、第三时钟信号线和第一节点电连接，用于在第三时钟信号线提供的第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
所述输出复位电路分别与第二节点、所述驱动信号端和所述第一电压线电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号端与所述第一电压线之间连通。
可选的，第三节点和第六节点为同一节点；或者，
所述驱动电路还包括第一导通控制电路；所述第一导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第三节点与所述第六节点之间连通。
可选的，所述第五节点和所述第二节点为同一节点；或者，
所述驱动电路还包括第二导通控制电路；所述第二导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第五节点与所述第二节点之间连通。
可选的，所述第三节点控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述第二时钟信号线电连接，所述第一晶体管的第一极与所述第一电压线电连接，所述第一晶体管的第二极与所述第三节点电连接；
所述第二晶体管的控制极与第五节点电连接，所述第二晶体管的第一极与第二时钟信号线电连接，所述第二晶体管的第二极与第三节点电连接；
所述第四节点控制电路包括第三晶体管和第一电容；
所述第三晶体管的控制极与所述第六节点电连接，所述第三晶体管的第一极与所述第三时钟信号线电连接，所述第三晶体管的第二极与所述第四节点电连接；
所述第一电容的第一极板与所述第六节点电连接，所述第一电容的第二极板与所述第四节点电连接；
所述第五节点控制电路包括第四晶体管和第五晶体管；
所述第四晶体管的控制极与第一时钟信号线电连接，所述第四晶体管的第一极与所述输入端电连接；
所述第五晶体管的控制极与所述第二时钟信号线电连接，所述第五晶体管的第一极与所述第四晶体管的第二极电连接，所述第五晶体管的第二极与所述第五节点电连接；
所述第二节点控制电路包括第六晶体管和第七晶体管；
所述第六晶体管的控制极与所述第三节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第七节点电连接；
所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与所述第三时钟信号线电连接，所述第七晶体管的第二极与所述第七节点电连接；
所述第一节点控制电路包括第八晶体管和第二电容；
所述第八晶体管的控制极与所述第三时钟信号线电连接，所述第八晶体管的第一极与所述第四节点电连接，所述第八晶体管的第二极与所述第一节点电连接；
所述第二电容的第一极板与所述第一节点电连接，所述第二电容的第二极板与所述第一时钟信号线电连接；
所述输出复位电路包括第九晶体管；
所述第九晶体管的控制极与所述第二节点电连接，所述第九晶体管的第一极与所述第一电压线电连接，所述第九晶体管的第二极与所述驱动信号端电连接。
在第二方面中，本公开实施例还提供了一种显示基板包括设置于基底上的上述的驱动电路。
可选的，所述驱动电路包括输出电路；所述输出电路包括输出晶体管；
所述输出晶体管的有源层包括沿第一方向延伸的至少一个第一沟道部分；
所述至少一个第一沟道部分沿第一方向的宽度的和值小于或等于第一预定宽度，以使得所述输出晶体管的的宽长比小于或等于第一预定宽长比。
所述驱动电路包括第一节点复位电路；所述第一节点复位电路包括第一节点复位晶体管；
所述第一节点复位晶体管的有源层包括至少一个第二沟道部分；
所述至少一个第二沟道部分沿第二方向的宽度的和值大于或等于第二预定宽度，以使得所述第一节点复位晶体管的宽长比大于或等于第二预定宽长比；
第一方向和第二方向交叉。
可选的，本公开至少一实施例所述的显示基板还包括设置于显示区域的栅线和数据线；
所述栅线包括沿所述第一方向延伸的部分，所述数据线包括沿第二方向 延伸的部分。
可选的，所述驱动电路包括第二节点控制电容；所述第二节点控制电容包括异层设置的第一极板和第二极板；所述第一极板和所述第二极板设置有绝缘层；
所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分重叠，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影之间的重叠面积大于或等于预定面积，以使得所述第二节点控制电容的电容值大于或等于预定电容值。
在第三个方面中，本公开实施例提供了一种显示装置，包括上的显示基板。
可选的，本公开至少一实施例所述的显示装置还包括电压提供电路；第一电压信号为低电压信号，第二电压信号为高电压信号；
所述电压提供电路用于提供第一电压信号和第二电压信号，并控制第二电压值与第一电压值之间的差值大于预定差值；
第二电压值为所述第二电压信号的电压值，第一电压值为所述第一电压信号的电压值；
当所述显示基板中的驱动电路包括的各时钟信号线提供的时钟信号的电位为低电压时，该时钟信号的电压值为第一电压值；
当所述各时钟信号线提供的时钟信号的电位为高电压时，该时钟信号的电压值为第二电压值。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的电路图；
图5-图9是本公开至少一实施例所述的驱动电路的仿真波形图；
图10是在图4的基础上，标出各晶体管的栅极与各电容的极板的示意图；
图11是本公开至少一实施例提供的驱动电路的一种布局示意图；
图12是图11中的有源层的示意图；
图13是图11中的第一栅金属层的示意图；
图14是图11中的第二栅金属层的示意图；
图15是在设置了有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层和第一层间介质层的基底上，设置的多个过孔的示意图；
图16是在图15的基础上设置了导电连接部L1的示意图；
图17是图11中的第一源漏金属层的示意图；
图18是图11中的有源层、第一栅金属层、第二栅金属层、第三栅金属层和第一源漏金属层的叠加示意图；
图19是图11中的第二源漏金属层的示意图；
图20是第一源漏金属层和第二源漏金属层的叠加示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的驱动电路包括输出电路、第一节点复位电路和第二节点控制电容；
所述输出电路用于在第一节点的电位的控制下，控制驱动信号端输出驱 动信号；
所述第一节点复位电路用于在第二节点的电位的控制下，控制对第一节点进行复位；
所述第二节点控制电容与所述第二节点电连接；
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；和/或，所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；和/或，所述第二节点控制电容的电容值大于或等于预定电容值；
所述第一预定宽长比的取值范围为大于或等于150/3.8而小于或等于230/3.8，所述第二预定宽长比的取值范围为大于或等于4/4.9而小于或等于6/4.9；所述预定电容值的取值范围为大于或等于143fF而小于或等于243fF。
本公开实施例所述的驱动电路通过优化设计，控制输出晶体管的宽长比小于或等于第一预定宽长比，和/或，控制第一节点复位晶体管的宽长比大于或等于第二预定宽长比，和/或，控制第二节点控制电容的电容值大于或等于预定电容值，使得驱动电路输出的驱动信号的波形正常。
在本公开实施例中，需满足以下至少一项：
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；
所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；
所述第二节点控制电容的电容值大于或等于预定电容值。
也即，在本公开至少一实施例中，
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；或者，
所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；或者，
所述第二节点控制电容的电容值大于或等于预定电容值；或者，
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；或者，
所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；所述第二节点控制电容的电容值大于或等于预定电容值；或者，
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；所述第二节点控制电容的电容值大于或等于预定电容值；或者，
所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；所述第二节点控制电容的电容值大于或等于预定电容值。
如图1所示，本公开实施例所述的驱动电路包括输出电路11和第一节点复位电路12；
所述输出电路11分别与N1和驱动信号端O1电连接，用于在第一节点N1的电位的控制下，控制所述驱动信号端O1输出驱动信号；
所述第一节点复位电路12分别与第二节点N2和第一节点N1电连接，用于在第二节点N2的电位的控制下，控制对第一节点N1进行复位；
所述输出电路11包括的输出晶体管的宽长比小于或等于第一预定宽长比；和/或，所述第一节点复位电路12包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比。
本公开实施例所述的驱动电路通过优化设计，控制输出晶体管的宽长比小于或等于第一预定宽长比，和/或，控制第一节点复位晶体管的宽长比大于或等于第二预定宽长比，使得驱动电路输出的驱动信号的波形正常。
在本公开至少一实施例中，所述驱动电路可以为栅极驱动电路或发光控制信号生成电路，但不以此为限。
在本公开至少一实施例中，所述第一预定宽长比的取值范围可以为大于或等于150/3.8而小于或等于230/3.8，所述第二预定宽长比的取值范围可以为大于或等于4/4.9而小于或等于6/4.9。
可选的，所述第一预定宽长比为210/3.8，所述第二预定宽长比为5/4.9，但不以此为限。
在本公开至少一实施例中，通过将输出晶体管的宽长比设置为较小，从而减小输出晶体管的极间电容，从而使得输出晶体管的反应时间快，能够快 速的打开或关断；
将第一节点复位晶体管的宽长比设置为较大，从而使得第一节点复位晶体管中的瞬间载流子较多，从而电压反应速度快，能够瞬间控制输出晶体管打开或关断。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第二节点控制电容C0；
所述第二节点控制电容C0与所述第二节点N2电连接，所述第二节点控制电容C0的电容值大于或等于预定电容值，以使得驱动电路输出的驱动信号的波形正常。
在本公开至少一实施例中，所述预定电容值的取值范围可以为大于或等于143fF而小于或等于243fF。
可选的，所述预定电容值为243fF，但不以此为限。
在本公开至少一实施例中，所述输出晶体管的宽长比、所述第一节点复位晶体管的宽长比、第二节点控制电容的电容值的最优搭配可以为：所述输出晶体管的宽长比为210/3.8，所述第一节点复位晶体管的宽长比为6/4.9，所述第二节点控制电容的电容值为243fF。
在本公开至少一实施例中，所述输出晶体管的控制极与第一节点电连接，所述输出晶体管的第一极与第一时钟信号线电连接，所述输出晶体管的第二极与所述驱动信号端电连接；
所述第一节点复位晶体管的控制极与所述第二节点电连接，所述第一节点复位晶体管的第一极与第一节点电连接，所述第一节点复位晶体管的第二极与第一时钟信号线电连接。
本公开至少一实施例所述的驱动电路还可以包括第三节点控制电路、第四节点控制电路、第五节点控制电路、第二节点控制电路、第一节点控制电路和输出复位电路；
所述第三节点控制电路分别与第二时钟信号线、第一电压线和第三节点电连接，用于在第二时钟信号线提供的第二时钟信号的控制下，控制将第一电压线提供的第一电压信号写入第三节点；
所述第四节点控制电路分别与第六节点、第三时钟信号线和第四节点电 连接，用于在所述第六节点的电位的控制下，控制第三时钟信号线将第三时钟信号写入第四节点，并根据第六节点的电位控制第四节点的电位；
所述第五节点控制电路分别与第二时钟信号线、第一时钟信号线、输入端和第五节点电连接，用于在所述第二时钟信号线提供的第二时钟信号和第一时钟信号线提供的第一时钟信号的控制下，控制所述输入端提供输入信号至第五节点；
所述第二节点控制电路分别与第三节点、第七节点、第二电压线、第二节点N2和第三时钟信号线电连接，用于在第三节点的电位的控制下，控制第七节点与第二电压线之间连通，并在所述第二节点的电位的控制下，控制所述第七节点与第三时钟信号线之间连通；
所述第二节点控制电容的第一极板与所述第七节点电连接，所述第二节点控制电容的第二极板与所述第二节点电连接；
所述第一节点控制电路分别与第四节点、第三时钟信号线和第一节点电连接，用于在第三时钟信号线提供的第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
所述输出复位电路分别与第二节点、所述驱动信号端和所述第一电压线电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号端与所述第一电压线之间连通。
可选的，第三节点和第六节点为同一节点；或者，
所述驱动电路还包括第一导通控制电路；所述第一导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第三节点与所述第六节点之间连通。
可选的，所述第五节点和所述第二节点为同一节点；或者，
所述驱动电路还包括第二导通控制电路；所述第二导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第五节点与所述第二节点之间连通。
如图3所示，在图2所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还包括第三节点控制电路31、第四节点控制电路32、第五节点控制电路33、第二节点控制电路34、第一节点控制电路35、输出 复位电路36、第一导通控制电路41和第二导通控制电路42；
所述输出电路11还与第一时钟信号线K1电连接，用于在第一节点N1的电位的控制下，控制所述第一时钟信号线K1提供第一时钟信号至所述驱动信号端；
所述第一节点复位电路12还与第一时钟信号线K1电连接，用于在第二节点N2的电位的控制下，控制所述第一节点N1与所述第一时钟信号线K1之间连通；
所述第三节点控制电路31分别与第二时钟信号线K2、第一电压线V1和第三节点N3电连接，用于在第二时钟信号线K2提供的第二时钟信号的控制下，控制将第一电压线V1提供的第一电压信号写入第三节点N3；
所述第四节点控制电路32分别与第六节点N6、第三时钟信号线K3和第四节点N4电连接，用于在所述第六节点N6的电位的控制下，控制第三时钟信号线K3将第三时钟信号写入第四节点N4，并根据第六节点N6的电位控制第四节点N4的电位；
所述第五节点控制电路33分别与第二时钟信号线K2、第一时钟信号线K1、输入端I1和第五节点N5电连接，用于在所述第二时钟信号线K2提供的第二时钟信号和第一时钟信号线K1提供的第一时钟信号的控制下，控制所述输入端I1提供输入信号至第五节点N5；
所述第二节点控制电路34分别与第三节点N3、第七节点N7、第二电压线V2、第二节点N2和第三时钟信号线K3电连接，用于在第三节点N3的电位的控制下，控制第七节点N7与第二电压线V2之间连通，并在所述第二节点N2的电位的控制下，控制所述第七节点N7与第三时钟信号线K3之间连通；
所述第二节点控制电容C0的第一极板与所述第七节点N7电连接，所述第二节点控制电容的第二极板与所述第二节点N2电连接；
所述第一节点控制电路35分别与第四节点N4、第三时钟信号线K3和第一节点N1电连接，用于在第三时钟信号线K3提供的第三时钟信号的控制下，控制所述第四节点N4与所述第一节点N1之间连通；
所述输出复位电路36分别与第二节点N2、所述驱动信号端O1和所述第 一电压线V1电连接，用于在所述第二节点N2的电位的控制下，控制所述驱动信号端O1与所述第一电压线V1之间连通；
所述第一导通控制电路41分别与第一电压线V1、第三节点N3和第六节点N6电连接，用于在第一电压线V1提供的第一电压信号的控制下，控制所述第三节点N3与所述第六节点N6之间连通；
所述第二导通控制电路42分别与第一电压线V1、第五节点N5和第二节点N2电连接，用于在第一电压线V1提供的第一电压信号的控制下，控制所述第五节点N5与所述第二节点N2之间连通。
本公开如图3所示的驱动电路的至少一实施例在工作时，所述第五节点控制电路33控制第五节点N5的电位，所述第三节点控制电路31控制第三节点N3的电位，所述第二节点控制电路34控制第二节点N2的电位，所述第四节点控制电路32控制第四节点N4的电位，所述第一节点控制电路35控制第一节点N1的电位，所述第一节点复位电路12在第二节点N2的电位的控制下，控制所述第一节点N1的电位；所述输出电路11在第一节点N1的电位的控制下，控制所述驱动信号端O1输出第一时钟信号；所述输出复位电路36在第二节点N2的电位的控制下，控制所述驱动信号端O1输出第一电压信号。
在本公开如图3所示的驱动电路的至少一实施例中，在第三节点N3与第六节点N6之间设置有第一导通控制电路41，在第五节点N5与第二节点N2之间设置有第二导通控制电路42。
在本公开至少一实施例中，所述第三节点控制电路包括第一晶体管和第二晶体管；
所述第一晶体管的控制极与所述第二时钟信号线电连接，所述第一晶体管的第一极与所述第一电压线电连接，所述第一晶体管的第二极与所述第三节点电连接；
所述第二晶体管的控制极与第五节点电连接，所述第二晶体管的第一极与第二时钟信号线电连接，所述第二晶体管的第二极与第三节点电连接；
所述第四节点控制电路包括第三晶体管和第一电容；
所述第三晶体管的控制极与所述第六节点电连接，所述第三晶体管的第 一极与所述第三时钟信号线电连接，所述第三晶体管的第二极与所述第四节点电连接；
所述第一电容的第一极板与所述第六节点电连接，所述第一电容的第二极板与所述第四节点电连接；
所述第五节点控制电路包括第四晶体管和第五晶体管；
所述第四晶体管的控制极与第一时钟信号线电连接，所述第四晶体管的第一极与所述输入端电连接；
所述第五晶体管的控制极与所述第二时钟信号线电连接，所述第五晶体管的第一极与所述第四晶体管的第二极电连接，所述第五晶体管的第二极与所述第五节点电连接；
所述第二节点控制电路包括第六晶体管和第七晶体管；
所述第六晶体管的控制极与所述第三节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第七节点电连接；
所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与所述第三时钟信号线电连接，所述第七晶体管的第二极与所述第七节点电连接；
所述第一节点控制电路包括第八晶体管和第二电容；
所述第八晶体管的控制极与所述第三时钟信号线电连接，所述第八晶体管的第一极与所述第四节点电连接，所述第八晶体管的第二极与所述第一节点电连接；
所述第二电容的第一极板与所述第一节点电连接，所述第二电容的第二极板与所述第一时钟信号线电连接；
所述输出复位电路包括第九晶体管；
所述第九晶体管的控制极与所述第二节点电连接，所述第九晶体管的第一极与所述第一电压线电连接，所述第九晶体管的第二极与所述驱动信号端电连接。
可选的，所述第一电压线为低电压端，所述第二电压线为高电压端。
如图4所示，在图3所示的驱动电路的至少一实施例的基础上，所述输出电路11包括输出晶体管T01，所述第一节点复位电路12包括第一节点复 位晶体管T02；
所述输出晶体管T01的栅极与第一节点N1电连接，所述输出晶体管T01的源极与第一时钟信号线K1电连接，所述输出晶体管T01的漏极与所述驱动信号端O1电连接；
所述第一节点复位晶体管T02的栅极与所述第二节点N2电连接，所述第一节点复位晶体管T02的源极与第一节点N1电连接，所述第一节点复位晶体管T02的漏极与第一时钟信号线K1电连接；
所述第二节点控制电容C0的第一极板与第七节点N7电连接，所述第二节点控制电容C0的第二极板与所述第二节点N2电连接；
所述第三节点控制电路31可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与所述第二时钟信号线K2电连接，所述第一晶体管T1的源极与低电压端电连接，所述第一晶体管T1的漏极与所述第三节点N3电连接；所述低电压端用于提供低电压信号VGL；
所述第二晶体管T2的栅极与第五节点N5电连接，所述第二晶体管T2的源极与第二时钟信号线K2电连接，所述第二晶体管T2的漏极与第三节点N3电连接；
所述第四节点控制电路32可以包括第三晶体管T3和第一电容C1；
所述第三晶体管T3的栅极与所述第六节点N6电连接，所述第三晶体管T3的源极与所述第三时钟信号线K3电连接，所述第三晶体管T3的漏极与所述第四节点N4电连接；
所述第一电容C1的第一极板与所述第六节点N6电连接，所述第一电容C1的第二极板与所述第四节点N4电连接；
所述第五节点控制电路33可以包括第四晶体管T4和第五晶体管T5；
所述第四晶体管T4的栅极与第一时钟信号线K1电连接，所述第四晶体管T4的源极与输入端I1电连接；
所述第五晶体管T5的栅极与所述第二时钟信号线K2电连接，所述第五晶体管T5的源极与所述第四晶体管T4的漏极电连接，所述第五晶体管T5的漏极与所述第五节点N5电连接；
所述第二节点控制电路34可以包括第六晶体管T6和第七晶体管T7；
所述第六晶体管T6的栅极与所述第三节点N3电连接，所述第六晶体管T6的源极与高电压端电连接，所述第六晶体管T6的漏极与所述第七节点N7电连接；所述高电压端用于提供高电压信号VGH；
所述第七晶体管T7的栅极与所述第二节点N2电连接，所述第七晶体管T7的源极与所述第三时钟信号线K3电连接，所述第七晶体管T7的漏极与所述第七节点N7电连接；
所述第一节点控制电路35可以包括第八晶体管T8和第二电容C2；
所述第八晶体管T8的栅极与所述第三时钟信号线K3电连接，所述第八晶体管T8的源极与所述第四节点N4电连接，所述第八晶体管T8的漏极与所述第一节点N1电连接；
所述第二电容C2的第一极板与所述第一节点N1电连接，所述第二电容的C2的第二极板与所述第一时钟信号线K1电连接；
所述输出复位电路36可以包括第九晶体管T9；
所述第九晶体管T9的栅极与所述第二节点N2电连接，所述第九晶体管T9的源极与所述低电压端电连接，所述第九晶体管T9的漏极与所述驱动信号端O1电连接；
所述第一导通控制电路41包括第十晶体管T10，所述第二导通控制电路42包括第十一晶体管T11；
所述第十晶体管T10的栅极与所述低电压端电连接，所述第十晶体管T10的源极与所述第三节点N3电连接，所述第十晶体管T10的漏极与第六节点N6电连接；
所述第十一晶体管T11的栅极与所述低电压端电连接，所述第十一晶体管T11的源极与第五节点N5电连接，所述第十一晶体管T11的漏极与所述第二节点N2电连接。
在图4所示的驱动电路的至少一实施例中，所有的晶体管都可以为p型薄膜晶体管，但不以此为限。
在图4所示的驱动电路的至少一实施例中，T10和T11可以为常开晶体管。本公开至少一实施例通过设置T10，能够稳定N6的电位，通过设置T11，以稳定N2的电位。
对图4所示的驱动电路的至少一实施例进行仿真，当T01的极间电容CV保持400fF不变时，如图5所示，当T01的宽长比小于或等于210/3.8时，驱动信号端O1输出的驱动信号正常。
在图5中，从上向下的波形(驱动信号端提供的驱动信号的波形)依次是：当T01的沟道宽度为100um，T01的沟道长度为3.8um时，驱动信号的波形；当T01的沟道宽度为150um，T01的沟道长度为3.8um时，驱动信号的波形；当T01的沟道宽度为210um，T01的沟道长度为3.8um时，驱动信号的波形；当T01的沟道宽度为250um，T01的沟道长度为3.8um时，驱动信号的波形。
对图4所示的驱动电路的至少一实施例进行仿真，当T01的CV保持400fF不变时，如图6所示，当T02的宽长比大于或等于5/4.9时，驱动信号端O1输出的驱动信号正常。
在图6中，从上向下的波形(驱动信号端提供的驱动信号的波形)依次是：当T02的沟道宽度为3um，T02的沟道长度为4.9um时，驱动信号的波形；当T02的沟道宽度为4um，T02的沟道长度为4.9um时，驱动信号的波形；当T02的沟道宽度为5um，T02的沟道长度为4.9um时，驱动信号的波形；当T02的沟道宽度为6um，T02的沟道长度为4.9um时，驱动信号的波形；当T02的沟道宽度为7um，T02的沟道长度为4.9um时，驱动信号的波形。
对图4所示的驱动电路的至少一实施例进行仿真，当T01的CV保持400fF不变时，如图7所示，当C0的电容值大于或等于143fF时，驱动信号端O1输出的驱动信号正常。
在图7中，从上向下的波形(驱动信号端提供的驱动信号的波形)依次是：当C0的电容值为93fF时，驱动信号的波形；当C0的电容值为143fF时，驱动信号的波形；当C0的电容值为193fF时，驱动信号的波形；当C0的电容值为243fF时，驱动信号的波形；当C0的电容值为293fF时，驱动信号的波形。
如图8所示，当T01的宽长比为210/3.8，T02的宽长比为6/4.9，C0的电容值为243fF时，对图4所示的驱动电路的至少一实施例进行仿真，驱动 信号的波形正常。
如图9所示，当T01的CV保持400fF不变时，在改变C2的电容值时，不会对驱动信号的波形进行改善。
在图9中，从上向下的波形(驱动信号端提供的驱动信号的波形)依次是：当C2的电容值为146fF时，驱动信号的波形；当C2的电容值为196fF时，驱动信号的波形；当C2的电容值为246fF时，驱动信号的波形；当C2的电容值为296fF时，驱动信号的波形；当C2的电容值为346fF时，驱动信号的波形。由图9中的波形可知，对C2的电容值进行调整不会改善驱动信号的波形。
本公开实施例所述的显示基板包括设置于基底上的上述的驱动电路。
在本公开至少一实施例中，所述驱动电路包括输出电路；所述输出电路包括输出晶体管；
所述输出晶体管的有源层包括沿第一方向延伸的至少一个第一沟道部分；
所述至少一个第一沟道部分沿第一方向的宽度的和值小于或等于第一预定宽度，以使得所述输出晶体管的的宽长比小于或等于第一预定宽长比。
在本公开至少一实施例中，当所述输出晶体管仅包括一个第一沟道部分时，该第一沟道部分沿第一方向的宽度即为所述输出晶体管的沟道的宽度。
可选的，所述第一方向可以为与设置于显示区域的栅线的延伸方向大致相同。
在本公开至少一实施例中，所述第一预定宽长比的取值范围可以为大于或等于150/3.8而小于或等于230/3.8，所述第二预定宽长比的取值范围可以为大于或等于4/4.9而小于或等于6/4.9。
可选的，所述第一预定宽长比为210/3.8，但不以此为限。
可选的，当所述输出晶体管的沟道的长度为3.8um时，所述第一预定宽度可以为210um。
在本公开至少一实施例中，所述驱动电路包括第一节点复位电路；所述第一节点复位电路包括第一节点复位晶体管；
所述第一节点复位晶体管的有源层包括至少一个第二沟道部分；
所述至少一个第二沟道部分沿第一方向的宽度的和值大于或等于第二预 定宽度，以使得所述第一节点复位晶体管的宽长比大于或等于第二预定宽长比。
在本公开至少一实施例中，当所述第一节点复位晶体管的有源层仅包括一个第二沟道部分时，该第二沟道部分沿第二方向上的宽度即为所述第一节点复位晶体管的沟道的宽度；
所述第一方向与所述第二方向交叉。
可选的，所述第二方向可以与设置于显示区域的数据线的延伸方向大致相同。
可选的，所述第二预定宽长比为5/4.9，但不以此为限。
可选的，当所述第一节点复位晶体管的沟道的长度为4.9um时，所述第二预定宽度可以为5um。
本公开至少一实施例所述的显示基板还包括设置于显示区域的栅线和数据线；
所述栅线包括沿所述第一方向延伸的部分，所述数据线包括沿所述第二方向延伸的部分。
在具体实施时，本公开至少一实施例所述的显示基板还可以包括设置于显示区域的多行栅线和多列数据线；
所述栅线包括沿第一方向延伸的部分，所述数据线包括沿第二方向延伸的部分，所述驱动电路可以设置于所述显示基板的第一边缘区域和/或所述显示基板的第二边缘区域。所述第一边缘区域可以设置于所述显示区域的左侧，所述第二边缘区域可以设置于显示区域的右侧。
在本公开至少一实施例中，所述驱动电路包括第二节点控制电容；所述第二节点控制电容包括异层设置的第一极板和第二极板；所述第一极板和所述第二极板设置有绝缘层；
所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分重叠，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影之间的重叠面积大于或等于预定面积，以使得所述第二节点控制电容的电容值大于或等于预定电容值。
在本公开至少一实施例中，所述预定电容值的取值范围可以为大于或等 于143fF而小于或等于243fF。
可选的，所述预定电容值可以为243fF，但不以此为限。
图10是在图4的基础上，标出各晶体管的栅极与各电容的极板的示意图。
在图10中，标号为G1的为T1的栅极，标号为G2的为T2的栅极，标号为G3的为T3的栅极，标号为G4的为T4的栅极，标号为G5的为T5的栅极，标号为G6的为T6的栅极，标号为G7的为T7的栅极，标号为G8的为T8的栅极，标号为G9的为T9的栅极。标号为G10的为T10的栅极，标号为G11的为T11的栅极，标号为G01的为T01的栅极标号为G02的为T02的栅极，标号为C0a的为C0的第一极板，标号为C1a的为C1的第一极板，标号为C2a的为C2的第一极板，标号为C1b的为C1的第二极板，标号为C2b的为C2的第二极板。
图11是本公开至少一实施例提供的驱动电路的一种布局示意图；图12是图11中的有源层的示意图；图13是图11中的第一栅金属层的示意图；图14是图11中的第二栅金属层的示意图；图17是图11中的第一源漏金属层的示意图；图19是图11中的第二源漏金属层的示意图。
在图11所示的布局示意图中，第一方向D1可以为竖直方向，第二方向D2可以为水平方向。
如图12所示，所述输出晶体管T01的有源层包括第一个第一沟道部分111、第二个第一沟道部分112、第三个第一沟道部分113、第四个第一沟道部分114、第五个第一沟道部分115和第六个第一沟道部分116；所述第一个第一沟道部分111、所述第二个第一沟道部分112、所述第三个第一沟道部分113、所述第四个第一沟道部分114、所述第五个第一沟道部分115和所述第六个第一沟道部分116都沿第一方向延伸；
所述第九晶体管T9的有源层包括沿着第一方向延伸的第一个第三沟道部分211和沿着第一方向延伸的第二个第三沟道部分212；
所述第一个第一沟道部分111沿第一方向的宽度、所述第二个第一沟道部分112沿第一方向的宽度、所述第三个第一沟道部分113沿第一方向的宽度、所述第四个第一沟道部分114沿第一方向的宽度、所述第五个第一沟道部分115沿第一方向的宽度，以及，所述第六个第一沟道部分116沿第一方 向的宽度之和，为所述输出晶体管T01的沟道的宽度。
如图12所示，所述第一节点复位晶体管T02的有源层包括一个第二沟道部分121；T02的沟道的宽度为所述第二沟道部分121沿第二方向的宽度。
在图12所示的至少一实施例中，T01的有源层和T9的有源层由第一半导体层10和第二半导体层20形成；所述第一半导体层10和所述第二半导体层20相互独立(为了防止由于晶体管的连续的有源层的面积较大，而引起的晶体管工作时的发热效应对晶体管的特性的影响，可以将第一半导体层10和第二半导体层20设置为相互独立)。
可选的，所述输出晶体管T01的有源层与第九晶体管T9的有源层也可以由一个连续的半导体层形成。
如图13所示，标号为G91的为T9的栅极包括的第一输出复位栅极图形，标号为G92的为T9的栅极包括的第二输出复位栅极图形，G01的栅极包括第一输出栅极图形G011、第二输出栅极图形G012、第三输出栅极图形G013、第四输出栅极图形G014、第五输出栅极图形G015和第六输出栅极图形G016；
标号为G1的为T1的栅极，T2的栅极包括第一栅极图形G21和第二栅极图形G22，标号为G3的为T3的栅极，标号为G4的为T4的栅极，标号为G5的为T5的栅极，标号为G6的为T6的栅极，标号为G7的为T7的栅极，标号为G8的为T8的栅极，标号为G10的为T10的栅极，标号为G11的为T11的栅极，标号为G02的为T02的栅极，标号为C0a的为C0的第一极板，标号为C1a的为C1的第一极板，标号为C2a的为C2的第一极板。
在图14中，标号为C0b的为C0的第二极板，标号为C1b的为C1的第二极板，标号为C2b的为C2的第二极板。
如图11、图13和图14所示，C0b在基底上的正投影在C0a在基底上的正投影内；C0a和C0b可以平行于所述基底，C0b在基底上的正投影的面积大于或等于预定面积，以使得C0的电容值大于或等于所述预定电容值。
在基底上依次设置有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层和第二栅金属层之后，在所述第二栅金属层背向所述第二栅绝缘层的一面设置第一层间介质层，并设置贯穿所述第一层间介质层的过孔。图15中所示的黑点所示的为贯穿所述第一层间介质层的过孔。
在所述第一层间介质层背向所述第二栅金属层的一面设置第三栅金属层；如图16所示，对所述第三栅金属层进行构图工艺，形成导电连接部L1。之后，在所述第三栅金属层背向所述所述第一层间介质层的一面设置第二层间介质层，并设置贯穿所述第二层间介质层的过孔，以使得所述导电连接部L1分别与K1和T01的源极电连接(如图18所示)。
在图17中，标号为V02的为提供高电压信号VGH的高电压线，标号为V01的为提供低电压信号VGL的低电压线；标号为K1的为第一时钟信号线，标号为K2的为第二时钟信号线，标号为K3的为第三时钟信号线，标号为K4的为第四时钟信号线。
在图17中，标号为S9的为T9的源极，T01的漏极包括第一漏极图形D011和第二漏极图形D012，T01的源极包括第一源极图形S011和第二源极图形S012：D011复用为T9的漏极。
图20是第一源漏金属层和第二源漏金属层叠加后的叠层图，在第一源漏金属层与所述第二源漏金属层之间可以依次设置有钝化层和第一平坦层；在图20中，黑色矩形和黑色圆点所示的是贯穿所述钝化层和所述第一平坦层的过孔。
在制作本公开至少一实施例所述的显示基板时，首先在基底上设置半导体材料层，对所述半导体材料层进行构图工艺，以形成各晶体管的有源层；在所述有源层背向所述基底的一面制作第一栅绝缘层；在所述第一栅绝缘层背向所述有源层的一面，制作第一栅金属层，对所述第一栅金属层进行构图工艺，形成驱动电路中的各晶体管的栅极以及各电容的第一极板。以各晶体管的栅极为掩膜，对有源层中未被所述栅极覆盖的部分进行掺杂，使得所述有源层中未被栅极覆盖的部分形成为导电部分，所述有源层中被所述栅极覆盖的部分形成为沟道部分；所述导电部分用作源极或漏极；或者，所述导电部分与源极或漏极耦接。在所述第一栅金属层背向所述有源层的一面制作第二栅绝缘层，在第二栅绝缘层背向所述第一栅金属层的一面设置第二栅金属层；对所述第二栅金属层进行构图工艺，形成所述驱动电路中的各电容的第二极板和连接导电部；在所述第二栅金属层背向所述第二栅绝缘层的一面设置第一层间介质层。在设置了有源层、第一栅绝缘层、第一栅金属层、第二 栅绝缘层、第二栅金属层和第一层间介质层的基底上，设置多个过孔。在所述第一层间介质层背向所述第二栅金属层的一面设置第三栅金属层。对所述第三栅金属层进行构图工艺，形成导电连接部L1。在所述第三栅金属层背向第一层间介质层的一面设置第二层间介质层。在所述第二层间介质层背向所述第三栅金属层的一面设置第一源漏金属层，对所述第一源漏金属层进行构图工艺，形成各时钟信号线、各电压线、连接导电部、T9的源极，T01的源极，以及，T01的漏极。在所述第一源漏金属层背向所述第二层间介质层的一面依次设置钝化层和平坦层。在设置了有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、第一层间介质层、第三栅金属层、第二层间介质层、第一源漏金属层、钝化层和平坦层的基底上制作过孔。在所述平坦层背向所述第一源漏金属层的一面设置第二源漏金属层。对所述第二源漏金属层进行构图工艺，形成连接导电部。
本公开实施例所述的显示装置包括上述的显示基板。
本公开至少一实施例所述的显示装置还包括电压提供电路；第一电压信号为低电压信号VGL，第二电压信号为高电压信号VGH；
所述电压提供电路用于提供第一电压信号和第二电压信号，并控制第二电压值与第一电压值之间的差值大于预定差值；
第二电压值为所述第二电压信号的电压值，第一电压值为所述第一电压信号的电压值；
当所述显示基板中的驱动电路包括的各时钟信号线提供的时钟信号的电位为低电压时，该时钟信号的电压值为第一电压值；
当所述各时钟信号线提供的时钟信号的电位为高电压时，该时钟信号的电压值为第二电压值。
本公开实施例增大VGH的电压值与VGL的电压值的压差，可以在T01需要关断时，使得T01的栅极电位能够关闭T01，达到驱动电路正常输出，使得画面显示正常。
在本公开至少一实施例中，所述预定差值可以为14V，但不以此为限。
例如，当图4所示的驱动电路的至少一实施例在工作时，当N2的电位为低电压，T02打开，以使得N1接入K1提供的第一时钟信号时，则当第一 时钟信号的电位为高电压时，通过增加高电压信号的电压值与低电压信号的电压值之间的压差，能够控制T01更好的关闭。
经过仿真，当图4所示的驱动电路的至少一实施例工作时，当VGH的电压值为7V，VGL的电压值为-7V时，并T01处于PBTS(正向偏压应力)时，T01的栅源电压为-8.24V，T01的漏源电压为2.98V；当VGH的电压值为10V，VGL的电压值为-10V时，并T01处于PBTS(正向偏压应力)时，T01的栅源电压为-13.65V，T01的漏源电压为0.99V。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种驱动电路，包括输出电路、第一节点复位电路和第二节点控制电容；
    所述输出电路用于在第一节点的电位的控制下，控制驱动信号端输出驱动信号；
    所述第一节点复位电路用于在第二节点的电位的控制下，控制对第一节点进行复位；
    所述第二节点控制电容与所述第二节点电连接；
    所述输出电路包括的输出晶体管的宽长比小于或等于第一预定宽长比；和/或，所述第一节点复位电路包括的第一节点复位晶体管的宽长比大于或等于第二预定宽长比；和/或，所述第二节点控制电容的电容值大于或等于预定电容值；
    所述第一预定宽长比的取值范围为大于或等于150/3.8而小于或等于230/3.8，所述第二预定宽长比的取值范围为大于或等于4/4.9而小于或等于6/4.9；所述预定电容值的取值范围为大于或等于143fF而小于或等于243fF。
  2. 如权利要求1所述的驱动电路，其中，所述第一预定宽长比为210/3.8，所述第二预定宽长比为5/4.9，所述预定电容值为243fF。
  3. 如权利要求1或2所述的驱动电路，其中，所述输出晶体管的控制极与第一节点电连接，所述输出晶体管的第一极与第一时钟信号线电连接，所述输出晶体管的第二极与所述驱动信号端电连接；
    所述第一节点复位晶体管的控制极与所述第二节点电连接，所述第一节点复位晶体管的第一极与第一节点电连接，所述第一节点复位晶体管的第二极与第一时钟信号线电连接。
  4. 如权利要求1或2所述的驱动电路，其中，所述驱动电路还包括第三节点控制电路、第四节点控制电路、第五节点控制电路、第二节点控制电路、第一节点控制电路和输出复位电路；
    所述第三节点控制电路分别与第二时钟信号线、第一电压线和第三节点电连接，用于在第二时钟信号线提供的第二时钟信号的控制下，控制将第一 电压线提供的第一电压信号写入第三节点；
    所述第四节点控制电路分别与第六节点、第三时钟信号线和第四节点电连接，用于在所述第六节点的电位的控制下，控制第三时钟信号线将第三时钟信号写入第四节点，并根据第六节点的电位控制第四节点的电位；
    所述第五节点控制电路分别与第二时钟信号线、第一时钟信号线、输入端和第五节点电连接，用于在所述第二时钟信号线提供的第二时钟信号和第一时钟信号线提供的第一时钟信号的控制下，控制所述输入端提供输入信号至第五节点；
    所述第二节点控制电路分别与第三节点、第七节点、第二电压线、第二节点和第三时钟信号线电连接，用于在第三节点的电位的控制下，控制第七节点与第二电压线之间连通，并在所述第二节点的电位的控制下，控制所述第七节点与第三时钟信号线之间连通；
    所述第二节点控制电容的第一极板与所述第七节点电连接，所述第二节点控制电容的第二极板与所述第二节点电连接；
    所述第一节点控制电路分别与第四节点、第三时钟信号线和第一节点电连接，用于在第三时钟信号线提供的第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
    所述输出复位电路分别与第二节点、所述驱动信号端和所述第一电压线电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号端与所述第一电压线之间连通。
  5. 如权利要求4所述的驱动电路，其中，第三节点和第六节点为同一节点；或者，
    所述驱动电路还包括第一导通控制电路；所述第一导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第三节点与所述第六节点之间连通。
  6. 如权利要求4所述的驱动电路，其中，所述第五节点和所述第二节点为同一节点；或者，
    所述驱动电路还包括第二导通控制电路；所述第二导通控制电路用于在第一电压线提供的第一电压信号的控制下，控制所述第五节点与所述第二节 点之间连通。
  7. 如权利要求4所述的驱动电路，其中，所述第三节点控制电路包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极与所述第二时钟信号线电连接，所述第一晶体管的第一极与所述第一电压线电连接，所述第一晶体管的第二极与所述第三节点电连接；
    所述第二晶体管的控制极与第五节点电连接，所述第二晶体管的第一极与第二时钟信号线电连接，所述第二晶体管的第二极与第三节点电连接；
    所述第四节点控制电路包括第三晶体管和第一电容；
    所述第三晶体管的控制极与所述第六节点电连接，所述第三晶体管的第一极与所述第三时钟信号线电连接，所述第三晶体管的第二极与所述第四节点电连接；
    所述第一电容的第一极板与所述第六节点电连接，所述第一电容的第二极板与所述第四节点电连接；
    所述第五节点控制电路包括第四晶体管和第五晶体管；
    所述第四晶体管的控制极与第一时钟信号线电连接，所述第四晶体管的第一极与所述输入端电连接；
    所述第五晶体管的控制极与所述第二时钟信号线电连接，所述第五晶体管的第一极与所述第四晶体管的第二极电连接，所述第五晶体管的第二极与所述第五节点电连接；
    所述第二节点控制电路包括第六晶体管和第七晶体管；
    所述第六晶体管的控制极与所述第三节点电连接，所述第六晶体管的第一极与第二电压线电连接，所述第六晶体管的第二极与所述第七节点电连接；
    所述第七晶体管的控制极与所述第二节点电连接，所述第七晶体管的第一极与所述第三时钟信号线电连接，所述第七晶体管的第二极与所述第七节点电连接；
    所述第一节点控制电路包括第八晶体管和第二电容；
    所述第八晶体管的控制极与所述第三时钟信号线电连接，所述第八晶体管的第一极与所述第四节点电连接，所述第八晶体管的第二极与所述第一节 点电连接；
    所述第二电容的第一极板与所述第一节点电连接，所述第二电容的第二极板与所述第一时钟信号线电连接；
    所述输出复位电路包括第九晶体管；
    所述第九晶体管的控制极与所述第二节点电连接，所述第九晶体管的第一极与所述第一电压线电连接，所述第九晶体管的第二极与所述驱动信号端电连接。
  8. 一种显示基板，包括设置于基底上的如权利要求7至9中任一权利要求所述的驱动电路。
  9. 如权利要求8所述的显示基板，其中，所述驱动电路包括输出电路；所述输出电路包括输出晶体管；
    所述输出晶体管的有源层包括沿第一方向延伸的至少一个第一沟道部分；
    所述至少一个第一沟道部分沿第一方向的宽度的和值小于或等于第一预定宽度，以使得所述输出晶体管的的宽长比小于或等于第一预定宽长比。
  10. 如权利要求8所述的显示基板，其中，所述驱动电路包括第一节点复位电路；所述第一节点复位电路包括第一节点复位晶体管；
    所述第一节点复位晶体管的有源层包括至少一个第二沟道部分；
    所述至少一个第二沟道部分沿第二方向的宽度的和值大于或等于第二预定宽度，以使得所述第一节点复位晶体管的宽长比大于或等于第二预定宽长比；
    第一方向和第二方向交叉。
  11. 如权利要求9或10所述的显示基板，其中，还包括设置于显示区域的栅线和数据线；
    所述栅线包括沿第一方向延伸的部分，所述数据线包括沿第二方向延伸的部分。
  12. 如权利要求8至10中任一权利要求所述的显示基板，其中，所述驱动电路包括第二节点控制电容；所述第二节点控制电容包括异层设置的第一极板和第二极板；所述第一极板和所述第二极板设置有绝缘层；
    所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正 投影至少部分重叠，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影之间的重叠面积大于或等于预定面积，以使得所述第二节点控制电容的电容值大于或等于预定电容值。
  13. 一种显示装置，包括如权利要求8至12中任一权利要求所述的显示基板。
  14. 如权利要求13所述的显示装置，其中，还包括电压提供电路；第一电压信号为低电压信号，第二电压信号为高电压信号；
    所述电压提供电路用于提供第一电压信号和第二电压信号，并控制第二电压值与第一电压值之间的差值大于预定差值；
    第二电压值为所述第二电压信号的电压值，第一电压值为所述第一电压信号的电压值；
    当所述显示基板中的驱动电路包括的各时钟信号线提供的时钟信号的电位为低电压时，该时钟信号的电压值为第一电压值；
    当所述各时钟信号线提供的时钟信号的电位为高电压时，该时钟信号的电压值为第二电压值。
PCT/CN2021/097860 2021-06-02 2021-06-02 驱动电路、显示基板和显示装置 WO2022252142A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN102270434A (zh) * 2010-06-03 2011-12-07 海帝士科技公司 显示驱动电路
CN102855938A (zh) * 2012-08-31 2013-01-02 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN103646636A (zh) * 2013-12-18 2014-03-19 合肥京东方光电科技有限公司 移位寄存器、栅极驱动电路及显示装置
CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

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CN102270434A (zh) * 2010-06-03 2011-12-07 海帝士科技公司 显示驱动电路
CN102855938A (zh) * 2012-08-31 2013-01-02 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
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