WO2022249397A1 - 半導体装置及び電力変換装置 - Google Patents

半導体装置及び電力変換装置 Download PDF

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WO2022249397A1
WO2022249397A1 PCT/JP2021/020212 JP2021020212W WO2022249397A1 WO 2022249397 A1 WO2022249397 A1 WO 2022249397A1 JP 2021020212 W JP2021020212 W JP 2021020212W WO 2022249397 A1 WO2022249397 A1 WO 2022249397A1
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region
semiconductor device
layer
trench
electrode
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French (fr)
Japanese (ja)
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亘平 足立
裕 福井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2021576486A priority Critical patent/JP7062143B1/ja
Priority to DE112021007715.5T priority patent/DE112021007715T5/de
Priority to US18/287,650 priority patent/US20240194780A1/en
Priority to CN202180098497.3A priority patent/CN117355945A/zh
Priority to PCT/JP2021/020212 priority patent/WO2022249397A1/ja
Publication of WO2022249397A1 publication Critical patent/WO2022249397A1/ja
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/669—Vertical DMOS [VDMOS] FETs having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/837—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs

Definitions

  • the present disclosure relates to semiconductor devices and power conversion devices.
  • switching devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as a means of switching on and off power supply to drive loads such as electric motors. It is
  • Vertical MOSFETs and vertical IGBTs with a vertical structure are often used for switching devices that are expected to be used as power semiconductor devices.
  • planar type MOSFETs and trench type (also called trench gate type) MOSFETs having different gate structures are known.
  • Patent Document 1 proposes a configuration in which the electric field applied to the gate insulating film at the bottom of the gate trench is relaxed by providing a protective diffusion layer such as a p-type electric field relaxation region so as to cover the bottom of the gate trench.
  • Patent Document 1 discloses a technique of mounting a sense cell for detecting overcurrent on the same semiconductor chip in order to suppress malfunctions in the device due to overcurrent due to surge during switching operation and overcurrent due to gate short circuit. is proposed.
  • the structure of the sense cell is similar to that of the main cell in the active region, and has a small-sized MOSFET region in which the influence of heat generation due to overcurrent is suppressed.
  • the main cell and the sense cell are mounted in the same chip, they are electrically separated because they require separate current paths.
  • the present disclosure has been made in view of the problems described above, and aims to provide a technique capable of reducing energy loss during switching operation.
  • a semiconductor device includes a main cell region and a sense cell region separated from each other, a first peripheral region adjacent to the main cell region between the main cell region and the sense cell region, and the main cell region.
  • the main cell region, the first peripheral region, the isolation region, the second peripheral region, and the sense cell region each include a first conductivity type drift layer.
  • Each of the main cell region and the sense cell region includes a second conductivity type body region provided on the drift layer, a first conductivity type source region provided on the body region, the body region and the a first trench penetrating through the source region and partially in contact with the drift layer; a gate electrode provided in the first trench via a gate insulating film; and a first trench provided at the bottom of the first trench. a two-conductivity-type first bottom protective layer; and a second-conductivity-type connection layer provided along at least a portion of a sidewall of the first trench and connecting the first bottom protective layer and the body region. Prepare more.
  • the main cell region further includes a source electrode connected to the source region.
  • the sense cell region further comprises a current sense electrode connected to the source region and separate from the source electrode.
  • the first peripheral region includes: a second trench provided above the drift layer and having a width wider than that of the first trench; and a second conductivity type second bottom protective layer provided on the bottom of the second trench. and further.
  • the second peripheral region includes a third trench provided above the drift layer and having a width wider than that of the first trench, and a third conductive type third bottom protective layer provided on the bottom of the third trench. and further. whether the second bottom protection layer is electrically connected to the source electrode or the third bottom protection layer is electrically connected to the current sense electrode; the second bottom protection layer and the third bottom A protective layer is electrically connected to the source electrode and the current sense electrode, respectively.
  • the second bottom protective layer is electrically connected to the source electrode, or the third bottom protective layer is electrically connected to the current sense electrode, the second bottom protective layer and the third bottom A protective layer is electrically connected to the source electrode and the current sense electrode, respectively.
  • energy loss during switching operation can be reduced.
  • FIG. 1 is a schematic plan view showing the configuration of a semiconductor device according to a first embodiment
  • FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment
  • FIG. 3 is a schematic cross-sectional view showing the configuration of a semiconductor device according to Modification 1
  • FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to Modification 2
  • FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to Modification 3;
  • FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to Modification 3; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are schematic cross-sectional views showing the method for manufacturing the semiconductor device
  • FIG. 10 is a schematic plan view showing the configuration of a semiconductor device according to a second embodiment
  • FIG. 5 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment
  • FIG. 11 is a schematic plan view showing the configuration of a semiconductor device according to a third embodiment
  • FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a third embodiment
  • FIG. 11 is a schematic plan view showing the configuration of a semiconductor device according to a fourth embodiment
  • FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment
  • FIG. 11 is a schematic diagram showing the configuration of a power converter diagram according to Embodiment 5;
  • a portion having a lower density than another portion means, for example, that the average density of the certain portion is lower than the average density of the other portion.
  • the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. .
  • FIG. 1 is a schematic plan view showing the configuration of the semiconductor device according to the first embodiment
  • FIG. 2 is a schematic cross-sectional view taken along line XX of FIG.
  • the semiconductor device according to the first embodiment will be described as a trench MOSFET containing silicon carbide (SiC).
  • the MOSFET according to the first embodiment includes a main cell region (also referred to as a MOSFET region), a sense cell region, a first peripheral region A, and a second peripheral region. and a separation region.
  • the main cell area and the sense cell area are separated from each other.
  • the peripheral region A is adjacent to the main cell region between the main cell region and the sense cell region.
  • the peripheral region B is adjacent to the sense cell region between the main cell region and the sense cell region.
  • the isolation area is located at the boundary between the peripheral area A and the peripheral area B, and separates the peripheral area A and the peripheral area B from each other.
  • the MOSFET according to the first embodiment includes an epitaxial substrate including an n-type SiC substrate 1 and an n-type SiC epitaxial layer (semiconductor layer) grown thereon.
  • a base region 3 which is a p-type body region, an n-type source region 4 and a p-type well contact layer 11 are provided above the epitaxial layer of the main cell region.
  • Drift layer 2 is an n-type region below base region 3 in the epitaxial substrate, and is included in at least one of SiC substrate 1 and the epitaxial layer.
  • the main cell region includes SiC substrate 1 , drift layer 2 , base region 3 , source region 4 and well contact layer 11 .
  • the well contact layer 11 has a p-type impurity concentration higher than that of the base region 3 .
  • the depth of well contact layer 11 is the same as or deeper than source region 4 , and well contact layer 11 is in contact with base region 3 .
  • Well contact layer 11 is selectively (partially) provided in source region 4 and surrounded by source region 4 in plan view, as shown in FIG. In FIG. 1, the shape of the well contact layer 11 in plan view is dot-like, but it may be stripe-like.
  • the main cell region includes a bottom protective layer 5 as a first bottom protective layer, a gate oxide film 6 as a gate insulating film, a trench 7 as a first trench, and a polycrystalline silicon layer as a gate electrode. It includes a silicon electrode 8 , a sidewall connection layer 9 as a connection layer, an interlayer oxide film 10 , a source electrode 13 and a drain electrode 14 .
  • the trench 7 penetrates the base region 3 and the source region 4 to reach the drift layer 2 and is partially in contact with the drift layer 2 .
  • a gate oxide film 6 is provided to cover the sidewalls and bottom of the trench 7 , and the polysilicon electrode 8 is embedded in the trench 7 via the gate oxide film 6 .
  • the gate electrode is not limited to the polysilicon electrode 8, and may be a metal electrode.
  • a polysilicon electrode 8 embedded in the trench 7 is electrically connected to a gate pad (not shown) of the MOSFET.
  • the electrical connection between the first component and the second component means that the first component and the second component are not insulated.
  • a p-type bottom protection layer 5 is provided at the bottom of the trench 7 .
  • the bottom protective layer 5 may be provided on at least part of the bottom of the trench 7 .
  • the bottom protective layer 5 may be provided, for example, periodically in the longitudinal direction of the trench 7 (the depth direction in FIG. 2), or may be provided on half of the bottom of the trench 7 in a cross section intersecting the longitudinal direction. Further, the bottom protective layer 5 may be provided on the entire bottom of the trench 7 , or may be provided on the bottom of the trench 7 so as to protrude into the drift layer 2 .
  • a p-type sidewall connection layer 9 is provided along at least part of the sidewall of the trench 7 .
  • the sidewall connection layer 9 may be provided only on one sidewall of the trench 7 or may be provided on both sidewalls.
  • Sidewall connection layer 9 connects bottom protective layer 5 and base region 3 .
  • the sidewall connection layers 9 may be arranged with any period along the longitudinal direction of the trenches 7 .
  • the interlayer oxide film 10 is provided on the upper surface of the epitaxial layer and covers the polysilicon electrode 8 .
  • Contact holes reaching the source region 4 and the base region 3 are provided in the interlayer oxide film 10, and low-resistance ohmic electrodes (not shown) are provided in the contact holes.
  • the source electrode 13 is connected to the source region 4 and well contact layer 11 in the main cell region.
  • source electrode 13 has a portion on interlayer oxide film 10 and an ohmic electrode in the contact hole of interlayer oxide film 10 .
  • the drain electrode 14 is provided on the lower surface of the SiC substrate 1 and is made of an electrode material such as an aluminum (Al) alloy.
  • the polysilicon electrodes 8 are arranged in a stripe shape in plan view. In the main cell area, the polysilicon electrode 8 and its peripheral portion function as a MOSFET.
  • the surface of the SiC substrate 1 is a plane angled at 4° with respect to the (0001) plane, which is the c-plane of the SiC crystal. This is for growing a crystal having a desired crystal structure in a SiC crystal having crystal polymorphism.
  • no atomic layer step occurs at the interface between the gate oxide film 6 and SiC. A layer step occurs.
  • this atomic layer step affects the amount of the interface state, and the gate withstand voltage is higher in the configuration in which the trench 7 is arranged parallel to the off-angle. For this reason, it is desirable that the striped trenches 7 forming the main cell region are arranged parallel to the off-angle.
  • the above-described side wall connection layer 9 can be arranged intensively on the surface having many interface states or all over the surface to suppress the decrease in the gate breakdown voltage. is possible.
  • the thickness of the side portions and the thickness of the bottom portion of the gate oxide film 6 shown in FIG. may be thicker than the thickness of the gate oxide film 6 in contact with the side of the . Only the portion in contact with the side of the polysilicon electrode 8 actually functions as the gate oxide film 6 for the operation of the MOSFET, and the portion in contact with the bottom does not contribute to the operation of the MOSFET. In addition, the electric field tends to concentrate on the bottom of the trench 7, and the gate oxide film 6 tends to become defective. Therefore, in addition to providing the bottom protective layer 5, the electric field applied to the gate oxide film 6 is further reduced by making the portion of the gate oxide film 6 in contact with the bottom of the polysilicon electrode 8 thicker than the other portions. can be mitigated.
  • the sense cell region has the same configuration as the main cell region, and is provided on the same semiconductor chip as the main cell region.
  • a sense cell region includes a SiC substrate 1, a drift layer 2, a base region 3, a source region 4, a bottom protective layer 5, a gate oxide film 6, a trench 7, a polysilicon electrode 8, and a sidewall connection layer 9. , an interlayer oxide film 10 , a well contact layer 11 and a drain electrode 14 .
  • the sense cell region includes a current sense electrode 13a instead of the source electrode 13.
  • the current sense electrode 13a is an individual electrode electrically isolated from the source electrode 13 and connected to the source region 4 and the well contact layer 11 in the sense cell region.
  • current sense electrode 13a has a portion on interlayer oxide film 10 and an ohmic electrode (not shown) in a contact hole of interlayer oxide film 10.
  • the sense cell area has a smaller area than the main cell area, and the amount of current that can flow is smaller than that of the main cell area.
  • the sense cell region since the sense cell region has the same structure as the main cell region, there is a certain correlation between the current flowing through the sense region and the current flowing through the main cell region. Therefore, a large current flowing through the main cell region can be detected based on a small current flowing through the sense region.
  • the current flowing in the main cell region is detected based on the signal of the minute current flowing in the current sense electrode 13a in the sense cell region, and the operation of the MOSFET is suppressed when the detected current is equal to or higher than the threshold. According to such a configuration, when an overcurrent flows in the main cell region, it is possible to suppress problems that occur in the main cell region due to heat generation due to the size of the area and the large amount of current.
  • a peripheral region A adjacent to the main cell region includes a SiC substrate 1, a drift layer 2, a bottom protective layer 5a as a second bottom protective layer, a gate oxide film 6, a trench 7a as a second trench, a capacitor An electrode 8a, an interlayer oxide film 10, a field insulating film 12 and a drain electrode 14 are provided.
  • the width of the peripheral region A is, for example, 5 ⁇ m to 100 ⁇ m.
  • the trench 7 a passes through the base region 3 and the source region 4 like the trench 7 and is provided above the drift layer 2 .
  • the width of trench 7a is wider than the width of trenches 7 in the main cell region and the sense cell region.
  • the p-type bottom protection layer 5a is provided on the bottom of the trench 7a and electrically connected to the source electrode 13. As shown in FIG. In Embodiment 1, the bottom protection layer 5 a is connected to the source electrode 13 via the sidewall connection layer 9 , the base region 3 and the well contact layer 11 .
  • the gate oxide film 6 and the field insulating film 12 are selectively provided on the bottom protection layer 5a.
  • Capacitor electrode 8 a is provided on gate oxide film 6 .
  • the capacitor electrode 8a is part of the polysilicon electrode 8 and is connected to the polysilicon electrode 8 in the trench 7 in the main cell region.
  • the interlayer oxide film 10 covers the gate oxide film 6, the field insulating film 12 and the capacitor electrode 8a.
  • the peripheral region B includes the SiC substrate 1, the drift layer 2, the bottom protective layer 5b that is the third bottom protective layer, the gate oxide film 6, the trench 7b that is the third trench, and the capacitor electrode. 8 b , an interlayer oxide film 10 , a field insulating film 12 and a drain electrode 14 .
  • the width of the peripheral region B is, for example, 5 ⁇ m to 100 ⁇ m.
  • the trench 7 b penetrates the base region 3 and the source region 4 like the trench 7 and is provided above the drift layer 2 .
  • the width of the trench 7b is wider than the width of the trenches 7 in the main cell region and the sense cell region.
  • the p-type bottom protective layer 5b is provided at the bottom of the trench 7b and electrically connected to the current sense electrode 13a.
  • the bottom protection layer 5b is connected to the current sense electrode 13a via the sidewall connection layer 9, the base region 3, and the well contact layer 11. As shown in FIG.
  • the gate oxide film 6 and the field insulating film 12 are selectively provided on the bottom protection layer 5b.
  • Capacitor electrode 8 b is provided on gate oxide film 6 .
  • the capacitance electrode 8b is a part of the polysilicon electrode 8 and is connected to the polysilicon electrode 8 within the trench 7 in the sense cell region.
  • the capacitive electrodes 8a and 8b may be common electrodes connected to metal electrodes (not shown) of the same potential located at both ends in the horizontal direction or the depth direction of FIG.
  • the interlayer oxide film 10 covers the gate oxide film 6, the field insulating film 12 and the capacitor electrode 8b.
  • the bottom protective layer 5a is electrically connected to the source electrode 13, and the bottom protective layer 5b is electrically connected to the current sense electrode 13a.
  • the withstand voltage of the MOSFET depends on the depth of the trench. Therefore, it is desirable that the depth of the trench 7a in the peripheral region A, the depth of the trench 7b in the peripheral region B, the depth of the trench 7 in the main cell region, and the depth of the trench 7 in the sense cell region are the same. With such a configuration, the breakdown voltage can be increased. If the trenches have different depths, the bottom protective layer 5a of the peripheral region A, the bottom protective layer 5b of the peripheral region B, the bottom protective layer 5 of the main cell region, and the bottom protective layer 5 of the sense cell region. It is desirable that formation conditions such as impurity concentration and depth be changed.
  • the isolation region comprises SiC substrate 1 , drift layer 2 , base region 3 , source region 4 , gate oxide film 6 , interlayer oxide film 10 , field insulating film 12 and drain electrode 14 .
  • a mesa 70 is provided between the peripheral area A and the peripheral area B. As shown in FIG. In Embodiment 1, mesa 70 includes drift layer 2 , base region 3 , and source region 4 . According to the configuration in which the mesa 70 includes the base region 3 as in the first embodiment, it is possible to suppress a decrease in breakdown voltage around the isolation region and an increase in the oxide film electric field. Although the mesa 70 includes the source region 4 in the first embodiment, it may not include the source region 4 . In the isolation region, instead of the mesa 70, a trench for electrically isolating the bottom protective layers 5a and 5b may be provided, or an insulating layer may be provided in the trench.
  • a mesa 70 separates the region between the trench 7a and the trench 7b.
  • the bottom protective layers 5a, 5b are also separated by a mesa 70.
  • the width of the mesa 70 is preferably less than or equal to the width of the mesa between the trenches 7 in the main cell region and less than or equal to the width of the mesa between the trenches 7 in the sense cell region. That is, the width of the mesa 70 is preferably less than or equal to the width of the mesa in the main cell region and less than or equal to the width of the mesa in the sense cell region.
  • the width of the mesa 70 is, for example, 1 ⁇ m to 5 ⁇ m, although it also depends on the width between the trenches 7 . According to such a configuration, it is possible to suppress a decrease in breakdown voltage of the entire MOSFET.
  • a field insulating film 12, a gate oxide film 6, and an interlayer oxide film 10 are provided on the mesa 70 in this order.
  • the capacitor electrodes 8a and 8b in the peripheral regions A and B may be provided so as to protrude into the isolation region.
  • the sidewall connection layer 9 may be provided only on one sidewall of the trench 7 . If it is provided only on one side wall, one of the bottom protective layers 5a and 5b does not have to be connected to the side wall connection layer 9.
  • the bottom protective layer 5a may not be electrically connected to the source electrode 13, but the bottom protective layer 5b may be electrically connected to the current sense electrode 13a (not shown). Even with these configurations, energy loss during switching operation can be reduced to some extent.
  • the bottom protective layer 5b which is not connected to the side wall connection layer 9, is extended in the in-plane direction so that it is connected to the bottom protective layer 5 in the sense cell region connected to the side wall connection layer 9.
  • bottom protective layer 5a not connected to sidewall connection layer 9 extends in the in-plane direction and is connected to bottom protective layer 5 in the main cell region connected to sidewall connection layer 9.
  • an impurity region 21 (a region indicated by a dotted line in FIG. 3), which is in contact with one side wall of the trench 7 where the side wall connection layer 9 is not provided and has a higher n-type impurity concentration than the drift layer 2, is the main region. It may be provided in at least one of the cell region and the sense region. With such a configuration, the on-resistance of at least one of the main cell region and the sense region can be reduced.
  • the capacitive electrodes 8a and 8b are spaced apart in the isolation region, but this is not the only option.
  • the capacitor electrodes 8a and 8b may be extended to the isolation region and connected to each other.
  • a p-type low-resistance layer 11a or an n-type low-resistance layer 4a which is in contact with the bottom protective layer 5a in the peripheral region A and has a lower resistance than the bottom protective layer 5a, may be provided.
  • a p-type low-resistance layer 11b or an n-type low-resistance layer 4b which is in contact with the bottom protective layer 5b in the peripheral region B and has a resistance lower than that of the bottom protective layer 5b, may be provided.
  • the low-resistance layers 11a and 11b may be high-concentration impurity layers similar to the well contact layer 11 as long as the impurity concentration is higher than that of the bottom protection layers 5a and 5b. High-concentration impurity layers having different thickness profiles may also be used.
  • the low-resistance layers 4a and 4b may be high-concentration impurity layers similar to the source region 4 as long as the impurity concentration is higher than that of the bottom protective layers 5a and 5b. may be high-concentration impurity layers with different values.
  • the sheet resistance of the path through which the displacement current flows in the bottom of the trench 7a in the peripheral region A can be reduced. can reduce the voltage generated by the influence of
  • the sheet resistance of the path through which the displacement current flows in the bottom of the trench 7b in the peripheral region B can be reduced. , the voltage generated by the influence of the displacement current can be reduced.
  • an epitaxial layer is formed on the SiC substrate 1 .
  • a low-resistance n-type SiC substrate 1 having a 4H polytype is prepared, and an epitaxial layer that will become an n-type drift layer 2 is formed thereon by chemical vapor deposition (CVD). grow epitaxially.
  • the n-type impurity concentration of the drift layer 2 is, for example, 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 and its thickness is, for example, 5 to 200 ⁇ m.
  • a base region 3 and a source region 4 are formed by ion-implanting a predetermined dopant into the upper surface of the epitaxial layer.
  • the base region 3 is formed by ion implantation of p-type impurities.
  • the depth of ion implantation of the p-type impurity is within the range not exceeding the thickness of the epitaxial layer, for example, about 0.5 to 3 ⁇ m.
  • the ion-implanted p-type impurity concentration is set higher than the n-type impurity concentration of the epitaxial layer.
  • the p-type impurity concentration of the base region 3 is, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • a region of the epitaxial layer deeper than the implantation depth of the p-type impurity ions remains as the n-type drift layer 2 .
  • Base region 3 may be formed by p-type epitaxial growth.
  • the impurity concentration and thickness of the base region 3 in that case are the same as those in the case of forming by ion implantation.
  • the source region 4 is formed by implanting n-type impurity ions into the upper surface of the base region 3 .
  • the depth of ion implantation of the n-type impurity is made shallower than the thickness of the base region 3 .
  • the concentration of the n-type impurity to be ion-implanted is made equal to or higher than the p-type impurity concentration of the base region 3 .
  • the n-type impurity concentration of the source region 4 is, for example, 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the order of ion implantation for forming the p-type and n-type regions need not be as described above as long as the structure shown in FIG. 2 is finally obtained.
  • a p-type well contact layer 11 is then formed by ion implantation into the source region 4 (see FIG. 7).
  • the p-type impurity concentration of the well contact layer 11 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 22 cm ⁇ 3 or less.
  • the thickness of the well contact layer 11 is formed to be equal to or greater than the thickness of the source region 4 so that the well contact layer 11 is reliably brought into contact with the base region 3 .
  • a silicon oxide film 15 is deposited on the upper surface of the epitaxial layer to a thickness of about 1 to 3 ⁇ m, and an etching mask 16 made of a resist material is formed thereon (see FIG. 8).
  • the etching mask 16 is formed into a pattern with openings in the forming regions of the trenches 7, 7a and 7b using a photolithographic technique.
  • RIE reactive ion etching
  • RIE is performed using the patterned silicon oxide film 15 as a mask to form trenches 7, 7a and 7b that penetrate the source region 4 and the base region 3 and reach the drift layer 2 (see FIG. 9).
  • the depths of the trenches 7, 7a and 7b are equal to or greater than the depth of the base region 3, and their thicknesses are, for example, about 1.0 to 6.0 ⁇ m.
  • an implantation mask is formed in a pattern in which at least part of the trenches 7, 7a and 7b are opened, and ion implantation is performed using this as a mask to form p-type bottom protective layers 5, 5a and 5b on the bottom of the trench 7.
  • the p-type impurity concentration of the bottom protective layers 5, 5a, 5b is, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 and their thickness is, for example, 0.1 to 2.0 ⁇ m. .
  • the impurity concentration of the bottom protective layers 5, 5a, 5b is determined based on the electric field applied to the gate oxide film 6 when a rated voltage is applied between the drain and source of the MOSFET.
  • the silicon oxide film 15, which is an etching mask for forming the trenches 7, 7a and 7b, may be used as the implantation mask for the bottom protection layers 5, 5a and 5b. In this case, simplification of the manufacturing process and cost reduction can be achieved.
  • the silicon oxide film 15 is used as an implantation mask for the bottom protective layers 5, 5a, 5b, the silicon oxide film 15 is formed so that a certain thickness of the silicon oxide film 15 remains after the trenches 7, 7a, 7b are formed. 15 thickness and etching conditions need to be adjusted. Since the bottom protective layer 5 forms a pn junction with the drift layer 2 , like the pn junction between the base region 3 and the drift layer 2 it can also be used as a diode.
  • p-type impurity ions are implanted obliquely into the side walls of the trenches 7, 7a and 7b using an implantation mask 17 having openings at arbitrary pitches in the depth direction of the cross section.
  • sidewall connection layers 9 are formed (see FIG. 11).
  • the drift layer 2 and the like in the isolation region are covered with an implantation mask 17 so that the sidewall connection layer 9 is not formed in the isolation region.
  • the sidewall connection layer 9 has a p-type impurity concentration of, eg, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 and a thickness of, eg, 0.1 to 2.0 ⁇ m.
  • the sidewall connection layer 9 may be formed by ion implantation from the surface of the epitaxial layer using a mask (not shown). In this case, it is desirable to perform ion implantation before opening the trenches 7, 7a and 7b.
  • concentration and thickness of sidewall connection layer 9 when using ion implantation from the epitaxial layer surface are similar to those when using ion implantation from the sidewalls of trenches 7, 7a, 7b.
  • the order of forming the n-type and p-type layers and regions formed in the drift layer 2 is not particularly limited.
  • the n-type impurity may be, for example, nitrogen (N) or phosphorus (P), and the p-type impurity may be, for example, aluminum (Al) or boron (B).
  • annealing is performed using a heat treatment apparatus to activate the impurities ion-implanted so far.
  • This annealing is performed in an inert gas atmosphere such as argon (Ar) gas or in vacuum at a temperature of 1300 to 1900° C. for a processing time of 30 seconds to 1 hour.
  • a silicon oxide film is formed on the entire upper surface of the epitaxial layer including the inner surfaces of the trenches 7 .
  • This silicon oxide film may be formed by thermally oxidizing the upper surface of the epitaxial layer, or may be deposited on the epitaxial layer.
  • a polysilicon film is deposited on the silicon oxide film by low pressure CVD, and the silicon oxide film and the polysilicon film are patterned or etched back to form a gate oxide film 6, a polysilicon electrode 8 and a capacitor electrode 8a, 8b (see FIG. 12).
  • an interlayer oxide film is formed on the entire upper surface of the structure thus far formed by the low pressure CVD method. cover the By patterning the interlayer oxide film, an interlayer oxide film 10 having contact holes reaching the base region 3 and the source region 4 is formed (see FIG. 13).
  • an ohmic electrode (not shown) is formed on the epitaxial layer exposed at the bottom of the contact hole of the interlayer oxide film 10 .
  • a metal film containing nickel (Ni) as a main component is formed on the entire upper surface of the structure formed so far, and heat treatment is performed at 600 to 1100° C. to react the metal film with the silicon carbide of the epitaxial layer.
  • a silicide film is formed as an ohmic electrode.
  • the unreacted metal film remaining on the interlayer oxide film 10 or the like is removed by wet etching using nitric acid, sulfuric acid, hydrochloric acid, or a mixture thereof with hydrogen peroxide water.
  • the heat treatment may be performed again. In this case, by performing the heat treatment at a higher temperature than the previous heat treatment, an ohmic contact with a lower contact resistance is formed. At this time, if the interlayer oxide film 10 is too thin, a reaction between the polysilicon electrode 8 and the metal film will occur, so it is desirable that the interlayer oxide film 10 has a sufficient thickness.
  • the source electrode 13 and the current sense electrode 13a are formed on the interlayer oxide film 10 and in the contact hole.
  • the drain electrode 14 is formed by depositing an electrode material such as Al alloy on the lower surface of the SiC substrate 1 .
  • the MOSFET according to the first embodiment shown in FIGS. 1 and 2 is obtained.
  • bottom protective layer 5a is electrically connected to source electrode 13
  • bottom protective layer 5b is electrically connected to current sense electrode 13a.
  • the MOSFET in which the drift layer 2 and the SiC substrate 1 (buffer layer) have the same conductivity type is described, but in the above configuration, the drift layer 2 and the SiC substrate 1 have different conductivity types. It is also applicable to IGBTs.
  • the SiC substrate 1 is of p-type, it becomes an IGBT.
  • the source region 4 and source electrode 13 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively, and the drain electrode 14 of the MOSFET corresponds to the collector electrode.
  • a semiconductor device containing SiC which is one of wide bandgap semiconductors, has been described, but the above configuration is applicable to other wide bandgap semiconductors such as gallium nitride (GaN)-based materials and diamond. It can also be applied to a semiconductor device including Reduction of energy loss during the switching operation described above is particularly effective in a semiconductor device including a wide bandgap semiconductor capable of using high voltage.
  • GaN gallium nitride
  • FIG. 14 is a schematic plan view showing the configuration of the semiconductor device according to the second embodiment
  • FIG. 15 is a schematic cross-sectional view taken along line XX of FIG.
  • both ends of the well contact layer 11 in the sense cell region are positioned outside both ends of the contact hole 10a adjacent to the well contact layer 11 in any cross section. is different from the first embodiment.
  • contact hole 10a in interlayer oxide film 10 in the sense cell region has a cross section in which contact hole 10a is not in contact with source region 4 but is in contact with well contact layer 11.
  • FIG. 11 Such a wide well contact layer 11 can be formed by changing the photolithography mask pattern used in forming the well contact layer 11 from that of the first embodiment.
  • the static electricity resistance is an amount indicating the resistance to the voltage applied to the gate oxide film 6 when static electricity is generated. is inversely proportional to Therefore, in order to increase the electrostatic resistance of the sense cell region, the voltage applied to the gate oxide film 6 should be reduced by increasing the capacitance between the gate and the current sense electrode.
  • contact hole 10a in interlayer oxide film 10 in the sense cell region is configured to partially have a cross section in contact with well contact layer 11 without contacting source region 4. .
  • a current can be detected in the cross section where the contact hole 10a is in contact with the source region 4.
  • the capacitance between the gate and the current sense electrode can be increased.
  • the electrostatic resistance of the sense cell region can be increased, and the area of the portion through which the current flows can be reduced in the sense cell region.
  • the well contact layer 11 having a wide width as described above may be provided for any contact hole 10a of any cross section.
  • the well contact layer 11 may be provided over the entire bottom surface of at least one contact hole 10a, or the well contact layer 11 may be provided over the entire bottom surface of the contact holes 10a at regular intervals.
  • the entire source region 4 may be replaced with the well contact layer 11 , or the well contact layer 11 may be formed at the bottom of the trench 7 in contact with the source region 4 .
  • both ends of well contact layer 11 in the sense cell region are located outside both ends of contact hole 10a adjacent to well contact layer 11 in any cross section. .
  • the static electricity resistance of the sense cell region can be increased, and the area of the portion through which the current flows can be reduced in the sense cell region.
  • FIG. 16 is a schematic plan view showing the configuration of the semiconductor device according to the third embodiment
  • FIG. 17 is a schematic cross-sectional view taken along line XX of FIG.
  • the capacitive electrode 8b is provided on the bottom protective layer 5b in the peripheral region B via the gate oxide film 6, which is an insulating film, the capacitive electrode 8b and the bottom protective layer 5b form a capacitor. ing.
  • the capacitive electrode 8b is connected to the polysilicon electrode 8 which is the gate electrode, and the bottom protective layer 5b is electrically connected to the current sense electrode 13a. It is possible to increase the capacitance area between the gate and the current sense electrode.
  • a capacitor is formed by the capacitive electrode 8b and the bottom protective layer 5b in part of the sense cell region.
  • field insulating film 12 separates capacitive electrode 8b from bottom protective layer 5b, so that a capacitor is not substantially formed.
  • the capacitance of the sense cell region can be increased by the capacitor formed by the capacitive electrode 8b and the bottom protective layer 5b, the effect is relatively small because the capacitor is formed only in a part of the sense cell region. small.
  • the field insulating film 12 is provided only in the portion adjacent to the isolation region, and the capacitor electrode 8b extends to the portion adjacent to the isolation region. It is As a result, a capacitor is also formed in the peripheral region B by the capacitive electrode 8b and the bottom protection layer 5b, so that the static electricity resistance of the sense cell region can be increased, and the area of the portion through which current flows can be reduced in the sense cell region. can.
  • the semiconductor device according to the third embodiment as described above can be formed by changing the photolithographic mask pattern used in forming the capacitor electrode 8b and the field insulating film 12 from that of the first embodiment. Also, since various shapes can be used for the shape of the capacitor when viewed from above, the shape of the capacitor when viewed from above does not have to be a stripe shape as shown in FIG.
  • a capacitor can be formed in the peripheral region B by the capacitive electrode 8b and the bottom protection layer 5b. With such a configuration, the static electricity resistance of the sense cell region can be increased, and the area of the portion through which the current flows can be reduced in the sense cell region.
  • FIG. 18 is a schematic plan view showing the configuration of a semiconductor device according to the fourth embodiment
  • FIG. 19 is a schematic cross-sectional view taken along line XX of FIG.
  • the bottom protection layers 5a and 5b of the peripheral regions A and B are connected to the source electrode 13 and the current sense electrode 13a through the sidewall connection layers 9, respectively.
  • the distance between the bottom protection layers 5a and 5b and the side wall connection layer 9 becomes relatively long, so the displacement current path during switching becomes long, resulting in displacement.
  • the high voltage generated by the current can cause the device to malfunction.
  • connection electrodes 18a and 18b are provided in the peripheral regions A and B, respectively.
  • ohmic electrodes are provided in contact holes provided in the interlayer oxide film 10 and the field insulating film 12 in the peripheral regions A and B.
  • the connection electrodes 18a and 18b have the ohmic electrodes and are provided on the bottom protective layers 5a and 5b, respectively.
  • the connection electrodes 18a and 18b are connected to the source electrode 13 and the current sense electrode 13a, respectively.
  • connection electrode 18a connects the bottom protective layer 5a and the source electrode 13
  • connection electrode 18a connects the bottom protective layer 5b and the current sense electrode 13a
  • connection electrodes 18a and 18b can be formed by changing the photolithography mask pattern used when forming the interlayer oxide film 10 from that of the first embodiment. Further, since various shapes can be used for the shape of the connection electrodes 18a and 18b when viewed from the top, the shape of the connection electrodes 18a and 18b when viewed from the top does not have to be an island shape as shown in FIG. For example, it may be striped. Moreover, although both connection electrodes 18a and 18b are provided in the above description, only one of the connection electrodes 18a and 18b may be provided.
  • connection electrodes 18a and 18b can suppress the generation of high voltage due to the displacement current in the peripheral regions A and B, so that the reliability of the device can be improved. .
  • the fifth embodiment applies the semiconductor devices according to the first to fourth embodiments described above to a power converter.
  • the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a fifth embodiment.
  • FIG. 20 is a block diagram showing the configuration of a power conversion system to which the power converter according to Embodiment 5 is applied.
  • the power conversion system shown in FIG. 20 is composed of a power supply 100, a power converter 200, and a load 300.
  • the power supply 100 is a DC power supply and supplies DC power to the power converter 200 .
  • the power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too.
  • the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300 , converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300 .
  • the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201. , and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 .
  • the drive circuit 202 turns off each normally-off switching element by setting the voltage of the gate electrode and the voltage of the source electrode to the same potential.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 .
  • the load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for air conditioning equipment.
  • the main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 .
  • the main conversion circuit 201 according to the fifth embodiment is a two-level three-phase full bridge circuit, and has six switching elements and respective switching elements. can consist of six freewheeling diodes anti-paralleled to .
  • a semiconductor device manufactured by the semiconductor device manufacturing method according to any one of the first to fourth embodiments described above is applied to each switching element of the main conversion circuit 201 .
  • each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
  • Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .
  • the drive circuit 202 generates a drive signal for driving the switching element of the main converter circuit 201 and supplies it to the control electrode of the switching element of the main converter circuit 201 .
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the driving signal is a voltage signal (ON signal) greater than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage lower than the threshold voltage of the switching element. signal (off signal).
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the silicon carbide semiconductor devices according to Embodiments 1 to 4 are applied as the switching elements of main converter circuit 201, power with improved reliability of low loss and high-speed switching can be obtained.
  • a conversion device can be implemented.
  • the present disclosure is not limited to this, and can be applied to various power converters.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it.
  • the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.
  • 2 drift layer 3 base region, 4 source region, 4a, 4b, 11a, 11b low resistance layer, 5, 5a, 5b bottom protective layer, 6 gate oxide film, 7, 7a, 7b trench, 8 polysilicon electrode, 8a , 8b capacity electrode, 9 sidewall connection layer, 10a contact hole, 11 well contact layer, 13 source electrode, 13a current sense electrode, 21 impurity region, 70 mesa, 201 main conversion circuit, 202 drive circuit, 203 control circuit.

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