WO2022249297A1 - 半導体素子の駆動方法、及び、駆動装置、並びに、電力変換装置 - Google Patents
半導体素子の駆動方法、及び、駆動装置、並びに、電力変換装置 Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
Definitions
- the present disclosure relates to a semiconductor device driving method, a driving device, and a power conversion device.
- MOS-FET Metal-Oxide-Semiconductor Field-Effect Transistor
- IGBT Insulated Gate Bipolar Transistor
- an overcurrent path including the semiconductor element may be formed by turning on the semiconductor element. Even in such a case, it is required to turn on and off the semiconductor element so as to avoid damage to the semiconductor element due to the influence of overcurrent.
- the semiconductor element in order to prevent the semiconductor element from being destroyed even when an overcurrent occurs, the semiconductor element must be turned off before the time until the semiconductor element is destroyed (so-called short-circuit resistance) elapses, or The condition is that the surge voltage generated in the process of interrupting the overcurrent must be suppressed below the withstand voltage capability of the semiconductor element. In order to satisfy this condition, it is desirable that the switching speed is low, contrary to the steady switching operation.
- Patent Document 1 while suppressing the occurrence of surge current by gently performing turn-on until the mirror period, when the mirror period is exceeded, turn-on is speeded up to reduce switching loss.
- a semiconductor drive is described for enabling a decreasing, active gate drive method even if the mirror period cannot be detected with precision. Specifically, it describes reducing both surge current and switching loss by PWM (Pulse Width Modulation) control of the gate input signal corresponding to the mirror period at turn-on or turn-off.
- PWM Pulse Width Modulation
- Patent Literature 1 The semiconductor driving device of Patent Literature 1 is mainly directed to reducing power loss and current surge in switching at steady state, and regarding the case where an overcurrent path is formed according to the turn-on of the semiconductor element, Not mentioned. For this reason, there is concern that the control of the gate voltage described in Patent Document 1 is less effective in reducing the possibility of damage to the semiconductor element in the event of an abnormality in which an overcurrent occurs.
- the present disclosure has been made to solve such problems, and the purpose of the present disclosure is to suppress the influence on the switching loss during normal operation and reduce the possibility of damage during overcurrent abnormalities. It is to control the switching of the semiconductor device so that it is reduced.
- a semiconductor device driving method for turning on and off a semiconductor device in accordance with a drive control signal includes (a) gates of a semiconductor device in an off state in response to a turn-on command in which a drive control signal transitions from a first level to a second level; and (b) in response to a turn-off command in which the drive control signal transitions from the second level to the first level, start the turn-off operation of discharging the gate of the on-state semiconductor device.
- the voltage drop period is provided so that the voltage of the gate temporarily drops due to discharge of the gate after the end of the mirror period.
- the voltage rise period is provided so that the voltage of the gate temporarily rises due to charging of the gate during the period in which the current of the semiconductor element is decreasing.
- a semiconductor element driving device for turning on and off a semiconductor element according to a drive control signal includes a drive adjustment section and a drive circuit.
- the drive adjustment unit is turned off in response to a turn-on command in which the drive control signal transitions from the first level to the second level and a turn-off command in which the drive control signal transitions from the second level to the first level.
- a drive signal is generated for controlling a turn-on operation for charging the gate of the semiconductor element and a turn-off operation for discharging the gate of the on-state semiconductor element.
- a drive circuit charges or discharges the gate according to the drive signal.
- the drive adjustment unit includes a voltage drop period provided within a period in which the drive control signal is maintained at the second level after the start of the turn-on operation, and a period in which the drive control signal is maintained at the first level after the start of the turn-off operation.
- the drive signal is generated so as to arrange at least one of the voltage rise period provided within the period.
- the voltage drop period is provided so that the voltage of the gate temporarily drops due to discharge of the gate after the end of the mirror period.
- the voltage rise period is provided so that the voltage of the gate temporarily rises due to charging of the gate during the period in which the current of the semiconductor element is decreasing.
- a power converter is provided in still another aspect of the present disclosure.
- the power conversion device includes at least one semiconductor element, and includes a main conversion circuit that converts input power and outputs the power, and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.
- the control signal includes a drive control signal for each semiconductor element.
- the main conversion circuit further includes the driving device arranged corresponding to each of the semiconductor elements. The drive device controls on/off of each semiconductor element according to the drive control signal.
- the present disclosure by temporarily providing a voltage drop period after the end of the mirror period during the turn-on operation, it is possible to suppress an increase in the drain current of the semiconductor element in the short-circuit state, and temporarily increase the voltage during the turn-off operation.
- By setting a period it is possible to suppress the surge voltage that occurs when the semiconductor device is turned off in a short-circuited state, so it is possible to suppress the impact on switching loss during normal operation and reduce the possibility of damage during overcurrent abnormalities. can control the switching of the semiconductor device.
- FIG. 3 is a block diagram for explaining the functions of the drive device according to the embodiment;
- FIG. FIG. 3 is a general operating waveform diagram in normal turn-on operation of a semiconductor device;
- FIG. 4 is a general operation waveform diagram in turn-on operation when a semiconductor device is abnormal. 4 is a graph illustrating the relationship between gate voltage and drain current when a short-circuit current flows through a semiconductor element;
- 1 is a block diagram for explaining a configuration example of a driving device according to Embodiment 1;
- FIG. FIG. 10 is an operating waveform diagram of the semiconductor element turned on by the driving device according to the first embodiment in normal state;
- FIG. 10 is an operation waveform diagram of the semiconductor element turned on by the driving device according to the first embodiment when there is an abnormality;
- FIG. 10 is an operation waveform diagram of the semiconductor device turned on by the drive device according to the modification of the first embodiment when there is an abnormality;
- FIG. 7 is a block diagram for explaining a configuration example of a driving device according to Embodiment 2;
- FIG. FIG. 2 is a general drain voltage-drain current characteristic diagram of a semiconductor device;
- FIG. 10 is an operation waveform diagram for explaining variable adjustment of a drop period using a drain voltage as an information amount in the driving device according to the second embodiment;
- FIG. 11 is a first flow chart for explaining control processing for variable adjustment of a decrease period in the drive device according to Embodiment 2;
- FIG. 11 is an operation waveform diagram for explaining variable adjustment of a decrease period using a drain current as an information amount in the driving device according to the second embodiment
- FIG. 5 is a graph for explaining the temperature dependence of FIG. 4
- FIG. 10 is an operation waveform diagram for explaining variable adjustment of a decrease period using an element temperature as an information amount in the driving device according to the second embodiment
- FIG. 10 is an operation waveform diagram for explaining variable adjustment of a decrease period using a gate voltage as an information amount in the driving device according to the second embodiment
- FIG. 10 is a second flowchart illustrating control processing for variable adjustment of the decrease period based on the information amount of the operating state of the semiconductor element in the drive device according to the second embodiment
- FIG. 3 is a general operation waveform diagram in turn-off operation when a semiconductor device is abnormal.
- FIG. 11 is a block diagram for explaining a configuration example of a driving device according to Embodiment 3;
- FIG. 11 is an operation waveform diagram of a semiconductor element that is turned off by the driving device according to the third embodiment when there is an abnormality;
- FIG. 11 is a block diagram for explaining a configuration example of a driving device according to Embodiment 4;
- FIG. 14 is a flowchart for explaining control processing for variable adjustment of the rising period based on the information amount of the operating state of the semiconductor element in the driving device according to the fourth embodiment;
- FIG. FIG. 14 is a flowchart for explaining control processing for selecting the arrangement of voltage rise periods in the drive device according to the fourth embodiment;
- FIG. FIG. 12 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 5 is applied;
- FIG. 1 is a block diagram for explaining the functions of the driving device according to this embodiment.
- the driving device 100 controls the on/off of the semiconductor element 10 connected between the high voltage terminal N1 and the low voltage terminal N2, that is, the switching operation, according to the drive control signal Ssw from the control circuit 20.
- the semiconductor element 10 has a drain 11 and a source 12, which are main electrodes, and a gate 15, which is a control electrode.
- the drain is connected with the high voltage terminal N1 and the source 12 is connected with the low voltage terminal N2.
- a current path is formed including the semiconductor element 10 in the ON state and a load (not shown) electrically connected to the high voltage terminal N1 or the low voltage terminal N2.
- a MOS-FET is exemplified as the semiconductor element 10 having a gate, but the semiconductor element 10 can also be an IGBT. In this case, instead of the drain and source, the collector and emitter are the main electrodes.
- the semiconductor element 10 is in a connection state (on state) in which a current is generated between the main electrodes, that is, between the drain 11 and the source 12 according to a gate-source voltage (hereinafter also simply referred to as “gate voltage”), and It is controlled to either an OFF state in which the connection between the drain 11 and the source 12 is cut off.
- the drive device 100 controls the gate voltage so that the semiconductor element 10 turns on and off according to the drive control signal Ssw.
- the drive control signal Ssw is set to "1" during the period when the semiconductor element 10 should be turned on, and set to "0" during the period when the semiconductor element 10 should be turned off. That is, the drive control signal is a binary signal set to either "0" corresponding to the "first level” or "1" corresponding to the "second level”.
- the control circuit 20 can be configured by a PWM pulse output circuit for turning the semiconductor device 10 on and off according to pulse width modulation (PWM) control.
- PWM pulse width modulation
- the semiconductor element 10 turns on when the gate voltage becomes a positive voltage exceeding a predetermined threshold voltage Vth. Therefore, the drive device 100 drives the gate 15 so that the gate voltage becomes a positive voltage exceeding the threshold voltage Vth during the period when the drive control signal Ssw is "1". On the other hand, the drive device 100 drives the gate 15 so that the gate voltage is equal to or lower than the threshold voltage, for example, 0 or a negative voltage during the period when the drive control signal Ssw is "0".
- driving device 100 When drive control signal Ssw changes from “0" to "1", driving device 100 causes gate 15 to increase the gate voltage in order to perform a turn-on operation to change semiconductor element 10 from an off state to an on state. drive. That is, at turn-on, driver 100 charges gate 15 .
- drive device 100 reduces the gate voltage in order to perform a turn-off operation to change semiconductor element 10 from the ON state to the OFF state. drives gate 15 as follows. That is, the driver 100 discharges the gate 15 at turn-off.
- the semiconductor element 10 itself consumes energy during the switching operation of the semiconductor element 10, that is, the turn-on operation and the turn-off operation. In the following, this energy consumption is also referred to as switching losses. If switching loss occurs, it causes heat generation in the semiconductor element 10, so it is desirable that the switching loss is as small as possible.
- FIG. 2 is a general operating waveform diagram for explaining the normal turn-on operation of a semiconductor device.
- the current in the current path including the load (not shown) flows through the semiconductor element 10 as described above.
- semiconductor element 10 is in an OFF state in which the main electrode (drain-source) is cut off, and drain-source voltage Vds (hereinafter referred to as Vds) is the voltage between the main electrodes. , also simply referred to as “drain voltage Vds”) is (Vdd ⁇ Vss), and the drain-source current Id (hereinafter also simply referred to as “drain current Id”), which is the current between the main electrodes, is 0. .
- the drive device 100 starts charging the gate 15 in response to the drive control signal Ssw changing from “0" to "1". That is, the turn-on operation starts at time ts.
- the gate 15 is connected to a power supply node supplying predetermined on-voltage VH. As a result, the gate voltage starts rising from time ts.
- the drain voltage Vds begins to decrease and the drain current Id begins to increase.
- the drain voltage Vds gradually decreases and the drain current Id gradually increases, so that the semiconductor element 10 gradually becomes conductive.
- the gate voltage Vg rises as the parasitic capacitance of the gate 15 is charged. Therefore, even if the gate 15 starts to be charged in accordance with the change in the drive control signal Ssw, the gate voltage Vg does not rise immediately and shows voltage behavior as shown in FIG.
- the parasitic capacitance (gate capacitance) of the gate 15 is not constant and has dependency on the drain voltage Vds.
- the feedback capacitance which is the capacitance between the gate and the drain, is added to the gate capacitance as apparent gate capacitance (so-called mirror capacitance).
- the above Miller capacitance depends on the drain voltage and increases as the drain voltage Vds decreases, but when the drain voltage Vds decreases sufficiently, the increase stops and no further increase occurs. Therefore, the change in the gate voltage Vg is not uniform, and a period called a mirror period 200 during which the gate voltage Vg does not rise occurs between times tb and tc, which corresponds to the period until the Miller capacitance stops increasing. That is, the start time and end time of the mirror period are times tb and tc.
- the gate voltage Vg in the mirror period 200 is hereinafter also referred to as the mirror voltage Vp.
- the drain voltage Vds continues to drop during the mirror period 200, Vds becomes approximately 0 as soon as the mirror period 200 ends. Therefore, at time tc when the mirror period 200 ends, the main electrodes (between the drain and the source) of the semiconductor element 10 become conductive and the turn-on ends. After the end of the mirror period 200, the gate voltage Vg continues to rise, reaches a predetermined voltage (voltage charged by the driving device 100), and saturates.
- the semiconductor device 10 consumes power (Vds ⁇ Id) corresponding to the product of the two when turned on.
- the integrated value of power loss at turn-on is indicated as "generated loss". The generated loss corresponds to the switching loss described above.
- FIG. 3 shows a general operating waveform diagram in a case where an overcurrent occurs in response to the turn-on of the semiconductor device 10 (hereinafter also referred to as an abnormal turn-on operation).
- FIG. 3 illustrates, as a representative example of overcurrent, an operating waveform in a case where a short-circuit path is formed by turning on the semiconductor element 10 .
- gate voltage Vg the drain voltage Vds, and the drain current Id from time ts to time ta are the same as in FIG. However, it is significantly different from FIG. 2 (normal). Specifically, after time ta, gate voltage Vg continues to rise until it reaches a predetermined voltage (voltage charged by driving device 100), including time tb to tc as in FIG.
- the semiconductor element 10 is turned on to form a short-circuit path, so that the drain voltage Vds remains almost unchanged and the mirror period 200 shown in FIG. 2 does not occur. That is, since the feedback capacitance, which is the capacitance between the gate and the drain, does not change, the parasitic capacitance (gate capacitance) of the gate 15 does not increase and remains substantially constant. Therefore, the gate capacitance when a short-circuit path is formed by turning on the semiconductor element 10 has a smaller value than that during a normal turn-on operation (FIG. 2).
- FIG. 4 shows a graph for explaining the relationship between the gate voltage Vg and the drain current Id when a short-circuit current flows through the semiconductor element 10.
- the drain current Id changes depending on the gate voltage Vg. Specifically, a characteristic is shown in which the drain current Id increases as the gate voltage Vg increases. Therefore, in the turn-on operation of the semiconductor device 10 in an abnormal state, the drain current Id continues to increase as the gate voltage Vg rises while the gate 15 is being charged by the drive circuit 150, as shown in the operation waveform example of FIG. . Furthermore, when the gate voltage Vg is saturated, the drain current Id is also saturated with a magnitude dependent on the gate voltage Vg.
- the loss generated in the semiconductor device when an overcurrent occurs due to the turn-on of the semiconductor device 10 is much higher than that during the normal turn-on operation shown in FIG. growing. If the generated loss at this time exceeds the destruction energy of the semiconductor element 10, the semiconductor element 10 will be destroyed.
- a protection circuit is provided for the semiconductor device 10 to turn off the semiconductor device 10 or cut off the short-circuit current path in response to detection of an overcurrent in order to avoid destruction due to overcurrent. be.
- the semiconductor element 10 may be damaged before the protection circuit operates effectively. It is feared that it will lead to destruction.
- the drain current Id does not depend on the gate voltage Vg as shown in FIG. Therefore, in the operation waveforms of FIG. 2, after the mirror period 200, the gate voltage Vg increases, but the drain current Id does not increase and the current value in the mirror period 200 is maintained.
- the loss generated when the semiconductor element 10 is turned on becomes smaller as the switching speed increases during the normal turn-on operation shown in FIG.
- the higher the switching speed the faster the gate voltage rises.
- the higher the switching speed the shorter the time from the start of turn-on until the generated loss reaches the breakdown energy of the semiconductor device 10 .
- FIG. 5 shows a block diagram for explaining a configuration example of the driving device 100 according to the first embodiment.
- FIG. 6 shows an operation waveform diagram in a normal turn-on operation of the semiconductor device on/off-controlled by the driving device 100 shown in FIG.
- the driving device 100 has a driving adjusting section 110 and a driving circuit 150.
- the drive device 100 has the drive control signal Ssw of " The semiconductor device 10 is driven such that there is a voltage drop period 210 during which the drive signal Sdr is set to "0" while being maintained at "1". As shown in FIG. 6, during the voltage drop period 210, the semiconductor device 10 is driven such that the gate voltage Vg begins to drop.
- the drive adjustment unit 110 generates the drive signal Sdr provided with the voltage drop period 210 (FIG. 6) based on the drive control signal Ssw.
- the drive adjustment section 110 has an edge detection section 120 , a delay circuit 130 , a memory 135 , an insertion pulse generation section 140 and a signal synthesis section 145 .
- the function of each element of the drive adjustment unit 110 may be realized by a dedicated electronic circuit (hardware), or may be realized by program processing (software).
- the memory 135 is a concept that represents an element that records time, and stores in advance a predetermined length of elapsed time (length of time) starting from the start of turn-on, as will be described later. Specifically, the memory 135 is configured to store time lengths Ta and Tb that respectively define the start timing and end timing of the voltage drop period 210 in FIG. That is, there is a relationship of Tb>Ta between Ta and Tb.
- the memory 135 can be configured including a digital circuit that stores the above Ta and Tb as digital values.
- the memory 135 may include an analog circuit that provides delay times corresponding to Ta and Tb, which are determined by the circuit constants of passive elements, the number of stages of inverters, or the like.
- the edge detection unit 120 detects a turn-on command and generates a one-shot pulse. That is, the time ts corresponds to the turn-on start timing.
- a one-shot pulse from edge detection section 120 is input to delay circuit 130 . Furthermore, the edge detector 120 transmits the drive control signal Ssw to the signal synthesizer 145 .
- the delay circuit 130 generates and inserts a first pulse P1 obtained by delaying the one-shot pulse from the edge detection unit 120 by Ta and a second pulse P2 by delaying the one-shot pulse from the edge detection unit 120 by Tb. Input to the pulse generator 140 .
- the insertion pulse generator 140 can detect the start timing and end timing of the voltage drop period 210 from the first pulse P1 and the second pulse P2. For example, during the turn-on operation, the insertion pulse generator 140 is set to "0" during the period from when the first pulse P1 is received until when the second pulse is received, and is set to "1" in other periods. off-pulse signal Pof is generated.
- the time lengths Ta and Tb which respectively define the start timing and end timing of the voltage drop period 210, correspond to the normal state of the semiconductor device 10 when the drive signal Sdr is fixed to “1” after time ts, as shown in FIG. It is set based on the operating waveform at turn-on.
- the voltage drop period 210 is set after the mirror period 200 (time tb to tc).
- the time length of the voltage drop period 210 that is, (Tb-Ta), is set so as to generate a period during which the gate voltage Vg turns to drop.
- the signal synthesizing section 145 in FIG. 5 generates the driving signal Sdr by AND operation of the driving control signal Ssw and the off-pulse signal Pof from the insertion pulse generating section 140 .
- the driving signal Sdr is set to "0" from the time t1 when the time length Ta has passed from the time ts to the time t2 when the time length Tb has passed from the time ts. In other periods, it has a waveform set to "1".
- a voltage drop period 210 is provided in the drive signal Sdr.
- the drive circuit 150 in FIG. 5 has a transistor 151 connected between the power node 161 and the gate 15 and a transistor 152 connected between the gate 15 and the power node 162 .
- Power supply node 161 supplies ON voltage VH (VH>Vth), which is a positive voltage for charging gate 15 .
- Power supply node 162 supplies off voltage VL for turning off semiconductor element 10 .
- the off-voltage VL is a negative voltage with respect to the source, but it is also possible to use a voltage Vss (FIG. 1) having the same potential as the source. That is, the power node 162 corresponds to one embodiment of the "first voltage terminal" and the power node 161 corresponds to one embodiment of the "second voltage terminal". Also, the off-voltage VL and the on-voltage VH correspond to the "first voltage” and the "second voltage", respectively.
- the drive signal Sdr is set to "1" according to the drive control signal Ssw. Therefore, from time ts to t1, the waveforms of the gate voltage Vg, drain voltage Vds, and drain current Id are similar to those shown in FIG. As a result, in FIG. 6 as well, when a turn-on command is issued at time ts, which is the same as in FIG. 2, gate voltage Vg exceeds threshold voltage Vth at time ta, which is the same as in FIG. ⁇ tc (mirror period 200) and then increases toward the ON voltage VH.
- the drain voltage Vds starts to decrease and the drain current Id starts to increase from time ta, as in FIG. Then, at time tc when the mirror period 200 ends, Vds is lowered to 0. Therefore, the loss generated up to this point is the same value as in FIG.
- the drive signal Sdr is set to "1" again, so the drive circuit 150 charges the gate 15 by turning on the transistor 151. As a result, the gate voltage Vg rises again toward the ON voltage VH.
- the voltage drop period 210 is provided with a short time length such that the gate voltage Vg does not drop below the mirror voltage Vp during the voltage drop period 210 .
- the gate voltage Vg becomes equal to or lower than the mirror voltage Vp, and the semiconductor element 10 does not shift to the turn-off operation.
- the waveforms of the drain current Id and the drain voltage Vds are the same as in FIG. 2 even during the voltage drop period 210 (time t1 to t2) and after the end thereof (after time t2).
- the behavior of the drain voltage Vds and the drain current Id of the semiconductor device 10 normally turned on by the drive device 100 according to the first embodiment is such that the drive signal Sdr is maintained at "1" without providing the voltage drop period 210.
- the general case (Fig. 2). As a result, even if the voltage drop period 210 is provided, it is understood that the loss generated during normal turn-on does not increase.
- FIG. 7 shows an operation waveform diagram when the semiconductor device 10 turned on by the driving device 100 according to the first embodiment is abnormal. 7, similar to FIG. 3, the voltage and current waveforms are shown in the case where an overcurrent occurs due to the formation of a short-circuit path in response to the turn-on of the semiconductor element 10 starting at time ts. It is
- the driving signal Sdr is set to "1" between times ts and t1 and then set to "0" between times t1 and t2, as in FIG. After t2, it is set to "1".
- a voltage drop period 210 similar to that in FIG. 6 is provided when the semiconductor element 10 is turned on. That is, the drive device 100 according to the first embodiment sets the drive signal Sdr in common between the normal state (FIG. 6) and the abnormal state (FIG. 7).
- the waveforms of the gate voltage Vg, the drain voltage Vds, and the drain current Id are the same as those in FIG. is.
- the gate voltage Vg drops due to the discharge of the gate 15 by the drive circuit 150 during the period from time t1 to t2.
- the mirror period 200 (FIGS. 2 and 6) does not occur unlike the normal state, so the charge in the gate 15 at time t1 is the time less than t1. Therefore, if the voltage drop period 210 is provided with the same period length, the drop amount of the gate voltage Vg during the voltage drop period 210 becomes larger than that in the normal state.
- the gate voltage Vg is lower than the mirror voltage Vp during the voltage drop period 210, unlike in FIG.
- the behaviors of the drain voltage Vds and the drain current Id change from those shown in FIG. 3 according to the drop in the gate voltage Vg described above.
- the drain current Id decreases according to the characteristic relationship shown in FIG.
- the drain voltage Vds momentarily increases due to the generation of a surge voltage due to the parasitic inductance (typically, the parasitic inductance of wiring) in the current path including the semiconductor element 10 as the drain current Id decreases. Increase.
- the voltage drop period 210 is provided. Therefore, it is possible to extend the time required until the generated loss exceeds the breaking energy of the semiconductor device 10 . As a result, it is possible to reduce the possibility that the semiconductor device 10 will be destroyed before the protection circuit described above operates effectively.
- the drive device 100 in the turn-on operation of the semiconductor element 10, by providing the voltage drop period 210 at a timing corresponding to the lapse of the mirror period 200, the switching loss in the normal state is reduced. It is possible to control the switching of the semiconductor element so as to reduce the possibility of breakage in the event of an overcurrent abnormality while suppressing the influence of .
- the upper limit of the time length of the voltage drop period 210 is limited to a value that does not allow the gate voltage Vg to drop to the mirror voltage Vp during normal operation.
- the start timing of the voltage drop period 210 during the turn-on operation must be after the end of the mirror period 200, it should not be too late in order to suppress the increase in the drain current Id in the event of an abnormality. It is desirable to set
- the optimal values for the start timing and end timing (that is, the start timing and time length) of the voltage drop period 210 differ depending on the characteristics of the semiconductor device 10. is assumed. For this reason, it is preferable that the optimum values suitable for the characteristics of the semiconductor element 10 are obtained in advance by actual machine tests or simulations using the semiconductor element 10 to be subjected to switching control by the drive device 100 .
- the voltage drop period 210 can be started in order to realize the effect of the first embodiment described above. At least one of timing and time length can be appropriately set.
- FIG. 8 shows an operation waveform diagram when the semiconductor device turned on by the drive device according to the modification of the first embodiment is abnormal.
- the voltage drop period 210 is configured to include a plurality of divided drop periods 211 and 212, which is different from the embodiment. different from 1.
- the start timing and end timing of the divided drop period 211 are defined by the time lengths Ta1 and Tb1 that elapse from the turn-on start point (time ts).
- the start timing and end timing of the split drop period 212 provided after the split drop period 211 are defined by the time lengths Ta2 and Tb2 (Ta1 ⁇ Tb1 ⁇ Ta2 ⁇ Tb2).
- the drop period including the split drop periods 211 and 212 is provided from time t1 to time t2# after time t2 as in FIGS.
- the voltage drop period 210 is formed with a plurality of divided drop periods 211 and 212 in this way, the drain current Id drop period and the surge voltage generation period are also divided. As a result, the amount of change (increase) in the drain voltage Vds during the voltage drop period 210 can be suppressed.
- the voltage drop period 210 should be arranged so that the gate voltage Vg does not drop to the mirror voltage Vp under normal conditions after the end of the mirror period 200 (FIGS. 2 and 6). is required. Accordingly, although not shown, waveforms of the drain voltage Vds and the drain current Id when the semiconductor device 10 is normally turned on according to the drive signal Sdr shown in FIG. ).
- a driving device can be realized, for example, by modifying the configuration shown in FIG. 5 as follows.
- the time lengths Ta1, Tb1, Ta2, and Tb2 are stored in advance in the memory 135, and the delay circuit 130 delays a total of four delays from time ts as the time lengths Ta1, Tb1, Ta2, and Tb2 elapse. is input to the insertion pulse generator 140 .
- the insertion pulse generation section 140 is set to "0" corresponding to the timing of the divided drop periods 211 and 212 in FIG. ”, the drive signal Sdr shown in FIG. 8 can be generated by the signal synthesis unit 145.
- FIG. 8 illustrates an example in which the voltage drop period 210 is composed of two divided drop periods 211 and 212, the number of divisions can be three or more.
- the surge voltage during the voltage drop period 210 in the turn-on operation when an overcurrent occurs is abnormal. can be suppressed.
- Embodiment 2 As can be understood from the descriptions of the first embodiment and its modification, in the driving device according to the present embodiment, setting the start timing and time length of the voltage drop period 210 is important. In the second embodiment, the amount of information (at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj) regarding the operating state of the semiconductor device 10 is used to vary the voltage drop period 210. A technique for adjusting to
- FIG. 9 shows a block diagram for explaining a configuration example of the driving device 101 according to the second embodiment.
- the drive device 101 according to the second embodiment has a drive adjustment section 110 instead of the drive adjustment section 110, as compared with the configuration of the drive device 100 (FIG. 5) according to the first embodiment.
- 111 is provided.
- Drive adjustment section 111 differs from drive adjustment section 110 in that an external interface circuit 170 is added.
- a value detected by the detector 18 provided in the semiconductor device 10 is input to the external interface circuit 170 .
- the detector 18 detects at least one of the gate voltage Vg, the gate current, the drain voltage Vds, the drain current Id, and the temperature Tj, which are the amount of information ST regarding the operating state of the semiconductor device 10 described above.
- the functions of edge detection section 120, insertion pulse generation section 140, and signal synthesis section 145 in drive adjustment section 110 are the same as those in the first embodiment, and thus detailed description will not be repeated.
- the drive adjustment section 110 includes a delay circuit 131 instead of the delay circuit 130 (FIG. 5) in the first embodiment.
- the delay circuit 131 acquires the value of the information amount ST via the external interface circuit 170 .
- the delay circuit 131 has a function of variably adjusting at least one of the start timing and the period length of the voltage drop period 210 according to the information amount ST.
- the delay circuit 131 is configured to generate the first pulse P1 and the second pulse P2 in such a manner that at least one of the time lengths Ta and Tb defining the voltage drop period 210 is corrected according to the information amount ST. be done.
- the insertion pulse generator 140 uses the first pulse P1 and the second pulse P2 from the delay circuit 131 to generate the off-pulse signal Pof. At least one of the start timing and the length of time can be variably adjusted according to the amount of information ST.
- the switching operation of the semiconductor element 10 changes depending on the variation in characteristics of the semiconductor element 10 and the operating environment such as temperature. Therefore, when the start timing and the end timing of the voltage drop period 210 are set fixedly, it is necessary to include a margin in consideration of variations in the switching operation of the semiconductor element 10 due to the variations in characteristics and operating environment described above. Become.
- the voltage drop period 210 is adjusted to correspond to the change in the switching operation described above.
- Optimal switching operation is realized by variably adjusting at least one of the start timing and the end timing of .
- variable adjustment of the voltage drop period 210 with respect to the information amount ST will be sequentially described.
- the drain voltage Vds of the semiconductor element 10 can be used as the information amount ST.
- FIG. 10 shows a general drain voltage-drain current characteristic diagram of the semiconductor device 10.
- the semiconductor device 10 has drain voltage-drain current characteristics that differ depending on the gate voltage Vg (Vg1 to Vg5 in FIG. 10).
- the drain current Id has a characteristic that the larger is, the larger is the drain current Id.
- FIG. 11 shows an operation waveform diagram for explaining the variable adjustment of the drop period with the drain voltage Vds as the information amount ST.
- the dotted line indicates the influence on the switching operation of the semiconductor element 10 when the drain voltage Vds is increased before the start of the mirror period 200.
- the higher the drain voltage Vds the faster the change in the drain current Id, so the mirror period 200 becomes shorter as the generation timing becomes earlier.
- the higher the drain voltage Vds the higher the gate voltage Vg at the time t1 corresponding to the pre-stored time length Ta.
- the higher the drain voltage Vds the earlier the start timing (reduce the time length Ta) and/or the longer the period length (increase Tb ⁇ Ta).
- the lengths Ta and Tb it is possible to optimize at least one of the start timing and the time length of the voltage drop period 210 in accordance with the actual switching operation of the semiconductor device 10 . This enhances the effect of extending the time required for the loss generated in the semiconductor element 10 to exceed the breakdown energy of the semiconductor element 10 in the event of an overcurrent occurrence, thereby further reducing the possibility of the semiconductor element 10 breaking down. can be reduced.
- FIG. 12 shows a first flowchart for explaining control processing for variable adjustment of the decrease period in the drive device 101 according to the second embodiment.
- the driving device 101 acquires the detection value by the detector 18, that is, the amount of information regarding the operating state of the semiconductor element at regular intervals via the external interface circuit 170. be able to.
- drive device 101 causes drive control signal Ssw to transition from “0” to “1”, that is, to switch semiconductor device 10 to step (hereinafter simply referred to as “S”) 110 .
- S drive control signal
- the processing by S110 is equivalent to the function of the edge detection unit 120.
- the drive device 101 When the drive device 101 detects the turn-on command (when determined as YES in S110), it executes the processes of S120 and S130. On the other hand, even if the turn-on operation is completed once and the process is returned to "START", the processes after S120 are not executed until the turn-on command is detected (NO determination in S110).
- the driving device 101 determines the value of the information amount ST used for variable adjustment of the voltage drop period 210 from the information amount ST acquired at regular intervals. For example, when using the drain voltage Vds before the start of the mirror period 200 described with reference to FIG. , before the start of the mirror period 200), the value of the amount of information ST used for adjustment can be determined by extracting the detection value acquired at a predetermined timing.
- the driving device 101 Based on the value of the information amount ST (here, the drain voltage Vds) determined in S120, the driving device 101 sets the time length Ta that defines the time t1 (the start timing of the voltage drop period 210) and the time t2 (the voltage At least one of the time length Tb that defines the end timing of the decrease period 210 is adjusted. For example, when the drain voltage Vds described above is used as the information amount ST, the higher the drain voltage Vds, the earlier the start timing of the voltage drop period 210 and/or the longer the time length. At least one of the time lengths Ta and Tb can be adjusted such that the lower the drain voltage Vds, the later the start timing of the voltage drop period 210 and/or the shorter the time length.
- the process of S130 is realized by pre-storing in the memory 135 a lookup table or a functional expression for determining the optimum values of the time lengths Ta and Tb with respect to the information amount ST (drain voltage Vds). be able to.
- the above-mentioned optimum value can be obtained in advance by a real machine test or simulation of the switching operation of the semiconductor element 10 under the condition that the information amount ST (drain voltage Vds) is changed.
- the memory 135 is composed of the analog circuit described above, it is also possible to provide a variable mechanism for switching the circuit constant value or the number of inverter stages with respect to the amount of information ST (drain voltage Vds) in the analog circuit. .
- the amount of information (here, the drain voltage Vds) regarding the operating state of the semiconductor device 10 is fed back, thereby reducing the voltage drop period 210.
- At least one of the start timing and the length of time can be appropriately variably adjusted.
- FIG. 13 shows an operation waveform diagram for explaining the variable adjustment of the drop period with the drain current Id as the information amount ST.
- the dotted line indicates the influence on the switching operation of the semiconductor element 10 when the drain current Id after turn-on becomes small.
- the mirror voltage Vp in the mirror period 200 decreases. As a result, the generation timing of the mirror period 200 is advanced, and the amount of drop in the gate voltage Vg that is allowed in the voltage drop period 210 is increased.
- the lengths Ta and Tb it is possible to optimize at least one of the start timing and the time length of the voltage drop period 210 in accordance with the actual switching operation of the semiconductor device 10 .
- the control process applied to the flowchart of FIG. 12 can be applied.
- the driving device 101 extracts the drain current Id in the previous turn-on operation of the semiconductor device 10 (after the time tb), and determines the amount of information ST used for variable adjustment of the voltage drop period 210. be able to.
- S120 it is also possible to determine the amount of information ST used for variable adjustment of the voltage drop period 210 by predicting the drain current Id using the current value of the load (not shown) before the current turn-on operation. . In this case, it is necessary to arrange the detector 18 corresponding to the load (not shown).
- the position and time length of the voltage drop period 210 can be appropriately variably adjusted also by the feedback of the drain current Id of the semiconductor device 10 .
- FIG. 14 shows a graph for explaining the temperature dependence of the relationship between the gate voltage Vg and the drain current Id when a short-circuit current flows through the semiconductor element 10 shown in FIG.
- FIG. 15 shows an operation waveform diagram for explaining the variable adjustment of the decrease period with the element temperature Tj as the information amount ST.
- the dotted line indicates the influence on the switching operation of the semiconductor element 10 when the element temperature Tj rises.
- the threshold voltage Vth of the semiconductor element 10 decreases. Moreover, since the mirror voltage Vp also changes in conjunction with the threshold voltage Vth, the mirror voltage Vp also decreases as the element temperature rises.
- time tb starting timing of mirror period 200
- time tc ending timing of mirror period 200
- the start timing is advanced (the time length Ta is decreased) and/or the period length is lengthened (Tb-Ta is increased).
- the lengths Ta and Tb it is possible to optimize at least one of the start timing and the time length of the voltage drop period 210 in accordance with the actual switching operation of the semiconductor device 10 .
- the control process applied to the flowchart of FIG. 12 can be applied.
- the drive device 101 extracts, for example, the element temperature Tj at the time of the turn-on command (time ts) of the semiconductor element 10, and determines the amount of information ST used for variable adjustment of the voltage drop period 210. be able to.
- At least one of the start timing and time length of the voltage drop period 210 can be appropriately variably adjusted by feedback of the element temperature Tj of the semiconductor element 10 as well.
- FIG. 16 shows an operation waveform diagram for explaining the variable adjustment of the drop period with the gate voltage Vg as the information amount ST.
- the gate voltage Vg By feeding back the gate voltage Vg as the information amount ST, it is possible to directly detect the mirror voltage Vp. Furthermore, by detecting a certain period of the gate voltage Vg, it is also possible to detect the start timing (time tb) and end timing (time tc) of the mirror period 200 . This makes it possible to appropriately set the start timing of the voltage drop period 210 in correspondence with detection of the end timing of the mirror period 200 .
- the feedback of the gate voltage Vg during the voltage drop period 210 can reliably prevent the gate voltage Vg from dropping to the mirror voltage Vp, and the voltage drop period 210 can be terminated.
- FIG. 17 shows a second flowchart for explaining control processing for variable adjustment of the decrease period in the driving device 101 according to the second embodiment.
- FIG. 17 shows control processing when the gate voltage Vg is fed back as the information amount ST as described above.
- drive device 101 detects a transition of drive control signal Ssw from “0" to "1", that is, a turn-on command to semiconductor element 10, in S210 similar to S110 in FIG. .
- the drive device 101 When the drive device 101 detects the turn-on command (when determined as YES in S210), it executes the processes of S220 and S230.
- the driving device 101 reads the gate voltage Vg by acquiring the detection value by the detector 18 at a constant cycle, and in S230, by monitoring the transition of the read gate voltage Vg, the voltage drop period 210 is detected. Decide when to start. For example, the optimum value of the preset time length from the end of the mirror period 200 to the start of the voltage drop period 210 (time tc to t1) and the start timing of the mirror period 200 detected from the transition of the gate voltage Vg ( The start timing (time t1) of the voltage drop period 210 can be determined from the time tc). At the start timing of the voltage drop period 210, the driving device 101 changes the driving signal Sdr from "1" to "0".
- the processes of S220 and S230 are repeatedly executed until the voltage drop period 210 starts (NO determination in S240).
- the drive device 101 executes the processes of S240 to S280 for determining the end timing of the voltage drop period 210.
- the driving device 101 reads the gate voltage Vg as in S220, and in S260 compares the gate voltage Vg read in S250 with the sum of the mirror voltage Vp and the margin value ⁇ .
- the mirror voltage Vp can be obtained in advance from the transition of the gate voltage Vg monitored in S230 to the YES determination in S240.
- the drive device 101 changes the drive signal Sdr from "0" to "1" in S280. This ends the voltage drop period 210 .
- the start timing and time length of the voltage drop period 210 can also be optimally variably adjusted. can do.
- the feedback of the amount of information about the operating state of the semiconductor device 10 allows the actual state of the semiconductor device 10 to change depending on the operating environment such as variations in characteristics and temperature.
- At least one of the start timing and the length of time of the voltage drop period 210 can be appropriately set in accordance with the switching operation.
- the effect of extending the time required for the loss generated in the semiconductor element 10 in the event of an abnormality to exceed the breakdown energy of the semiconductor element 10, as described in the first embodiment is enhanced, and the semiconductor element 10 can be destroyed. can be further reduced.
- At least one of the above-described gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj can be used as the information amount ST to be fed back, and a plurality of information amounts ST can be fed back. It is also possible to For example, by determining in advance the optimal values of the time lengths Ta and Tb for combinations of a plurality of information amounts ST and storing them in the memory 135, the voltage drop period 210 can be varied according to the control processing shown in the flowchart of FIG. Adjustments can be made.
- the start timing of the voltage drop period 210 is determined by the control processing in FIG. 12, while the end timing of the voltage drop period 210 is determined by the combination determined by the processing of S250 to S280 in FIG.
- a variable adjustment of 210 is also possible.
- the voltage drop period 210 can be composed of two or more divided drop periods. In this case as well, it is possible to adjust the start and end timings of each divided drop period by feedback of the amount of information regarding the operating state of the semiconductor device 10 .
- Embodiment 3 switching control during turn-off operation will be described.
- an abnormal state such as an overcurrent caused by a load short-circuit
- the semiconductor device may be destroyed due to the generation of an excessive surge voltage.
- FIG. 18 shows a general operating waveform diagram in the turn-on operation when the semiconductor device is abnormal. Also in the example of FIG. 18, the operation waveforms when the semiconductor element 10 (on state) included in the short-circuit path is turned off are shown as a case where the surge voltage is the largest.
- Drain current Id is a finite value according to gate voltage Vg (that is, on-voltage VH) according to the characteristic relationship shown in FIG.
- Vg gate voltage
- VH on-voltage
- the drive device 100 starts discharging the gate 15 in response to the drive control signal Ssw changing from “1" to "0". That is, the turn-off operation starts at time te.
- the gate 15 is connected to the power supply node that supplies the off voltage VL (negative voltage here).
- VL negative voltage here
- the gate voltage begins to drop from time te.
- the gate voltage Vg drops to the threshold voltage Vth, and after time tf, Vg ⁇ Vth.
- the drain current Id decreases as the gate voltage Vg decreases.
- FIG. 19 shows a block diagram for explaining a configuration example of the drive device 102 according to the third embodiment.
- FIG. 20 shows an operation waveform diagram of a turn-on operation in an abnormal state (short-circuit state) of a semiconductor element on/off-controlled by the drive device 102 according to the third embodiment.
- the drive device 102 has a drive adjustment section 112 and a drive circuit 150 .
- the drive control signal Ssw when the drive control signal Ssw transitions from “1" to “0" during turn-off, the drive control signal Ssw is "
- the semiconductor element 10 is driven such that the voltage rise period 410 in which the drive signal Sdr is set to “1” is provided while the voltage is maintained at “0".
- the semiconductor device 10 in the voltage rising period 410, the semiconductor device 10 is driven such that the gate voltage Vg turns to rising.
- the drive adjustment unit 112 generates the drive signal Sdr provided with the voltage rise period 410 (FIG. 20) based on the drive control signal Ssw.
- the drive adjustment section 112 has an edge detection section 122 , a delay circuit 132 , a memory 135 , an insertion pulse generation section 142 and a signal synthesis section 146 .
- the function of each element of the drive adjustment unit 112 may also be realized by a dedicated electronic circuit (hardware) or by program processing (software).
- the memory 135 is configured to store time lengths Tc and Td that define the start timing and end timing of the voltage rise period 410 in FIG. 20, respectively. That is, a relationship of Td>Tc is established between Tc and Td.
- the memory 135 stores the time lengths Tc and Td in common with the time lengths defining the start timing and end timing of the voltage drop period 210 during the turn-on operation in the first embodiment and its modification. Can be configured.
- the edge detection unit 122 detects a turn-off command and generates a one-shot pulse. That is, the time te corresponds to the turn-off start timing.
- a one-shot pulse from edge detection section 122 is input to delay circuit 132 . Furthermore, the edge detection section 122 transmits the drive control signal Ssw to the signal combining section 146 .
- the delay circuit 132 generates and inserts a third pulse P3 obtained by delaying the one-shot pulse from the edge detection unit 120 by Tc and a fourth pulse P4 by delaying the one-shot pulse from the edge detection unit 120 by Td. Input to the pulse generator 142 .
- the insertion pulse generator 142 can detect the start timing and end timing of the voltage rise period 410 from the third pulse P3 and the fourth pulse P4. For example, during the turn-off operation, the insertion pulse generator 142 is set to "1" from the time the third pulse P3 is received until the time the fourth pulse P4 is received, while it is set to "0" in other periods. It generates an on-pulse signal Pon to be set.
- the signal synthesizer 146 generates the drive signal Sdr by logical sum (OR) operation of the drive control signal Ssw and the on-pulse signal Pon from the insertion pulse generator 142 .
- the drive signal Sdr is set to "1" from time t3 to time t4. and is set to "0" in other periods.
- a voltage rise period 410 is provided in the drive signal Sdr.
- the drive circuit 150 has a configuration similar to that described in the first embodiment (FIG. 5), and discharges the gate 15 while the drive signal Sdr is "0", while discharging the gate 15 while the drive signal Sdr is "1". During the period of , the gate 15 is charged.
- the length of time of the voltage rise period 410 that is, (Td-Tc) is set so as to generate a period during which the gate voltage Vg turns to rise.
- the time t3 corresponds to the timing when the time length Tc has passed since the time te when the turn-off operation is started, and the time t4 corresponds to the timing when the time length Td has passed since the time te.
- the gate voltage Vg temporarily rises during the voltage rise period 410 provided from time t3 to t4.
- the drain current Id in the short-circuit state depends on the gate voltage Vg, so the increase in the gate voltage Vg during the voltage increase period 410 reduces the rate of decrease in the drain current Id.
- the surge voltage decreases, so the drain voltage Vds once turns to decrease in the middle of the rising period in FIG.
- the voltage rise period 410 is in the middle of the period during which the surge voltage rises, that is, the period during which the drain current Id is reduced (dropped to 0). It is preferable to provide it at a relatively early timing during the turn-off operation. Therefore, unlike the voltage drop period 210 during the turn-on operation, the voltage increase period 410 during the turn-off operation is assumed to be provided earlier than the mirror period 200 during the normal turn-off operation with the time te as the starting point.
- the timing at which the gate voltage Vg drops to the threshold voltage Vth is time tf', which is later than the time tf equivalent to FIG.
- the delay time from time tf to time tf′, that is, the amount of increase in the required time until the turn-off operation is completed depends on the time length of voltage rise period 410 .
- the length of time of the voltage rise period 410 can be set as short as possible within a range in which the rise of the drain voltage Vds can be temporarily stopped by the rise of the gate voltage Vg. Therefore, by minimizing the delay time, it is possible to suppress an increase in the generated loss due to the application of the voltage rise period 410 . At least, in order to reduce the rate of decrease of the drain current Id, the switching speed is reduced throughout the turn-off operation. It will be appreciated that the amount of increase in generated loss that is traded for is greatly reduced.
- the short-pulse voltage rise period 410 is provided in the turn-off operation of the semiconductor element 10, thereby suppressing an increase in the generated loss during normal operation. It is possible to reduce the possibility of damage to the semiconductor element 10 by suppressing the surge voltage at the time of abnormality accompanied by the occurrence of overcurrent. As a result, even in the turn-off operation, the switching of the semiconductor element can be controlled so as to reduce the possibility of damage in the event of an overcurrent abnormality, while suppressing the influence on the switching loss during normal operation.
- the behavior of the turn-off operation of the semiconductor element 10 also differs according to the characteristics of the semiconductor element 10 . Therefore, the optimum values for the position and time length (that is, start timing and end timing) of the voltage rise period 410 are obtained in advance by actual machine tests or simulations using the semiconductor device 10 to be subjected to switching control by the driving device 102. is preferred.
- the voltage rise period 410 can be set appropriately in order to achieve the effect of the above-described third embodiment. It becomes possible to provide at a suitable position and time length.
- the division setting of the voltage drop period 210 in the modified example of the first embodiment can be similarly applied to the voltage rise period 410.
- the voltage rise period 410 can also be divided into arbitrary multiple times.
- Embodiment 4 the amount of information (at least one of the gate voltage Vg, the gate current, the drain voltage Vds, the drain current Id, and the element temperature Tj) regarding the operating state of the semiconductor element 10 is obtained in the same manner as in the second embodiment. is used to variably set the voltage rise period 410.
- FIG. 4 the amount of information (at least one of the gate voltage Vg, the gate current, the drain voltage Vds, the drain current Id, and the element temperature Tj) regarding the operating state of the semiconductor element 10 is obtained in the same manner as in the second embodiment. is used to variably set the voltage rise period 410.
- FIG. 21 shows a block diagram for explaining a configuration example of the driving device 103 according to the fourth embodiment.
- the drive device 103 has a drive adjustment unit 113 is provided.
- Drive adjustment section 113 differs from drive adjustment section 112 in that an external interface circuit 170 is added.
- the external interface circuit 170 stores at least one of the gate voltage Vg, the gate current, the drain voltage Vds, the drain current Id, and the temperature Tj, which are the amount of information ST regarding the operating state of the semiconductor device 10.
- One detected value (detector 18) is input.
- the functions of edge detecting section 122, insertion pulse generating section 142, and signal synthesizing section 146 in drive adjusting section 112 are the same as those in the third embodiment, so detailed description will not be repeated.
- the drive adjustment section 112 includes a delay circuit 133 instead of the delay circuit 132 (FIG. 5) in the third embodiment.
- the delay circuit 133 acquires the value of the information amount ST via the external interface circuit 170 .
- the delay circuit 133 has a function of variably adjusting at least one of the start timing and time length of the voltage rise period 410 according to the information amount ST.
- the delay circuit 133 is configured to generate the third pulse P3 and the fourth pulse P4 in such a manner that at least one of the time lengths Tc and Td defining the voltage rise period 410 is corrected according to the information amount ST. be done.
- the insertion pulse generator 142 uses the third pulse P3 and the fourth pulse P4 from the delay circuit 133 to generate the on-pulse signal Pon. At least one of the timing and the length of time can be variably adjusted according to the amount of information ST, as in the voltage drop period 210 (second embodiment) during the turn-on operation.
- the higher the drain voltage Vds or the larger the drain current Id the longer the voltage rise period 410.
- At least one of the time lengths Tc and Td can be adjusted such that the start timing is set earlier and/or the period length of the voltage rise period 410 is lengthened.
- the gate voltage Vg and the drain current Id in the short-circuited state can also be used as ST. As shown in FIG. 4, the higher the gate voltage Vg, the larger the drain current Id. And/or at least one of the time lengths Tc and Td can be adjusted so as to lengthen the period length of the voltage rise period 410 .
- the threshold voltage Vth of the semiconductor element 10 decreases as the element temperature Tj increases. Therefore, the lower the element temperature Tj, the longer the time required for the turn-off operation of the semiconductor element 10 (the length of time from time te to tf' in FIG. 20). Therefore, the lower the element temperature Tj at the start of turn-off (time te), the earlier the start timing of the voltage rise period 410 is set and/or the length of the voltage rise period 410 is lengthened. At least one of Td can be adjusted.
- FIG. 22 shows a flowchart for explaining control processing for variable adjustment of the rising period based on the information amount of the operating state of the semiconductor element in the driving device according to the fourth embodiment.
- the driving device 101 acquires the detection value by the detector 18, that is, the amount of information regarding the operating state of the semiconductor element at regular intervals via the external interface circuit 170. be able to.
- drive device 103 detects a transition of drive control signal Ssw from “1" to "0", ie, a turn-off command to semiconductor element 10, in S150.
- the processing by S ⁇ b>150 is equivalent to the function of the edge detection unit 122 .
- the drive device 103 When the drive device 103 detects the turn-off command (when determined as YES in S150), it executes the processes of S160 and S170. On the other hand, even if the turn-off operation is completed once and the process is returned to "START", the processes after S160 are not executed until the turn-off command is detected (NO determination in S150).
- the drive device 103 extracts the value of the information amount ST used for variable adjustment of the voltage rise period 410 from the information amount ST acquired at regular intervals. For example, as described above, by extracting the detection value obtained at the start timing of the turn-off command (time te) or at a predetermined timing included before the start of turn-off, the amount of information ST used for adjustment is value can be determined.
- the driving device 103 determines the time length Ta that defines the time t3 (the start timing of the voltage rise period 410) and the time t4 (the end of the voltage rise period 410) based on the value of the information amount ST determined in S160. timing) is adjusted.
- the process of S170 can be executed in the same manner as S130 of Embodiment 2 (FIG. 12). That is, representatively, it can be realized by pre-storing in the memory 135 a lookup table or a functional expression for determining the optimum values of the time lengths Tc and Td with respect to the information amount ST. Optimal values of the time lengths Tc and Td in the turn-off operation can also be obtained in advance by actual machine tests or simulations of the switching operation of the semiconductor device 10 under varying information amounts ST.
- At S170 it is also possible to adjust at least one of the time lengths Tc and Td by feedback of a plurality of information amounts ST. In this case, it is necessary to determine in advance the optimum values of the time lengths Tc and Td for combinations of a plurality of information amounts ST.
- the amount of information regarding the operating state of the semiconductor device 10 (gate voltage Vg, gate current, drain voltage Vds, drain current Id, and , element temperature Tj), at least one of the start timing and time length of the voltage rise period 410 can be appropriately variably adjusted.
- the feedback of the amount of information about the operating state of the semiconductor device 10 enables the actual switching operation that changes depending on the operating environment such as variations in characteristics of the semiconductor device 10 and temperature.
- at least one of the start timing and the length of time of the voltage rise period 410 can be set appropriately.
- the surge voltage suppressing effect can be enhanced, and the possibility that the semiconductor element 10 will be destroyed can be further reduced.
- the turn-off operation starts normal turn-off operation and excessive turn-off operation at the time of detection of the turn-off command based on the information amount ST of the semiconductor element 10 before the turn-off operation starts (on state). It is possible to distinguish which one is the turn-off operation at the abnormal time when the current is generated. Also, as described above, the voltage rise period 410 is not always positioned after the end of the mirror period 200, so there is concern that it may have some effect on the switching loss (generated loss) during normal operation. .
- FIG. 23 shows a flowchart for explaining control processing for selecting the arrangement of the voltage rise period during the turn-off operation by the drive device 103 according to the fourth embodiment.
- drive device 103 detects transition of drive control signal Ssw from “1" to "0", that is, a turn-off command to semiconductor device 10, in S250 similar to S160 in FIG. .
- the amount is obtained at regular intervals.
- the drive device 103 When the drive device 103 detects the turn-off command (when determined as YES in S250), it executes the processes of S260 and S270.
- the driving device 103 extracts the amount of information ST used for detection of the overcurrent state in S270 from the detection value of the detector 18 read while the semiconductor element 10 is in the ON state. For example, in S260, the instantaneous value of the current or voltage such as the drain current Id and the drain voltage Vds at or before the detection of the turn-off command (time te), or the average value, maximum value, etc. in a certain period is extracted.
- the driving device 103 determines whether or not the semiconductor element 10 before turn-off is in an overcurrent state by comparing the amount of information ST extracted in S170 with a predetermined determination value. Typically, an overcurrent condition can be detected when the drain current Id is greater than the criterion value.
- the drive device 103 places the voltage rise period 410 in the turn-off operation in S280.
- the voltage rise period 410 can be fixedly set using predetermined time lengths Tc and Td.
- the information amount ST at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj
- the information amount ST is fed back. , it is possible to variably set the time lengths Tc and Td.
- the driving device 103 executes the turn-off operation by disabling the voltage rise period 410 in S290.
- drive signal Sdr is maintained at "0" after time te until the next turn-on command is generated.
- the overcurrent state occurs without increasing the generated loss in the normal turn-off operation in which the overcurrent state does not occur. It is possible to suppress the surge voltage in the turn-off operation at the time of abnormality.
- the start point timing and time length of the voltage rise period 410 can be set specifically for suppression of surge voltage in an abnormal state without considering an increase in steady-state loss in a normal state, so that the effect of suppressing surge voltage can be enhanced. can be expected. This can further reduce the possibility that the semiconductor element 10 will be destroyed.
- the voltage rise period 410 can be divided into any number of times. As a result, it can be expected that the effect of suppressing the surge voltage in the event of an abnormality will be further enhanced.
- the voltage applied to the gate 15 during the voltage drop period 210 is the off voltage VL of the semiconductor element 10, as described in FIGS.
- the voltage applied to the gate 15 during the voltage rising period 410 is shared with the on-voltage VH of the semiconductor element 10 . This allows the voltage drop period 210 and/or the voltage rise period 410 to be provided without increasing the number of steps in the voltage level applied to the gate 15 by the drivers 100-103. As a result, complication of the circuit configuration can be avoided.
- each function of the drive adjustment units 110 to 113 can be configured by either hardware or software.
- all the functions of the drive adjustment units 110 to 113 are implemented by software, it is also possible to configure the drive adjustment unit using part of the functions of the control circuit 20 shown in FIG. .
- the control circuit 20 sends a drive signal Sdr containing an OFF pulse corresponding to the voltage drop period 210 and/or an ON pulse corresponding to the voltage rise period 410 to the drive circuit 150 forming the drive device 100. It can be configured to be entered directly. Even in this case, the driving signal Sdr and the driving control signal Ssw described in the present embodiment can be identified by comparing the number of times the signal level changes with the actual number of times the semiconductor element 10 is turned on and off. .
- the drive adjustment units 110 to 113 are realized by software, it is possible to facilitate adjustment of the start timing and time length in the voltage drop period 210 and/or the voltage rise period 410.
- the hardware since the drive circuit 150 can be designed specifically for the function of turning on and off the semiconductor element 10 at high speed, fine adjustment such as adjustment of the gate resistance becomes unnecessary, and the design load can be reduced. can be done.
- the switching of the semiconductor element is controlled so as to reduce the switching loss during normal operation and reduce the possibility of damage during abnormal overcurrent. can do.
- the driving device 100 or 101 according to the first and second embodiments, the third embodiment, and the driving device 100 or 101 according to the first and second embodiments are arranged so as to set both the voltage drop period 210 in the turn-on operation and the voltage rise period 410 in the turn-off operation. It is also possible to control the switching of the semiconductor element 10 in combination with the drive device 103 or 104 according to 4. For example, the drive signal Sdr from the drive adjustment unit 110 or 111 of the drive device 100 or 101 and the drive signal Sdr from the drive adjustment unit 112 or 113 of the drive device 102 or 103 are operated according to the drive control signal Ssw. Such switching control can be realized by selectively transmitting to the driving circuit 150 using a selector or the like.
- Embodiment 5 a configuration example of a power conversion device to which the driving device of the semiconductor element described in the first to fourth embodiments is applied will be described.
- FIG. 24 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 5 is applied.
- the power conversion system includes a power supply 190, a power conversion device 250, and a load 300.
- the power supply 190 is a DC power supply and supplies DC power to the power conversion device 250 .
- the power supply 190 can be configured with various things, for example, it can be configured with a DC system, a solar battery, or a storage battery. Alternatively, the power supply 190 may be composed of a rectifier circuit or an AC/DC converter connected to an AC system. Furthermore, the power supply 190 can also be configured by a DC/DC converter that converts the DC power output from the DC system into predetermined power.
- the load 300 is typically a three-phase electric motor driven by AC power supplied from the power conversion device 250 .
- the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices.
- a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an electric motor for an air conditioner is used as the load 300 .
- the power conversion device 250 is, for example, a three-phase inverter connected between the power supply 190 and the load 300, converts the DC power supplied from the power supply 190 into AC power, and supplies the AC power to the load 300.
- the power conversion device 250 includes a main conversion circuit 251 that converts DC power into AC power and outputs it, and a control circuit 255 that outputs a control signal 256 for controlling the main conversion circuit 251 to the main conversion circuit 251 .
- the main conversion circuit 251 includes at least one semiconductor element 10 and a driving device 100X arranged corresponding to each semiconductor element 10.
- the drive device 100X comprehensively describes the drive devices 101 to 103 described in the present embodiment and combinations thereof.
- a control signal 256 from the control circuit 255 includes a drive control signal Ssw for controlling on/off of the semiconductor element 10 .
- Each semiconductor element 10 is turned on and off according to the respective drive control signal Ssw, so that the main conversion circuit 251 converts the DC power supplied from the power supply 190 into AC power and supplies it to the load 300 .
- the main converter circuit 251 may have various specific circuit configurations. It can consist of six connected freewheeling diodes.
- the six semiconductor elements 10 are connected in series every two semiconductor elements 10 to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
- Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 251 are connected to the load 300 .
- the control circuit 255 controls the on/off of the semiconductor element 10 of the main conversion circuit 251 so that the desired power is supplied to the load 300 . Specifically, the control circuit 255 calculates the time (on time) during which each semiconductor element 10 of the main conversion circuit 251 should be in the ON state based on the power to be supplied to the load 300 .
- the main conversion circuit 251 can be controlled according to PWM control that modulates the ON time of each semiconductor element 10 according to the voltage to be output.
- control circuit 255 sets the drive control signal Ssw of the semiconductor element 10 to be turned on to "1", while setting the drive control signal Ssw of the semiconductor element 10 to be turned off to "0". ”.
- the drive device 100X controls the gate voltage of the corresponding semiconductor element 10 according to the drive control signal Ssw from the control circuit 255.
- the switching of each semiconductor element 10 can be controlled so as to reduce the possibility of damage in the event of an overcurrent abnormality, while suppressing the effect on switching loss in each semiconductor element 10 during normal operation.
- the power conversion device 250 can also achieve high power conversion efficiency due to low switching loss and a reduction in the possibility of damage when a short circuit occurs in the load 300 or the like.
- the driving device 100X may be incorporated in a semiconductor module (not shown) in which the semiconductor element 10 is incorporated, or may be externally connected to the semiconductor module.
- the power converter 250 may be a three-level or multi-level power converter, and if the load 300 is a single-phase AC load, the power converter 250 may be configured with a single-phase inverter.
- the power conversion device 250 can be configured by a DC/DC converter or an AC/DC converter.
- semiconductor element 10 can be turned on and off by drive apparatus according to Embodiments 1 to 4, or by drive apparatus 100X according to a combination thereof. can be done.
- the control signal 256 from the control circuit 255 may include the drive signal Sdr including the off-pulse corresponding to the voltage drop period 210 and/or the on-pulse corresponding to the voltage rise period 410. .
- the drive signal Sdr and the drive control signal Ssw can be identified by comparing the number of times the signal level changes and the actual number of times the semiconductor element 10 is turned on and off.
- the power conversion device is not limited to the case where the above-described load is an electric motor, and for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a power supply device for a contactless power supply system It can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.
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Abstract
Description
図1は、本実施の形態に従う駆動装置の機能を説明するためのブロック図である。
図8には、実施の形態1の変形例に係る駆動装置によってターンオンされた半導体素子の異常時の動作波形図が示される。
実施の形態1及びその変形例での説明から理解される様に、本実施の形態に係る駆動装置では、電圧低下期間210の開始タイミング及び時間長の設定が重要である。実施の形態2では、半導体素子10の動作状態に関する情報量(ゲート電圧Vg、ゲート電流、ドレイン電圧Vds、ドレイン電流Id、及び、温度Tjの少なくとも1つ)を用いて、電圧低下期間210を可変に調整する技術を説明する。
第1の例として、情報量STとして半導体素子10のドレイン電圧Vdsを用いることができる。
実施の形態3では、ターンオフ動作時のスイッチング制御について説明する。負荷短絡等による過電流が生じた異常時に半導体素子をターンオフする場合には、過大なサージ電圧の発生によって半導体素子が破壊に至ることが懸念される。
実施の形態4では、実施の形態2と同様の、半導体素子10の動作状態に関する情報量(ゲート電圧Vg、ゲート電流、ドレイン電圧Vds、ドレイン電流Id、及び、素子温度Tjの少なくとも1つ)を用いて、電圧上昇期間410を可変に設定する技術を説明する。
実施の形態5では、実施の形態1~4で説明した半導体素子の駆動装置を適用した電力変換装置の構成例について説明する。
Claims (15)
- 駆動制御信号に従ってオンオフされる半導体素子の駆動方法であって、
前記駆動制御信号が第1のレベルから第2のレベルへ遷移するターンオン指令に応じて、オフ状態の前記半導体素子のゲートを充電するターンオン動作を開始するステップと、
前記駆動制御信号が前記第2のレベルから前記第1のレベルへ遷移するターンオフ指令に応じて、オン状態の前記半導体素子の前記ゲートを放電するターンオフ動作を開始するステップと、
前記ターンオン動作の開始後の前記駆動制御信号が前記第2のレベルに維持される期間内に設けられる電圧低下期間と、前記ターンオフ動作の開始後の前記駆動制御信号が前記第1のレベルに維持される期間内に設けられる電圧上昇期間との少なくとも一方を配置するステップとを備え、
前記電圧低下期間は、ミラー期間の終了後において、前記ゲートの放電によって前記ゲートの電圧が一時的に低下する様に設けられ、
前記電圧上昇期間は、前記半導体素子の電流が低下している期間中において、前記ゲートの充電によって前記ゲートの電圧が一時的に上昇する様に設けられる、半導体素子の駆動方法。 - 前記配置するステップは、
前記半導体素子の動作状態の情報量に応じて、前記ターンオン動作に配置される前記電圧低下期間の開始タイミング及び時間長の少なくとも一方を可変に調整するステップを含む、請求項1記載の半導体素子の駆動方法。 - 前記配置するステップは、
前記半導体素子の動作状態の情報量に応じて、前記ターンオフ動作に配置される前記電圧上昇期間の開始タイミング及び時間長の少なくとも一方を可変に調整するステップを含む、請求項1記載の半導体素子の駆動方法。 - 前記動作状態の情報量は、前記半導体素子の主電極間の電圧、主電極間の電流、ゲート電圧、及び、素子温度の少なくとも1つを含む、請求項2又は3に記載の半導体素子の駆動方法。
- 前記電圧低下期間及び前記電圧上昇期間は、複数個に分割して配置される、請求項1~4のいずれか1項に記載の半導体素子の駆動方法。
- 前記ターンオフ指令に応じて、当該ターンオフ指令よりも前での前記半導体素子のオン状態での電流又は電圧に基づいて前記半導体素子の過電流状態を検出するステップと、
当該ターンオフ指令に対応する前記ターンオフ動作において、前記過電流状態の検出時に前記電圧上昇期間を配置する一方で、前記過電流状態の非検出時には前記電圧上昇期間を非配置とするステップとを更に備える、請求項1~5のいずれか1項に記載の半導体素子の駆動方法。 - 前記電圧低下期間と、前記ターンオフ動作での前記ゲートの放電期間との各々において、前記ゲートには共通の第1の電圧が印加され、
前記電圧上昇期間と、前記ターンオン動作での前記ゲートの充電期間との各々において、前記ゲートには共通の第2の電圧が印加される、請求項1~6のいずれか1項に記載の半導体素子の駆動方法。 - 駆動制御信号に従ってオンオフされる半導体素子の駆動装置であって、
前記駆動制御信号が第1のレベルから第2のレベルへ遷移するターンオン指令、及び、駆動制御信号が前記第2のレベルから前記第1のレベルへ遷移するターンオフ指令に応じて、オフ状態の前記半導体素子のゲートを充電するターンオン動作、及び、オン状態の前記半導体素子の前記ゲートを放電するターンオフ動作を制御するための駆動信号を生成する駆動調整部と、
前記駆動信号に従って前記ゲートを充電又は放電する駆動回路とを備え、
前記駆動調整部は、
前記ターンオン動作の開始後の前記駆動制御信号が前記第2のレベルに維持される期間内に設けられる電圧低下期間と、前記ターンオフ動作の開始後の前記駆動制御信号が前記第1のレベルに維持される期間内に設けられる電圧上昇期間との少なくとも一方を配置する様に、前記駆動信号を生成し、
前記電圧低下期間は、ミラー期間の終了後において、前記ゲートの放電によって前記ゲートの電圧が一時的に低下する様に設けられ、
前記電圧上昇期間は、前記半導体素子の電流が低下している期間中において、前記ゲートの充電によって前記ゲートの電圧が一時的に上昇する様に設けられる、半導体素子の駆動装置。 - 前記半導体素子に設けられた検出器からの、前記半導体素子の動作状態の情報量の検出値が入力されるインターフェイス回路を更に備え、
前記駆動調整部は、前記インターフェイス回路に入力された前記情報量の値を用いて、前記ターンオン動作に配置される前記電圧低下期間の開始タイミング及び時間長の少なくとも一方を可変に調整する、請求項8記載の半導体素子の駆動装置。 - 前記半導体素子に設けられた検出器による、前記半導体素子の動作状態の情報量の検出値が入力されるインターフェイス回路を更に備え、
前記駆動調整部は、前記インターフェイス回路に入力された前記情報量の値を用いて、前記ターンオフ動作に配置される前記電圧上昇期間の開始タイミング及び時間長の少なくとも一方を可変にする、請求項8記載の半導体素子の駆動装置。 - 前記動作状態の情報量は、前記半導体素子の主電極間の電圧、主電極間の電流、ゲート電圧、及び、素子温度の少なくとも1つを含む、請求項9又は10に記載の半導体素子の駆動装置。
- 前記駆動調整部は、前記電圧低下期間及び前記電圧上昇期間を、複数個に分割して配置する、請求項8~11のいずれか1項に記載の半導体素子の駆動装置。
- 前記駆動調整部は、前記ターンオフ指令に応じて、当該ターンオフ指令よりも前での前記半導体素子のオン状態での電流又は電圧に基づいて前記半導体素子の過電流状態を検出するとともに、当該ターンオフ指令に対応する前記ターンオフ動作において、前記過電流状態の検出時に前記電圧上昇期間を配置する一方で、前記過電流状態の非検出時には前記電圧上昇期間を非配置とする、請求項8~12のいずれか1項に記載の半導体素子の駆動装置。
- 前記駆動回路は、前記駆動信号が前記第1のレベルであるときに前記ゲートを第1の電圧端と電気的に接続する一方で、前記駆動信号が前記第2のレベルであるときに第2の電圧端と前記ゲートとを電気的に接続し、
前記駆動調整部は、前記駆動制御信号が前記第1のレベルである期間において、前記電圧上昇期間では前記駆動信号を前記第2のレベルに設定する一方で、前記電圧上昇期間を除く期間では前記駆動信号を第1のレベルに設定し、
前記駆動調整部は、前記駆動制御信号が前記第2のレベルである期間において、前記電圧低下期間では前記駆動信号を前記第1のレベルに設定する一方で、前記電圧低下期間を除く期間では前記駆動信号を第2のレベルに設定する、請求項8~13のいずれか1項に記載の半導体素子の駆動装置。 - 少なくとも1個の前記半導体素子を含んで構成されて、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備え、
前記制御信号は、各前記半導体素子の前記駆動制御信号を含み、
前記主変換回路は、前記半導体素子の各々に対応して配置された、請求項8~14のいずれか1項に記載の駆動装置を更に含み、
前記駆動装置は、前記駆動制御信号に従って各前記半導体素子のオンオフを制御する、電力変換装置。
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