WO2022246744A1 - 显示基板及其制作方法、显示装置 - Google Patents
显示基板及其制作方法、显示装置 Download PDFInfo
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- WO2022246744A1 WO2022246744A1 PCT/CN2021/096427 CN2021096427W WO2022246744A1 WO 2022246744 A1 WO2022246744 A1 WO 2022246744A1 CN 2021096427 W CN2021096427 W CN 2021096427W WO 2022246744 A1 WO2022246744 A1 WO 2022246744A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 174
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 45
- 238000000059 patterning Methods 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 145
- 229920002120 photoresistant polymer Polymers 0.000 claims description 135
- 238000005530 etching Methods 0.000 claims description 67
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 36
- 238000000137 annealing Methods 0.000 claims description 30
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 18
- 230000007704 transition Effects 0.000 claims description 18
- 238000002834 transmittance Methods 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 235000006408 oxalic acid Nutrition 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 11
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 9
- 229910017604 nitric acid Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 324
- 238000010586 diagram Methods 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 238000005424 photoluminescence Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000002096 quantum dot Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
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- 238000005401 electroluminescence Methods 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/82—Interconnections, e.g. terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Definitions
- the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
- an embodiment of the present disclosure provides a display substrate, including:
- At least one wiring layer is located on the substrate, and at least one wiring layer includes a plurality of first wirings and second wirings arranged at intervals using different patterning techniques in the wiring area, at least partially The first wiring and the second wiring are adjacently arranged, and the distance between the adjacent first wiring and the second wiring is less than 2um.
- the first wiring and the second wiring of at least one wiring layer are alternately arranged at intervals.
- the above-mentioned display substrate provided by an embodiment of the present disclosure includes a display area and a frame area, the display area includes a first display area and a second display area, and the light transmittance of the first display area is greater than the The light transmittance of the second display area;
- the first display area includes a plurality of sub-pixels distributed in an array, the sub-pixels include a light-emitting device and a pixel circuit, and the pixel circuit is located in the frame area adjacent to the first display area, or, the
- the second display area has a transition area adjacent to the first display area, the pixel circuit is located in the transition area, or the pixel circuit is distributed in the second display area;
- the wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light emitting device and the pixel circuit;
- the first wiring is used to electrically connect the corresponding light emitting device and the pixel circuit
- the second wiring is used to electrically connect the corresponding light emitting device and the pixel circuit.
- the material of the first wiring is p-ITO
- the material of the second wiring is a-ITO
- the material of the p-ITO The grains are larger than the grains of the a-ITO, the grain boundaries of the p-ITO are less than the grain boundaries of the a-ITO, and the resistance of the p-ITO is smaller than the resistance of the a-ITO.
- the material of the first wiring is a-ITO
- the material of the second wiring includes at least one of doped a-Si, IZO, and IGZO. one.
- the material of the first wiring is a-ITO
- the second wiring includes the first sub-wiring arranged on the substrate and the On the second sub-route on the side of the first sub-route away from the substrate, the pattern of the first sub-route is consistent with that of the second sub-route and substantially overlaps, and the first sub-route
- the material of the second sub-wire is a-ITO
- the material of the second sub-wire includes at least one of doped a-Si, IZO, and IGZO.
- the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a planar layer located on the side of the wiring layer away from the substrate, and the flat layer corresponds to each of the first wiring and the There is a first via hole at the position of the second trace, and the anode of the light emitting device is electrically connected to the first trace and the second trace through the corresponding first via hole.
- the above-mentioned display substrate provided by the embodiments of the present disclosure includes a display area and a frame area, the display area includes a plurality of signal lines, and the frame area includes the wiring area;
- the first wiring is used to electrically connect the corresponding signal lines
- the second wiring is used to electrically connect the corresponding signal lines.
- a gate metal layer and a source-drain metal layer are sequentially formed on the substrate, and the wiring layer is located on the gate metal layer and/or The source-drain metal layer.
- the distance between the adjacent first wiring and the second wiring is 0.15um-0.35um, and the first wiring
- the line width of the second wiring is less than or equal to 2um, and the line width of the second wiring is less than or equal to 2um.
- the number of the wiring layers is multiple layers, and the wiring layers of each layer are insulated from each other.
- the orthographic projections of the wiring layers on the substrate are independently distributed.
- an embodiment of the present disclosure also provides a method for manufacturing a display substrate, including:
- a substrate is provided; the substrate has a routing area;
- At least one wiring layer is formed in the wiring area of the substrate, and different patterning processes are used to pattern the wiring area corresponding to each wiring layer to obtain first and second wirings arranged at intervals; wherein , at least part of the first traces and the second traces are arranged adjacently, and the distance between the adjacent first traces and the second traces is less than 2um.
- different patterning techniques are used to pattern the wiring area corresponding to each wiring layer to obtain the first wiring and the second wiring arranged at intervals, specifically including :
- the first etching material is used to etch the annealed first conductive layer, and a plurality of first conductive layers arranged at intervals are formed on the annealed first conductive layer. a line;
- the material of the second conductive layer is the same as that of the first conductive layer before annealing;
- the second conductive layer is etched with the second etching material to form a second wiring between adjacent first wirings.
- different patterning techniques are used to pattern the wiring area corresponding to each wiring layer to obtain the first wiring and the second wiring arranged at intervals, specifically including :
- first photoresist layer as a mask, using a second etching material to etch the first conductive layer, forming a plurality of first wirings arranged at intervals on the first conductive layer;
- the second conductive layer is etched with the second etching material to form a second wiring between adjacent first wirings.
- the display substrate includes a display area and a frame area, the display area includes a first display area and a second display area, and the transparent The light rate is greater than the light transmittance of the second display area;
- the first display area includes a plurality of sub-pixels distributed in an array, and the sub-pixels include a light emitting device and a pixel circuit, and the pixel circuit is located in the same position as the first display area.
- the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area, or, the pixel circuit is distributed in the In the second display area;
- the wiring area is at least partly located in the first display area, and the wiring layer is located between the anode of the light emitting device and the pixel circuit;
- the first wiring is used For electrically connecting the corresponding light-emitting device and the pixel circuit, the second wiring is used to electrically connect the anode of the corresponding light-emitting device and the pixel circuit;
- the material of the first conductive layer after annealing is p-ITO, and the material of the second conductive layer is a-ITO; wherein, the p-ITO is annealed at high temperature, and the a-ITO is annealed at room temperature, so
- the grains of the p-ITO are larger than the grains of the a-ITO, the grain boundaries of the p-ITO are less than the grain boundaries of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO resistance.
- a display area and a frame area are included, the display area includes a plurality of signal lines, the frame area includes the routing area; the first routing area being used to electrically connect the corresponding signal lines, and the second wiring is used to electrically connect the corresponding signal lines;
- the material of the second conductive layer is the same metal material as the material of the first conductive layer before annealing.
- different patterning techniques are used to pattern the wiring area corresponding to each wiring layer to obtain the first wiring and the second wiring arranged at intervals, specifically including :
- first photoresist layer as a mask, using a second etching material to etch the first conductive layer, forming a plurality of first wirings arranged at intervals on the first conductive layer;
- the second photoresist layer as a mask, using a first etching material to etch the second conductive layer to form a second wiring between adjacent first wirings;
- the second etch material is different from the first etch material.
- different patterning techniques are used to pattern the wiring area corresponding to each wiring layer to obtain the first wiring and the second wiring arranged at intervals, specifically including :
- the first photoresist is coated on the side of the second conductive layer away from the substrate, and the first photoresist is exposed and developed to form alternately arranged first photoresist completely removed regions and first photoresists. Resist retaining regions to form a patterned first photoresist layer;
- first photoresist layer as a mask, using a first etching material to etch the second conductive layer, forming a plurality of second sub-wires arranged at intervals on the second conductive layer;
- the second photoresist layer as a mask, and using a second etching material to etch the first conductive layer to form first wirings located between adjacent second sub-wirings, and forming a first sub-wire below the second sub-wire, the first sub-wire and the second sub-wire constitute the second wire; the second etching material and the The first etching materials are different.
- the display substrate includes a display area and a frame area, the display area includes a first display area and a second display area, and the transparent The light rate is greater than the light transmittance of the second display area;
- the first display area includes a plurality of sub-pixels distributed in an array, and the sub-pixels include a light emitting device and a pixel circuit, and the pixel circuit is located in the same position as the first display area.
- the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area, or, the pixel circuit is distributed in the In the second display area;
- the wiring area is at least partly located in the first display area, and the wiring layer is located between the anode of the light emitting device and the pixel circuit;
- the first wiring is used For electrically connecting the anode of the corresponding light-emitting device and the pixel circuit
- the second wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit;
- the material of the first conductive layer is a-ITO, and the material of the second conductive layer includes at least one of doped a-Si, IZO, and IGZO.
- the display substrate includes a display area and a frame area, the display area includes a plurality of signal lines, and the frame area includes the wiring area;
- the first wiring is used to electrically connect the corresponding signal lines, and the second wiring is used to electrically connect the corresponding signal lines;
- the material of the first conductive layer and the material of the second conductive layer are different metal materials.
- a plurality of anodes are formed on the side of the flat layer formed with the first via holes away from the substrate, each of the anodes communicates with the first trace or the second trace through the corresponding first via hole. Wire connection.
- the first etching material includes nitric acid.
- the second etching material includes oxalic acid.
- an embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the above.
- FIG. 1 is a schematic top view of a display substrate provided by an embodiment of the present disclosure
- FIG. 2 is a schematic diagram of the line width and line spacing of the wiring layer prepared by photoresist technology in the related art
- FIG. 3 is a schematic structural diagram of a display substrate provided in the related art
- FIG. 4 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 6 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 7 is a schematic top view of another display substrate provided by an embodiment of the present disclosure.
- FIG. 8 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 9 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic top view of another display substrate provided by an embodiment of the present disclosure.
- FIG. 11 is a schematic top view of a first wiring and a second wiring in the prior art
- FIG. 12 is a schematic structural diagram of a first wiring and a second wiring provided by an embodiment of the present disclosure.
- FIG. 13 is a schematic top view of the first wiring and the second wiring shown in FIG. 12;
- FIG. 14A is a schematic structural diagram of a first wiring and a second wiring provided in the prior art
- FIG. 14B is a schematic diagram of the layout of FIG. 14A;
- FIG. 15A is a schematic structural diagram of a first wiring and a second wiring provided by an embodiment of the present disclosure.
- FIG. 15B is a schematic diagram of the layout of FIG. 15A;
- FIG. 16 is a schematic flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure
- 17A-17H are cross-sectional schematic diagrams after each step of making the display substrate shown in FIG. 4;
- 18A-18G are cross-sectional schematic diagrams after each step of making the display substrate shown in FIG. 5;
- 19A-19G are schematic cross-sectional views after each step of manufacturing the display substrate shown in FIG. 6 .
- the under-screen camera technology generally sets a first display area AA1 and a second display area AA2 in the display area AA, wherein the second display area AA2 occupies most of the display area, and the first display area AA1 occupies a smaller part of the display area, and the first display area AA1 is where the camera under the screen is placed.
- the under-screen camera means that the front camera is located at the bottom of the screen but does not affect the display function of the screen. When the front camera is not used, the screen above the camera can still display images normally. So from the appearance point of view, the camera under the screen will not have any camera holes, which truly achieves a full-screen display effect.
- the pixel circuit of the first display area AA1 is arranged in the frame area BB above the first display area AA1 or in the second display area AA2 adjacent to the first display area AA1, so as to The pixel circuit is set in the frame area BB above the first display area AA1 as an example.
- the pixel circuit is connected to the light-emitting device in the first display area AA1 through the ITO wiring 100, so as to transmit the surrounding pixel signals to the under-screen camera area.
- Figure 2 is a schematic diagram of the ITO wiring on the same layer.
- the ITO wiring is formed by the photoresist exposure, development and etching process.
- the ITO on the same layer has a minimum line width.
- Width and line spacing space
- the current general limit in the factory is Width (about 2um and above) and space (about 2um and above), so the number of ITO cables on the same layer is limited.
- multi-layer ITO wiring is required, as shown in Figure 3.
- Figure 3 is an example of using 4-layer ITO wiring to connect pixel circuits and light-emitting devices
- the 4 layers of ITO traces are respectively shown as 10, 20, 30, 40, and each layer of ITO needs to be covered by an organic layer (flat layer), that is, four layers of flat layers (50, 60, 70, 80) are required.
- the four flat layers (50, 60, 70, 80) are respectively patterned to form via holes corresponding to the anode 90 of the light-emitting device. In this way, the number of patterned masks (masks) is large, resulting in long process time and high cost. Actual mass production is more difficult.
- an embodiment of the present disclosure provides a display substrate, as shown in the figure 4-shown in Figure 6, including:
- the substrate 1 has a routing area, and only the routing area is shown in Figures 4-6;
- At least one wiring layer 2 is located on the substrate 1. At least one wiring layer 2 includes a plurality of first wirings 21 and second wirings 22 arranged at intervals using different patterning techniques in the wiring area. At least part of the first wiring A trace 21 and a second trace 22 are arranged adjacently, and the distance d between the adjacent first trace 21 and the second trace 22 is less than 2 um.
- the first wiring 21 and the second wiring 22 arranged at intervals are obtained on the same wiring layer by using different patterning processes, so that the first wiring 21 and the second wiring 22 formed by the two patterning processes
- the two wirings 22 can be wired on the same layer (that is, the first wiring 21 and the second wiring 22 are made on the same film layer), so that the distance between the wirings can be reduced, and the adjacent first wirings 21 can be fabricated.
- the distance between the second trace and the second trace is less than 2um, so that more wires can be laid in the same wiring space, so that for the same number of traces, this disclosure can reduce the number of layers of traces, which can reduce the number of layers above the traces.
- a flat layer thereby reducing the number of masks (masks) for patterning, reducing production costs, shortening investment time, and achieving narrower borders.
- At least one wiring layer 2 (FIG.
- the first wiring 21 and the second wiring 22 may be alternately arranged at intervals.
- the first traces 21 arranged at intervals can be formed first on the substrate 1 through a patterning process, and then the second traces 22 can be formed between adjacent first traces 21 through a second patterning process, so that the same trace can be formed.
- Arrange more wires in the wire layer that is, make more first wires 21 and second wires 22 in the same film layer).
- the display substrate in the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in FIG. 1 and FIG. 7 , it includes a display area AA and a frame area BB. , the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2;
- the first display area AA1 includes a plurality of sub-pixels (not shown) distributed in an array, and the sub-pixels include a light emitting device and a pixel circuit (not shown), as shown in FIG. 1 , the pixel circuit can be located adjacent to the first display area AA1 or, as shown in FIG. 7, the second display area AA2 has a transition area CC adjacent to the first display area AA1, and the pixel circuits can be located in the transition area CC, or the pixel circuits can also be distributed in the second display area AA1.
- the display area AA2 In the display area AA2;
- the wiring area shown in Figure 4 is at least partly located in the first display area AA1; as shown in Figure 8, the wiring layer 2 is located between the anode 3 and the pixel circuit 4 of the light emitting device, and the wiring The line layer 2 is electrically connected to the pixel circuit 4; the pixel circuit 4 can be but not limited to a 7T1C structure including 7 transistors and a capacitor, and the pixel circuit 4 includes a gate line layer, a source-drain electrode layer, a wiring layer 2 and a pixel circuit 4, the gate line layer and/or the source-drain electrode layer are electrically connected;
- the first wiring 21 is used to electrically connect the anode 3 of the corresponding light emitting device and the pixel circuit 4
- the second wiring 22 is used to electrically connect the anode 3 of the corresponding light emitting device and the pixel circuit 4 .
- the above display substrate provided by the embodiment of the present disclosure, as shown in FIG. 8 , it also includes a first flat layer 5 located between the pixel circuit 4 and the wiring layer 2.
- the second flat layer 6 has a plurality of via holes 61 corresponding to the anode 3;
- the first trace 21 is electrically connected to the pixel circuit 4 through the corresponding via hole 51
- the second trace 22 is electrically connected to the pixel circuit 4 through the corresponding via hole 52
- each anode 3 is connected to the first trace through the corresponding via hole 61 respectively.
- the line 21 is electrically connected with the second wiring 22 .
- indium tin oxide (ITO) material types can be divided into crystalline and amorphous, crystalline ITO (hereinafter referred to as "p-ITO"), amorphous (amorphous) ITO ( Hereinafter referred to as "a-ITO”), p-ITO and a-ITO can be etched with different etching materials to form corresponding wiring, so in the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in Figure 4
- the material of the first wiring 21 can be p-ITO
- the material of the second wiring 22 can be a-ITO; wherein, the grain of p-ITO is larger than the grain of a-ITO, and the grain of p-ITO The grain boundary of p-ITO is less than that of a-ITO, and the resistance of p-ITO is smaller than that of a-ITO.
- a-ITO is obtained by annealing ITO material at normal temperature
- p-ITO is obtained by annealing a-ITO at high temperature
- the annealing temperature of high temperature annealing can be 160°C-200°C, for example, it can be 160°C, 170°C °C, 180°C, 190°C, 200°C
- the annealing temperature of room temperature annealing can be 50°C-70°C, for example, it can be 50°C, 60°C, 70°C; °C)
- the present disclosure can deposit a layer of a-ITO on the substrate 1, etch the a-ITO, and then perform high-temperature annealing on the etched a-ITO, thereby forming a material made of p-ITO
- the first wiring 21; then a layer of a-ITO is deposited on the first wiring 21 to make the second wiring 22.
- the embodiment of the present disclosure can obtain the first wiring 21 and the second wiring 22 arranged at intervals on the same wiring layer through different patterning processes, so that the first wiring 21 and the second wiring 22 formed by two patterning processes can be Wiring on the same layer allows more lines to be laid in the same wiring space, reduces the number of masks (masks) for composition, reduces manufacturing costs, shortens investment time, and achieves narrower borders.
- the material of the first wiring 21 may be a-ITO
- the material of the second wiring 22 may include doped a-Si , IZO, IGZO at least one.
- the embodiment of the present disclosure can deposit a layer of a-ITO on the substrate 1, etch the a-ITO to form the first wiring 21 made of a-ITO; and then deposit a layer of material on the first wiring 21
- the film layer of doping a-Si, IZO or IGZO is used to make the second wiring 22, because the etching materials adopted by a-ITO and doping a-Si, IZO, IGZO are different, so the first wiring
- the doped a-Si, IZO or IGZO above 21 is etched, the first wiring 21 whose material is a-ITO will not be etched, so that the material is doped a-ITO can be formed between the first wiring 21
- the embodiment of the present disclosure can obtain the first wiring 21 and the second wiring 22 arranged at intervals on the same wiring layer through different patterning processes, so that the first wiring 21 and the second wiring 22 formed by two patterning processes can be Wiring on the same layer allows more lines to be laid in the same wiring space, reduces the number of masks (masks) for composition, reduces manufacturing costs, shortens investment time, and achieves narrower borders.
- masks masks
- the material of the first wiring 21 may be a-ITO
- the second wiring 22 includes the first The sub-route 221 and the second sub-route 222 arranged on the side of the first sub-route 221 away from the substrate 1, the pattern of the first sub-route 221 and the second sub-route 222 are consistent and roughly overlapped
- the material of the wire 221 may be a-ITO
- the material of the second sub-wire 222 may include at least one of doped a-Si, IZO, and IGZO.
- the film layer of a-ITO can be deposited on the substrate 1 first, and then the film layer of doped a-Si, IZO or IGZO (for example, deposited doped a-Si) can be deposited above the a-ITO film layer, The doped a-Si film layer is etched first. Since the etching materials used for a-ITO and doped a-Si are different, when the doped a-Si film layer is etched, the lower layer will not be etched.
- the material is a film layer of a-ITO, so that the second sub-wiring 222 whose material is doped a-Si can be formed above the film layer of a-ITO, and then the etching material different from that of doped a-Si can be used.
- the film layer of a-ITO is etched, the first sub-wire 221 is formed under the second sub-wire 222 , and the first wire 21 is formed between adjacent first sub-wires 221 .
- the embodiment of the present disclosure can obtain the first wiring 21 and the second wiring 22 arranged at intervals on the same wiring layer through different patterning processes, so that the first wiring 21 and the second wiring 22 formed by two patterning processes can be Wiring on the same layer allows more lines to be laid in the same wiring space, reduces the number of masks (masks) for composition, reduces manufacturing costs, shortens investment time, and achieves narrower borders.
- masks masks
- FIG. 8 is a schematic illustration using a wiring layer 2 as an example.
- the number of wiring layer 2 It can also be 2 layers or even more layers, and the wiring layers 2 of each layer are insulated.
- Figure 9 is an example of a two-layer wiring layer 2
- the first layer of wiring layer 2 and the pixel circuit 4 (drain) have a first flat layer 5, the first layer of wiring
- a second flat layer 6 between the second wiring layer 2 and the anode 3
- the line 21 and the second wiring 22 are electrically connected to the pixel circuit 4 through the via holes penetrating the first flat layer 5 respectively, and the first wiring 21 and the second wiring 22 in the second wiring layer 2 pass through the first flat layer 5 respectively.
- the via holes of the three flat layers 7 and the first flat layer 5 are electrically connected to the pixel circuit 4, and part of the anode 3 respectively passes through the via holes of the second flat layer 6 and the third flat layer 7 and the first layer of wiring layer 2.
- the first wiring 21 and the second wiring 22 are electrically connected, and the other part of the anode 3 is respectively connected to the first wiring 21 and the second wiring 22 in the second layer wiring layer 2 through the via hole penetrating the second flat layer 6 electrical connection.
- the disclosure can arrange more wiring on the same wiring layer in the embodiment of the present disclosure, that is, in the same wiring space More traces can be arranged, so that for the same number of traces, the disclosure can reduce the number of layers of traces, and the flat layer above the trace layer can be reduced, thereby reducing the number of mask (mask) for patterning and reducing the number of fabrication Costs are reduced, investment time is shortened, and narrower borders can also be achieved.
- mask mask
- Fig. 12 is an example of a two-layer wiring layer 2.
- a flat layer is provided above each wiring layer 2, and each subsequent layer
- the first wiring 21 and the second wiring 22 are electrically connected to the pixel circuit through the via holes penetrating the corresponding flat layer
- the anode 3 is electrically connected to the first wiring 21 and the second wiring 22 through the via holes penetrating the corresponding flat layer.
- the orthographic projections of each wiring layer 2 on the substrate 1 can be independently distributed, which facilitates fabrication.
- the routing area shown in Figures 4-6 is not only applicable to the under-screen camera area, but also applicable to the fan-shaped area (the fan-shaped area is used to connect the display area AA Signal lines such as data lines are connected to an external driver chip to realize signal transmission), as shown in FIG. S2, S3].
- the border area BB includes the routing area shown in Figure 4- Figure 6 (the routing area is the fan-shaped area DD);
- the first wiring 21 is used to electrically connect corresponding signal lines (such as data lines S1, S2 ... Sn), and the second wiring 22 is used to electrically connect corresponding signal lines (such as data lines Sn, S(n+1) ).
- the line width of the first trace 21 and the second trace 22 can be adjusted according to actual needs, and further can be the line of the first trace 21
- the width is less than or equal to 2um
- the line width of the second wiring 22 is less than or equal to 2um.
- FIG. 11 is a top view of the same wiring layer in the prior art Schematic diagram
- only 50 traces (21' and 22') can be arranged on one layer; however, by adopting the scheme of the embodiment of the present disclosure, the line width/line distance can be further reduced, as shown in Figure 12 and Figure 13, the figure 12 is a schematic cross-sectional view of a wiring layer in the present disclosure, and FIG. 13 is a schematic top view of FIG.
- the distance d between the second traces 22 is 0.35 um as an example, then 89 traces can be arranged in the 200 um wiring space, so that the number of trace layers can be reduced, the mask quantity of the flat layer can be saved, and the cost can be reduced.
- the line width of the first wire 21 and/or the second wire 22 can be set to different widths in different areas, and some of the first wires 21 and/or Or the line width of the second wiring 22 is less than or equal to 2um, and the line width of some of the first wiring 21 and/or the second wiring 22 is greater than 2um. In order to adjust the resistance value of the first wiring 21 and/or the second wiring, and adjust the load of the first wiring 21 and/or the second wiring.
- FIG. 14A is a schematic cross-sectional view of two wiring layers fabricated by photoresist technology in the prior art
- FIG. 14B is a schematic layout (layout) schematic diagram of FIG. 14A
- FIG. 15A is a schematic cross-sectional view of two wiring layers fabricated by photoresist technology in the present disclosure
- FIG. 15B is a schematic layout (layout) diagram of FIG.
- the first wiring 21 and the second wiring 22 of the embodiment of the disclosure The width of the line and the spacing between the first line 21 and the second line 22 can be made smaller than in the prior art, so when the same number of lines is produced in the embodiment of the present disclosure and in the prior art, the present invention
- the disclosed embodiment can arrange more wirings in the same wiring space (same wiring layer). For example, the disclosed embodiment only needs one wiring layer to arrange all the wirings, while in the prior art
- the number of wirings arranged in the same wiring layer is smaller than the embodiment of the present disclosure, so at least two wiring layers are required, so the embodiment of the disclosure can reduce the number of wiring layers, save the number of masks of the flat layer, and reduce costs.
- an embodiment of the present disclosure also provides a method for manufacturing any one of the above display substrates, as shown in FIG. 16 , including:
- S1602. Form at least one wiring layer in the wiring area of the substrate, and use different patterning techniques to pattern the wiring area corresponding to each wiring layer to obtain first wiring and second wiring arranged at intervals; wherein, at least Part of the first traces and the second traces are arranged adjacently, and the distance between the adjacent first traces and the second traces is less than 2um.
- the first photoresist is coated on the side of the first conductive layer 2' away from the substrate 1, and the first photoresist is exposed and developed to form a patterned first photoresist Layer, using the first photoresist layer as a mask, using a second etching material (such as oxalic acid) to etch the first conductive layer 2' (such as a-ITO), and forming intervals on the first conductive layer 2' A plurality of first wires 21 (before annealing).
- a second etching material such as oxalic acid
- the material of the second conductive layer 2" is different from the material type of the annealed first conductive layer 2', as shown in the figure 17D.
- the material of the first conductive layer 2' after annealing is p-ITO
- the material of the second conductive layer 2" is a-ITO.
- the first wiring 21 is an annealed material (such as p-ITO), and the material of the second conductive layer 2" is a-ITO, since the etching materials of a-ITO and p-ITO are different, therefore When the second etching material is used to etch the second conductive layer 2", the annealed first wiring 21 will not be etched.
- FIG. 17F deposit a flat layer 6 on the side of the wiring layer 2 away from the substrate 1; pattern the flat layer 6 to form the first wiring 21 and the second wiring 22 respectively.
- Vias 61 as shown in FIG. 17G; a plurality of anodes 3 are formed on the side of the flat layer 6 formed with the first via holes 61 away from the substrate 1, and each anode 3 is connected to the first wiring through the corresponding first via hole 61.
- 21 or the second wiring 22 are electrically connected, as shown in FIG. 17H .
- the display substrate shown in FIG. 4 prepared by the above-mentioned steps (1)-(6) is processed by using the second etching material (nitric acid) on the first conductive layer 2' (such as a-ITO).
- the first conductive layer 2' can also be annealed first, and then the first photoresist is coated on the side of the annealed first conductive layer (p-ITO) away from the substrate 1, and Exposing and developing the first photoresist to form a patterned first photoresist layer; then using the first photoresist layer as a mask, using the first etching material (oxalic acid) to anneal the first conductive layer (p-ITO) is etched, and a plurality of first wiring lines 21 (p-ITO) arranged at intervals are formed on the first conductive layer after annealing; then the first wiring line 21 is deposited on the side away from the base Two conductive layers (a-ITO), the second etching material (nitric acid) on the first
- Resist reserved area to form the second photoresist layer of patterning; Then use the second photoresist layer as a mask, adopt the second etching material (oxalic acid) to etch the second conductive layer (a-ITO) eclipses to form second traces between adjacent first traces.
- the second etching material oxalic acid
- a-ITO second conductive layer
- the display substrate may include a display area AA and a frame area BB, and the display area AA includes the first display area AA1 and the second display area AA2, the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2; the first display area AA1 includes a plurality of sub-pixels (not shown) distributed in an array, and the sub-pixels include light emitting Devices and pixel circuits (not shown), as shown in Figure 1, the pixel circuit can be located in the frame area BB adjacent to the first display area AA1, or, as shown in Figure 7, the second display area AA2 has In the transition area CC of the display area AA1, the pixel circuit can be located in the transition area CC, or the pixel circuit can also be distributed in the second display area AA2; as shown in Figure 1 and Figure 7, the wiring area shown in Figure 4 is at least Part of it
- the material of the first conductive layer 2' after annealing can be p-ITO, and the material of the second conductive layer 2" can be a- ITO;
- p-ITO is high-temperature annealing
- a-ITO is normal temperature annealing
- the grains of p-ITO are larger than the grains of a-ITO
- the grain boundaries of p-ITO are less than the grain boundaries of a-ITO
- p-ITO The resistance of p-ITO is less than that of a-ITO.
- p-ITO can be obtained by annealing a-ITO at high temperature.
- the border area BB includes the routing area shown in Figure 4 (the routing area is the fan-shaped area DD);
- the first wiring 21 is used to electrically connect corresponding signal lines (such as data lines S1, S2 ... Sn), and the second wiring 22 is used to electrically connect corresponding signal lines (such as data lines Sn, S(n+1) ...);
- the material of the second conductive layer 2" and the material of the first conductive layer 2' before annealing can be the same metal material.
- metal materials etched with different etching materials can be used to make the first wiring and the second wiring, so that the first wiring and the second wiring arranged alternately can be formed on the same wiring layer.
- the manufacturing method of the display substrate shown in FIG. 5 will be described in detail below, which may specifically include the following steps:
- first photoresist layer 10 uses a second etching material (such as oxalic acid) to etch the first conductive layer 2' (a-ITO) to form a spacer in the first conductive layer 2'
- a second etching material such as oxalic acid
- the material of the second conductive layer 2 ′′ is the same as that of the first conductive layer 2 ′
- the materials are different, as shown in Figure 18D.
- the material of the first conductive layer 2' is a-ITO
- the material of the second conductive layer 2" is doped a-Si.
- the second photoresist layer 20 uses the first etching material (such as nitric acid) to etch the second conductive layer 2" (a-ITO), and in each adjacent first wiring 21 to form a second wiring 22, the second etching material (oxalic acid) is different from the first etching material (nitric acid), as shown in FIG. 18F .
- first etching material such as nitric acid
- second etching material oxalic acid
- the second conductive layer 2'' (a-Si) is etched with a first etching material (such as nitric acid), and the second conductive layer 2'' A plurality of second sub-wires 222 arranged at intervals are formed, as shown in FIG. 19D .
- a first etching material such as nitric acid
- the second photoresist layer 20 uses a second etching material (such as oxalic acid) to etch the first conductive layer 2' (a-ITO), and the second etching material (such as oxalic acid) Different from the first etching material (such as nitric acid), the first wiring 21 is formed between the adjacent second sub-wiring 222, and the first sub-wiring 221 is formed under the second sub-wiring 222, The first sub-wire 221 and the second sub-wire 222 constitute the second wire 22 , as shown in FIG. 19F .
- a second etching material such as oxalic acid
- the display substrate may include a display area AA and a frame area BB, and the display area AA includes the first display area AA1 and the second display area AA2, the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2; the first display area AA1 includes a plurality of sub-pixels (not shown) distributed in an array, and the sub-pixels include light emitting Devices and pixel circuits (not shown), as shown in Figure 1, the pixel circuit can be located in the frame area BB adjacent to the first display area AA1, or, as shown in Figure 7, the second display area AA2 has In the transition area CC of the display area AA1, the pixel circuit can be located in the transition area CC, or the pixel circuit can also be distributed in the second display area AA2; as shown in Figure 1 and Figure 7, the wiring area shown in Figure 4 is at least Part of it
- the display substrate shown in FIG. 5 prepared by the steps shown in FIG. 18A-FIG. 18G, and the display substrate shown in FIG. 6 prepared by the steps shown in FIG. 19A-FIG. 19G, the first conductive layer 2'
- the material can be a-ITO
- the material of the second conductive layer 2" can include at least one of doped a-Si, IZO, IGZO.
- a-ITO can be etched with nitric acid, a-Si, IZO, IGZO Oxalic acid etching can be used.
- the border area BB includes the routing area shown in Figure 4 (the routing area is the fan-shaped area DD);
- the first wiring 21 is used to electrically connect corresponding signal lines (such as data lines S1, S2 ... Sn), and the second wiring 22 is used to electrically connect corresponding signal lines (such as data lines Sn, S(n+1) ...);
- the first conductive layer 2' material and the material of the second conductive layer 2" can be different metal materials.
- metal materials that can be etched with different etching materials are selected to make the first wiring and the second wiring, so that alternate wiring can be formed on the same wiring layer. Set the first trace and the second trace.
- the first etching material is not limited to the nitric acid provided by the embodiment of the present disclosure
- the second etching material is not limited to the oxalic acid provided by the embodiment of the present disclosure, as long as the first etching material and the second etching material can respectively etch Just etch the first conductive layer and the second conductive layer.
- wet etching can be used for etching with the first etching material, and dry etching can be used for etching with the second etching material; or dry etching can be used for etching with the first etching material, and dry etching can be used for etching with the second etching material.
- the second etching material can be etched by wet etching.
- the etching of the first conductive layer and the second conductive layer can use two different etching gases respectively, and the etching process does not affect each other; dry etching and wet etching can also be used.
- the process of etching two layers separately is used to achieve the purpose of wiring on the same layer of the two layers, but the mutual etching is not affected.
- the shape of the first display area AA1 may be a circle as shown in FIG. 1 and FIG. 7 , or may be other shapes such as rectangle, ellipse, or polygon, which may be specifically designed according to actual needs. It is not limited here.
- the second display area AA2 can surround the periphery of the first display area AA1 as shown in FIG. 1 and FIG.
- the upper border of the first display area AA1 coincides with the upper border of the second display area AA2 .
- the first display area AA1 is configured to install a photosensitive device, such as a camera module. Since there are only light-emitting devices in the first display area AA1 in the present disclosure, a larger light-transmitting area can be provided, which helps to adapt to a larger-sized camera module.
- an embodiment of the present disclosure further provides a display device, including the above-mentioned display substrate.
- the above display device further includes a photosensitive device (such as a camera module), and the photosensitive device is arranged in the first display area of the display substrate.
- the photosensitive device may be a camera module.
- the display device may be an electroluminescence display device or a photoluminescence display device.
- the electroluminescent display device may be an organic electroluminescent display device (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes, referred to as QLED).
- the display device is a photoluminescence display device
- the photoluminescence display device may be a quantum dot photoluminescence display device.
- the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like.
- a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like.
- Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present invention.
- the problem-solving principle of the display device is similar to the problem-solving principle of the above-mentioned display substrate, the implementation of the display device can refer to the above-mentioned embodiment of the display substrate, and repeated descriptions will not be repeated.
- the embodiments of the present disclosure provide a display substrate, its manufacturing method, and a display device.
- the first wiring and the second wiring that are arranged at intervals are obtained on the same wiring layer by using different patterning processes.
- the second wiring formed by the two patterning processes The first trace and the second trace can be routed on the same layer, so that the distance between the traces can be reduced, and the distance between the adjacent first trace and the second trace can be made to be less than 2um, so that in the same More lines can be laid out in the wiring space, so that the disclosure can reduce the number of layers of wiring for the same number of wiring, and then reduce the flat layer above the wiring layer, thereby reducing the number of masks (masks) for patterning and reducing the number of fabrication Costs are reduced, investment time is shortened, and narrower borders can also be achieved.
- masks masks
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Abstract
一种显示基板及其制作方法、显示装置,包括:基底(1),具有走线区;至少一层走线层(2),位于基底(1)上,每一走线层(2)在走线区包括多条采用不同构图工艺得到间隔设置的第一走线(21)和第二走线(22),至少部分第一走线(21)和第二走线(22)相邻设置,且相邻设置的第一走线(21)和第二走线(22)之间的距离小于2um。
Description
本公开涉及显示技术领域,特别涉及一种显示基板及其制作方法、显示装置。
随着智能手机的高速发展,不仅要求手机的外形美观,还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比,使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展,在性能和功能上的提升需求也与日俱增,屏下摄像头在不影响高屏占比的前提下,在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
一方面,本公开实施例提供了一种显示基板,包括:
基底,具有走线区;
至少一层走线层,位于所述基底上,至少一层所述走线层在所述走线区包括多条采用不同构图工艺得到间隔设置的第一走线和第二走线,至少部分所述第一走线和所述第二走线相邻设置,且相邻设置的所述第一走线和所述第二走线之间的距离小于2um。
可选地,在本公开实施例提供的上述显示基板中,至少一层所述走线层的所述第一走线和所述第二走线交替间隔设置。
可选地,在本公开实施例提供的上述显示基板中,包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;
所述第一显示区包括呈阵列分布的多个子像素,所述子像素包括发光器 件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;
所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;
所述第一走线用于电连接对应的所述发光器件和所述像素电路,所述第二走线用于电连接对应的所述发光器件和所述像素电路。
可选地,在本公开实施例提供的上述显示基板中,所述第一走线的材料为p-ITO,所述第二走线的材料为a-ITO;其中,所述p-ITO的晶粒大于所述a-ITO的晶粒,所述p-ITO的晶界少于所述a-ITO的晶界,所述p-ITO的电阻小于所述a-ITO的电阻。
可选地,在本公开实施例提供的上述显示基板中,所述第一走线的材料为a-ITO,所述第二走线的材料包括掺杂a-Si、IZO、IGZO中至少之一。
可选地,在本公开实施例提供的上述显示基板中,所述第一走线的材料为a-ITO,所述第二走线包括设置在所述基底上的第一子走线以及设置在所述第一子走线背离所述基底一侧的第二子走线,所述第一子走线与所述第二子走线的图案一致且大致重叠,所述第一子走线的材料为a-ITO,所述第二子走线的材料包括掺杂a-Si、IZO、IGZO中至少之一。
可选地,在本公开实施例提供的上述显示基板中,还包括位于所述走线层背离所述基底一侧的平坦层,所述平坦层中对应各所述第一走线和所述第二走线的位置处具有第一过孔,所述发光器件的阳极通过对应的所述第一过孔与所述第一走线、所述第二走线电连接。
可选地,在本公开实施例提供的上述显示基板中,包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;
所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线。
可选地,在本公开实施例提供的上述显示基板中,包括依次形成于所述 基底上的栅极金属层和源漏金属层,所述走线层位于所述栅极金属层和/或所述源漏金属层。
可选地,在本公开实施例提供的上述显示基板中,相邻设置的所述第一走线和所述第二走线之间的距离为0.15um-0.35um,所述第一走线的线宽小于或等于2um,所述第二走线的线宽小于或等于2um。
可选地,在本公开实施例提供的上述显示基板中,所述走线层的数量为多层,各层所述走线层之间绝缘设置。
可选地,在本公开实施例提供的上述显示基板中,各所述走线层在所述基底上的正投影独立分布。
另一方面,本公开实施例还提供了一种显示基板的制作方法,包括:
提供基底;所述基底具有走线区;
在所述基底的走线区形成至少一层走线层,并且采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线;其中,至少部分所述第一走线和所述第二走线相邻设置,且相邻设置的所述第一走线和所述第二走线之间的距离小于2um。
可选地,在本公开实施例提供的上述制作方法中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:
在所述基底的走线区沉积第一导电层;
对所述第一导电层进行退火处理;
在退火后的所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;
以所述第一光刻胶层为掩膜,采用第一刻蚀材料对退火后的所述第一导电层进行刻蚀,在退火后的所述第一导电层形成间隔设置的多条第一走线;
在所述多条第一走线背离所述基底的一侧沉积第二导电层,所述第二导电层的材料与退火前的所述第一导电层的材料相同;
在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光 刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;
以所述第二光刻胶层为掩膜,采用所述第二刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线。
可选地,在本公开实施例提供的上述制作方法中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:
在所述基底的走线区沉积第一导电层;
在所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;
以所述第一光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,在所述第一导电层形成间隔设置的多条第一走线;
对形成有所述多条第一走线的第一导电层进行退火处理;
在退火后的所述第一导电层背离所述基底的一侧沉积第二导电层,所述第二导电层的材料与退火后的所述第一导电层的材料类型不同;
在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;
以所述第二光刻胶层为掩膜,采用所述第二刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线。
可选地,在本公开实施例提供的上述制作方法中,所述显示基板包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;所述第一显示区包括呈阵列分布的多个子像素,所述子像素包括发光器件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第 一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;所述第一走线用于电连接对应的所述发光器件和所述像素电路,所述第二走线用于电连接对应的所述发光器件的阳极和所述像素电路;其中,
退火后的所述第一导电层的材料为p-ITO,所述第二导电层的材料为a-ITO;其中,所述p-ITO为高温退火,所述a-ITO为常温退火,所述p-ITO的晶粒大于所述a-ITO的晶粒,所述p-ITO的晶界少于所述a-ITO的晶界,所述p-ITO的电阻小于所述a-ITO的电阻。
可选地,在本公开实施例提供的上述制作方法中,包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线;
所述第二导电层的材料和退火前的所述第一导电层的材料为相同的金属材料。
可选地,在本公开实施例提供的上述制作方法中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:
在所述基底的走线区沉积第一导电层;
在所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;
以所述第一光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,在所述第一导电层形成间隔设置的多条第一走线;
在形成有所述多条第一走线的第一导电层背离所述基底的一侧沉积第二导电层,所述第二导电层的材料与所述第一导电层的材料不同;
在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成 图案化的第二光刻胶层;
以所述第二光刻胶层为掩膜,采用第一刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线;所述第二刻蚀材料与所述第一刻蚀材料不同。
可选地,在本公开实施例提供的上述制作方法中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:
在所述基底的走线区沉积第一导电层;
在所述第一导电层背离所述基底一侧沉积第二导电层;所述第二导电层的材料和所述第一导电层的材料不同;
在所述第二导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成交替设置的第一光刻胶完全去除区域和第一光刻胶保留区域,以形成图案化的第一光刻胶层;
以所述第一光刻胶层为掩膜,采用第一刻蚀材料对所述第二导电层进行刻蚀,在所述第二导电层形成间隔设置的多条第二子走线;
在形成有所述多条第二子走线的第二导电层背离所述基底的一侧沉积第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第二子走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第二子走线之间对应的区域形成第二光刻胶保留区域,且所述第二光刻胶保留区域与所述第二子走线之间具有预设间隙,以形成图案化的第二光刻胶层;
以所述第二光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,形成位于各相邻所述第二子走线之间的第一走线,以及形成位于所述第二子走线下方的第一子走线,所述第一子走线和所述第二子走线构成所述第二走线;所述第二刻蚀材料与所述第一刻蚀材料不同。
可选地,在本公开实施例提供的上述制作方法中,所述显示基板包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;所述第一显示区包括呈阵列分布的 多个子像素,所述子像素包括发光器件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;所述第一走线用于电连接对应的所述发光器件的阳极和所述像素电路,所述第二走线用于电连接对应的所述发光器件和所述像素电路;其中,
所述第一导电层的材料为a-ITO,所述第二导电层的材料包括掺杂a-Si、IZO、IGZO中至少之一。
可选地,在本公开实施例提供的上述制作方法中,所述显示基板包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线;其中,
所述第一导电层的材料和所述第二导电层的材料为不同的金属材料。
可选地,在本公开实施例提供的上述制作方法中,还包括:
在所述走线层背离所述基底的一侧沉积平坦层;
对所述平坦层进行构图,形成分别与所述第一走线和所述第二走线对应的第一过孔;
在形成有所述第一过孔的平坦层背离所述基底的一侧形成多个阳极,各所述阳极通过对应的所述第一过孔与所述第一走线或所述第二走线电连接。
可选地,在本公开实施例提供的上述制作方法中,所述第一刻蚀材料包括硝酸。
可选地,在本公开实施例提供的上述制作方法中,所述第二刻蚀材料包括草酸。
另一方面,本公开实施例还提供了一种显示装置,包括上述任一项所述的显示基板。
图1为本公开实施例提供的一种显示基板的俯视结构示意图;
图2为相关技术中采用光刻胶工艺制得的走线层的线宽线距示意图;
图3为相关技术中提供的一种显示基板的结构示意图;
图4为本公开实施例提供的一种显示基板的结构示意图;
图5为本公开实施例提供的又一种显示基板的结构示意图;
图6为本公开实施例提供的又一种显示基板的结构示意图;
图7为本公开实施例提供的又一种显示基板的俯视结构示意图;
图8为本公开实施例提供的又一种显示基板的结构示意图;
图9为本公开实施例提供的又一种显示基板的结构示意图;
图10为本公开实施例提供的又一种显示基板的俯视示意图;
图11为现有技术中第一走线和第二走线的俯视示意图;
图12为本公开实施例提供的第一走线和第二走线的结构示意图;
图13为图12所示的第一走线和第二走线的俯视示意图;
图14A为现有技术中提供的第一走线和第二走线的结构示意图;
图14B为图14A的版图示意图;
图15A为本公开实施例提供的第一走线和第二走线的结构示意图;
图15B为图15A的版图示意图;
图16为本公开实施例提供的一种显示基板的制作方法流程示意图;
图17A-图17H为制作图4所示的显示基板在执行每一步骤之后的截面示意图;
图18A-图18G为制作图5所示的显示基板在执行每一步骤之后的截面示意图;
图19A-图19G为制作图6所示的显示基板在执行每一步骤之后的截面示意图。
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。并且在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
需要注意的是,附图中各图形的尺寸和形状不反映真实比例,目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
相关技术中,如图1所示,屏下摄像头技术一般在显示区AA内设置第一显示区AA1和第二显示区AA2,其中第二显示区AA2占显示区绝大部分,第一显示区AA1占据显示区较小部分,第一显示区AA1是屏下摄像头放置的位置。屏下摄像头就是指前置摄像头位于屏幕下方但并不影响屏幕显示功能,不使用前置摄像头的时候,摄像头上方的屏幕仍可以正常显示图像。所以从外观上看,屏下摄像头不会有任何相机孔,真正的达到了全面屏显示效果。但是,目前在屏下摄像头设计方案中,是将第一显示区AA1的像素电路设置在第一显示区AA1上方的边框区BB或设置在邻近第一显示区AA1的第二显示区AA2,以像素电路设置在第一显示区AA1上方的边框区BB为例,像素 电路与第一显示区AA1内的发光器件通过ITO走线100连接,以此将周边的像素信号传递到屏下摄像头区域。如图2所示,图2为同一层ITO走线示意图,ITO走线采用光刻胶曝光显影刻蚀工艺形成,由于光刻胶最小曝光距离和最小曝光线宽要求,同层ITO具有最小线宽(Width)和线距(space),目前厂内一般极限为Width(约2um及以上)和space(约2um及以上),因此同一层ITO的排线数量受到限制。当第一显示区AA1(屏下摄像头区域)内发光器件较多时,就需要采用多层ITO走线,如图3所示,图3为采用4层ITO走线连接像素电路和发光器件为例,4层ITO走线分别示意为10、20、30、40,每一层ITO需要一层有机层(平坦层)覆盖,即需要四层平坦层(50、60、70、80),需要对四层平坦层(50、60、70、80)分别构图形成与发光器件的阳极90对应的过孔,这样构图的mask(掩膜)数量较多,造成工艺时间长,成本较高,应用于实际量产有较大困难。
为了解决现有技术中由于同一层ITO的排线数量受到限制,需要采用多层ITO走线,导致mask数量较多、成本较高的问题,本公开实施例提供了一种显示基板,如图4-图6所示,包括:
基底1,具有走线区,图4-图6中仅示意出走线区;
至少一层走线层2,位于基底1上,至少一层走线层2在走线区包括多条采用不同构图工艺得到间隔设置的第一走线21和第二走线22,至少部分第一走线21和第二走线22相邻设置,且相邻设置的第一走线21和第二走线22之间的距离d小于2um。
本公开实施例提供的上述显示基板,通过采用不同构图工艺在同一走线层得到间隔设置的第一走线21和第二走线22,这样两次构图工艺形成的第一走线21和第二走线22可以同层布线(即在同一膜层制作第一走线21和第二走线22),从而可以减小走线之间的距离,可以使制作出相邻第一走线21和第二走线之间的距离小于2um,使得在相同的布线空间可以布更多的线,从而对于相同的走线数量本公开可以减少走线的层数,则可以减少走线层上方的平坦层,从而减少构图的mask(掩膜)数量,降低制作成本,缩短投入时 间,也可以实现更窄边框。
在具体实施时,在本公开实施例提供的上述显示基板中,如图4-图6所示,至少一层走线层2(图4-图6仅示意一层走线层2)的第一走线21和第二走线22可以交替间隔设置。这样可以通过一次构图工艺在基底1上先形成间隔设置的第一走线21,然后通过二次构图工艺在各相邻第一走线21之间形成第二走线22,这样可以在同一走线层排布更多的走线(即在同一膜层制作更多的第一走线21和第二走线22)。
在具体实施时,在本公开实施例提供的上述显示基板中,如图1和图7所示,包括显示区AA和边框区BB,显示区AA包括第一显示区AA1和第二显示区AA2,第一显示区AA1的透光率大于第二显示区AA2的透光率;
第一显示区AA1包括呈阵列分布的多个子像素(未示出),子像素包括发光器件和像素电路(未示出),如图1所示,像素电路可以位于与第一显示区AA1邻近的边框区BB内,或者,如图7所示,第二显示区AA2具有邻近第一显示区AA1的过渡区CC,像素电路可以位于过渡区CC内,或者,像素电路也可以分布于第二显示区AA2内;
如图1和图7所示,图4所示的走线区至少部分位于第一显示区AA1;如图8所示,走线层2位于发光器件的阳极3和像素电路4之间,走线层2和像素电路4电连接;像素电路4可以是但不限于包括7个晶体管和一个电容的7T1C结构,像素电路4包括栅极线层、源漏电极层,走线层2和像素电路4的栅极线层和/或源漏电极层电连接;
如图8所示,第一走线21用于电连接对应的发光器件的阳极3和像素电路4,第二走线22用于电连接对应的发光器件的阳极3和像素电路4。
在具体实施时,在本公开实施例提供的上述显示基板中,如图8所示,还包括位于像素电路4和走线层2之间的第一平坦层5,第一平坦层5具有与第一走线21对应的多个过孔51,第一平坦层5具有与第二走线22对应的多个过孔52;还包括位于走线层2和阳极3之间的第二平坦层6,第二平坦层6具有与阳极3对应的多个过孔61;
第一走线21通过对应的过孔51与像素电路4电连接,第二走线22通过对应的过孔52与像素电路4电连接,各阳极3分别通过对应的过孔61与第一走线21、第二走线22电连接。
在具体实施时,氧化铟锡(ITO)材料类型可以分为结晶性的和非晶质的,结晶性的ITO(以下记作“p-ITO”),非晶质(非晶)的ITO(以下记作“a-ITO”),p-ITO和a-ITO可以采用不同的刻蚀材料进行刻蚀以形成相应的走线,因此在本公开实施例提供的上述显示基板中,如图4所示,第一走线21的材料可以为p-ITO,第二走线22的材料可以为a-ITO;其中,p-ITO的晶粒大于a-ITO的晶粒,p-ITO的晶界少于a-ITO的晶界,p-ITO的电阻小于a-ITO的电阻。具体地,a-ITO为ITO材料在常温下退火得到,p-ITO为a-ITO在高温下退火得到,其中,高温退火的退火温度可以为160℃-200℃,例如可以为160℃、170℃、180℃、190℃、200℃;常温退火的退火温度可以为50℃-70℃,例如可以为50℃、60℃、70℃;由于p-ITO可以由a-ITO在高温(例如180℃)下退火得到,从而本公开可以在基底1上沉积一层a-ITO,对a-ITO进行刻蚀,然后对刻蚀后的a-ITO进行高温退火,从而形成材料为p-ITO的第一走线21;然后在第一走线21上面沉积一层a-ITO用于制作第二走线22,由于a-ITO和p-ITO采用的刻蚀材料不同,因此在对第一走线21上方的a-ITO进行刻蚀时,不会刻蚀第一走线21,从而可以在第一走线21之间形成材料为a-ITO的第二走线22。因此本公开实施例可以通过不同构图工艺在同一走线层得到间隔设置的第一走线21和第二走线22,这样两次构图工艺形成的第一走线21和第二走线22可以同层布线,使得在相同的布线空间可以布更多的线,减少构图的mask(掩膜)数量,降低制作成本,缩短投入时间,也可以实现更窄边框。
在具体实施时,在本公开实施例提供的上述显示基板中,如图5所示,第一走线21的材料可以为a-ITO,第二走线22的材料可以包括掺杂a-Si、IZO、IGZO中至少之一。这样本公开实施例可以在基底1上沉积一层a-ITO,对a-ITO进行刻蚀,形成材料为a-ITO的第一走线21;然后在第一走线21上面沉积一层材料为掺杂a-Si、IZO或IGZO的膜层用于制作第二走线22,由于a-ITO和 掺杂a-Si、IZO、IGZO采用的刻蚀材料不同,因此在对第一走线21上方的掺杂a-Si、IZO或IGZO进行刻蚀时,不会刻蚀材料为a-ITO的第一走线21,从而可以在第一走线21之间形成材料为掺杂a-Si、IZO或IGZO的第二走线22。因此本公开实施例可以通过不同构图工艺在同一走线层得到间隔设置的第一走线21和第二走线22,这样两次构图工艺形成的第一走线21和第二走线22可以同层布线,使得在相同的布线空间可以布更多的线,减少构图的mask(掩膜)数量,降低制作成本,缩短投入时间,也可以实现更窄边框。
在具体实施时,在本公开实施例提供的上述显示基板中,如图6所示,第一走线21的材料可以为a-ITO,第二走线22包括设置在基底1上的第一子走线221以及设置在第一子走线221背离基底1一侧的第二子走线222,第一子走线221与第二子走线222的图案一致且大致重叠,第一子走线221的材料可以为a-ITO,第二子走线222的材料可以包括掺杂a-Si、IZO、IGZO中至少之一。这样可以在基底1上先沉积材料为a-ITO的膜层,然后在a-ITO膜层上方沉积材料为掺杂a-Si、IZO或IGZO的膜层(例如沉积掺杂a-Si),先对掺杂a-Si膜层进行刻蚀,由于a-ITO和掺杂a-Si采用的刻蚀材料不同,因此在对掺杂a-Si膜层进行刻蚀时,不会刻蚀下方材料为a-ITO的膜层,从而可以在a-ITO的膜层上方形成材料为掺杂a-Si的第二子走线222,然后采用不同于刻蚀掺杂a-Si的刻蚀材料对a-ITO的膜层进行刻蚀,在第二子走线222下方形成第一子走线221,以及在相邻第一子走线221之间形成第一走线21。因此本公开实施例可以通过不同构图工艺在同一走线层得到间隔设置的第一走线21和第二走线22,这样两次构图工艺形成的第一走线21和第二走线22可以同层布线,使得在相同的布线空间可以布更多的线,减少构图的mask(掩膜)数量,降低制作成本,缩短投入时间,也可以实现更窄边框。
需要说明的是,图4-图6中相邻第一走线21和第二走线22之间的距离d以及第一走线21和第二走线22的线宽仅是示意性说明,不代表真实尺寸。
需要说明的是,图8是以一个走线层2为例进行示意说明的,当然,在具体实施时,当单层走线无法满足排布较多的走线时,走线层2的数量也可 以是2层甚至更多层,各层走线层2之间绝缘设置。例如,如图9所示,图9是以两层走线层2为例,第一层走线层2与像素电路4(漏极)之间具有第一平坦层5,第一层走线层2与第二层走线层2之间具有第三平坦层7,第二层走线层2与阳极3之间具有第二平坦层6,第一层走线层2中的第一走线21和第二走线22分别通过贯穿第一平坦层5的过孔与像素电路4电连接,第二层走线层2中的第一走线21和第二走线22分别通过贯穿第三平坦层7、第一平坦层5的过孔与像素电路4电连接,部分阳极3分别通过贯穿第二平坦层6、第三平坦层7的过孔与第一层走线层2中的第一走线21和第二走线22电连接,另一部分阳极3分别通过贯穿第二平坦层6的过孔与第二层走线层2中的第一走线21和第二走线22电连接。本公开实施例的图12的布线方式与现有技术中图3所示的布线方式相比,本公开实施例中在同一走线层可以布置更多的走线,即在相同的布线空间内可以排布更多的走线,从而对于相同的走线数量本公开可以减少走线的层数,则可以减少走线层上方的平坦层,从而减少构图的mask(掩膜)数量,降低制作成本,缩短投入时间,也可以实现更窄边框。
需要说明的是,图12是以2层走线层2为例进行示意的,当采用更多层走线层2时,每一走线层2上方均设置一层平坦层,后续每一层的第一走线21、第二走线22通过贯穿对应平坦层的过孔与像素电路电连接,阳极3通过贯穿对应平坦层的过孔与第一走线21和第二走线22电连接。
在具体实施时,在本公开实施例提供的上述显示基板中,如图9所示,各走线层2在基底1上的正投影可以独立分布,这样可以方便制作。
在具体实施时,在本公开实施例提供的上述显示基板中,图4-图6所示的走线区不仅适用于屏下摄像头区域,还适用于扇形区(扇形区用于将显示区AA的信号线如数据线连接至外部的驱动芯片以实现信号传输),如图10所示,该显示基板包括显示区AA和边框区BB,显示区AA包括多条信号线(例如数据线S1、S2、S3……),边框区BB包括图4-图6所示的走线区(该走线区即扇形区DD);
第一走线21用于电连接对应的信号线(例如数据线S1、S2……Sn),第二走线22用于电连接对应的信号线(例如数据线Sn、S(n+1)……)。
在具体实施时,在本公开实施例提供的上述显示基板中,如图10所示,包括依次形成于基底1上的栅极金属层和源漏金属层,走线层2可以位于栅极金属层和/或源漏金属层。这样,只需要在形成栅极金属层或源漏金属层时改变原有的构图图形,即可通过一次构图工艺形成第一走线层2与栅极金属层或源漏金属层的图形,不用增加单独制备第一走线层2的工艺,可以简化制备工艺流程,节省生产成本,提高生产效率。
在具体实施时,在本公开实施例提供的上述显示基板中,如图4-图6所示,相邻设置的第一走线21和第二走线22之间的距离d可以为0.15um-0.35um,进一步可以为0.18um、0.2um、0.25um、0.3um;第一走线21和第二走线22的线宽根据实际需要可以做调整,进一步可以为第一走线21的线宽小于或等于2um,第二走线22的线宽小于或等于2um。这样同一层走线层可以排布更多的走线,以此减少mask数量,降低成本,缩短投入时间,也可以实现更窄边框。以200um的布线空间为例,现有技术中采用光刻胶工艺,走线的宽度和间距分别为2um/2um,如图11所示,图11为现有技术中同一层走线层的俯视示意图,一层只能排布50根走线(21’和22’);而采用本公开实施例的方案,可以将线宽/线距进一步减小,如图12和图13所示,图12为本公开中一层走线层的截面示意图,图13为图12的俯视示意图,以第一走线21和第二走线22的线宽为1.9um,相邻第一走线21和第二走线22之间的距离d为0.35um为例,则200um的布线空间例如可以排布下89根走线,从而可以减少走线的层数,节省平坦层的mask数量,降低成本。
进一步地,在满足走线排布数量要求的区域,第一走线21和/或第二走线22的线宽可以在不同的区域设置为不同的线宽,部分第一走线21和/或第二走线22的线宽小于或等于2um,部分第一走线21和/或第二走线22的线宽大于2um。以便调整第一走线21和/或第二走线的电阻值,调整第一走线21和/或第二走线的负载。
进一步地,在具体实施时,如图14A-图15B所示,图14A为现有技术中采用光刻胶工艺制作两层走线层的截面示意图,图14B为图14A的layout(版图)示意图,图15A为本公开中采用光刻胶工艺制作两层走线层的截面示意图,图15B为图15A的layout(版图)示意图,本公开实施例的第一走线21、第二走线22的线宽以及第一走线21和第二走线22之间的间距可以制作的比现有技术中更小,因此当本公开实施例和现有技术中制作相同的走线数量时,本公开实施例可以在同一布线空间内(同一走线层)布置更多的走线,例如本公开实施例仅需一层走线层就可以将所有走线排布完,而现有技术中在同一走线层布置的走线数量小于本公开实施例,因此至少需要两层走线层,因此本公开实施例可以减少走线的层数,节省平坦层的mask数量,降低成本。
基于同一发明构思,本公开实施例还提供了一种上述任一种显示基板的制作方法,如图16所示,包括:
S1601、提供基底;基底具有走线区;
S1602、在基底的走线区形成至少一层走线层,并且采用不同构图工艺在每一走线层对应的走线区构图得到间隔设置的第一走线和第二走线;其中,至少部分第一走线和第二走线相邻设置,且相邻设置的第一走线和第二走线之间的距离小于2um。
下面对图4所示的显示基板的制作方法进行详细说明,具体可以包括以下步骤:
(1)在基底1的走线区沉积第一导电层2’,如图17A所示;当图4所示的走线区位于屏下摄像头区域时,第一导电层2’的材料为透明导电材料,例如a-ITO等;当图4所示的走线区位于边框区域的扇形区域时,第一导电层2’的材料为金属材料,例如Ag、Al等。
(2)如图17B所示,在第一导电层2’背离基底1的一侧涂覆第一光刻胶,并对第一光刻胶进行曝光显影,形成图案化的第一光刻胶层,以第一光刻胶层为掩膜,采用第二刻蚀材料(例如草酸)对第一导电层2’(例如a-ITO)进行刻蚀,在第一导电层2’形成间隔设置的多条第一走线21(退火前)。
(3)对形成有多条第一走线21的第一导电层2’进行退火处理,如图17C所示,得到退火后的多条第一走线21(退火后)。
(4)在退火后的第一导电层背离基底1的一侧沉积第二导电层2”,第二导电层2”的材料与退火后的第一导电层2’的材料类型不同,如图17D所示。例如,退火后的第一导电层2’的材料为p-ITO,第二导电层2”的材料为a-ITO。
(5)在第二导电层2”背离基底1一侧涂覆第二光刻胶,并对第二光刻胶进行曝光显影,在第一走线21对应的区域形成第二光刻胶完全去除区域,在相邻第一走线21之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层,接着以第二光刻胶层为掩膜,采用第二刻蚀材料(例如草酸)对第二导电层2”(a-ITO)进行刻蚀,在各相邻第一走线21之间形成第二走线22,如图17E所示。具体地,由于第一走线21为退火后的材料(例如p-ITO),而第二导电层2”的材料为a-ITO,由于a-ITO和p-ITO的刻蚀材料不同,因此采用第二刻蚀材料对第二导电层2”进行刻蚀时,不会刻蚀退火后的第一走线21。
(6)如图17F所示,在走线层2背离基底1的一侧沉积平坦层6;对平坦层6进行构图,形成分别与第一走线21和第二走线22对应的第一过孔61,如图17G所示;在形成有第一过孔61的平坦层6背离基底1的一侧形成多个阳极3,各阳极3通过对应的第一过孔61与第一走线21或第二走线22电连接,如图17H所示。
需要说明的是,上述采用步骤(1)-(6)制得的图4所示的显示基板,是对第一导电层2’(例如a-ITO)采用第二刻蚀材料(硝酸)进行刻蚀后再退火处理,当然也可以对第一导电层2’先进行退火处理,然后在退火后的第一导电层(p-ITO)背离基底1一侧涂覆第一光刻胶,并对第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;接着以第一光刻胶层为掩膜,采用第一刻蚀材料(草酸)对退火后的第一导电层(p-ITO)进行刻蚀,在退火后的第一导电层形成间隔设置的多条第一走线21(p-ITO);然后在多条第一走线 21背离基底的一侧沉积第二导电层(a-ITO),第二导电层的材料(a-ITO)与退火前的第一导电层的材料(a-ITO)相同;然后在第二导电层背离基底一侧涂覆第二光刻胶,并对第二光刻胶进行曝光显影,在第一走线对应的区域形成第二光刻胶完全去除区域,在相邻第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;然后以第二光刻胶层为掩膜,采用第二刻蚀材料(草酸)对第二导电层(a-ITO)进行刻蚀,在各相邻第一走线之间形成第二走线。
在具体实施时,在本公开实施例提供的上述显示基板制作方法中,如图1和图7所示,该显示基板可以包括显示区AA和边框区BB,显示区AA包括第一显示区AA1和第二显示区AA2,第一显示区AA1的透光率大于第二显示区AA2的透光率;第一显示区AA1包括呈阵列分布的多个子像素(未示出),子像素包括发光器件和像素电路(未示出),如图1所示,像素电路可以位于与第一显示区AA1邻近的边框区BB内,或者,如图7所示,第二显示区AA2具有邻近第一显示区AA1的过渡区CC,像素电路可以位于过渡区CC内,或者,像素电路也可以分布于第二显示区AA2内;如图1和图7所示,图4所示的走线区至少部分位于第一显示区AA1;如图8所示,走线层2位于发光器件的阳极3和像素电路4之间;第一走线21用于电连接对应的发光器件的阳极和像素电路,第二走线22用于电连接对应的发光器件的阳极和像素电路;其中,
采用图17A-图17H所示的步骤制得的图4所示的显示基板,退火后的第一导电层2’的材料可以为p-ITO,第二导电层2”的材料可以为a-ITO;其中,p-ITO为高温退火,a-ITO为常温退火,p-ITO的晶粒大于a-ITO的晶粒,p-ITO的晶界少于a-ITO的晶界,p-ITO的电阻小于a-ITO的电阻。具体地,p-ITO可以由a-ITO在高温下退火得到。
在具体实施时,在本公开实施例提供的上述显示基板制作方法中,如图10所示,包括显示区AA和边框区BB,显示区AA包括多条信号线(例如数据线S1、S2……Sn),边框区BB包括图4所示的走线区(该走线区即扇形区 DD);
第一走线21用于电连接对应的信号线(例如数据线S1、S2……Sn),第二走线22用于电连接对应的信号线(例如数据线Sn、S(n+1)……);
采用图17A-图17H所示的步骤制得的图4所示的显示基板,第二导电层2”的材料和退火前的第一导电层2’的材料可以为相同的金属材料。这样选择退火前后可以采用不同刻蚀材料刻蚀的金属材料制作第一走线和第二走线,从而可以在同一走线层形成交替设置的第一走线和第二走线。
下面对图5所示的显示基板的制作方法进行详细说明,具体可以包括以下步骤:
(1)在基底1的走线区沉积第一导电层2’,如图18A所示;当图5所示的走线区位于屏下摄像头区域时,第一导电层2’的材料为透明导电材料,例如a-ITO等;当图5所示的走线区位于边框区域的扇形区域时,第一导电层2’的材料为金属材料,例如Ag、Al等。
(2)在第一导电层2’背离基底1的一侧涂覆第一光刻胶,并对第一光刻胶进行曝光显影,形成图案化的第一光刻胶层10,如图18B所示。
(3)以第一光刻胶层10为掩膜,采用第二刻蚀材料(例如草酸)对第一导电层2’(a-ITO)进行刻蚀,在第一导电层2’形成间隔设置的多条第一走线21,如图18C所示。
(4)对形成有多条第一走线21的第一导电层2’背离基底1的一侧沉积第二导电层2”,第二导电层2”的材料与第一导电层2’的材料不同,如图18D所示。例如,第一导电层2’的材料为a-ITO,第二导电层2”的材料为掺杂a-Si。
(5)在第二导电层2”背离基底1一侧涂覆第二光刻胶,并对第二光刻胶进行曝光显影,在第一走线21对应的区域形成第二光刻胶完全去除区域,在相邻第一走线21之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层20,如图18E所示。
(6)接着以第二光刻胶层20为掩膜,采用第一刻蚀材料(例如硝酸) 对第二导电层2”(a-ITO)进行刻蚀,在各相邻第一走线21之间形成第二走线22,第二刻蚀材料(草酸)与第一刻蚀材料(硝酸)不同,如图18F所示。
(7)接着,在走线层2背离基底1的一侧沉积平坦层6,对平坦层6进行构图,形成分别与第一走线21和第二走线22对应的第一过孔61,在形成有第一过孔61的平坦层6背离基底1的一侧形成多个阳极3,各阳极3通过对应的第一过孔61与第一走线21或第二走线22电连接,如图18G所示。
下面对图6所示的显示基板的制作方法进行详细说明,具体可以包括以下步骤:
(1)在基底1的走线区沉积第一导电层2’,如图19A所示;当图6所示的走线区位于屏下摄像头区域时,第一导电层2’的材料为透明导电材料,例如a-ITO等;当图6所示的走线区位于边框区域的扇形区域时,第一导电层2’的材料为金属材料,例如Ag、Al等。
(2)在第一导电层2’背离基底1的一侧沉积第二导电层2”;第二导电层2”的材料(例如a-Si)和第一导电层2’(a-ITO)的材料不同,如图19B所示。
(3)在第二导电层2”背离基底1一侧涂覆第一光刻胶,并对第一光刻胶进行曝光显影,形成交替设置的第一光刻胶完全去除区域和第一光刻胶保留区域,以形成图案化的第一光刻胶层10,如图19C所示。
(4)以第一光刻胶层10为掩膜,采用第一刻蚀材料(例如硝酸)对第二导电层2’’(a-Si)进行刻蚀,在第二导电层2’’形成间隔设置的多条第二子走线222,如图19D所示。
(5)在形成有多条第二子走线222的第二导电层2”背离基底1的一侧沉积第二光刻胶,并对第二光刻胶进行曝光显影,在第二子走线222对应的区域形成第二光刻胶完全去除区域,在相邻第二子走线222之间对应的区域形成第二光刻胶保留区域,且第二光刻胶保留区域与第二子走线222之间具有预设间隙,以形成图案化的第二光刻胶层20,如图19E所示。
(6)以第二光刻胶层20为掩膜,采用第二刻蚀材料(例如草酸)对第 一导电层2’(a-ITO)进行刻蚀,第二刻蚀材料(例如草酸)与第一刻蚀材料(例如硝酸)不同,形成位于各相邻第二子走线222之间的第一走线21,以及形成位于第二子走线222下方的第一子走线221,第一子走线221和第二子走线222构成第二走线22,如图19F所示。
(7)接着,在走线层2背离基底1的一侧沉积平坦层6,对平坦层6进行构图,形成分别与第一走线21和第二走线22对应的第一过孔61,在形成有第一过孔61的平坦层6背离基底1的一侧形成多个阳极3,各阳极3通过对应的第一过孔61与第一走线21或第二走线22电连接,如图19G所示。
在具体实施时,在本公开实施例提供的上述显示基板制作方法中,如图1和图7所示,该显示基板可以包括显示区AA和边框区BB,显示区AA包括第一显示区AA1和第二显示区AA2,第一显示区AA1的透光率大于第二显示区AA2的透光率;第一显示区AA1包括呈阵列分布的多个子像素(未示出),子像素包括发光器件和像素电路(未示出),如图1所示,像素电路可以位于与第一显示区AA1邻近的边框区BB内,或者,如图7所示,第二显示区AA2具有邻近第一显示区AA1的过渡区CC,像素电路可以位于过渡区CC内,或者,像素电路也可以分布于第二显示区AA2内;如图1和图7所示,图4所示的走线区至少部分位于第一显示区AA1;如图8所示,走线层2位于发光器件的阳极3和像素电路4之间;第一走线21用于电连接对应的发光器件的阳极和像素电路,第二走线22用于电连接对应的发光器件的阳极和像素电路;其中,
采用图18A-图18G所示的步骤制得的图5所示的显示基板,以及采用图19A-图19G所示的步骤制得的图6所示的显示基板,第一导电层2’的材料可以为a-ITO,第二导电层2”的材料可以包括掺杂a-Si、IZO、IGZO中至少之一。具体地,a-ITO可以采用硝酸刻蚀,a-Si、IZO、IGZO可以采用草酸刻蚀。
在具体实施时,在本公开实施例提供的上述显示基板制作方法中,如图10所示,包括显示区AA和边框区BB,显示区AA包括多条信号线(例如数 据线S1、S2……Sn),边框区BB包括图4所示的走线区(该走线区即扇形区DD);
第一走线21用于电连接对应的信号线(例如数据线S1、S2……Sn),第二走线22用于电连接对应的信号线(例如数据线Sn、S(n+1)……);
采用图18A-图18G所示的步骤制得的图5所示的显示基板,以及采用图19A-图19G所示的步骤制得的图6所示的显示基板,第一导电层2’的材料和第二导电层2”的材料可以为不同的金属材料。这样选择可以采用不同刻蚀材料刻蚀的金属材料制作第一走线和第二走线,从而可以在同一走线层形成交替设置的第一走线和第二走线。
需要说明的是,第一刻蚀材料不限于本公开实施例提供的硝酸,第二刻蚀材料不限于本公开实施例提供的草酸,只要第一刻蚀材料和第二刻蚀材料分别能够刻蚀第一导电层和第二导电层即可。
需要说明的是,采用第一刻蚀材料刻蚀时可以采用湿刻,采用第二刻蚀材料刻蚀时可以采用干刻;或者采用第一刻蚀材料刻蚀时可以采用干刻,采用第二刻蚀材料刻蚀时可以采用湿刻。
需要说明的是,本公开实施例提供的上述第一导电层和第二导电层的刻蚀可以分别采用两种不同的刻蚀气体,且刻蚀过程不互相影响;也可以采用干刻和湿刻分别刻蚀两层的工艺,以达到两层走线同层布线,但互相刻蚀不受影响的目的。
需要说明的是,在本公开中第一显示区AA1的形状可以为图1和图7所示的圆形,也可以为矩形、椭圆形或多边形等其他形状,具体可根据实际需要进行设计,在此不做限定。第二显示区AA2可以如图1和图7所示环绕第一显示区AA1的周边;也可以包围部分第一显示区AA1,例如包围第一显示区AA1的左侧、下侧和右侧,而第一显示区AA1的上侧边界与第二显示区AA2的上侧边界重合。
可选地,在本公开实施例提供的上述显示基板中,如图1和图7所示,第一显示区AA1被配置为安装感光器件,例如摄像头模组。由于在本公开中 第一显示区AA1内仅存在发光器件,因此能够提供更大面积的透光区域,有助于适配更大尺寸的摄像头模组。
基于同一发明构思,本公开实施例还提供了一种显示装置,包括上述显示基板。
在具体实施时,上述显示装置还包括感光器件(例如摄像头模组),感光器件被设置在显示基板的第一显示区。可选地,感光器件可以为摄像头模组。该显示装置可以为电致发光显示装置或光致发光显示装置。在该显示装置为电致发光显示装置的情况下,电致发光显示装置可以为有机电致发光显示装置(Organic Light-Emitting Diode,简称OLED)或量子点电致发光显示装置(Quantum Dot Light Emitting Diodes,简称QLED)。在该显示装置为光致发光显示装置的情况下,光致发光显示装置可以为量子点光致发光显示装置。
该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本发明的限制。另外,由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似,因此,该显示装置的实施可以参见上述显示基板的实施例,重复之处不再赘述。
本公开实施例提供的一种显示基板及其制作方法、显示装置,通过采用不同构图工艺在同一走线层得到间隔设置的第一走线和第二走线,这样两次构图工艺形成的第一走线和第二走线可以同层布线,从而可以减小走线之间的距离,可以使制作出相邻第一走线和第二走线之间的距离小于2um,使得在相同的布线空间可以布更多的线,从而对于相同的走线数量本公开可以减少走线的层数,则可以减少走线层上方的平坦层,从而减少构图的mask(掩膜)数量,降低制作成本,缩短投入时间,也可以实现更窄边框。
尽管已描述了本公开的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例作出另外的变更和修改。所以,所附权 利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然,本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样,倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (25)
- 一种显示基板,其中,包括:基底,具有走线区;至少一层走线层,位于所述基底上,至少一层所述走线层在所述走线区包括多条采用不同构图工艺得到间隔设置的第一走线和第二走线,至少部分所述第一走线和所述第二走线相邻设置,且相邻设置的所述第一走线和所述第二走线之间的距离小于2um。
- 如权利要求1所述的显示基板,其中,至少一层所述走线层的所述第一走线和所述第二走线交替间隔设置。
- 如权利要求1所述的显示基板,其中,包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;所述第一显示区包括呈阵列分布的多个子像素,所述子像素包括发光器件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;所述第一走线用于电连接对应的所述发光器件和所述像素电路,所述第二走线用于电连接对应的所述发光器件和所述像素电路。
- 如权利要求3所述的显示基板,其中,所述第一走线的材料为p-ITO,所述第二走线的材料为a-ITO;其中,所述p-ITO的晶粒大于所述a-ITO的晶粒,所述p-ITO的晶界少于所述a-ITO的晶界,所述p-ITO的电阻小于所述a-ITO的电阻。
- 如权利要求3所述的显示基板,其中,所述第一走线的材料为a-ITO,所述第二走线的材料包括掺杂a-Si、IZO、IGZO中至少之一。
- 如权利要求3所述的显示基板,其中,所述第一走线的材料为a-ITO,所述第二走线包括设置在所述基底上的第一子走线以及设置在所述第一子走线背离所述基底一侧的第二子走线,所述第一子走线与所述第二子走线的图案一致且大致重叠,所述第一子走线的材料为a-ITO,所述第二子走线的材料包括掺杂a-Si、IZO、IGZO中至少之一。
- 如权利要求3-6任一项所述的显示基板,其中,还包括位于所述走线层背离所述基底一侧的平坦层,所述平坦层中对应各所述第一走线和所述第二走线的位置处具有第一过孔,所述发光器件的阳极通过对应的所述第一过孔与所述第一走线、所述第二走线电连接。
- 如权利要求1所述的显示基板,其中,包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线。
- 如权利要求8所述的显示基板,其中,包括依次形成于所述基底上的栅极金属层和源漏金属层,所述走线层位于所述栅极金属层和/或所述源漏金属层。
- 如权利要求1所述的显示基板,其中,相邻设置的所述第一走线和所述第二走线之间的距离为0.15um-0.35um,所述第一走线的线宽小于或等于2um,所述第二走线的线宽小于或等于2um。
- 如权利要求1所述的显示基板,其中,所述走线层的数量为多层,各层所述走线层之间绝缘设置。
- 如权利要求11所述的显示基板,其中,各所述走线层在所述基底上的正投影独立分布。
- 一种显示基板的制作方法,其中,包括:提供基底;所述基底具有走线区;在所述基底的走线区形成至少一层走线层,并且采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线;其中, 至少部分所述第一走线和所述第二走线相邻设置,且相邻设置的所述第一走线和所述第二走线之间的距离小于2um。
- 如权利要求13所述的制作方法,其中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:在所述基底的走线区沉积第一导电层;对所述第一导电层进行退火处理;在退火后的所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;以所述第一光刻胶层为掩膜,采用第一刻蚀材料对退火后的所述第一导电层进行刻蚀,在退火后的所述第一导电层形成间隔设置的多条第一走线;在所述多条第一走线背离所述基底的一侧沉积第二导电层,所述第二导电层的材料与退火前的所述第一导电层的材料相同;在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;以所述第二光刻胶层为掩膜,采用所述第二刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线。
- 如权利要求13所述的制作方法,其中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:在所述基底的走线区沉积第一导电层;在所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;以所述第一光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,在所述第一导电层形成间隔设置的多条第一走线;对形成有所述多条第一走线的第一导电层进行退火处理;在退火后的所述第一导电层背离所述基底的一侧沉积第二导电层,所述 第二导电层的材料与退火后的所述第一导电层的材料类型不同;在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;以所述第二光刻胶层为掩膜,采用所述第二刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线。
- 如权利要求14或15所述的制作方法,其中,所述显示基板包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;所述第一显示区包括呈阵列分布的多个子像素,所述子像素包括发光器件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;所述第一走线用于电连接对应的所述发光器件和所述像素电路,所述第二走线用于电连接对应的所述发光器件和所述像素电路;其中,退火后的所述第一导电层的材料为p-ITO,所述第二导电层的材料为a-ITO;其中,所述p-ITO为高温退火,所述a-ITO为常温退火,所述p-ITO的晶粒大于所述a-ITO的晶粒,所述p-ITO的晶界少于所述a-ITO的晶界,所述p-ITO的电阻小于所述a-ITO的电阻。
- 如权利要求14或15所述的制作方法,其中,包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线;所述第二导电层的材料和退火前的所述第一导电层的材料为相同的金属材料。
- 如权利要求13所述的制作方法,其中,采用不同构图工艺在每一所 述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:在所述基底的走线区沉积第一导电层;在所述第一导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成图案化的第一光刻胶层;以所述第一光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,在所述第一导电层形成间隔设置的多条第一走线;在形成有所述多条第一走线的第一导电层背离所述基底的一侧沉积第二导电层,所述第二导电层的材料与所述第一导电层的材料不同;在所述第二导电层背离所述基底一侧涂覆第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第一走线对应的区域形成第二光刻胶完全去除区域,在相邻所述第一走线之间对应的区域形成第二光刻胶保留区域,以形成图案化的第二光刻胶层;以所述第二光刻胶层为掩膜,采用第一刻蚀材料对所述第二导电层进行刻蚀,在各相邻所述第一走线之间形成第二走线;所述第二刻蚀材料与所述第一刻蚀材料不同。
- 如权利要求13所述的制作方法,其中,采用不同构图工艺在每一所述走线层对应的走线区构图得到间隔设置的第一走线和第二走线,具体包括:在所述基底的走线区沉积第一导电层;在所述第一导电层背离所述基底一侧沉积第二导电层;所述第二导电层的材料和所述第一导电层的材料不同;在所述第二导电层背离所述基底一侧涂覆第一光刻胶,并对所述第一光刻胶进行曝光显影,形成交替设置的第一光刻胶完全去除区域和第一光刻胶保留区域,以形成图案化的第一光刻胶层;以所述第一光刻胶层为掩膜,采用第一刻蚀材料对所述第二导电层进行刻蚀,在所述第二导电层形成间隔设置的多条第二子走线;在形成有所述多条第二子走线的第二导电层背离所述基底的一侧沉积第二光刻胶,并对所述第二光刻胶进行曝光显影,在所述第二子走线对应的区 域形成第二光刻胶完全去除区域,在相邻所述第二子走线之间对应的区域形成第二光刻胶保留区域,且所述第二光刻胶保留区域与所述第二子走线之间具有预设间隙,以形成图案化的第二光刻胶层;以所述第二光刻胶层为掩膜,采用第二刻蚀材料对所述第一导电层进行刻蚀,形成位于各相邻所述第二子走线之间的第一走线,以及形成位于所述第二子走线下方的第一子走线,所述第一子走线和所述第二子走线构成所述第二走线;所述第二刻蚀材料与所述第一刻蚀材料不同。
- 如权利要求18或19所述的制作方法,其中,所述显示基板包括显示区和边框区,所述显示区包括第一显示区和第二显示区,所述第一显示区的透光率大于所述第二显示区的透光率;所述第一显示区包括呈阵列分布的多个子像素,所述子像素包括发光器件和像素电路,所述像素电路位于与所述第一显示区邻近的所述边框区内,或者,所述第二显示区具有邻近所述第一显示区的过渡区,所述像素电路位于所述过渡区内,或者,所述像素电路分布于所述第二显示区内;所述走线区至少部分位于所述第一显示区,且所述走线层位于所述发光器件的阳极和所述像素电路之间;所述第一走线用于电连接对应的所述发光器件和所述像素电路,所述第二走线用于电连接对应的所述发光器件和所述像素电路;其中,所述第一导电层的材料为a-ITO,所述第二导电层的材料包括掺杂a-Si、IZO、IGZO中至少之一。
- 如权利要求18或19所述的制作方法,其中,所述显示基板包括显示区和边框区,所述显示区包括多条信号线,所述边框区包括所述走线区;所述第一走线用于电连接对应的所述信号线,所述第二走线用于电连接对应的所述信号线;其中,所述第一导电层的材料和所述第二导电层的材料为不同的金属材料。
- 如权利要求20所述的制作方法,其中,还包括:在所述走线层背离所述基底的一侧沉积平坦层;对所述平坦层进行构图,形成分别与所述第一走线和所述第二走线对应 的第一过孔;在形成有所述第一过孔的平坦层背离所述基底的一侧形成多个阳极,各所述阳极通过对应的所述第一过孔与所述第一走线或所述第二走线电连接。
- 如权利要求14、18、19任一项所述的制作方法,其中,所述第一刻蚀材料包括硝酸。
- 如权利要求14、15、18或19所述的制作方法,其中,所述第二刻蚀材料包括草酸。
- 一种显示装置,其中,包括如权利要求1-12任一项所述的显示基板。
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