WO2022246668A1 - 一种测试电路、集成芯片及测试方法 - Google Patents

一种测试电路、集成芯片及测试方法 Download PDF

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Publication number
WO2022246668A1
WO2022246668A1 PCT/CN2021/095892 CN2021095892W WO2022246668A1 WO 2022246668 A1 WO2022246668 A1 WO 2022246668A1 CN 2021095892 W CN2021095892 W CN 2021095892W WO 2022246668 A1 WO2022246668 A1 WO 2022246668A1
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Prior art keywords
data
test
bits
address
response analyzer
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PCT/CN2021/095892
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English (en)
French (fr)
Inventor
许团辉
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华为技术有限公司
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Priority to PCT/CN2021/095892 priority Critical patent/WO2022246668A1/zh
Priority to CN202180088171.2A priority patent/CN116670768A/zh
Publication of WO2022246668A1 publication Critical patent/WO2022246668A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices

Definitions

  • the present application relates to the field of chip technology, in particular to a test circuit, an integrated chip and a test method.
  • a system-on-chip such as a system on chip (SoC) is a chip that integrates a processor and a memory.
  • the memory in a system-on-chip can also be regarded as an embedded memory (memory), for example, it can be a static random memory Access memory (static random access memory, SRAM), dynamic random access memory (dynamic random access memory, DRAM), flash memory (flash), magnetic random access memory (magnetic random access memory, MRAM), etc.
  • DFT design for test
  • the built-in self-test (memory build-in self testing, MBIST) circuit is a typical DFT circuit.
  • the structure of a common MBIST circuit can be shown in FIG. 1 .
  • the MBIST circuit consists of two parts, the BIST controller and the response analyzer.
  • the BIST controller is used to control the testing of multiple memories, and each memory is configured with a response analyzer.
  • the BIST controller generates read and write operations for accessing the memory according to the test algorithm, as well as the data of the write operation and the expected data of the read operation; the response analyzer implements the read and write of the memory according to the information provided by the BIST controller, thereby testing the memory.
  • the process of testing the memory may be: the BIST controller sends a write command to the response analyzer (the write instruction write effectively represents the write command), including address (address), write data ( data_in), write instruction (write); after receiving the write instruction, the response analyzer sends the write instruction to the corresponding memory, including address (address), write data (write data), write instruction (write ) three kinds of information, so that the memory writes the corresponding data in the corresponding address.
  • the BIST controller sends a read command to the response analyzer (the read indication read effectively represents the read command), including the address (address), the data to be compared (compare data) (that is, the read operation Expected data), read instruction (read) three kinds of information; after receiving the read instruction, the response analyzer sends a read instruction to the corresponding memory, including address (address), read instruction (read) two kinds of information, so that The memory reads the data in the address; the memory sends the read data (read data) to the response analyzer, and the response analyzer compares the read data (read data) with the data to be compared (compare data); if two If the two are consistent, a pass message is sent to the BIST controller, and if the two are inconsistent, a fail message is sent to the BIST controller.
  • the response analyzer the read indication read effectively represents the read command
  • the response analyzer that is, the read operation Expected data
  • the response analyzer sends a read instruction to the corresponding memory, including address (
  • the response analyzer when the response analyzer reads and writes data for a certain address, it needs to read and write the full bit width of the memory. For example, if the bit width of the memory is 16 bits, the response analyzer needs to support simultaneous processing of 16 bits data Read, write, and compare operations. Compared with the read and write operations, the comparison operation requires more logic during implementation (for example, the comparator needs to be configured with XOR gates, AND gates, registers, etc.). Therefore, in the response analyzer, in order to support full-bit-width data comparison, the circuit area of the comparator occupies a relatively large proportion. The area of the comparator is linear with the bit width of the memory. Therefore, the larger the bit width of the memory, the larger the area of the comparator, the larger the area of the response analyzer, and the larger the area of the MBIST circuit.
  • Embodiments of the present application provide a test circuit, an integrated chip and a test method, which are used to reduce the area of the test circuit.
  • an embodiment of the present application provides a test circuit, the test circuit is used for testing a memory, and the test circuit includes a controller and a response analyzer.
  • the controller is used to send a first read command to the response analyzer to read the first data corresponding to the first address, the first read command carries the first address, the second data and the first test sequence number, the first test sequence number Used to instruct the Response Analyzer to test the first set of bits.
  • the first data includes M bits, and the first part of bits corresponds to the nth bit to the n+P bit in the M bits, M>0, P ⁇ M, n ⁇ 0;
  • the response analyzer is used to send the second read to the memory
  • the instruction is fetched, and the second read instruction carries the first address;
  • the response analyzer is also used to receive the first data sent by the memory, and according to the first test sequence number, combine the sub-data in the first part of the first data with the second comparing the sub-data located in the first part of the two data, and outputting the first test result to the controller.
  • the first data corresponding to the first address is the first data stored in the first address.
  • the first data includes M bits, that is, the bit width of the memory is M bits, and the data stored in a certain address of the memory includes M bits, that is, the [0]th bit to the [M-1]th bit.
  • the first part of bits represents the nth bit to the n+Pth bit in the M bits.
  • the first data includes 6 bits, and the first part of bits is the second bit to the third bit in the 6 bits.
  • the response analyzer After the response analyzer reads the first data, it does not test all bits, but only tests some bits.
  • the response analyzer only tests some bits of the first data each time, so the response analyzer can perform multiple tests to realize the comparison of the full bit width data. Therefore, the comparator circuit in the response analyzer can only support part of the bit-bit test, and there is no need to test the full-bit width data at one time, so the area of the comparator can be saved, thereby reducing the area of the test circuit.
  • the first test result indicates that the test is passed; if the sub-data in the first part of the first data If the sub-data of bits is inconsistent with the sub-data in the first part of the second data, the first test result indicates that the test fails.
  • the controller is further configured to: after receiving the first test result, determine whether all the bits of the first data have been tested; in the case that all the bits of the first data have been tested , determining the test result of the storage space corresponding to the first address in the memory according to all the received test results.
  • the response analyzer compares the read-back first data with the second data, it does not compare the full bit width data at one time, but only compares part of the bits each time; through multiple comparisons, the first data is completed Comparison with the second data. After the comparison between the first data and the second data is completed, the controller determines the final test result of the storage space corresponding to the first address by integrating multiple test results received after multiple comparisons.
  • the controller determines the test result of the storage space corresponding to the first address in the memory according to all the test results received, it may be implemented in the following manner: if all the test results indicate that the test is passed, then determine the test result of the storage space corresponding to the first address The storage space test passes; otherwise, it is determined that the storage space test corresponding to the first address fails.
  • test results indicate that the test is passed, it means that when any bit of the first data is tested, the test is passed, so it can be determined that the test of the storage space corresponding to the first address is passed; if any test result indicates that the test is not passed, It means that some bits of the first data have failed the test, so it can be determined that the storage space corresponding to the first address has failed the test.
  • the controller is further configured to: send a third read instruction to the response analyzer to read the first data when all the bits of the first data have not been tested, and the third The read command carries the first address, the second data, and the second test sequence number, and the second test sequence number is used to instruct the response analyzer to test the second part of the bits, and the second part of the bits corresponds to the n+th part of the M bits.
  • the response analyzer is also used to: send a fourth read command to the memory, the fourth read command carries the first address; receive the first data sent by the memory, and according to The second test sequence number compares the sub-data in the second part of the first data with the sub-data in the second part of the second data, and outputs the second test result to the controller.
  • the controller controls the response analyzer to test the second part of bits.
  • the number of bits included in the first part of bits is equal to the number of bits included in the second part of bits, both of which are N, where N ⁇ 1.
  • the response analyzer includes N comparison modules and OR gate circuits; each comparison module in the N comparison modules is used to compare the sub-data on the first bit in the first data and the second Whether the sub-data on the first bit in the data is consistent; the OR gate circuit is used to perform an OR operation on the test results of each comparison module.
  • each comparison module is used for comparing the sub-data on the same bit in the first data and the second data.
  • the OR gate circuit is used for OR operation on the test results of each comparison module. Assuming that the comparison module outputs a low level when the comparison result is consistent, and outputs a low level when the comparison result is inconsistent, then.
  • the OR gate circuit can output a low level when each comparison module outputs a low level, and output a high level in other cases. It is not difficult to understand that when each comparison module determines that the comparison result is consistent, the OR gate circuit outputs a low level; otherwise, the OR gate circuit outputs a high level. That is to say, when the OR gate circuit outputs a low level, it means that the storage space test corresponding to the first address passes; when the OR gate circuit outputs a high level, it means that the storage space test corresponding to the first address fails. .
  • each comparison module includes a data selector, an XOR gate circuit, an AND gate circuit and a register; wherein the data selector is used to select and output the first bit in the first data according to the first test sequence number The sub-data on the first data; the XOR gate circuit is used to perform XOR operation on the sub-data on the first bit in the first data and the sub-data on the first bit in the second data; The output signal of the XOR circuit and the read instruction signal are ANDed, and the read instruction signal is used to instruct the response analyzer to execute the read instruction when it is valid; the register is used to retrieve and output the output signal of the AND circuit.
  • the selected sub-data is output to the XOR gate; the other input terminal of the XOR gate also inputs the corresponding bit in the second data Sub-data; the XOR gate performs an XOR operation on the sub-data input at the two input terminals: when the two sub-data are consistent, the XOR gate outputs a low level; when the two sub-data are inconsistent, the XOR gate outputs a high level; The output terminal of the XOR gate is connected to the AND gate.
  • the AND gate When the read indication signal is valid, the AND gate outputs the output signal of the XOR gate to the register for latching; finally, the comparison result of each comparison module (that is, the output signal of the XOR gate)
  • the OR operation is performed through the OR gate: when each comparison module outputs a low level, the OR gate outputs a low level; if any comparison module in the comparison module outputs a high level, the OR gate outputs a high level. That is to say, only when the sub-data of each bit in the first data and the second data are consistent, the OR gate outputs a low level; otherwise, the OR gate outputs a high level. Then, when the OR gate outputs a low level, it means that the test of the storage space corresponding to the first address passes; when the OR gate outputs a high level, it means that the test of the storage space corresponding to the first address fails.
  • each comparison module includes a first data selector, an XOR gate circuit, a second data selector and a register;
  • the first data selector is used to select and output the sub-data located on the first bit in the first data according to the first test sequence number;
  • the XOR gate circuit is used to select the sub-data located on the first bit in the first data and The sub-data located on the first bit in the second data performs exclusive OR operation;
  • the second data selector is used to select the output signal of the exclusive OR gate circuit when the read indication signal is valid, and is used to indicate the response analyzer when the read indication signal is valid Execute the read instruction;
  • the register is used to retrieve and output the output signal of the AND circuit.
  • the selected sub-data is output to the XOR gate; the other input terminal of the XOR gate also inputs the corresponding bit in the second data Sub-data; the XOR gate performs an XOR operation on the sub-data input at the two input terminals: when the two sub-data are consistent, the XOR gate outputs a low level; when the two sub-data are inconsistent, the XOR gate outputs a high level;
  • the output terminal of the XOR gate is connected with the second data selector, and when the read indication signal is valid, the second data selector outputs the output signal of the XOR gate to the register for latching; finally the comparison result of each comparison module (ie The output signal of the XOR gate) is performed through the OR gate: when each comparison module outputs a low level, the OR gate outputs a low level; if any comparison module in the comparison module outputs a high level, the OR gate outputs
  • the controller is further configured to: after sending the first read instruction to the response analyzer, send a fifth read instruction to the response analyzer to read third data corresponding to the second address, The fifth read command carries the second address, the fourth data, and the first test sequence number; the response analyzer is also used to: send the sixth read command to the memory, and the sixth read command carries the second address; receive the memory sent and compare the sub-data in the first part of the third data with the sub-data in the first part of the fourth data according to the first test sequence number, and output the third test result to the controller .
  • the first data includes M bits, which means that the bit width of the memory is M bits, and the data stored at a certain address of the memory includes M bits.
  • the third data stored in the second address also includes M bits, and for the third data, the first part of bits also corresponds to the nth bit to the n+Pth bit in the M bits.
  • the controller can also control the response analyzer to test the storage space corresponding to the second address. Likewise, when testing the storage space corresponding to the second address, only a part of bits are tested each time.
  • the controller is further configured to: before sending the first read instruction to the response analyzer, send a first write instruction to the response analyzer to instruct the memory to write the second For data, the first write command carries the first address and the second data.
  • the controller controls the response analyzer to write the second data at the first address.
  • the storage space corresponding to the first address in the memory can be tested to determine whether the storage space corresponding to the first address has physical defects : If the first data is consistent with the second data, it means that there is no physical defect in the storage space corresponding to the first address; if the first data is inconsistent with the second data, it means that there is a physical defect in the storage space corresponding to the first address. Every address in every memory is tested to determine if the memory is physically defective.
  • an embodiment of the present application provides an integrated chip, the integrated chip includes a memory and the test circuit provided in the first aspect and any possible design thereof, the test circuit is used to test the memory.
  • the embodiment of the present application provides a testing method, which includes the following steps: the controller sends a first read instruction to the response analyzer to read the first data corresponding to the first address, and the first read instruction carry the first address, the second data and the first test sequence number, the first test sequence number is used to instruct the response analyzer to test the first part of the bits, the first data includes M bits, and the first part of the bits corresponds to the first part of the M bits n bits to n+P bits, M>0, P ⁇ M, n ⁇ 0; the controller receives the first test result sent by the response analyzer, and the first test result is the first part of bits of the first data sent by the response analyzer The controller judges whether all the bits of the first data have been tested; the controller determines the test result of the memory according to all the test results received when all the bits of the first data have been tested. .
  • the controller determines the test result of the memory according to all the test results received, including: when all the test results indicate that the test is passed, the controller determines the storage space test corresponding to the first address in the memory Pass; otherwise, the controller determines that the storage space test corresponding to the first address in the memory fails.
  • the test method provided by the third aspect further includes: the controller sends a third read instruction to the response analyzer to read the The first data, the third read command carries the first address, the second data and the second test sequence number, the second test sequence number is used to instruct the response analyzer to test the second part of the bits, and the second part of the bits corresponds to M The n+P+1 bit to the n+2P+1 bit in the bit; the controller receives the second test result sent by the response analyzer, and the second test result is the response analyzer to the second part of the first data bits The results of the tests performed.
  • the controller may also send a fifth read instruction to the response analyzer to read the third data corresponding to the second address, in the fifth read instruction Carrying the second address, the fourth data and the first test sequence number; the controller receives the third test result sent by the response analyzer, and the third test result is the result of the response analyzer testing the first part of the second data bits.
  • the embodiment of the present application provides a testing method, the method comprising: generating circuit design code according to the structural information of the memory; converting the circuit design code into a netlist, and the netlist is used to generate the first aspect and its any A test circuit is provided for one possible design.
  • the embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores instructions, and when it is run on a computer, the computer executes the above-mentioned third aspect and any possible Design the method described.
  • the present application further provides a computer program product containing instructions, which, when run on a computer, cause the computer to execute the method described in the above third aspect and any possible design thereof.
  • FIG. 1 is a schematic structural diagram of a MBIST circuit provided by the prior art
  • FIG. 2 is a schematic structural diagram of a system-on-a-chip provided in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a test circuit provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a SRAM provided in an embodiment of the present application.
  • Fig. 5 is a kind of test flowchart provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a response analyzer provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another response analyzer provided in the embodiment of the present application.
  • Fig. 8 is a schematic flow chart of a test method provided in the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an integrated chip provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of another testing method provided in the embodiment of the present application.
  • an integrated chip 200 includes a test circuit 201 and a memory 202 .
  • the memory 202 can be regarded as an embedded memory in the chip, and the testing circuit 201 is used to test whether there is a physical defect in the memory 202 .
  • test circuit 201 can be regarded as the MBIST circuit in FIG. 1
  • memory 202 can be regarded as the memory in FIG. 1; the memory 202 includes but is not limited to SRAM, DRAM, flash memory (flash), MRAM, etc.
  • the principle of testing the memory 202 by the test circuit 201 is: the test circuit 201 generates a write instruction to a certain address of the memory 202 according to a test algorithm, so as to write data1 at the address. After receiving the write instruction, the memory 202 executes the write operation. If there is no physical defect in the memory 202, data1 will be written into this address; but if there is a physical defect in the memory 202, data1 may be written into a wrong address, or wrong data may be written under this address. After issuing the write command, the test circuit 201 issues a read command for the address to read the data corresponding to the address; the memory 202 sends data2 to the test circuit 201 after receiving the read command. The test circuit 201 can determine whether the memory 202 can correctly execute the write and read instructions by comparing whether the data1 and data2 are consistent, thereby determining whether the memory 202 has physical defects.
  • the test circuit 201 may include a controller 201a and a response analyzer 201b.
  • the controller 201a is used to generate write instructions and read instructions according to the test algorithm, integrate test results, and control the entire test process;
  • the response analyzer 201b is used to interact with the memory 202 to instruct the memory 202 to execute the write instructions and read instructions. Instruction fetch, response analyzer 201b is also used to compare data.
  • test circuit 201 and the memory 202 can be designed in one chip (die), or can be designed as two dies respectively; or, the test circuit 201 and the memory 202 can be integrated on the same printed Two dies on a printed circuit board (PCB), the specific forms of the test circuit 201 and the memory 202 are not limited in the embodiment of the present application.
  • the response analyzer 201b when the response analyzer 201b performs data comparison, the response analyzer 201b performs data comparison at one time for the data read back from the memory. For example, if the bit width of the memory 202 is 16 bits, then the response analyzer 201b simultaneously Compare the 16bits data. Since the comparison operation currently requires more logic, the area of the response analyzer 201b is larger in order to support full bit-width data comparison. The larger the bit width of the memory 202 is, the larger the area of the response analyzer 201b is, and the larger the area of the testing circuit 201 is.
  • the structure and test process of the test circuit 201 are improved to reduce the area of the response analyzer 201 b, thereby reducing the area of the test circuit 201 .
  • the test circuit 201 includes a controller 201a and a response analyzer 201b.
  • the controller 201a is configured to send a first read command to the response analyzer 201b to read the first data corresponding to the first address, and the first read command carries the first address, the second data and the first test sequence number , the first test sequence number is used to instruct the response analyzer 201b to test the first part of bits
  • the first data includes M bits, the first part of bits corresponds to the nth bit to the n+Pth bit in the M bits, M>0, P ⁇ M, n ⁇ 0;
  • the response analyzer 201b is used to send a second read instruction to the memory, and the second read instruction carries the first address;
  • the response analyzer 201b is also used to receive the first data sent by the memory, and The sub-data in the first part of the first data is compared with the sub-data in the first part of
  • the second data is used for comparison with the read-back first data, so as to test whether the data written in the memory is wrong.
  • the controller 201a may also send the first write instruction to the response analyzer 201b to instruct the memory to write the second data in the first address, the first The write command carries the first address and the second data.
  • the controller 201a controls the response analyzer 201b to write the second data at the first address.
  • the storage space corresponding to the first address in the memory can be tested to determine whether the storage space corresponding to the first address has physical defects : If the first data is consistent with the second data, it means that there is no physical defect in the storage space corresponding to the first address; if the first data is inconsistent with the second data, it means that there is a physical defect in the storage space corresponding to the first address. Every address in every memory is tested to determine if the memory is physically defective.
  • the first part of bits can be understood as follows: the first data includes M bits, then the bit width of the memory is M bits, and the data stored in any address of the memory includes M bits.
  • the first part of bits represents a part of the M bits (nth bit to n+P bit). That is to say, the first part of bits refers to bits at a specific position.
  • the first test sequence number is used to indicate the first part of bits. For example, in the above example, if the first part of bits is bit[0] ⁇ bit[1], the first test sequence number can be 0; If the bits in the first part are bit[2]-bit[3], the first test sequence number may be 1... .
  • the first part of bits is for the full bit width, not only for the first data. That is to say, for any data stored in any address, the bits in the first part of the data have the same designation.
  • the first part of bits corresponds to bit[0] ⁇ bit[1], so no matter for the first data or the second data, the first part of bits corresponds to bit[0] ⁇ bit[1].
  • the response analyzer 201b After the response analyzer 201b reads the first data, it does not compare all the bits in the first data, but only compares sub-data on some bits. Through multiple comparisons, the comparison of full bit width data can be realized. For example, the bit width of the memory is 6 bits, and the response analyzer 201b first tests the first two bits, then tests the middle two bits, and then tests the last two bits, and then realizes the full bit width data through three comparison processes Comparison. Therefore, in the embodiment of the present application, the comparator circuit in the response analyzer 201b can only support the test of some bits, and there is no need to test the full bit width data at one time, so the area of the comparator can be saved, thereby reducing the test circuit 201 square feet.
  • the first test result sent by the response analyzer 201b to the controller 201a indicates that the test is passed. ; If the sub-data located in the first part of bits in the first data is inconsistent with the sub-data located in the first part of bits in the second data, the first test result indicates that the test fails.
  • controller 201a is also used to: after receiving the first test result, determine whether all the bits of the first data have been tested; if all the bits of the first data have been tested, according to the received All test results determine the test results of the storage space corresponding to the first address in the memory.
  • the controller 201a determines the final test result of the storage space corresponding to the first address by integrating multiple test results received after multiple comparisons. Specifically, if all the test results indicate that the test is passed, it is determined that the storage space corresponding to the first address has passed the test, and there is no physical defect in the storage space corresponding to the first address; otherwise, it is determined that the storage space corresponding to the first address has failed the test. , the storage space corresponding to the first address has a physical defect.
  • the controller 201a may continue to send a third read command to the response analyzer 201b to read the first data, the third read command carries the first address, the second data and the second test sequence number, and the second test
  • the sequence number is used to indicate that the response analyzer 201b tests the second part of bits, and the second part of bits corresponds to the n+P+1 bit to the n+2P+1 bit in the M bits; the response analyzer 201b sends to the memory
  • the fourth read instruction carrying the first address in the fourth read instruction; receiving the first data sent by the memory, and combining the sub-data in the second part of the first data with the second data according to the second test sequence number
  • the sub-data in the second part of the bits are compared, and the second test result is output to the controller 201a.
  • the controller 201a can send a read instruction to the response analyzer 201b again to instruct the response analyzer 201b to read the first data, so that the untested
  • the second part is bit by bit testing.
  • the response analyzer 201b when the response analyzer 201b interacts with the memory to read the first data, the response analyzer 201b will read back the full bit width data at one time no matter which part of bits is being compared this time. After the first data is read back, it is determined which part of bits to test according to the test sequence number.
  • the controller 201a is also configured to: after sending the first read instruction to the response analyzer 201b, send a fifth read instruction to the response analyzer 201b to read the third data corresponding to the second address, and the fifth read
  • the instruction fetch carries the second address, the fourth data, and the first test sequence number
  • the response analyzer 201b is also used to: send the sixth read instruction to the memory, and the sixth read instruction carries the second address; receive the sixth read instruction sent by the memory; For the third data, compare the sub-data in the first part of the third data with the sub-data in the first part of the fourth data according to the first test sequence number, and output the third test result to the controller 201a.
  • controller 201a may also control the response analyzer 201b to test the storage space corresponding to the second address. Likewise, when testing the storage space corresponding to the second address, only a part of bits are tested each time.
  • the controller 201a may first send the first read instruction to the response analyzer 201b.
  • Three read instructions to indicate that the second part of the first data is tested
  • send the fifth read instruction to the response analyzer 201b (to indicate that the first part of the second data is tested)
  • the fifth read instruction may be sent to the response analyzer 201b first (to indicate that the first part of the second data is tested), and then the third read instruction is sent to the response analyzer 201b (to indicate that the first part of the first data is tested). Two parts of the bits are tested).
  • the number of bits included in the second part of bits and the first part of bits may be the same or different.
  • the number of bits contained in the second part of bits and the first part of bits can be set to be the same, so that the number of bits that the response analyzer 201b compares each time is the same, Comparators are designed without redundancy.
  • the number of bits included in the first part of bits is equal to the number of bits included in the second part of bits, both of which are N, where N ⁇ 1.
  • the bit width of the memory is M bits, N ⁇ M.
  • a comparator for comparing N-bit data may be configured in the response analyzer 201b.
  • the solution provided by the embodiment of the present application can reduce the area of the comparator, thereby reducing the area of the test circuit 201 .
  • the process of testing the memory is different in the embodiment of the present application.
  • the controller 201a sends the address (address), write data (data_in), data to be compared (compare data), and read data to the response analyzer 201b.
  • a test sequence number (subword_sel) is also sent to the response analyzer 201b, and the test sequence number is used to instruct the response analyzer 201b to test which bits in the read-back data.
  • the response analyzer 201b After receiving the instruction from the controller 201a, the response analyzer 201b interacts with the memory, executes the corresponding read and write instructions, and reads back the data according to the test sequence number (subword_sel) to read back the subwords located in some bits in the data. The data is compared with the data at the corresponding bit in the data to be compared (compare data), the test result is determined, and reported to the controller 201a.
  • each time the response analyzer 201b performs a test it reports a test result to the controller 201a. After the comparison of the full bit width data is completed, the controller 201a will receive multiple test results. After integrating the multiple test results, the controller 201a can determine whether the storage space corresponding to the first address passes the test according to the multiple test results.
  • the memory in FIG. 3 may be an SRAM.
  • Figure 4 shows the storage space of an SRAM.
  • different filling patterns represent the bit cells (bit cells) to be tested when different subword_sel values are used.
  • sub-data 0 is compared with the data on the corresponding bit in the second data
  • sub-data 1 is compared with the data on the corresponding bit in the second data
  • the test of the storage space corresponding to address 0 can be completed after three rounds of traversal.
  • the storage space corresponding to each address is tested according to the above process, and the SRAM test can be completed.
  • the test circuit when the test circuit tests the storage space corresponding to a certain address, it needs to test the full bit width data, that is, to test sub-data 0 to sub-data 5 at the same time, so the comparison
  • the bit width of the device is 6bits.
  • the bit width of the comparator only needs to be 2 bits, and the area of the comparator is greatly reduced.
  • bit width of the comparator is not limited to 2 bits.
  • the number of bits for each test is not limited in the embodiment of the present application.
  • the test method of traversing the subword first as shown in FIG. 5 can be adopted.
  • a test method of traversing addresses in priority may also be used. For example, after the controller 201a starts the test, the subword_sel value is set to 0.
  • the response analyzer 201b only supports the comparison of some bits, and does not need to support the comparison of the full bit width data. Therefore, compared with the prior art, the structure of the response analyzer 201b in the embodiment of the present application can be simplified.
  • the response analyzer 201b may include N comparison modules and OR gate circuits (hereinafter referred to as OR gates); each comparison module in the N comparison modules is used to compare the sub-data located on the first bit in the first data And whether the sub-data on the first bit in the second data is consistent; the OR gate circuit is used to perform an OR operation on the test results of each comparison module.
  • OR gates OR gate circuits
  • the first bit is any bit.
  • Each comparison module is used for comparing the sub-data on the same bit in the first data and the second data.
  • the OR gate circuit is used for OR operation on the test results of each comparison module. Assuming that the comparison module outputs a low level when the comparison result is consistent, and outputs a low level when the comparison result is inconsistent, then.
  • the OR gate circuit can output a low level when each comparison module outputs a low level, and output a high level in other cases. It is not difficult to understand that when each comparison module determines that the comparison result is consistent, the OR gate circuit outputs a low level; otherwise, the OR gate circuit outputs a high level. That is to say, when the OR gate circuit outputs a low level, it means that the storage space test corresponding to the first address passes; when the OR gate circuit outputs a high level, it means that the storage space test corresponding to the first address fails. .
  • comparison module can be implemented in various ways, two of which are listed below.
  • each comparison module includes a data selector, an exclusive OR gate circuit (hereinafter referred to as an exclusive OR gate), an AND gate circuit (hereinafter referred to as an OR gate) and a register, as shown in Figure 6; wherein, the data selector uses Select and output the sub-data located on the first bit in the first data according to the first test sequence number; the XOR gate circuit is used for sub-data located on the first bit in the first data and the sub-data located on the first bit in the second data Perform XOR operation on the sub-data on the bit; the AND gate circuit is used to perform AND operation on the output signal of the XOR gate circuit and the read indication signal, and when the read indication signal is valid, it is used to instruct the test circuit to execute the read instruction; the register is used for The output signal of the AND gate circuit is retrieved and output.
  • an exclusive OR gate hereinafter referred to as an exclusive OR gate
  • an OR gate AND gate circuit
  • the data selector selects the bit to be tested in the first data output from the memory according to the test sequence number. For simplicity of illustration, the above description is still used, and the bit width of the memory is M, then the first data can be split into sub-data [0] ⁇ sub-data [M-1]. Take the structure shown in FIG. 4 as an example. In FIG. 4, the response analyzer only compares two sub-data at a time, so the response analyzer includes two comparison modules. The data selectors in the two comparison modules are called data selector 1 and data selector 2 respectively.
  • the data selector 1 is used to select and output sub-data 0, sub-data 2 and sub-data 4 according to the test sequence number
  • the data selector 2 is used to select and output sub-data 1, sub-data 3 and sub-data 5 according to the test sequence number.
  • data selector 1 selects and outputs subdata 0 according to the test sequence number
  • data selector 2 selects and outputs subdata 1 according to the test sequence number
  • the data selector 2 selects and outputs sub-data 3 according to the test sequence number
  • data selector 2 selects and outputs sub-data 5 according to the test sequence number.
  • the data selector selects the sub-data of the first data pair according to the test sequence number
  • the selected sub-data is output to the XOR gate; the other input end of the XOR gate also inputs the sub-data of the corresponding bit in the second data;
  • the OR gate performs an XOR operation on the sub-data input at the two input terminals: when the two sub-data are consistent, the XOR gate outputs a low level; when the two sub-data are inconsistent, the XOR gate outputs a high level; the XOR gate outputs a high level;
  • the output terminal is connected with the AND gate, and when the read indication signal is effective (that is, the response analyzer 201b receives the read instruction of the controller), the AND gate outputs the output signal of the XOR gate to the register for latching; finally each comparison module
  • the comparison result that is, the output signal of the XOR gate
  • the OR gate outputs a low level; otherwise, the OR gate outputs a high level. Then, when the OR gate outputs a low level, it means that the test of the storage space corresponding to the first address passes; when the OR gate outputs a high level, it means that the test of the storage space corresponding to the first address fails.
  • each comparison module includes a first data selector, an XOR gate circuit, a second data selector and a register, as shown in Figure 7; wherein, the first data selector is used to select output the sub-data located on the first bit in the first data; the XOR gate circuit is used to perform sub-data located on the first bit in the first data and the sub-data located on the first bit in the second data exclusive OR operation; the second data selector is used to select and output the output signal of the exclusive OR gate circuit when the read indication signal is valid; the register is used to retrieve and output the output signal of the AND gate circuit.
  • the process of selecting sub-data by the first data selector is similar to the process of selecting sub-data by the data selector in the first implementation, and will not be repeated here.
  • the data selector selects the sub-data of the first data pair according to the test sequence number
  • the selected sub-data is output to the XOR gate; the other input end of the XOR gate also inputs the sub-data of the corresponding bit in the second data;
  • the OR gate performs an XOR operation on the sub-data input at the two input terminals: when the two sub-data are consistent, the XOR gate outputs a low level; when the two sub-data are inconsistent, the XOR gate outputs a high level; the XOR gate outputs a high level;
  • the output terminal is connected to the second data selector, and when the read indication signal is valid (that is, when the response analyzer receives the read instruction of the controller), the second data selector outputs the output signal of the XOR gate to the register for latching;
  • the comparison result of each comparison module that is, the output signal of the XOR gate
  • the OR gate outputs a low level
  • comparison module is not limited to the implementation shown in Figure 6 or Figure 7, as long as the comparison module can compare the sub-data on the corresponding bit according to the indication of the test sequence number That's it.
  • the test circuit 201 provided in the embodiment of the present application, after the response analyzer 201b reads the first data, it does not test all bits, but only tests some bits.
  • the test circuit 201 only tests some bits of the first data each time, so the test circuit 201 can perform multiple tests to realize the comparison of full-bit width data.
  • the bit width of the memory is 6 bits, and the response analyzer 201b first tests the first two bits, then tests the middle two bits, and then tests the last two bits, and then realizes the full bit width data through three comparison processes Comparison.
  • the comparator circuit in the response analyzer 201b can only support part of the bit-bit test, and there is no need to test the full-bit width data at one time, so the area of the comparator can be saved, thereby reducing the area of the test circuit 201 .
  • an embodiment of the present application further provides a testing method, as shown in FIG. 8 , the testing method includes the following steps.
  • S801 The controller sends a first read instruction to a response analyzer to read first data corresponding to a first address.
  • the first read command carries the first address, the second data and the first test sequence number
  • the first test sequence number is used to instruct the response analyzer to test the first part of bits
  • the first data includes M bits, the first part of bits The bit corresponds to the nth bit to the n+Pth bit among the M bits, M>0, P ⁇ M, n ⁇ 0.
  • S802 The controller receives the first test result sent by the response analyzer.
  • the first test result is a result of testing the first part of bits by the response analyzer.
  • S803 The controller judges whether all the bits of the first data have been tested.
  • S804 The controller determines a test result of the memory according to all received test results when all the bits of the first data are tested.
  • the controller determines the test result of the memory according to all the test results received, which may be implemented in the following manner: the controller determines that the memory test passes when all the test results indicate that the test is passed; otherwise, the controller determines that the memory test is passed. The test failed.
  • the test method shown in FIG. 8 may further include: the controller sends a third read instruction to the response analyzer to read the first data when all the bits of the first data have not been fully tested, and the first The third read command carries the first address, the second data and the second test sequence number, and the second test sequence number is used to instruct the response analyzer to test the second part of the bits, and the second part of the bits corresponds to the nth part of the M bits +P+1 bit to n+2P+1 bit; the controller receives the second test result sent by the response analyzer, and the second test result is the result of testing the second part of bits by the response analyzer.
  • the test method shown in FIG. 8 may further include: the controller sends a fifth read instruction to the response analyzer to read the first read instruction corresponding to the second address. Three data, the fifth read command carries the second address, the fourth data and the first test sequence number; the controller receives the third test result sent by the response analyzer, and the third test result is the response analyzer's response to the second data of the second data The result of testing a portion of bits.
  • the controller may first send a third read instruction to the response analyzer (to indicate to test the first part of the bits) The second part of the first data is tested), and then the fifth read command is sent to the response analyzer (to indicate that the first part of the second data is tested); it is also possible to first send the fifth read to the response analyzer An instruction is fetched (to instruct to test the first part of bits of the second data), and then a third read instruction is sent to the response analyzer (to instruct to be tested on the second part of bits of the first data). That is to say, in the test method shown in FIG. 8 , the method of traversing the test serial number in priority may be adopted, and the method of traversing the address in priority may also be adopted.
  • test method shown in FIG. 8 can be regarded as a method executed by the controller 201a in the test circuit 201.
  • the implementation and technical effects not described in detail in the test method shown in FIG. 8 can be referred to in FIG. 2 Relevant descriptions in , will not be repeated here.
  • an embodiment of the present application also provides an integrated chip.
  • the integrated chip 900 includes a memory 901 and the aforementioned test circuit 201 , and the test circuit 201 is used to test the memory 901 .
  • test circuit 201 can refer to the relevant description in FIG. 2 , which will not be repeated here.
  • test method includes the following steps.
  • S1001 Generate circuit design codes according to the structure information of the memory.
  • S1002 Convert the circuit design code into a netlist (netlist), and the netlist is used to generate a test circuit.
  • the foregoing test circuit may be any test circuit in the embodiments of the present application.
  • the execution body of the test method shown in FIG. 10 may be the Mbist tool, or electronic design automation (electronic design automation, EDA) software including the Mbist tool.
  • the Mbist tool is equivalent to the software package loaded with the test method shown in Figure 10.
  • each memory 202 has a specific mbist model.
  • the Mbist tool can obtain the structure information of the memory 202 according to the mbist model, and then generate the Mbist code according to the structure information of the memory 202.
  • the developer can convert the inserted circuit design code into netlist information. Developers can do back-end design and circuit manufacturing based on these netlist information, and finally get the above test circuit, and use the test circuit to execute the corresponding test method to test the memory.

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Abstract

一种测试电路、集成芯片及测试方法，用以减小测试电路的面积。测试电路用于对存储器进行测试，包括控制器和响应分析器。控制器用于向响应分析器发送第一读取指令，以读取第一地址对应的第一数据，第一读取指令中携带第一地址、第二数据和第一测试序号，第一测试序号用于指示响应分析器对第一部分比特位进行测试，第一数据包括M比特，第一部分比特位对应M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；响应分析器用于向存储器发送第二读取指令，然后接收存储器发送的第一数据，并根据第一测试信号将第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据进行比较，将第一测试结果输出至控制器。

Description

一种测试电路、集成芯片及测试方法 技术领域
本申请涉及芯片技术领域，尤其涉及一种测试电路、集成芯片及测试方法。
背景技术
系统级芯片，比如片上系统(system on chip，SoC)，是一种集成有处理器和存储器的芯片，系统级芯片中的存储器也可以视为嵌入式内存(memory)，例如可以是静态随机存取存储器(static random access memory，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、闪存(flash)、磁性随机存储器(magnetic random access memory，MRAM)等。
芯片在生产制造时，由于生产工艺等问题，会导致嵌入式memory存在物理上的缺陷。而嵌入式memory的数据读写过程与芯片的处理逻辑相关联，因而无法通过外部激励的方式对嵌入式memory进行测试，只能在芯片内部设计测试电路专门用于对嵌入式memory进行测试。这种测试电路可以称为可测性设计(design for test，DFT)电路。
内建自测试(memory build-in self testing，MBIST)电路是一种典型的DFT电路。一种常见的MBIST电路的结构可以如图1所示。MBIST电路包括两部分，即BIST控制器和响应分析器。BIST控制器用于控制对多个memory的测试，每个memory对应配置一个响应分析器。BIST控制器根据测试算法生成访问memory的读写操作，以及写操作的数据和读操作的期望数据；响应分析器根据BIST控制器提供的信息实现对memory的读写，从而对memory进行测试。
具体地，如图1所示，对memory进行测试的过程可以是：BIST控制器向响应分析器发送写入指令(写指示write有效代表写入指令)，包括地址(address)、写入数据(data_in)、写指示(write)三种信息；响应分析器在接收到写入指令后，向对应的memory发送写入指令，包括地址(address)、写入数据(write data)、写指示(write)三种信息，使得memory在相应地址中写入相应数据。然后，针对前述已经写入数据的地址，BIST控制器向响应分析器发送读取指令(读指示read有效代表读取指令)，包括地址(address)、待比较数据(compare data)(即读操作的期望数据)、读指示(read)三种信息；响应分析器在接收到读取指令后，向对应的memory发送读取指令，包括地址(address)、读指示(read)两种信息，使得memory读取该地址中的数据；memory将读取的数据(read data)发送至响应分析器，响应分析器将读取的数据(read data)与待比较数据(compare data)做比较；若二者一致，则向BIST控制器发送通过(pass)消息，若二者不一致，则向BIST控制器发送未通过(fail)消息。
在现有方案中，响应分析器针对某一地址进行数据读写时，需要对memory的全位宽进行读写，比如memory的位宽为16bits，则响应分析器需要支持同时对16bits的数据进行读、写和比较操作。与读写操作相比，比较操作在实现时需要的逻辑更多(例如比较器中需要配置异或门、与门和寄存器等期间)。因此，在响应分析器中，为了支持全位宽的数据比较，比较器的电路面积占比较大。比较器的面积与memory的位宽成线性关系。因此，memory的位宽越大，比较器的面积越大，响应分析器的面积越大，MBIST电路的面积也 越大。
在系统级芯片的设计中，随着嵌入式memory位宽的增加，MBIST电路的面积也越来越大。因此，亟需一种测试方案，来减小芯片中MBIST电路的面积。
发明内容
本申请实施例提供了一种测试电路、集成芯片及测试方法，用以减小测试电路的面积。
第一方面，本申请实施例提供一种测试电路，该测试电路用于对存储器进行测试，该测试电路包括控制器和响应分析器。控制器用于向响应分析器发送第一读取指令，以读取第一地址对应的第一数据，第一读取指令中携带第一地址、第二数据以及第一测试序号，第一测试序号用于指示响应分析器对第一部分比特位进行测试。其中，第一数据包括M比特，第一部分比特位对应M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；响应分析器用于向存储器发送第二读取指令，第二读取指令中携带第一地址；响应分析器还用于接收存储器发送的第一数据，并根据第一测试序号将第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据进行比较，将第一测试结果输出至控制器。
其中，第一地址对应的第一数据，即存储在第一地址中的第一数据。第一数据包括M比特，也就是说，存储器的位宽为M比特，存储在存储器的某一地址的数据均包括M比特，即第[0]比特～第[M-1]比特。第一部分比特位代表M比特中的第n比特～第n+P比特。例如，第一数据包括6比特，第一部分比特位为6比特中的第2比特～第3比特。
采用第一方面提供的测试电路，响应分析器在读取到第一数据以后，并不针对所有比特位进行测试，而是仅测试部分比特位。响应分析器每次仅对第一数据的部分比特位进行测试，那么响应分析器可以通过多次测试，实现全位宽数据的比较。因此，响应分析器中的比较器电路可以仅支持部分比特位的测试，无需一次性对全位宽数据进行测试，因而可以节省比较器的面积，从而减小测试电路的面积。
具体地，若第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据一致，则第一测试结果指示测试通过；若第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据不一致，则第一测试结果指示测试未通过。
在一种可能的设计中，控制器还用于：在接收到第一测试结果之后，判断第一数据的所有比特位是否全部测试完成；在第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定存储器中第一地址对应的存储空间的测试结果。
响应分析器在将读回的第一数据与第二数据进行比较时，并不是一次性针对全位宽数据进行比较，而是每次仅比较部分比特位；通过多次比较，完成第一数据和第二数据的比较。第一数据和第二数据比较完成后，控制器通过整合多次比较后所接收到的多个测试结果，来确定第一地址对应的存储空间的最终测试结果。
进一步地，控制器在根据接收到的所有测试结果确定存储器中第一地址对应的存储空间的测试结果时，可以通过如下方式实现：若所有测试结果均指示测试通过，则确定第一地址对应的存储空间测试通过；否则，则确定第一地址对应的存储空间测试未通过。
若所有测试结果均指示测试通过，则说明对第一数据的任一比特位进行测试时，均测试通过，因此可以确定第一地址对应的存储空间测试通过；若有测试结果指示测试未通过， 则说明第一数据的一部分比特位测试未通过，因而可以确定第一地址对应的存储空间测试未通过。
在一种可能的设计中，控制器还用于：在第一数据的所有比特位未全部测试完成的情况下，向响应分析器发送第三读取指令，以读取第一数据，第三读取指令中携带第一地址、第二数据以及第二测试序号，第二测试序号用于指示响应分析器对第二部分比特位进行测试，第二部分比特位对应M比特中的第n+P+1比特至第n+2P+1比特；响应分析器还用于：向存储器发送第四读取指令，第四读取指令中携带第一地址；接收存储器发送的第一数据，并根据第二测试序号将第一数据中位于第二部分比特位的子数据，与第二数据中位于第二部分比特位的子数据进行比较，将第二测试结果输出至控制器。
采用上述方案，在第一数据的所有比特位未全部测试完成的情况下，控制器控制响应分析器对第二部分比特位进行测试。
在一种可能的设计中，第一部分比特位包含的比特位的数量与第二部分比特位包含的比特位的数量相等，均为N，N≥1。
实际应用中，由于第一部分比特位对应M比特中的第n比特至第n+P比特，因而N可以为(n+P)-n+1＝P+1。采用上述方案，响应分析器每次进行比较的比特位数相同，均为N，比较器的设计不会出现冗余。
在一种可能的设计中，响应分析器包括N个比较模块以及或门电路；N个比较模块中的每个比较模块用于比较第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据是否一致；或门电路用于对每个比较模块的测试结果进行或运算。
采用上述方案，其中，第一比特位为任一比特位。每个比较模块用于对第一数据和第二数据中位于同一比特位上的子数据进行比较。或门电路用于对每个比较模块的测试结果进行或运算。假设比较模块在比较结果一致的情况下输出低电平，在比较结果不一致的情况下输出低电平，那么。通过对每个比较模块的输出进行或运算，或门电路可以在每个比较模块均输出低电平的情况下输出低电平、其他情况输出高电平。不难理解，在每个比较模块确定比较结果一致的情况下，或门电路输出低电平；否则，或门电路输出高电平。也就是说，在或门电路输出低电平的情况下，表示第一地址对应的存储空间测试通过；在或门电路输出高电平的情况下，表示第一地址对应的存储空间测试未通过。
下面对比较模块的具体结构进行介绍。
实现方式一
在一种可能的设计中，每个比较模块包括数据选择器、异或门电路、与门电路和寄存器；其中，数据选择器用于根据第一测试序号选择输出第一数据中位于第一比特位上的子数据；异或门电路用于对第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据进行异或运算；与门电路用于对异或门电路的输出信号与读指示信号进行与运算，读指示信号有效时用于指示响应分析器执行读取指令；寄存器用于对与门电路的输出信号进行索存并输出。
采用上述方案，在数据选择器根据测试序号选择第一数据对的子数据之后，将选择的子数据输出至异或门；异或门的另一个输入端也输入第二数据中相应比特位的子数据；异或门对两个输入端输入的子数据进行异或运算：当两个子数据一致时，异或门输出低电平；当两个子数据不一致时，异或门输出高电平；异或门的输出端与与门连接，当读指示信号有效时，与门将异或门的输出信号输出至寄存器中锁存；最终每个比较模块的比较结果(即 异或门的输出信号)经过或门进行或运算：当每个比较模块均输出低电平时，或门输出低电平；若比较模块中有任一比较模块输出高电平，则或门输出高电平。也就是说，只有在第一数据和第二数据中各个比特位的子数据均一致时，或门输出低电平；否则，或门输出高电平。那么，或门输出低电平时，表示第一地址对应的存储空间测试通过；或门输出高电平时，表示第一地址对应的存储空间测试未通过。
实现方式二
在一种可能的设计中，每个比较模块包括第一数据选择器、异或门电路、第二数据选择器和寄存器；
其中，第一数据选择器用于根据第一测试序号选择输出第一数据中位于第一比特位上的子数据；异或门电路用于对第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据进行异或运算；第二数据选择器用于在读指示信号有效时选择输出异或门电路的输出信号，读指示信号有效时用于指示响应分析器执行读取指令；寄存器用于对与门电路的输出信号进行索存并输出。
采用上述方案，在数据选择器根据测试序号选择第一数据对的子数据之后，将选择的子数据输出至异或门；异或门的另一个输入端也输入第二数据中相应比特位的子数据；异或门对两个输入端输入的子数据进行异或运算：当两个子数据一致时，异或门输出低电平；当两个子数据不一致时，异或门输出高电平；异或门的输出端与第二数据选择器连接，当读指示信号有效时，第二数据选择器将异或门的输出信号输出至寄存器中锁存；最终每个比较模块的比较结果(即异或门的输出信号)经过或门进行或运算：当每个比较模块均输出低电平时，或门输出低电平；若比较模块中有任一比较模块输出高电平，则或门输出高电平。最终，或门输出低电平时，表示第一地址对应的存储空间测试通过；或门输出高电平时，表示第一地址对应的存储空间测试未通过。
在一种可能的设计中，控制器还用于：在向响应分析器发送第一读取指令之后，向响应分析器发送第五读取指令，以读取第二地址对应的第三数据，第五读取指令中携带第二地址、第四数据以及第一测试序号；响应分析器还用于：向存储器发送第六读取指令，第六读取指令中携带第二地址；接收存储器发送的第三数据，并根据第一测试序号将第三数据中位于第一部分比特位的子数据，与第四数据中位于第一部分比特位的子数据进行比较，将第三测试结果输出至控制器。
前面已经讲到，第一数据包括M比特即表示存储器的位宽为M比特，存储在存储器的某一地址的数据均包括M比特。那么，存储在第二地址的第三数据也包括M比特，对于第三数据来说，第一部分比特位也是对应M比特中的第n比特至第n+P比特。
采用上述方案，控制器还可以控制响应分析器对第二地址对应的存储空间进行测试。同样地，对第二地址对应的存储空间进行测试时，每次仅仅对部分比特位进行测试。
在一种可能的设计中，控制器还用于：在向响应分析器发送第一读取指令之前，向响应分析器发送第一写入指令，以指示存储器在第一地址中写入第二数据，第一写入指令中携带第一地址和第二数据。
采用上述方案，在读取第一地址对应的第一数据之前，控制器控制响应分析器在第一地址下写入了第二数据。将从第一地址读回的第一数据与之前写入的第二数据进行比较，即可对存储器中第一地址对应的存储空间进行测试，以确定第一地址对应的存储空间是否有物理缺陷：若第一数据与第二数据一致，则说明第一地址对应的存储空间不存在物理缺 陷；若第一数据与第二数据不一致，则说明第一地址对应的存储空间存在物理缺陷。针对每个存储器中的每个地址均进行测试，即可确定存储器是否存在物理缺陷。
第二方面，本申请实施例提供一种集成芯片，该集成芯片包括存储器以及第一方面及其任一可能的设计中提供的测试电路，测试电路用于对存储器进行测试。
第三方面，本申请实施例提供一种测试方法，该方法包括如下步骤：控制器向响应分析器发送第一读取指令，以读取第一地址对应的第一数据，第一读取指令中携带第一地址、第二数据以及第一测试序号，第一测试序号用于指示响应分析器对第一部分比特位进行测试，第一数据包括M比特，第一部分比特位对应M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；控制器接收响应分析器发送的第一测试结果，第一测试结果为响应分析器对第一数据的第一部分比特位进行测试的结果；控制器判断第一数据的所有比特位是否全部测试完成；控制器在第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定存储器的测试结果。
在一种可能的设计中，控制器根据接收到的所有测试结果确定存储器的测试结果，包括：控制器在所有测试结果均指示测试通过的情况下，确定存储器中第一地址对应的存储空间测试通过；否则，控制器确定存储器中第一地址对应的存储空间测试未通过。
在一种可能的设计中，第三方面提供的测试方法还包括：控制器在第一数据的所有比特位未全部测试完成的情况下，向响应分析器发送第三读取指令，以读取第一数据，第三读取指令中携带第一地址、第二数据以及第二测试序号，第二测试序号用于指示响应分析器对第二部分比特位进行测试，第二部分比特位对应M比特中的第n+P+1比特至第n+2P+1比特；控制器接收响应分析器发送的第二测试结果，第二测试结果为响应分析器对第一数据的第二部分比特位进行测试的结果。
此外，在控制器向响应分析器发送第一读取指令之后，控制器还可以向响应分析器发送第五读取指令，以读取第二地址对应的第三数据，第五读取指令中携带第二地址、第四数据以及第一测试序号；控制器接收响应分析器发送的第三测试结果，第三测试结果为响应分析器对第二数据的第一部分比特位进行测试的结果。
第四方面，本申请实施例提供一种测试方法，该方法包括：根据存储器的结构信息，生成电路设计代码；将电路设计代码转换为网表，该网表用于生成第一方面及其任一可能的设计中提供的测试电路。
第五方面，本申请实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第三方面及其任一种可能设计所述的方法。
第六方面，本申请还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第三方面及其任一种可能设计所述的方法。
另外，应理解，第二方面～第六方面及其任一种可能设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为现有技术提供的一种MBIST电路的结构示意图；
图2为本申请实施例提供的一种系统级芯片的结构示意图；
图3为本申请实施例提供的一种测试电路的结构示意图；
图4为本申请实施例提供的一种SRAM的结构示意图；
图5为本申请实施例提供的一种测试流程图；
图6为本申请实施例提供的一种响应分析器的结构示意图；
图7为本申请实施例提供的另一种响应分析器的结构示意图；
图8为本申请实施例提供的一种测试方法的流程示意图；
图9为本申请实施例提供的一种集成芯片的结构示意图；
图10为本申请实施例提供的另一种测试方法的流程示意图。
具体实施方式
下面，首先对本申请实施例的应用场景进行介绍。
本申请实施例可应用于图2所示的集成芯片。参见图2，集成芯片200包括测试电路201和存储器202。存储器202可以视为芯片内的嵌入式memory，测试电路201用于测试存储器202中是否存在物理缺陷。
具体地，测试电路201可以视为图1中的MBIST电路，存储器202可以视为图1中的内存(memory)；存储器202包括但不限于SRAM、DRAM、闪存(flash)、MRAM等。
测试电路201对存储器202进行测试的原理是：测试电路201根据测试算法生成对存储器202某一地址的写入指令，以在该地址下写入data1。存储器202在接收到写入指令后，执行写入操作。在存储器202不存在物理缺陷的情况下，会将data1写入该地址；但是在存储器202存在物理缺陷的情况下，可能将data1写入错误的地址，或者在该地址下写入错误的数据。发出写入指令之后，测试电路201再针对该地址发出读取指令，以读取该地址对应的数据；存储器202在接收到读取指令后，将data2发送给测试电路201。测试电路201通过比较data1和data2是否一致，即可判断存储器202是否能正确地执行写入和读取指令，从而判断存储器202是否存在物理缺陷。
具体地，测试电路201可以包括控制器201a和响应分析器201b。控制器201a用于根据测试算法生成写入指令和读取指令、整合测试结果，以及对整个测试过程进行控制；响应分析器201b用于与存储器202交互，以指示存储器202执行写入指令和读取指令，响应分析器201b还用于对数据进行比较。
需要说明的是，本申请实施例中，测试电路201和存储器202可以设计在一个芯片(die)中，也可以分别设计成两个die；或者，测试电路201和存储器202可以是集成在同一印刷电路板(printed circuit board，PCB)上的两个die，本申请实施例中对测试电路201和存储器202的具体形态不做限定。
现有技术中，响应分析器201b在进行数据比较时，针对从存储器读回来的数据，响应分析器201b一次性进行数据的比较，比如存储器202的位宽为16bits，那么响应分析器201b则同时对16bits的数据进行比较。由于比较操作现时需要的逻辑更多，因而为了支持全位宽的数据比较，响应分析器201b的面积较大。存储器202的位宽越大，响应分析器201b的面积越大，测试电路201的面积也越大。
本申请实施例中对测试电路201的结构和测试流程进行改进，以减小响应分析器201b的面积，从而减小测试电路201的面积。
下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请实施例中，多个是指两个或两个以上。另外，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
本申请实施例提供一种测试电路，该测试电路用于对存储器进行测试。如图2所示，测试电路201包括控制器201a和响应分析器201b。其中，控制器201a用于向响应分析器201b发送第一读取指令，以读取第一地址对应的第一数据，第一读取指令中携带第一地址、第二数据以及第一测试序号，第一测试序号用于指示响应分析器201b对第一部分比特位进行测试，第一数据包括M比特，第一部分比特位对应M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；响应分析器201b用于向存储器发送第二读取指令，第二读取指令中携带第一地址；响应分析器201b还用于接收存储器发送的第一数据，并根据第一测试序号将第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据进行比较，将第一测试结果输出至控制器201a。
其中，第二数据用于与读回的第一数据进行比较，以测试存储器写入数据是否有误。具体地，在向响应分析器201b发送第一读取指令之前，控制器201a还可以向响应分析器201b发送第一写入指令，以指示存储器在第一地址中写入第二数据，第一写入指令中携带第一地址和第二数据。
不难理解，在读取第一地址对应的第一数据之前，控制器201a控制响应分析器201b在第一地址下写入了第二数据。将从第一地址读回的第一数据与之前写入的第二数据进行比较，即可对存储器中第一地址对应的存储空间进行测试，以确定第一地址对应的存储空间是否有物理缺陷：若第一数据与第二数据一致，则说明第一地址对应的存储空间不存在物理缺陷；若第一数据与第二数据不一致，则说明第一地址对应的存储空间存在物理缺陷。针对每个存储器中的每个地址均进行测试，即可确定存储器是否存在物理缺陷。
此外，本申请实施例中，关于第一部分比特位可以有如下理解：第一数据包括M比特，则存储器的位宽为M bits，在该存储器的任一地址中存储的数据均包括M比特。第一部分比特位表示M比特中的一部分比特(第n比特至第n+P比特)。也就是说，第一部分比特位是指特定位置的比特位。比如，存储器的位宽为M bits，分别为bit[0]～bit[M-1]；那么，在P＝2的情况下，第一部分比特位可以对应bit[0]～bit[1]，或者对应bit[2]～bit[3]，……，也可以对应bit[M-2]～bit[M-1]等。本申请实施例中，第一测试序号用于指示第一部分比特位，比如在上面的例子中，若第一部分比特位为bit[0]～bit[1]，则第一测试序号可以为0；若第一部分比特位为bit[2]～bit[3]，则第一测试序号可以为1……。
需要说明的是，第一部分比特位是针对全位宽而言的，并不是仅针对第一数据而言的。也就是说，对于任一地址中存储的任一数据，该数据的第一部分比特位的指代相同。比如，第一部分比特位对应bit[0]～bit[1]，那么无论对于第一数据还是第二数据，第一部分比特位均对应bit[0]～bit[1]。
响应分析器201b在读取到第一数据以后，并不对第一数据中所有比特位进行比较，而是仅比较部分比特位上的子数据。通过多次比较，可以实现全位宽数据的比较。比如，存储器的位宽为6bits，响应分析器201b先对前两个bits进行测试，再对中间两个bits进行测试，然后对最后两个bits进行测试，进而通过三次比较过程实现全位宽数据的比较。因此，本申请实施例中，响应分析器201b中的比较器电路可以仅支持部分比特位的测试，无需一次性对全位宽数据进行测试，因而可以节省比较器的面积，从而减小测试电路201 的面积。
具体地，若第一数据中位于第一部分比特位的子数据，与第二数据中位于第一部分比特位的子数据一致，则响应分析器201b向控制器201a发送的第一测试结果指示测试通过；若第一数据中位于第一部分比特位的子数据与第二数据中位于第一部分比特位的子数据不一致，则第一测试结果指示测试未通过。
此外，控制器201a还用于：在接收到第一测试结果之后，判断第一数据的所有比特位是否全部测试完成；在第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定存储器中第一地址对应的存储空间的测试结果。
如前所述，响应分析器201b在将读回的第一数据与第二数据进行比较时，并不是一次性针对全位宽数据进行比较，而是每次仅比较部分比特位；通过多次比较，完成第一数据和第二数据的比较。第一数据和第二数据比较完成后，控制器201a通过整合多次比较后所接收到的多个测试结果，来确定第一地址对应的存储空间的最终测试结果。具体地，若所有测试结果均指示测试通过，则确定第一地址对应的存储空间测试通过，第一地址对应的存储空间不存在物理缺陷；否则，则确定第一地址对应的存储空间测试未通过，第一地址对应的存储空间存在物理缺陷。
在第一数据的所有比特位未全部测试完成的情况下，说明第一数据和第二数据未比较完成。此时，控制器201a可以继续向响应分析器201b发送第三读取指令，以读取第一数据，第三读取指令中携带第一地址、第二数据以及第二测试序号，第二测试序号用于指示响应分析器201b对第二部分比特位进行测试，第二部分比特位对应M比特中的第n+P+1比特至第n+2P+1比特；响应分析器201b向存储器发送第四读取指令，第四读取指令中携带第一地址；接收存储器发送的第一数据，并根据第二测试序号将第一数据中位于第二部分比特位的子数据，与第二数据中位于第二部分比特位的子数据进行比较，将第二测试结果输出至控制器201a。
其中，关于第二部分比特位的含义可以参照前面关于第一部分比特位的描述，此处不再赘述。
也就是说，若未完成第一数据中全部比特位的比较，控制器201a可以再次向响应分析器201b发送读取指令，以指示响应分析器201b读取第一数据，从而对未经过测试的第二部分比特位进行测试。对位于第二部分比特位所的子数据进行比较时，与对位于第一部分比特位所的子数据进行比较的具体过程类似，此处不再赘述。
值得注意的是，响应分析器201b在与存储器进行交互以读取第一数据时，无论此次进行比较的是哪一部分比特位，响应分析器201b均一次性将全位宽数据读回。读回第一数据之后，再根据测试序号确定对哪一部分比特位进行测试。
此外，控制器201a还用于：在向响应分析器201b发送第一读取指令之后，向响应分析器201b发送第五读取指令，以读取第二地址对应的第三数据，第五读取指令中携带第二地址、第四数据以及第一测试序号；响应分析器201b还用于：向存储器发送第六读取指令，第六读取指令中携带第二地址；接收存储器发送的第三数据，根据第一测试序号将第三数据中位于第一部分比特位的子数据，与第四数据中位于第一部分比特位的子数据进行比较，将第三测试结果输出至控制器201a。
也就是说，控制器201a还可以控制响应分析器201b对第二地址对应的存储空间进行测试。同样地，对第二地址对应的存储空间进行测试时，每次仅仅对部分比特位进行测试。
需要说明的是，本申请实施例中，控制器201a在向响应分析器201b发送第一读取指令以指示对第一数据的第一部分比特位进行测试之后，可以先向响应分析器201b发送第三读取指令(以指示对第一数据的第二部分比特位进行测试)，再向响应分析器201b发送第五读取指令(以指示对第二数据的第一部分比特位进行测试)；也可以先向响应分析器201b发送第五读取指令(以指示对第二数据的第一部分比特位进行测试)，再向响应分析器201b发送第三读取指令(以指示对第一数据的第二部分比特位进行测试)。也就是说，本申请实施例中，可以先对某一数据的所有比特位均测试结束后再对下一地址进行测试，这种方式称为优先遍历测试序号的方式；或者，可以先针对所有数据的第一部分比特位进行测试，再针对所有数据的第二部分比特位进行测试……，这种方式称为优先遍历地址的方式。
本申请实施例中，第二部分比特位和第一部分比特位包含的比特位数量可以相同也可以不同。为了简化响应分析器201b中比较电路的设计，可以将第二部分比特位和第一部分比特位包含的比特位数量设置成相同，这样的话，响应分析器201b每次进行比较的比特位数相同，比较器的设计不会出现冗余。
在一种可能的示例中，第一部分比特位包含的比特位的数量与第二部分比特位包含的比特位的数量相等，均为N，N≥1。实际应用中，由于第一部分比特位对应M比特中的第n比特至第n+P比特，因而N可以为(n+P)-n+1＝P+1。
如前所述，存储器的位宽为M bits，N＜M。那么，响应分析器201b中可以配置用于比较N比特数据的比较器。与现有技术中需配置用于比较M比特数据的比较器相比，采用本申请实施例提供的方案，可以减小比较器的面积，从而减小测试电路201的面积。
与图1所示的对memory进行测试的过程相比，本申请实施例中，对存储器进行测试的过程有所不同。如图3所示，本申请实施例中，在对存储器进行测试时，控制器201a除了向响应分析器201b发送地址(address)、写入数据(data_in)、待比较数据(compare data)、读指示(read)/写指示(write)之外，还向响应分析器201b发送测试序号(subword_sel)，该测试序号用于指示响应分析器201b对读回数据中的哪些比特位进行测试。响应分析器201b在接收到控制器201a的指令后，与存储器进行交互，执行相应的读写指令，并在读回数据后，根据测试序号(subword_sel)将读回数据中的位于部分比特位的子数据与待比较数据(compare data)中位于相应比特位上的数据进行比较，确定测试结果，并上报给控制器201a。
需要说明的是，响应分析器201b每进行一次测试，即向控制器201a上报一次测试结果。对全位宽数据均比较完成后，控制器201a会收到多个测试结果，控制器201a整合多个测试结果后，可以根据多个测试结果确定第一地址对应的存储空间是否测试通过。
在一个具体的示例中，图3中的存储器可以为SRAM。图4示出了一个SRAM的存储空间。其中，不同的填充图案表示不同subword_sel值时所需测试的比特位(bit cell)。以测试SRAM中地址0对应的存储空间为例，控制器201a执行图5所示的流程：控制器201a启动测试后，设置subword_sel值为0，subword_sel＝0时响应分析器201b只测试地址0下的子数据0和子数据1(即将子数据0与第二数据中相应比特位上的数据进行比较，同时将子数据1与第二数据中相应比特位上的数据进行比较)；subword_sel＝0测试完成后，对subword_sel的值进行加一操作，subword_sel＝1；subword_sel＝1时响应分析器201b只测试地址0下的子数据2和子数据3；subword_sel＝1测试完成后，对subword_sel的值进行加 一操作，subword_sel＝2；subword_sel＝2时响应分析器201b只测试地址0下的子数据4和子数据5，当控制器201a确定subword_sel＝2时，不再对subword_sel进行加一操作，控制器201a判断已完成地址0对应的存储空间的测试。
不难看出，在该示例中，经过三轮遍历即可完成对地址0对应的存储空间的测试。对每个地址对应的存储空间均按照上述流程进行测试，即可完成SRAM的测试。
现有技术中，针对图4所示的SRAM，测试电路在对某一地址对应的存储空间进行测试时，需要测试全位宽数据，即同时对子数据0～子数据5进行测试，因而比较器的位宽为6bits。但是采用本申请实施例提供的方案后，比较器的位宽只需要2bits，比较器的面积大幅减少。
需要说明的是，图4和图5所示的方案仅为示例，实际应用中，比较器的位宽并不限定为2bits。只要对同一地址对应的存储空间进行测试时分批次测试即可，本申请实施例中对每次测试的比特位数不做限定。
同样需要说明的是，针对图4所示的SRAM的存储空间，可以采用图5所示的优先遍历subword的测试方式。此外，也可以采用优先遍历地址的测试方式。比如，控制器201a启动测试后，设置subword_sel值为0，subword_sel＝0时响应分析器201b只测试地址0下的子数据0和子数据1；测试完成后，对地址进行加一操作，测试地址1下的子数据0和子数据1；测试完成后，对地址进行加一操作，测试地址2下的子数据0和子数据1……；对所有地址(地址0～地址7)下的子数据0和子数据1均测试完成后，对subword_sel的值进行加一操作，subword_sel＝1，然后采用同样方式对所有地址(地址0～地址7)下的子数据2和子数据3进行测试；对所有地址(地址0～地址7)下的子数据2和子数据3均测试完成后，对subword_sel的值进行加一操作，subword_sel＝2，然后采用同样方式对所有地址(地址0～地址7)下的子数据4和子数据5进行测试。
不难看出，与现有技术相比，本申请实施例中，响应分析器201b仅支持部分比特位的比较即可，无需支持全位宽数据的比较。因而与现有技术相比，本申请实施例中的响应分析器201b的结构可以得到简化。
下面对响应分析器201b的具体结构进行介绍。
具体地，响应分析器201b可以包括N个比较模块以及或门电路(以下简称或门)；N个比较模块中的每个比较模块用于比较第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据是否一致；或门电路用于对每个比较模块的测试结果进行或运算。
其中，第一比特位为任一比特位。每个比较模块用于对第一数据和第二数据中位于同一比特位上的子数据进行比较。或门电路用于对每个比较模块的测试结果进行或运算。假设比较模块在比较结果一致的情况下输出低电平，在比较结果不一致的情况下输出低电平，那么。通过对每个比较模块的输出进行或运算，或门电路可以在每个比较模块均输出低电平的情况下输出低电平、其他情况输出高电平。不难理解，在每个比较模块确定比较结果一致的情况下，或门电路输出低电平；否则，或门电路输出高电平。也就是说，在或门电路输出低电平的情况下，表示第一地址对应的存储空间测试通过；在或门电路输出高电平的情况下，表示第一地址对应的存储空间测试未通过。
实际应用中，比较模块可以通过多种方式实现，下面列举其中两种实现方式。
实现方式一
在实现方式一中，每个比较模块包括数据选择器、异或门电路(以下简称异或门)、与门电路(以下简称或门)和寄存器，如图6所示；其中，数据选择器用于根据第一测试序号选择输出第一数据中位于第一比特位上的子数据；异或门电路用于对第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据进行异或运算；与门电路用于对异或门电路的输出信号与读指示信号进行与运算，读指示信号有效时用于指示测试电路执行读取指令；寄存器用于对与门电路的输出信号进行索存并输出。
在图6示出的响应分析器中，数据选择器根据测试序号选择存储器输出的第一数据中需要进行测试的比特位。为了示意简便，仍沿用前文的描述，存储器的位宽为M，那么第一数据可以拆分成子数据[0]～子数据[M-1]。以图4所示的结构为例，在图4中，响应分析器每次仅比较两个子数据，则响应分析器中包括两个比较模块。将两个比较模块中的数据选择器分别称为数据选择器1和数据选择器2。那么，数据选择器1用于根据测试序号选择输出子数据0、子数据2和子数据4，数据选择器2用于根据测试序号选择输出子数据1、子数据3和子数据5。比如，subword_sel＝0时，数据选择器1根据测试序号选择输出子数据0，数据选择器2根据测试序号选择输出子数据1；subword_sel＝1时，数据选择器1根据测试序号选择输出子数据2，数据选择器2根据测试序号选择输出子数据3；subword_sel＝2时，数据选择器1根据测试序号选择输出子数据4，数据选择器2根据测试序号选择输出子数据5。
在数据选择器根据测试序号选择第一数据对的子数据之后，将选择的子数据输出至异或门；异或门的另一个输入端也输入第二数据中相应比特位的子数据；异或门对两个输入端输入的子数据进行异或运算：当两个子数据一致时，异或门输出低电平；当两个子数据不一致时，异或门输出高电平；异或门的输出端与与门连接，当读指示信号有效(即响应分析器201b接收到控制器的读取指令)时，与门将异或门的输出信号输出至寄存器中锁存；最终每个比较模块的比较结果(即异或门的输出信号)经过或门进行或运算：当每个比较模块均输出低电平时，或门输出低电平；若比较模块中有任一比较模块输出高电平，则或门输出高电平。也就是说，只有在第一数据和第二数据中各个比特位的子数据均一致时，或门输出低电平；否则，或门输出高电平。那么，或门输出低电平时，表示第一地址对应的存储空间测试通过；或门输出高电平时，表示第一地址对应的存储空间测试未通过。
实现方式二
在实现方式二中，每个比较模块包括第一数据选择器、异或门电路、第二数据选择器和寄存器，如图7所示；其中，第一数据选择器用于根据第一测试序号选择输出第一数据中位于第一比特位上的子数据；异或门电路用于对第一数据中位于第一比特位上的子数据以及第二数据中位于第一比特位上的子数据进行异或运算；第二数据选择器用于在读指示信号有效时选择输出异或门电路的输出信号；寄存器用于对与门电路的输出信号进行索存并输出。
在实现方式二中，第一数据选择器选择子数据的过程与实现方式一中数据选择器选择子数据的过程类似，此处不再赘述。
在数据选择器根据测试序号选择第一数据对的子数据之后，将选择的子数据输出至异或门；异或门的另一个输入端也输入第二数据中相应比特位的子数据；异或门对两个输入端输入的子数据进行异或运算：当两个子数据一致时，异或门输出低电平；当两个子数据不一致时，异或门输出高电平；异或门的输出端与第二数据选择器连接，当读指示信号有 效(即响应分析器接收到控制器的读取指令)时，第二数据选择器将异或门的输出信号输出至寄存器中锁存；最终每个比较模块的比较结果(即异或门的输出信号)经过或门进行或运算：当每个比较模块均输出低电平时，或门输出低电平；若比较模块中有任一比较模块输出高电平，则或门输出高电平。最终，或门输出低电平时，表示第一地址对应的存储空间测试通过；或门输出高电平时，表示第一地址对应的存储空间测试未通过。
需要说明的是，本申请实施例中，比较模块的具体结构并不限定为图6或图7所示的实现方式，只要比较模块可以根据测试序号的指示对相应比特位上的子数据进行比较即可。
综上，采用本申请实施例提供的测试电路201，响应分析器201b在读取到第一数据以后，并不针对所有比特位进行测试，而是仅测试部分比特位。测试电路201每次仅对第一数据的部分比特位进行测试，那么测试电路201可以通过多次测试，实现全位宽数据的比较。比如，存储器的位宽为6bits，响应分析器201b先对前两个bits进行测试，再对中间两个bits进行测试，然后对最后两个bits进行测试，进而通过三次比较过程实现全位宽数据的比较。因此，响应分析器201b中的比较器电路可以仅支持部分比特位的测试，无需一次性对全位宽数据进行测试，因而可以节省比较器的面积，从而减小测试电路201的面积。
基于同一发明构思，本申请实施例还提供一种测试方法，如图8所示，该测试方法包括如下步骤。
S801：控制器向响应分析器发送第一读取指令，以读取第一地址对应的第一数据。
其中，第一读取指令中携带第一地址、第二数据以及第一测试序号，第一测试序号用于指示响应分析器对第一部分比特位进行测试，第一数据包括M比特，第一部分比特位对应M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0。
S802：控制器接收响应分析器发送的第一测试结果。
其中，第一测试结果为响应分析器对第一部分比特位进行测试的结果。
S803：控制器判断第一数据的所有比特位是否全部测试完成。
S804：控制器在第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定存储器的测试结果。
在S804中，控制器根据接收到的所有测试结果确定存储器的测试结果，可以通过如下方式实现：控制器在所有测试结果均指示测试通过的情况下，确定存储器测试通过；否则，控制器确定存储器测试未通过。
此外，图8所示的测试方法还可以包括：控制器在第一数据的所有比特位未全部测试完成的情况下，向响应分析器发送第三读取指令，以读取第一数据，第三读取指令中携带第一地址、第二数据以及第二测试序号，第二测试序号用于指示响应分析器对第二部分比特位进行测试，第二部分比特位对应M比特中的第n+P+1比特至第n+2P+1比特；控制器接收响应分析器发送的第二测试结果，第二测试结果为响应分析器对第二部分比特位进行测试的结果。
此外，在控制器向响应分析器发送第一读取指令之后，图8所示的测试方法还可以包括：控制器向响应分析器发送第五读取指令，以读取第二地址对应的第三数据，第五读取指令中携带第二地址、第四数据以及第一测试序号；控制器接收响应分析器发送的第三测试结果，第三测试结果为响应分析器对第二数据的第一部分比特位进行测试的结果。
应理解，控制器在执行S801向响应分析器发送第一读取指令以指示对第一数据的第一部分比特位进行测试之后，可以先向响应分析器发送第三读取指令(以指示对第一数据的第二部分比特位进行测试)，再向响应分析器发送第五读取指令(以指示对第二数据的第一部分比特位进行测试)；也可以先向响应分析器发送第五读取指令(以指示对第二数据的第一部分比特位进行测试)，再向响应分析器发送第三读取指令(以指示对第一数据的第二部分比特位进行测试)。也就是说，在图8所示的测试方式中，可以采用优先遍历测试序号的方式，也可以采用优先遍历地址的方式。
需要说明的是，图8所示的测试方法可以视为测试电路201中的控制器201a所执行的方法，图8所示的测试方法中未详尽描述的实现方式及其技术效果可以参见图2中的相关描述，此处不再赘述。
基于同一发明构思，本申请实施例还提供一种集成芯片，如图9所示，该集成芯片900包括存储器901以及前述测试电路201，测试电路201用于对存储器901进行测试。
需要说明的是，图9所示的集成芯片900中，测试电路201的具体操作可以参见图2中的相关描述，此处不再赘述。
此外，本申请实施例还提供一种测试方法。如图10所示，该测试方法包括如下步骤。
S1001：根据存储器的结构信息，生成电路设计代码。
S1002：将电路设计代码转换为网表(netlist)，该网表用于生成测试电路。上述测试电路可以是本申请实施例中的任意一种测试电路。
图10所示的测试方法的执行主体可以是Mbist工具，或者是包含Mbist工具的电子设计自动化(electronic design automation，EDA)软件。Mbist工具相当于加载有图10所示测试方法的软件包。在一种实施方式中，每个存储器202均具有特定的mbist模型(mbist model)。Mbist工具根据mbist model可以获取存储器202的结构信息，进而根据存储器202的结构信息生成Mbist代码。Mbist工具将Mbist代码插入到测试电路的电路设计代码之后，开发者就可以将插入后的电路设计代码转换为网表信息。开发者可以根据这些网表信息做后端(back end)设计，以及电路的制造，最后得到上述测试电路，并使用测试电路执行对应的测试方法，对存储器进行测试。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (19)

  1. 一种测试电路，其特征在于，所述测试电路用于对存储器进行测试，包括：
    控制器，用于向响应分析器发送第一读取指令，以读取第一地址对应的第一数据，所述第一读取指令中携带所述第一地址、第二数据以及第一测试序号，所述第一测试序号用于指示所述响应分析器对第一部分比特位进行测试，所述第一数据包括M比特，所述第一部分比特位对应所述M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；
    所述响应分析器，用于向所述存储器发送第二读取指令，所述第二读取指令中携带所述第一地址；所述响应分析器还用于接收所述存储器发送的所述第一数据，并根据所述第一测试序号将所述第一数据中位于所述第一部分比特位的子数据，与所述第二数据中位于所述第一部分比特位的子数据进行比较，将第一测试结果输出至所述控制器。
  2. 如权利要求1所述的测试电路，其特征在于，若所述第一数据中位于所述第一部分比特位的子数据，与所述第二数据中位于所述第一部分比特位的子数据一致，则所述第一测试结果指示测试通过；若所述第一数据中位于所述第一部分比特位的子数据，与所述第二数据中位于所述第一部分比特位的子数据不一致，则所述第一测试结果指示测试未通过。
  3. 如权利要求1或2所述的测试电路，其特征在于，所述控制器还用于：
    在接收到所述第一测试结果之后，判断所述第一数据的所有比特位是否全部测试完成；
    在所述第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定所述存储器中所述第一地址对应的存储空间的测试结果。
  4. 如权利要求3所述的测试电路，其特征在于，所述控制器在根据接收到的所有测试结果确定所述存储器中所述第一地址对应的存储空间的测试结果时，具体用于：
    若所有测试结果均指示测试通过，则确定所述第一地址对应的存储空间测试通过；否则，则确定所述第一地址对应的存储空间测试未通过。
  5. 如权利要求3或4所述的测试电路，其特征在于，所述控制器还用于：
    在所述第一数据的所有比特位未全部测试完成的情况下，向所述响应分析器发送第三读取指令，以读取所述第一数据，所述第三读取指令中携带所述第一地址、所述第二数据以及第二测试序号，所述第二测试序号用于指示所述响应分析器对第二部分比特位进行测试，所述第二部分比特位对应所述M比特中的第n+P+1比特至第n+2P+1比特；
    所述响应分析器还用于：
    向所述存储器发送第四读取指令，所述第四读取指令中携带所述第一地址；接收所述存储器发送的所述第一数据，并根据所述第二测试序号将所述第一数据中位于所述第二部分比特位的子数据，与所述第二数据中位于所述第二部分比特位的子数据进行比较，将第二测试结果输出至所述控制器。
  6. 如权利要求5所述的测试电路，其特征在于，所述第一部分比特位包含的比特位的数量与所述第二部分比特位包含的比特位的数量相等，均为N，N≥1。
  7. 如权利要求6所述的测试电路，其特征在于，所述响应分析器包括N个比较模块以及或门电路；所述N个比较模块中的每个比较模块用于比较所述第一数据中位于第一比特位上的子数据以及所述第二数据中位于所述第一比特位上的子数据是否一致；所述或门电路用于对所述每个比较模块的测试结果进行或运算。
  8. 如权利要求7所述的测试电路，其特征在于，所述每个比较模块包括数据选择器、异或门电路、与门电路和寄存器；
    其中，所述数据选择器用于根据所述第一测试序号选择输出所述第一数据中位于所述第一比特位上的子数据；所述异或门电路用于对所述第一数据中位于所述第一比特位上的子数据以及所述第二数据中位于所述第一比特位上的子数据进行异或运算；所述与门电路用于对所述异或门电路的输出信号与所述读指示信号进行与运算，所述读指示信号有效时用于指示所述响应分析器执行读取指令；所述寄存器用于对所述与门电路的输出信号进行索存并输出。
  9. 如权利要求7所述的测试电路，其特征在于，所述每个比较模块包括第一数据选择器、异或门电路、第二数据选择器和寄存器；
    其中，所述第一数据选择器用于根据所述第一测试序号选择输出所述第一数据中位于所述第一比特位上的子数据；所述异或门电路用于对所述第一数据中位于所述第一比特位上的子数据以及所述第二数据中位于所述第一比特位上的子数据进行异或运算；所述第二数据选择器用于在所述读指示信号有效时选择输出所述异或门电路的输出信号，所述读指示信号有效时用于指示所述响应分析器执行读取指令；所述寄存器用于对所述与门电路的输出信号进行索存并输出。
  10. 如权利要求1～9任一项所述的测试电路，其特征在于，所述控制器还用于：
    在向响应分析器发送第一读取指令之后，向所述响应分析器发送第五读取指令，以读取第二地址对应的第三数据，所述第五读取指令中携带所述第二地址、第四数据以及所述第一测试序号；
    所述响应分析器还用于：
    向所述存储器发送第六读取指令，所述第六读取指令中携带所述第二地址；接收所述存储器发送的所述第三数据，并根据所述第一测试序号将所述第三数据中位于所述第一部分比特位的子数据，与所述第四数据中位于所述第一部分比特位的子数据进行比较，将第三测试结果输出至所述控制器。
  11. 如权利要求1～10任一项所述的测试电路，其特征在于，所述控制器还用于：
    在向所述响应分析器发送所述第一读取指令之前，向所述响应分析器发送第一写入指令，以指示所述存储器在所述第一地址中写入所述第二数据，所述第一写入指令中携带所述第一地址和所述第二数据。
  12. 一种集成芯片，其特征在于，包括存储器以及如权利要求1～11任一项所述的测试 电路，所述测试电路用于对所述存储器进行测试。
  13. 一种测试方法，其特征在于，包括：
    控制器向响应分析器发送第一读取指令，以读取第一地址对应的第一数据，所述第一读取指令中携带所述第一地址、第二数据以及第一测试序号，所述第一测试序号用于指示所述响应分析器对第一部分比特位进行测试，所述第一数据包括M比特，所述第一部分比特位对应所述M比特中的第n比特至第n+P比特，M＞0，P＜M，n≥0；
    所述控制器接收所述响应分析器发送的第一测试结果，所述第一测试结果为所述响应分析器对所述第一数据的所述第一部分比特位进行测试的结果；
    所述控制器判断所述第一数据的所有比特位是否全部测试完成；
    所述控制器在所述第一数据的所有比特位全部测试完成的情况下，根据接收到的所有测试结果确定所述存储器的测试结果。
  14. 如权利要求13所述的方法，其特征在于，控制器根据接收到的所有测试结果确定所述存储器的测试结果，包括：
    所述控制器在所有测试结果均指示测试通过的情况下，确定所述存储器中所述第一地址对应的存储空间测试通过；否则，所述控制器确定所述存储器中所述第一地址对应的存储空间测试未通过。
  15. 如权利要求13或14所述的方法，其特征在于，还包括：
    所述控制器在所述第一数据的所有比特位未全部测试完成的情况下，向所述响应分析器发送第三读取指令，以读取所述第一数据，所述第三读取指令中携带所述第一地址、所述第二数据以及第二测试序号，所述第二测试序号用于指示所述响应分析器对第二部分比特位进行测试，所述第二部分比特位对应所述M比特中的第n+P+1比特至第n+2P+1比特；
    所述控制器接收所述响应分析器发送的第二测试结果，所述第二测试结果为所述响应分析器对所述第一数据的所述第二部分比特位进行测试的结果。
  16. 如权利要求13～15任一项所述的方法，其特征在于，在控制器向响应分析器发送第一读取指令之后，还包括：
    所述控制器向所述响应分析器发送第五读取指令，以读取第二地址对应的第三数据，所述第五读取指令中携带所述第二地址、第四数据以及所述第一测试序号；
    所述控制器接收所述响应分析器发送的第三测试结果，所述第三测试结果为所述响应分析器对所述第二数据的所述第一部分比特位进行测试的结果。
  17. 一种测试方法，其特征在于，包括：
    根据存储器的结构信息，生成电路设计代码；
    将所述电路设计代码转换为网表，所述网表用于生成如权利要求1～11任一项所述的测试电路。
  18. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令， 当其在计算机上运行时，使得计算机执行如权利要求13～16任一项所述的方法。
  19. 一种计算机程序产品，其特征在于，所述计算机程序产品包括指令，当所述指令在计算机上运行时，使得计算机执行如权利要求13～16任一项所述的方法。
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