WO2022242273A1 - 基于rlgc电路模型的衰减可调电路及芯片 - Google Patents

基于rlgc电路模型的衰减可调电路及芯片 Download PDF

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Publication number
WO2022242273A1
WO2022242273A1 PCT/CN2022/079957 CN2022079957W WO2022242273A1 WO 2022242273 A1 WO2022242273 A1 WO 2022242273A1 CN 2022079957 W CN2022079957 W CN 2022079957W WO 2022242273 A1 WO2022242273 A1 WO 2022242273A1
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Prior art keywords
attenuation
circuit
transistor
adjustable
switched capacitor
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PCT/CN2022/079957
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English (en)
French (fr)
Inventor
王爱伟
陈莹梅
吴琪琳
张国峰
张琴梅
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华为技术有限公司
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Publication of WO2022242273A1 publication Critical patent/WO2022242273A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and in particular to an attenuation adjustable circuit and chip based on an RLGC circuit model.
  • Serializer/deserializer (serializer/deserializer, SerDes for short) is an interface device with high-speed transmission function.
  • the low-speed parallel signal is converted into a high-speed serial signal through the serializer, and then passed through the transmission medium (such as Optical cable or copper wire, etc.) transmit the serial signal to the receiving end, and then convert the high-speed serial signal into a low-speed parallel signal through the deserializer at the receiving end.
  • the transmission medium such as Optical cable or copper wire, etc.
  • the transmission medium of the above-mentioned serial signal is called a SerDes channel.
  • a normalized loop-back winding board is used to simulate the SerDes channel to test the performance of the SerDes.
  • each board to be tested includes multiple SerDes, and for SerDes at the same position, the lengths of the SerDes channels of various boards to be tested may be different, and different SerDes channels make The degree of attenuation of the signal may be different.
  • the normalized loopback board is used to simulate the SerDes channel. The attenuation simulation of the SerDes channel by the normalized loopback board is fixed. Therefore, the normalized loopback board cannot be used for The maximum stress applied to the SerDes channel of various single boards to be tested requires that the normalized loop-back winding board is used to simulate the SerDes channel, and its applicability is poor.
  • Embodiments of the present application provide an attenuation adjustable circuit and chip based on the RLGC circuit model, which can meet different attenuation requirements and have good applicability.
  • an embodiment of the present application provides an attenuation adjustable circuit based on an RLGC circuit model, including: a switched capacitor array circuit, a first impedance circuit, and a second impedance circuit.
  • the input end of the first impedance circuit is coupled to the input end of the attenuation adjustable circuit
  • the output end of the first impedance circuit is connected to the input end of the second impedance circuit
  • the output end of the second impedance circuit is coupled to the output of the attenuation adjustable circuit terminal
  • the output terminal of the first impedance circuit and the input terminal of the second impedance circuit are respectively connected to the first terminal of the switched capacitor array circuit
  • the second terminal of the switched capacitor array circuit is grounded.
  • the first impedance circuit and the second impedance circuit include inductance elements and resistance elements
  • the switched capacitor array circuit includes capacitance elements and switch elements.
  • the switched capacitor array circuit is used to adjust the attenuation value of the attenuation adjustable circuit within the first attenuation range.
  • the attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application can realize the adjustment of the attenuation value of the circuit by controlling the switched capacitor array of the attenuation adjustable circuit. Since the attenuation value of the attenuation adjustable circuit can be adjusted in Therefore, in practical applications, the adjustable attenuation circuit can be adjusted according to the demand for the attenuation value to make the attenuation value reach the expected value, which has good applicability.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application can be used to simulate SerDes channels with different attenuation ranges, there is no need to design or develop a test tool board for each SerDes channel, Can greatly save costs.
  • the above switched capacitor array circuit is specifically configured to adjust the attenuation value of the adjustable attenuation circuit within the first attenuation range by adjusting the capacitance value and conductance value of the adjustable attenuation circuit.
  • the attenuation value of the circuit can be adjusted by adjusting various parameters in the circuit, such as at least one of the resistance value, inductance value, conductance value or capacitance value, provided in the embodiment of the present application
  • the attenuation value of the attenuation adjustable circuit is adjusted by adjusting the capacitance value and the conductance value in the attenuation adjustable circuit.
  • the switched capacitor array circuit is composed of N switched capacitor modules formed by N capacitive elements and N switching elements connected in parallel, and the first end of the ith switched capacitor module is coupled to the first terminal of the switched capacitor array circuit.
  • the second end of the i-th switched capacitor module is coupled to the second end of the switched capacitor array circuit;
  • N is a positive integer greater than or equal to 2, and i is any one of 1, 2, ..., N.
  • the i-th capacitive element among the N capacitive elements is connected in series with the i-th switching element among the N switching elements to form the i-th switched capacitor module of the switched capacitor array circuit.
  • the N switch elements are used to control one or more capacitive elements in the N capacitive elements to connect or not connect to the attenuation adjustment circuit, so as to adjust the capacitance value and conductance value of the attenuation adjustable circuit.
  • the above N switching elements are N transistors; the drain of the i-th transistor among the N transistors is connected to the first end of the i-th capacitive element, and the source of the i-th transistor is coupled to The second end of the i-th switched capacitor module, the gate of the i-th transistor is connected to the signal controller, and the second end of the i-th capacitor is coupled to the first end of the switched capacitor module.
  • the first impedance circuit includes a first resistance element and a first inductance element, and the first resistance element and the first inductance element are connected in parallel.
  • the first end of the first resistance element and the first end of the first inductance element are coupled to the input end of the first impedance circuit, and the second end of the first resistance element and the second end of the first inductance element are coupled to the first output of the impedance circuit.
  • the second impedance circuit includes a second resistance element and a second inductance element, and the second resistance element and the second inductance element are connected in parallel.
  • the first end of the second resistance element and the first end of the second inductance element are coupled to the input end of the second impedance circuit, and the second end of the second resistance element and the second end of the second inductance element are coupled to the second output of the impedance circuit.
  • the signal controller controls the N transistors to be turned on or off, so that the N capacitors are connected to the circuit, or not connected to the circuit.
  • the first attenuation range The attenuation value of the attenuation adjustable circuit is adjusted.
  • the adjustable attenuation circuit can be equivalent to a two-port network, calculate the S parameter matrix of the two-port network, and obtain the insertion loss of the adjustable attenuation circuit according to the calculation relationship between the S parameter matrix and the insertion loss of the circuit, The insertion loss is the attenuation value of the attenuation adjustable circuit.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a first attenuation adjustment circuit, the input end of the first attenuation adjustment circuit is coupled to the input end of the attenuation adjustable circuit, The output end of the first attenuation adjustment circuit is coupled to the output end of the attenuation adjustable circuit, and the first attenuation adjustment circuit includes an inductance element and a switch element.
  • the first attenuation adjustment circuit and the switched capacitor array circuit are used to adjust the attenuation value of the attenuation adjustable circuit within the second attenuation range; wherein, the first attenuation adjustment circuit is used to adjust the inductance value and resistance value of the attenuation adjustable circuit,
  • the switched capacitor array circuit is used for adjusting the capacitance value and conductance value of the attenuation adjustable circuit.
  • the first attenuation adjustment circuit includes a third inductance element, a first switch element, and a second switch element, wherein the first switch element, the third inductance element, and the second switch element are connected in series in sequence.
  • the first switch element and the second switch element are used to control whether the third inductance element is connected to the adjustable attenuation circuit or not connected to the adjustable attenuation circuit, so as to adjust the inductance and resistance of the adjustable attenuation circuit.
  • the switching element is a transistor
  • the first switching element is a first transistor
  • the second switching element is a second transistor.
  • the drain of the first transistor is coupled to the input end of the first attenuation adjustment circuit
  • the source of the first transistor is connected to the first end of the third inductance element
  • the source of the second transistor is connected to the second end of the third inductance element
  • the drain of the second transistor is coupled to the output terminal of the first attenuation adjustment circuit
  • the gate of the first transistor and the gate of the second transistor are connected to the signal controller.
  • the first transistor and the second transistor are N-channel MOS transistors having the same parameters.
  • the signal controller controls the N transistors to be turned on or off, so that the N capacitors are connected to the circuit, or not connected to the circuit, and the control connection The amount of capacitance input into the circuit, so as to adjust the attenuation value of the attenuation adjustable circuit within the second attenuation range.
  • the adjustable attenuation circuit can be equivalent to a two-port network, calculate the S parameter matrix of the two-port network, and obtain the insertion loss of the adjustable attenuation circuit according to the calculation relationship between the S parameter matrix and the insertion loss of the circuit, The insertion loss is the attenuation value of the attenuation adjustable circuit.
  • the first attenuation adjustment circuit further includes a third transistor and a fourth transistor; wherein, the drain of the third transistor is connected to the source of the first transistor, and the drain of the fourth transistor is connected to the source of the second transistor.
  • the source, the source of the third transistor and the source of the fourth transistor are both grounded, and the gate of the third transistor and the gate of the fourth transistor are both connected to the signal controller.
  • the level input to the gate of the third transistor by the signal controller is opposite to the level input to the gate of the first transistor, and the level input to the gate of the fourth transistor by the signal controller is opposite to the level input to the gate of the second transistor.
  • the level of the gate input is reversed.
  • the third transistor and the fourth transistor are used to conduct the AC voltage of the first attenuation adjustment circuit to ground when the first attenuation adjustment circuit is not connected to the attenuation adjustable circuit.
  • the first transistor and the second transistor when the level input by the signal controller to the first attenuation adjustment circuit through its output terminal is a low level, that is, when the first attenuation adjustment circuit is in a non-working state, the first transistor and the second transistor have an alternating current. Voltage (at this time, the first transistor and the second transistor are equivalent to large capacitance), at this time, because the gate input of the third transistor and the fourth transistor is a high level, therefore, the third transistor and the fourth transistor The AC voltage can be conducted to the ground, so that the output terminal of the first attenuation adjustment circuit does not output a signal, so that the first attenuation adjustment circuit does not interfere with the output signals of other parts of the circuit.
  • the function of the third transistor and the fourth transistor is to improve the isolation of the first attenuation adjustment circuit.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a second attenuation adjustment circuit, the input end of the second attenuation adjustment circuit is coupled to the input end of the attenuation adjustable circuit, The output end of the second attenuation adjustment circuit is coupled to the output end of the attenuation adjustable circuit, and the second attenuation adjustment circuit includes an inductance element, a capacitance element and a switch element.
  • the second attenuation adjustment circuit and the switched capacitor array circuit are used to adjust the attenuation value of the attenuation adjustable circuit within the third attenuation range; wherein, the second attenuation adjustment circuit is used to adjust the inductance value and resistance value of the attenuation adjustable circuit, Or adjust the inductance value, resistance value, capacitance value and conductance value of the attenuation adjustable circuit; the switched capacitor array circuit is used to adjust the capacitance value and conductance value of the attenuation adjustable circuit.
  • the above-mentioned second attenuation adjustment circuit includes a fourth inductance element, a third switch element, a fourth switch element, a first switched capacitor module, and a second switched capacitor module.
  • the first end of the third switching element is coupled to the input end of the attenuation adjustable circuit
  • the second end of the third switching element is connected to the first end of the fourth inductance element and the first end of the first switched capacitor module, and the first The second end of the switched capacitor module is grounded
  • the first end of the fourth switch element is coupled to the output end of the attenuation adjustable circuit
  • the second end of the fourth switch element is connected to the second end of the fourth inductance element and the second switched capacitor module
  • the first terminal of the second switched capacitor module is grounded.
  • the third switch element and the fourth switch element are used to control whether the fourth inductance element is connected to the adjustable attenuation circuit or not connected to the adjustable attenuation circuit, so as to adjust the inductance and resistance of the adjustable attenuation circuit.
  • the first switched capacitor module is formed by connecting the first capacitor element and the fifth switch element in series
  • the second switched capacitor module is formed by connecting the second capacitor element and the sixth switch element in series.
  • the fifth switch element is used to control whether the first capacitive element is connected to the attenuation adjustment circuit or not to adjust the capacitance value and conductance value of the attenuation adjustable circuit
  • the sixth switch element is used to control the second capacitive element to be connected to the attenuation adjustment circuit. Enter or not access the attenuation adjustment circuit to adjust the capacitance value and conductance value of the attenuation adjustable circuit.
  • the fifth switching element and the sixth switching element are transistors, and the fifth switching element is a fifth transistor, and the sixth switching element is a sixth transistor; the third switching element and the fourth switching element are transistor, and the third switch element is the seventh transistor, and the fourth switch element is the eighth transistor.
  • the drain of the seventh transistor is coupled to the input end of the second attenuation adjustment circuit, the source of the seventh transistor is connected to the first end of the fourth inductance element; the second end of the fourth inductance element is connected to the source of the eighth transistor , the drain of the eighth transistor is coupled to the output terminal of the second attenuation adjustment circuit; the gate of the seventh transistor and the gate of the eighth transistor are connected to the signal controller.
  • the drain of the fifth transistor is connected to the first end of the first capacitive element, the second end of the first capacitive element is connected to the source of the seventh transistor, the drain of the sixth transistor is connected to the first end of the second capacitive element, and the second The second terminal of the capacitive element is connected to the source of the eighth transistor, the source of the fifth transistor and the source of the sixth transistor are both grounded, and the gate of the fifth transistor and the gate of the sixth transistor are respectively connected to the signal controller.
  • the signal controller controls the N transistors to be turned on or off, so that the N capacitors are connected to the circuit, Or not connected to the circuit, by controlling the number of capacitors connected to the circuit, and through the signal controller to control the fifth transistor and the sixth transistor to be turned on or off, so that the first capacitor and the second capacitor are connected to the circuit, or not connected circuit, so as to adjust the attenuation value of the attenuation adjustable circuit within the third attenuation range.
  • the adjustable attenuation circuit can be equivalent to a two-port network, calculate the S parameter matrix of the two-port network, and obtain the insertion loss of the adjustable attenuation circuit according to the calculation relationship between the S parameter matrix and the insertion loss of the circuit,
  • the insertion loss is the attenuation value of the attenuation adjustable circuit.
  • the above-mentioned second attenuation adjustment circuit further includes a ninth transistor; the source of the ninth transistor is grounded, the drain of the ninth transistor is connected to the second end of the fourth inductance element, and the gate of the ninth transistor
  • the signal controller is connected; the level input to the gate of the ninth transistor through the signal controller is opposite to the level input to the gate of the eighth transistor.
  • the ninth transistor is used to conduct the AC voltage of the second attenuation adjustment circuit to ground when the second attenuation adjustment circuit is not connected to the attenuation adjustable circuit.
  • the seventh transistor and the eighth transistor in the second attenuation adjustment circuit have AC voltage (at this time, the seventh transistor and the eighth transistor are equivalent to large capacitors)
  • the ninth transistor can conduct the AC voltage to the ground, so that the second The output terminal of the attenuation adjustment circuit does not output a signal, that is, the second attenuation adjustment circuit does not interfere with output signals of other attenuation adjustment circuits.
  • the function of the ninth transistor is to improve the isolation of the second attenuation adjustment circuit.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a seventh switching element and an eighth switching element; the seventh switching element and the eighth switching element are used to control the second Whether the attenuation adjustment circuit works independently.
  • the seventh switch element and the eighth switch element are not turned on, only the second attenuation adjustment circuit is included in the attenuation adjustable circuit, and the second attenuation adjustment circuit works independently; the second attenuation adjustment circuit is used for the fourth attenuation adjustment circuit Adjust the attenuation value of the attenuation adjustable circuit within the range.
  • the seventh switch element and the eighth switch element are transistors, and the seventh switch element is a tenth transistor, and the eighth switch element is an eleventh transistor.
  • the drain of the tenth transistor is coupled to the input end of the attenuation adjustable circuit
  • the source of the tenth transistor is coupled to the input end of the first impedance circuit and the input end of the first attenuation adjustment circuit
  • the drain of the eleventh transistor Coupled to the output end of the attenuation adjustable circuit
  • the source of the eleventh transistor is coupled to the output end of the second impedance circuit and the output end of the first attenuation adjustment circuit
  • the gate of the tenth transistor and the gate of the eleventh transistor Connect the signal controller.
  • the signal controller controls the fifth transistor and the The six transistors are turned on or off, so that the first capacitor and the second capacitor are connected to the circuit, or not connected to the circuit, so as to adjust the attenuation value of the attenuation adjustable circuit within the first attenuation range.
  • the adjustable attenuation circuit can be equivalent to a two-port network, calculate the S parameter matrix of the two-port network, and obtain the insertion loss of the adjustable attenuation circuit according to the calculation relationship between the S parameter matrix and the insertion loss of the circuit,
  • the insertion loss is the attenuation value of the attenuation adjustable circuit.
  • the adjustable attenuation circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a twelfth transistor and a thirteenth transistor.
  • the drain of the twelfth transistor is coupled to the input end of the first impedance circuit
  • the drain of the thirteenth transistor is coupled to the output end of the second impedance circuit
  • the source of the twelfth transistor and the source of the thirteenth transistor Both poles are grounded
  • the gate of the twelfth transistor and the gate of the thirteenth transistor are both connected to the signal controller
  • the level of the signal controller is opposite to the level input to the gate of the thirteenth transistor and the level input to the gate of the eleventh transistor is opposite.
  • the twelfth transistor and the thirteenth transistor are used for conducting the AC voltage of the attenuation adjustable circuit to ground when the second attenuation adjustment circuit works independently.
  • the tenth transistor and the eleventh transistor when the tenth transistor and the eleventh transistor are turned off, the tenth transistor and the eleventh transistor have an AC voltage (at this time, the tenth transistor and the eleventh transistor have an AC voltage equivalent to a large capacitance) , since the gate input of the twelfth transistor and the thirteenth transistor is a high level, the twelfth transistor and the thirteenth transistor can conduct the AC voltage to the ground, so that the attenuation described in the first aspect can be reduced
  • the output terminal of the attenuation adjustment circuit (which may be called the third attenuation adjustment circuit) does not output a signal, that is, the third attenuation adjustment circuit does not interfere with the output signals of other attenuation adjustment circuits (first attenuation adjustment circuit).
  • the function of the twelfth transistor and the thirteenth transistor is to improve the isolation of the third attenuation adjustment circuit.
  • an embodiment of the present application provides an adjustable attenuation chip, including: the adjustable attenuation circuit described in any one of the multiple first aspects and possible implementations thereof, the multiple adjustable attenuation circuits are divided into Multiple sets of attenuation adjustable circuits are symmetrically arranged.
  • the attenuation adjustable chip provided by the embodiment of the present application can be applied to the scenario where multiple SerDes work in parallel, for example, the scenario where multiple SerDes channels transmit signals at the same time, and each attenuation adjustable circuit in the attenuation adjustable chip can work independently and interact with each other. No influence, and the attenuation adjustable chip has high integration and small area.
  • the adjustable attenuation chip provided in the embodiment of the present application further includes a signal controller; the signal controller is used to provide digital control signals for multiple adjustable attenuation circuits, so as to control the multiple attenuation adjustable circuits. working status.
  • the packaging method for the adjustable attenuation chip provided by the embodiment of the present application is a miniaturized multi-DIE packaging technology.
  • Each group of the above-mentioned adjustable attenuation circuits can be called a DIE.
  • This packaging method can not only reduce the packaging wiring
  • the length of the chip reduces the attenuation value (insertion loss) caused by the package wiring to the signal, and all the indicators of the attenuation adjustable chip are up to the standard, such as isolation and crosstalk, all meet the expected indicators.
  • Fig. 1 is the structural representation of a kind of RLGC circuit model and two-port network that the embodiment of the application provides;
  • FIG. 2 is a schematic diagram of a SerDes test principle provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 4 is a structural schematic diagram 2 of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application
  • FIG. 6 is a structural schematic diagram 4 of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application.
  • FIG. 8 is an equivalent circuit diagram 1 of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application;
  • FIG. 9 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application VI;
  • FIG. 10 is a schematic structural diagram of an attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application VII;
  • FIG. 11 is a schematic structural diagram eighth of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application.
  • Fig. 12 is an equivalent circuit diagram 2 of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application;
  • FIG. 13 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 14 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • Fig. 15 is a structural schematic diagram eleven of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application;
  • FIG. 16 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application.
  • Fig. 18 is an equivalent circuit diagram 3 of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application;
  • FIG. 19 is a fourteenth structural schematic diagram of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application;
  • FIG. 21 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application.
  • Fig. 22 is an equivalent circuit diagram 4 of an attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application;
  • FIG. 23 is a schematic structural diagram of an attenuation adjustable circuit based on an RLGC circuit model provided in an embodiment of the present application.
  • FIG. 24 is a first structural schematic diagram of an attenuation adjustable chip provided by an embodiment of the present application.
  • Fig. 25 is a schematic structural diagram II of an attenuation adjustable chip provided by an embodiment of the present application.
  • FIG. 26 is a schematic diagram of a packaging effect of an attenuation adjustable chip provided by an embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • the first impedance circuit, the second impedance circuit, etc. are used to distinguish different impedance circuits, not to describe a specific order of the impedance circuits.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • the adjustable attenuation circuit based on the RLGC circuit model provided in the embodiment of the present application can be used for simulating a transmission channel.
  • the use of the adjustable attenuation circuit for simulating a SerDes channel is used as an example for illustration.
  • RLGC circuit model It is a circuit model for equivalent transmission lines.
  • the RLGC circuit model includes four distribution parameters, namely resistance (R), inductance (L), conductance (G) and capacitance (C).
  • R resistance
  • L inductance
  • G conductance
  • C capacitance
  • the transmission line may be cut into infinitely many small RLGC units with length dz by using the microelement method, and the attenuation characteristics of the small RLGC units are basically the same as those of the transmission line.
  • (a) in Figure 1 is a structure of a RLGC small unit and an equivalent schematic diagram of a transmission line. When using an RLGC circuit to simulate a transmission line, multiple RLGC small units can be connected in series to simulate the transmission line. For details, refer to (b) in Figure 1.
  • the SerDes test circuit has a certain attenuation effect on the signal.
  • the SerDes test circuit has a certain attenuation effect on the signal.
  • the attenuation value caused by the circuit to the signal is equal to the insertion loss of the SerDes test circuit, and the insertion loss of the circuit is related to the impedance (DC impedance or AC impedance) of each component in the circuit.
  • the SerDes test circuit can be equivalent to a two-port network, based on the two-port network, the insertion loss of the SerDes test circuit can be calculated.
  • Two-port network Referring to (c) in Figure 1, a brief introduction to the two-port network is given.
  • the voltage at one end of the two-port network can be v 1 and the current is i 1
  • the voltage at the other port is v 2 and the current is
  • the directions of i 2 , current i 1 and current i 2 refer to (c) in FIG. 1 .
  • the two-port network can be described by different parameters, for example, the two-port network can be described by Z parameters, Y parameters or A parameters.
  • the Z parameter matrix ie impedance matrix
  • the Y parameter matrix that is, the admittance matrix
  • the A parameter matrix that is, the above-mentioned ABCD transfer matrix
  • the element S 11 of the S parameter matrix represents the forward reflection coefficient, which can reflect the matching situation of the input end
  • S 22 represents the reverse reflection coefficient, which can reflect the matching situation of the output end
  • S 21 represents the forward power transfer coefficient, which can reflect the gain or Attenuation
  • S 12 represents the reverse power transmission coefficient, which is used to reflect the isolation.
  • the insertion loss of the two-port network can be calculated by the following formula (1).
  • IL represents insertion loss
  • S 21 is an element in the above S parameter matrix.
  • the port matching condition of the two-port network is: 20log
  • the insertion loss of the two-port network that is, the attenuation value, can be calculated according to formula (1).
  • the attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application can be equivalent to a two-port network.
  • the two-port network can be represented by the above-mentioned A parameter, Z parameter or Y parameter, and then the The insertion loss of the attenuation adjustable circuit can be obtained by converting the A parameter, Z parameter or Y parameter into an S parameter.
  • the ABCD transfer matrix, Z parameter matrix, and Y parameter matrix of the circuit all have a direct relationship with the values of resistance, inductance, conductance, and capacitance in the RLGC model circuit.
  • the tuning circuit can adjust the attenuation value of the circuit by adjusting the value of one or more components of the circuit.
  • SerDes The abbreviation of serializer/deserializer, using SerDes for signal transmission is a mainstream time division multiplexing (TDM), point-to-point (P2P) serial communication technology. Convert multiple low-speed parallel signals into high-speed serial signals at the sending end, pass through the transmission medium (optical cable or copper wire, etc.), and finally convert the high-speed serial signals into low-speed parallel signals at the receiving end.
  • TDM time division multiplexing
  • P2P point-to-point serial communication technology
  • This point-to-point serial communication technology can make full use of the channel capacity of the transmission medium, reduce the number of required transmission channels and device pins, and increase the transmission speed of signals, thereby significantly reducing communication costs.
  • the path that the signal passes from the sending end to the receiving end is called a channel (channel), which can also be called a SerDes channel.
  • the SerDes channel can include PCB traces. Vias, cables, connectors and other components.
  • testing the SerDes refers to testing the attenuation performance of the SerDes, that is, testing the attenuation caused by the signal during signal transmission through the SerDes. For example, test the limit attenuation value that the SerDes can achieve, etc.
  • the test object is usually a single board to be tested, and the single board to be tested includes some devices such as chips.
  • the single board to be tested includes a switching chip, and the switching chip includes one or more SerDes, and (a) in Figure 2 takes the switching chip including one SerDes as an example for illustration,
  • the test board (the test board includes a test chip for simulating the SerDes channel) is docked with the single board to be tested, wherein, for each SerDes, in the single board to be tested , also includes components such as PCB transmission lines and connectors connecting the SerDes and the test board, and the test board also includes connectors, PCB transmission lines, etc.
  • components such as PCB transmission lines and connectors connecting the SerDes and the test chip are also part of the SerDes channel, which will also cause signal attenuation during the signal transmission process; and the packaging and routing of the test chip in the test board will also causing signal attenuation.
  • the board to be tested includes multiple SerDes, for different SerDes on the board to be tested, the components connected to the SerDes and the test board may be different, or the length of the PCB transmission line may be different, etc., so that different SerDes may affect the signal The degree of attenuation varies.
  • the attenuation caused to the signal in the SerDes channel can include two parts: the first part of the attenuation is the connection between the SerDes and the test chip
  • the attenuation value corresponding to the above-mentioned first part of attenuation is usually fixed; the attenuation caused by the above-mentioned test chip can include two aspects, the first aspect is the attenuation caused by the test circuit in the test chip, and the second aspect is the test circuit in the test chip.
  • the attenuation caused by packaging (wiring), that is, the attenuation of the package, (b) in Figure 2 shows the attenuation of the package.
  • the attenuation value caused by the test chip itself to the channel is also fixed, that is, the attenuation value cannot be adjusted. .
  • the same test board that is, the normalized loopback winding board
  • the maximum applied stress requirement of the channel i.e. the applicability of the test board is lower.
  • the embodiment of the present application provides an attenuation adjustable circuit and chip based on the RLGC circuit model.
  • the switch capacitor array in the attenuation adjustable circuit can adjust the attenuation value of the attenuation adjustable circuit within a certain attenuation range.
  • the adjustable attenuation circuit can be used to simulate SerDes channels with different attenuation values, and has good applicability.
  • the input end of the adjustable attenuation circuit is connected to the output end of the serializer, that is, the serializer will serialize multiple
  • the output parallel signal is input to the attenuation adjustable circuit
  • the output end of the attenuation adjustable circuit is connected to the deserializer, that is, the parallel signal output by the attenuation adjustable circuit is input to the input end of the deserializer,
  • the deserializer converts the parallel signal into multiple serial signals.
  • the embodiment of the present application provides an adjustable attenuation circuit based on the RLGC circuit model, including: a switched capacitor array circuit 31 , a first impedance circuit 32 , and a second impedance circuit 33 .
  • the input end 321 of the first impedance circuit 32 is coupled to the input end of the attenuation adjustable circuit
  • the output end of the first impedance circuit 32 is connected to the input end 331 of the second impedance circuit 33
  • the output end 332 of the second impedance circuit 33 is coupled To the output end of the attenuation adjustable circuit
  • the output end 322 of the first impedance circuit 32 and the input end 331 of the second impedance circuit 33 are respectively connected to the first end 311 of the switched capacitor array circuit 31, and the second end of the switched capacitor array circuit 31 312 is grounded.
  • the first impedance circuit 32 and the second impedance circuit 33 include inductance elements and resistance elements
  • the switched capacitor array circuit 31 includes capacitance elements and switch elements.
  • the above switched capacitor array circuit 31 is used to adjust the attenuation value of the attenuation adjustable circuit within the first attenuation range.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of this application can be equivalent to a two-port network, and the attenuation adjustable circuit can be calculated based on the method for calculating insertion loss in the two-port network described in the above embodiment
  • the insertion loss of the attenuation adjustable circuit is the attenuation value of the attenuation adjustable circuit.
  • the attenuation value of the circuit can be adjusted by controlling the switched capacitor array of the attenuation adjustable circuit. Since the attenuation value of the attenuation adjustable circuit can be adjusted within the first attenuation range, the attenuation The adjustable circuit can simulate transmission channels with different attenuation values within the first attenuation range, and has good applicability.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application can be used to simulate SerDes channels with different attenuation ranges, there is no need to design or develop a test tool board for each SerDes channel, Can greatly save costs.
  • the above-mentioned switched capacitor array circuit is specifically used to adjust the attenuation value of the adjustable attenuation circuit within the first attenuation range by adjusting the capacitance value and conductance value of the adjustable attenuation circuit.
  • the attenuation value of the circuit can be adjusted by adjusting various parameters in the circuit, such as at least one of the resistance value, inductance value, conductance value or capacitance value, provided in the embodiment of the present application
  • the attenuation value of the attenuation adjustable circuit is adjusted by adjusting the capacitance value and the conductance value in the attenuation adjustable circuit.
  • the conductance value can also be ignored because the conductance value is usually small and has little influence on the attenuation value of the circuit.
  • the switched capacitor array circuit 31 is composed of N switched capacitor modules formed by N capacitive elements and N switching elements connected in parallel.
  • the first end of the i-th switched capacitor module 31-i is coupled to the first end 311 of the switched capacitor array circuit 31, and the second end of the i-th switched capacitor module is coupled to the second end 312 of the switched capacitor array circuit 31 ;
  • N is a positive integer greater than or equal to 2, i is any one of 1, 2, ..., N.
  • the i-th capacitive element among the above-mentioned N capacitive elements is connected in series with the i-th switching element among the N switching elements to form the i-th switched capacitor module of the switched capacitor array circuit 31, which can
  • the N capacitive elements are capacitors.
  • the above N switch elements are used to control one or more of the N capacitive elements to be connected to or not connected to the attenuation adjustment circuit, so as to adjust the capacitance value and conductance value of the attenuation adjustable circuit.
  • the N switching elements in FIG. 5 above are N transistors, and the drain of the i-th transistor M'1 among the N transistors is connected to the first end, the source of the i-th transistor is coupled to the second end of the i-th switched capacitor module 31-i, the gate of the i-th transistor is connected to the signal controller, and the second end of the i-th capacitor is coupled to the switched capacitor The first end of the module 31-i.
  • the gate of the i-th transistor M'i among the above-mentioned N transistors is connected to the output terminal SCi of the signal controller, and the control signal output through the output terminal SCi of the signal controller is used to control the i-th transistor M'i It is turned on or off, so as to control whether the i-th capacitor C'i is connected to the circuit or not connected to the circuit.
  • the i-th transistor M'i when the level of the output terminal SCi of the signal controller is high level, the i-th transistor M'i is turned on, and the i-th capacitor C'i is connected to the circuit; when the level of the output terminal SCi of the signal controller is When the level is low, the i-th transistor M'i is turned off, and the i-th capacitor C'i is not connected to the circuit.
  • the above-mentioned first impedance circuit 32 includes a first resistance element R1 and a first inductance element L1, and the first resistance element R1 and the first inductance element L1 are connected in parallel.
  • the first end of the first resistance element R1 and the first end of the first inductance element L1 are coupled to the input end 321 of the first impedance circuit 32, the second end of the first resistance element R1 and the first end of the first inductance element L1
  • the two terminals are coupled to the output terminal 321 of the first impedance circuit 32 .
  • the above-mentioned second impedance circuit 33 includes a second resistance element R2 and a second inductance element L2, and the second resistance element R1 and the second inductance element L2 are connected in parallel.
  • the first end of the second resistance element R2 and the first end of the second inductance element L2 are coupled to the input end 331 of the second impedance circuit 33, the second end of the second resistance element R2 and the first end of the second inductance element L2
  • the two terminals are coupled to the output terminal 332 of the second impedance circuit 33 .
  • the output levels of the output terminal SC1 to the output terminal SCN of the signal controller are not limited, and the levels of the output terminal SC1 to the output terminal SCN are specifically controlled according to actual needs. It can be seen that the functions of the output terminal SC1 to the output terminal SCN are similar to switches.
  • the transistors M'1 to M'N are controlled to be turned on or off, so that the capacitor C '1 to C'N are connected to the circuit, or not connected to the circuit, and the attenuation value of the attenuation adjustable circuit is adjusted by controlling the number of capacitors connected to the circuit among the capacitors C'1 to C'N.
  • transistors M'1 to M'N are equivalent to switches, and when the transistors
  • each transistor has a certain turn-on circuit, so the attenuation adjustable circuit shown in Figure 7 can be equivalent to the circuit shown in Figure 8, in
  • R'on1 to R'onN are the on-resistances of transistors M'1 to M'N respectively
  • C'1 to C'N are the capacitance values of capacitors C'1 to C'N respectively
  • L 1 is the inductance value of the first inductor L1
  • L2 is the inductance value of the second inductor L2
  • R1 is the resistance value of the first resistor
  • R2 is the resistance value of the second resistor.
  • the equivalent circuit of the attenuation adjustable circuit shown in Figure 8 is a two-port network, by controlling the states of the switches SC1 and SCN to be different states, the attenuation value of the circuit in the first attenuation range Make adjustments.
  • the switches SC1 to SCN closed as an example, the calculation process of the attenuation value of the equivalent circuit shown in FIG. 8 is introduced below.
  • the above-mentioned ABCD transition matrix is normalized and transformed into an S parameter matrix.
  • the conversion formula between the normalized ABCD transfer matrix and the S parameter matrix is as follows:
  • the insertion loss of the equivalent circuit shown in FIG. 8 can be calculated by using the above formula (1), so as to obtain the attenuation value of the attenuation adjustable circuit.
  • the attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application further includes a first attenuation adjustment circuit 34 , and the input of the first attenuation adjustment circuit 34
  • the terminal 341 is coupled to the input terminal of the adjustable attenuation circuit
  • the output terminal 342 of the first attenuation adjusting circuit 34 is coupled to the output terminal of the adjustable attenuation circuit.
  • the first attenuation adjustment circuit 34 includes an inductance element and a switch element.
  • the first attenuation adjustment circuit 34 and the switched capacitor array circuit 31 are used to adjust the attenuation value of the attenuation adjustable circuit within the second attenuation range.
  • the first attenuation adjustment circuit 34 is used to adjust the inductance and resistance of the attenuation adjustable circuit
  • the switched capacitor array circuit 31 is used to adjust the capacitance and conductance of the attenuation adjustable circuit.
  • the attenuation value of the adjustable attenuation circuit is adjusted by adjusting the inductance value, resistance value, capacitance value and conductance value of the attenuation adjustable circuit.
  • the first attenuation adjustment circuit 34 includes a third inductance element L3 , a first switching element S1 and a second switching element S2 .
  • the first switch element S1, the third inductance element L3 and the second switch element S2 are connected in series in sequence.
  • the first switch element S1 and the second switch element S2 are used to control the third inductance element L3 to connect to the adjustable attenuation circuit or not to connect to the adjustable attenuation circuit, so as to adjust the inductance and resistance of the adjustable attenuation circuit.
  • the above switching elements are transistors.
  • the first switching element S1 is a first transistor M1
  • the second switching element S2 is a second transistor M2.
  • the drain of the first transistor M1 is coupled to the input terminal 341 of the first attenuation adjustment circuit 34
  • the source of the first transistor M1 is connected to the first terminal of the third inductance element L3
  • the source of the second transistor M2 is connected to the third
  • the second end of the inductance element L3 and the drain of the second transistor M2 are coupled to the output end 342 of the first attenuation adjustment circuit 34 ;
  • the gates of the first transistor M1 and the second transistor M2 are connected to the signal controller.
  • first transistor M1 and the second transistor M2 are N-channel metal oxide semiconductor (metal oxide semiconductor, MOS) transistors with the same parameters.
  • MOS metal oxide semiconductor
  • the gate of the first transistor M1 and the gate of the second transistor M2 are connected to the output terminal SR2 of the signal controller, that is, the output signal of the output terminal SR2 of the signal controller is used to control the first transistor M1 and the second transistor M2 on or off.
  • the signal controller outputs a high level to the output terminal SR2, both the first transistor M1 and the ninth transistor M2 are turned on; when the signal controller outputs a low level to the output terminal SR2, the first transistor M1 and the second transistor M2 are both turned on. due.
  • the functions of the output terminal SC1 to the output terminal SCN of the signal controller are similar to switches, and the level of the output terminal SC1 to the output terminal SCN of the signal controller is controlled by the signal controller to control the transistor M '1 to M'N is turned on or off, so that capacitors C'1 to C'N are connected to the circuit, or not connected to the circuit, by controlling the number of capacitors connected to the circuit in the capacitors C'1 to C'N, the attenuation The attenuation value of the adjustable circuit can be adjusted.
  • the output levels of the output terminal SC1 to the output terminal SCN of the signal controller are not limited, and the levels of the output terminal SC1 to the output terminal SCN are specifically controlled according to actual needs.
  • the above-mentioned first transistor M1, second transistor M2, and transistors M'1 to M'N are equivalent to switches, and when the above-mentioned first transistor M1 and second transistor M2 are turned on, the transistor M' Each transistor has a certain on-resistance when one or more of 1 to M'N is on.
  • the adjustable attenuation circuit shown in FIG. 11 can be equivalent to the circuit shown in FIG. 12 .
  • R'on1 to R'onN are the on-resistances of transistors M'1 to M'N respectively
  • C' 1 to C'N are the capacitance values of capacitors C'1 to C'N respectively
  • L 1 is the inductance value of the first inductor L1
  • L 2 is the inductance value of the second inductor L2
  • R 1 is the resistance value of the first resistor
  • R 2 is the resistance value of the second resistor
  • R on1 and R on2 are the first
  • L3 is the inductance value of the third inductor L3.
  • the equivalent circuit shown in Figure 12 is also a two-port network.
  • the attenuation can be adjusted within the second attenuation range.
  • the attenuation value of the circuit Taking the switches SC1 to SCN all closed as an example, the calculation process of the attenuation value of the equivalent circuit shown in FIG. 12 is introduced below.
  • the parameter matrix of the equivalent circuit shown in FIG. 12 is determined. It should be understood that in FIG. 12 , the first attenuation adjustment circuit 34 is connected in parallel with both ends of the original attenuation adjustable circuit (ie, the attenuation adjustable circuit shown in FIG. 7 ).
  • the adjustable attenuation circuit shown in FIG. 7 is collectively referred to as a third attenuation adjustment circuit.
  • the Z parameter matrix of the equivalent circuit is the sum of the Z parameter matrix corresponding to the first attenuation adjustment circuit 34 and the Z parameter matrix corresponding to the third attenuation adjustment circuit.
  • the Z parameter matrix is
  • the insertion loss of the equivalent circuit shown in FIG. 12 can be calculated by using the above formula (1), so as to obtain the attenuation value of the adjustable attenuation circuit.
  • the first attenuation adjustment circuit 34 further includes a third transistor M3 and a fourth transistor M4 .
  • the drain of the third transistor M3 is connected to the source of the first transistor
  • the drain of the fourth transistor M4 is connected to the source of the second transistor M2
  • the source of the third transistor M3 and the source of the fourth transistor M4 are both grounded
  • the gate of the third transistor M3 and the gate of the fourth transistor M4 are both connected to the signal controller.
  • the level input to the gate of the third transistor M3 through the signal controller is opposite to the level input to the gate of the first transistor M1, and the level input to the gate of the fourth transistor M4 through the signal controller The level is opposite to the level input to the gate of the second transistor M2.
  • the third transistor M3 and the fourth transistor M4 are used to conduct the AC voltage of the first attenuation adjustment circuit 34 to ground when the first attenuation adjustment circuit 34 is not connected to the attenuation adjustable circuit.
  • the first transistor M1 and the first transistor M1 when the level input by the signal controller to the first attenuation adjustment circuit 34 through its output terminal SR2 is a low level, that is, when the first attenuation adjustment circuit 34 is in a non-operating state, the first transistor M1 and the first transistor M1
  • the second transistor M2 has an AC voltage (at this moment, the first transistor M1 and the second transistor M2 are equivalent to a large capacitance), and at this moment, because the grid input of the third transistor M3 and the fourth transistor M4 is a high level, therefore , the third transistor M3 and the fourth transistor M4 can conduct the AC voltage to the ground, so that the output terminal of the first attenuation adjustment circuit 34 does not output a signal, so that the first attenuation adjustment circuit 34 does not interfere with the output of the third attenuation adjustment circuit Signal.
  • the function of the third transistor M3 and the fourth transistor M4 is to improve the isolation of the first attenuation adjustment circuit 34 .
  • the third transistor M3 and the fourth transistor M4 may be N-channel MOS transistors with the same parameters.
  • the gates of the third transistor M3 and the fourth transistor M4 are coupled together and connected to the output terminal SK2 of the signal controller, or connected to the above-mentioned SR2 through an inverter, the output terminal of the inverter is SR2B, and the level of the output terminal SR2B It is opposite to the level of the output terminal SR2.
  • the attenuation adjustable circuit based on the RLGC circuit model provided by the embodiment of the present application further includes a second attenuation adjustment circuit 35, and the input of the second attenuation adjustment circuit 35 Terminal 351 is coupled to the input terminal of the adjustable attenuation circuit, and the output terminal 352 of the second attenuation adjustment circuit 35 is coupled to the output end of the attenuation adjustable circuit; the second attenuation adjustment circuit 35 includes an inductance element, a capacitance element and a switch element.
  • the second attenuation adjustment circuit 35 and the switched capacitor array circuit 31 are used to adjust the attenuation value of the attenuation adjustable circuit within the third attenuation range.
  • the second attenuation adjustment circuit 35 is used to adjust the inductance value and resistance value of the attenuation adjustable circuit, or adjust the inductance value, resistance value, capacitance value and conductance value of the attenuation adjustable circuit;
  • the switched capacitor array circuit is used to adjust Capacitance and conductance values of the attenuation adjustable circuit.
  • the second attenuation adjustment circuit 35 includes an inductance element, a capacitance element, and a switch element, it is possible to control whether the inductance element and the capacitance element are connected through the switch element. Attenuation adjustable circuit, thereby adjusting the inductance value and resistance value of the circuit, or adjusting the inductance value, resistance value, capacitance value and conductance value of the circuit.
  • the resistance value and the conductance value are usually small and have little influence on the attenuation value of the circuit, the resistance value and the conductance value can also be ignored.
  • the second attenuation adjustment circuit 35 includes a fourth inductance element L4 , a third switch element S3 , a fourth switch element S4 , a first switched capacitor module CS1 and a second switched capacitor module CS2 .
  • the first end of the third switching element S3 is coupled to the input end of the attenuation adjustable circuit, and the second end of the third switching element S3 is connected to the first end of the fourth inductance element L4 and the first end of the first switched capacitor module CS1.
  • the second end of the first switched capacitor module CS1 is grounded; the first end of the fourth switch element S4 is coupled to the output end of the attenuation adjustable circuit, and the second end of the fourth switch element S4 is connected to the first end of the fourth inductance element L4 Two terminals and the first terminal of the second switched capacitor module CS1, and the second terminal of the second switched capacitor module CS1 are grounded.
  • the third switch element S3 and the fourth switch element S4 are used to control the fourth inductance element L4 to connect to the adjustable attenuation circuit or not to connect to the adjustable attenuation circuit, so as to adjust the inductance and resistance of the adjustable attenuation circuit.
  • the above-mentioned first switched capacitor module CS1 is formed by connecting the first capacitor element C1 and the fifth switch element S5 in series
  • the second switched capacitor module CS2 is formed by the second capacitor element C2 and the sixth switch element S6. formed in series.
  • the fifth switch element S5 is used to control whether the first capacitive element C1 is connected to or not connected to the attenuation adjustment circuit, so as to adjust the capacitance value and conductance value of the attenuation adjustable circuit
  • the sixth switch element S6 is used to control the second The capacitive element 2 is connected or not connected to the attenuation adjustment circuit to adjust the capacitance value and conductance value of the attenuation adjustable circuit.
  • third switch element S3, fourth switch element S4, fifth switch element S5, and sixth switch element S6 can cooperate with each other to adjust the inductance value, resistance value, capacitance value and conductance value of the attenuation adjustable circuit. .
  • the fifth switching element S5 and the sixth switching element S6 are transistors, and the fifth switching element S5 is a fifth transistor M5, and the sixth switching element S6 is a sixth transistor M6; the third The switching element S3 and the fourth switching element S4 are transistors, and the third switching element is a seventh transistor M7, and the fourth switching element is an eighth transistor M8.
  • the drain of the seventh transistor M7 is coupled to the input terminal 351 of the second attenuation adjustment circuit 35, the source of the seventh transistor M7 is connected to the first end of the fourth inductance element L4; the second end of the fourth inductance element L4 is connected to The source and drain of the eighth transistor M8 are coupled to the output terminal 352 of the second attenuation adjustment circuit 35; the gates of the seventh transistor M7 and the eighth transistor M98 are connected to the signal controller.
  • the drain of the fifth transistor M5 is connected to the first end of the first capacitive element C1, the second end of the first capacitive element C1 is connected to the source of the seventh transistor M7, and the drain of the sixth transistor M6 is connected to the second end of the second capacitive element C2.
  • the first end, the second end of the second capacitive element C2 is connected to the source of the eighth transistor M8, the source of the fifth transistor M5 and the source of the sixth transistor M6 are both grounded, and the gate of the fifth transistor M5 and the sixth transistor M5 are connected to the ground.
  • the gates of the transistor M6 are respectively connected to the signal controller.
  • the seventh transistor M7 and the eighth transistor M8 are N-channel MOS transistors with the same parameters.
  • the gates of the seventh transistor M7 and the eighth transistor M8 are connected to the output terminal SR1 of the signal controller, that is, the output signal of the output terminal SR1 of the signal controller is used to control the seventh transistor M7 and the eighth transistor M8 to turn on or due.
  • the signal controller outputs a high level to the output terminal SR1, both the seventh transistor M7 and the eighth transistor M8 are turned on; when the signal controller outputs a low level to the output terminal SR1, the seventh transistor M7 and the eighth transistor M8 are both turned on. due.
  • the first attenuation adjustment circuit 34 when the signal controller outputs a high level to the output terminal SR1 and outputs a low level to the output terminal SR2, the first attenuation adjustment circuit 34 is not connected to the attenuation adjustment circuit 34.
  • the attenuation adjustable circuit that is, the first attenuation adjustment circuit 34 is not working, and the second attenuation adjustment circuit 35 and the third attenuation adjustment circuit are in working state.
  • the circuit shown in FIG. 17 is equivalent to the circuit shown in FIG. 18 .
  • the functions of the output terminals SC1 to SCN of the signal controller are similar to switches.
  • the transistors M'1 to SCN are controlled.
  • M'N is turned on or off, so that capacitors C'1 to C'N are connected to the circuit, or not connected to the circuit, and the attenuation is adjustable by controlling the number of capacitors connected to the circuit in capacitors C'1 to C'N The attenuation value of the circuit is adjusted.
  • the output levels of the output terminal SC1 to the output terminal SCN of the signal controller are not limited, and the levels of the output terminal SC1 to the output terminal SCN are specifically controlled according to actual needs.
  • the function of the output end SW1 and the output end SW2 of the signal controller is similar to a switch, and by controlling the levels of the output end SW1 and the output end SW2 of the signal controller, the fifth transistor M5 and the sixth transistor M6 are controlled to be turned on or Cut off, so that the first capacitor C1 and the second capacitor C2 are connected to the circuit, or not connected to the circuit, so as to adjust the attenuation value of the attenuation adjustable circuit.
  • R'on1 to R'onN are the on-resistances of transistors M'1 to M'N respectively
  • C'1 to C'N are the capacitance values of capacitors C'1 to C'N respectively
  • L 1 is the inductance value of the first inductor L1
  • L2 is the inductance value of the second inductor L2
  • R1 is the resistance of the first resistor
  • R2 is the resistance value of the second resistor.
  • R on7 is the on-resistance of the seventh transistor M7
  • R on8 is the on-resistance of the eighth transistor M8
  • L4 is the inductance value of the fourth inductor L4
  • R on5 is the on-resistance of the fifth transistor M5
  • R on6 is For the on-resistance of the sixth transistor M6, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.
  • the equivalent circuit shown in FIG. 18 is also a two-port network.
  • the attenuation value of the circuit is adjusted within the third attenuation range.
  • the calculation process of the attenuation value of the equivalent circuit shown in FIG. 18 is introduced below.
  • the parameter matrix of the equivalent circuit shown in FIG. 18 is determined. It should be understood that in FIG. 18 , the second attenuation adjustment circuit 35 and the third attenuation adjustment circuit are connected in parallel, and the ABCD transfer matrices corresponding to the second attenuation adjustment circuit 35 and the third attenuation adjustment circuit are respectively determined first, and the representation process is as follows:
  • the Z parameter matrix is
  • the insertion loss of the equivalent circuit shown in FIG. 18 can be calculated by using the above formula (1), so as to obtain the attenuation value of the attenuation adjustable circuit.
  • the above-mentioned second attenuation adjustment circuit 35 further includes a ninth transistor M9, the source of the ninth transistor M9 is grounded, and the drain of the ninth transistor M9 is connected to the fourth inductance element L4. Two terminals, the gate of the ninth transistor M9 is connected to the signal controller. It should be noted that the level input to the gate of the ninth transistor M9 through the signal controller is opposite to the level input to the gate of the eighth transistor.
  • the ninth transistor M9 is configured to conduct the AC voltage of the second attenuation adjustment circuit 35 to ground when the second attenuation adjustment circuit 35 is not connected to the attenuation adjustable circuit.
  • the seventh transistor M7 in the second attenuation adjustment circuit 35 and the The eighth transistor M8 has an AC voltage (at this time, the seventh transistor M7 and the eighth transistor M8 are equivalent to a large capacitance), and since the gate input of the ninth transistor M9 is a high level, the ninth transistor M9 can The AC voltage is grounded so that the output terminal of the second attenuation adjustment circuit 35 does not output a signal, that is, the second attenuation adjustment circuit 35 does not interfere with the output signals of other attenuation adjustment circuits.
  • the function of the ninth transistor M9 is to increase the isolation of the second attenuation adjustment circuit 35 .
  • the gate of the ninth transistor M9 can be connected to the output terminal SK1 of the signal controller, or connected to the above-mentioned SR1 through an inverter, the output terminal of the inverter is SR1B, and the level of the output terminal SR1B is the same as that of the output terminal SR1 level is opposite.
  • the adjustable attenuation circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a seventh switching element S7 and an eighth switching element S8 .
  • the seventh switch element and the eighth switch element are used to control whether the second attenuation adjustment circuit 35 works independently.
  • the seventh switch element S7 and the eighth switch element S8 are not turned on, only the second attenuation adjustment circuit 35 is included in the attenuation adjustable circuit, and the second attenuation adjustment circuit 35 works independently.
  • the second attenuation adjustment circuit 35 is configured to adjust the attenuation value of the attenuation adjustable circuit within the fourth attenuation range.
  • the seventh switch element S7 and the eighth switch element S8 are not turned on, the above-mentioned first attenuation adjustment circuit 34 and the third attenuation adjustment circuit are both in a non-working state, and the second attenuation adjustment circuit 35 works independently.
  • the second attenuation adjustment circuit 35 is also a RLGC circuit model, which can be used to simulate the SerDes channel in the first attenuation range.
  • the seventh switch element S7 and the eighth switch element S8 are transistors, and the seventh switch element S7 is the tenth transistor M10, and the eighth switch element S8 is the eleventh transistor M10. Transistor M11.
  • the drain of the tenth transistor M10 is coupled to the input end of the attenuation adjustable circuit
  • the source of the tenth transistor M10 is coupled to the input end 321 of the first impedance circuit 32 and the input end 341 of the first attenuation adjustment circuit 34
  • the first The drain of the eleventh transistor M11 is coupled to the output end of the attenuation adjustable circuit
  • the source of the eleventh transistor M11 is coupled to the output end 331 of the second impedance circuit 33 and the output end 342 of the first attenuation adjustment circuit 34
  • the gate of the transistor M10 and the gate of the eleventh transistor M11 are connected to the signal controller.
  • the gate of the tenth transistor M10 and the gate of the eleventh transistor M11 are connected to the output terminal SR3 of the signal controller, that is, the output signal of the output terminal SR3 of the signal controller is used to control the gate of the tenth transistor M10 and the gate of the eleventh transistor M11.
  • the eleventh transistor M11 is turned on or off. When the signal controller outputs a high level to the output terminal SR3, both the gate of the tenth transistor M10 and the eleventh transistor M11 are turned on; when the signal controller outputs a low level to the output terminal SR3, the gate of the tenth transistor M10 Both the gate and the eleventh transistor M11 are turned off.
  • the first attenuation adjustment circuit 34 and the second attenuation adjustment circuit 34 when the signal controller outputs a low level to the output terminal SR3 and a high level to the output terminal SR1, the first attenuation adjustment circuit 34 and the second attenuation adjustment circuit 34
  • the three attenuation adjustment circuits are not connected to the attenuation adjustable circuit, that is, the first attenuation adjustment circuit 34 and the third attenuation adjustment circuit are in the non-working state, and the second attenuation adjustment circuit 35 and the third attenuation adjustment circuit are in the working state, as shown in Figure 21
  • the circuit shown is equivalent to the circuit shown in Figure 22.
  • the function of the output end SW1 and the output end SW2 of the above-mentioned signal controller is similar to a switch, and the level of the output end SW1 and the output end SW2 of the signal controller is controlled by the signal controller, so that the first capacitor C1 and /Or the second capacitor C2 is connected to the circuit, or not connected to the circuit, so as to adjust the attenuation value of the attenuation adjustable circuit.
  • the output levels of the output terminal SW1 and the output terminal SW2 of the signal controller are not limited, and the levels of the output terminal SW1 and the output terminal SW2 are specifically controlled according to actual needs.
  • R on7 is the on-resistance of the seventh transistor M7
  • R on8 is the on-resistance of the eighth transistor M8
  • L4 is the inductance value of the fourth inductor L4
  • R on5 is the on-resistance of the fifth transistor M5.
  • the resistor, R on6 is the on-resistance of the sixth transistor M6, C 1 is the capacitance of the first capacitor C1, and C 2 is the capacitance of the second capacitor C2.
  • the equivalent circuit shown in FIG. 22 is a two-port network, wherein the states of switches SW1 and SW2 can be different states, for example, both SW1 and SW2 are open, or SW1 is closed and SW2 is open, or SW1 is open and SW2 is closed, Or both SW1 and SW2 are closed.
  • the attenuation value of the circuit is adjusted within the fourth attenuation range.
  • the switches SW1 and SW2 both closed as an example, the following describes the calculation process of the attenuation value of the equivalent circuit shown in FIG. 22 .
  • the insertion loss of the equivalent circuit shown in FIG. 22 can be calculated by using the above formula (1), so as to obtain the attenuation value of the attenuation adjustable circuit.
  • the first attenuation range, the second attenuation range, the third attenuation range, and the fourth attenuation range are different, and the corresponding attenuation ranges decrease sequentially, and the corresponding attenuation values decrease sequentially.
  • the first attenuation range may be above 10 decibels (dB)
  • the second attenuation range may be 5-10 dB
  • the third attenuation range may be 3-5 dB
  • the fourth attenuation range may be 2-3 dB.
  • the above-mentioned first attenuation range is a high attenuation range
  • the second attenuation range is a higher attenuation range
  • the third attenuation range is a medium attenuation range
  • the fourth attenuation range is a low attenuation range.
  • the attenuation adjustable circuit based on the RLGC circuit model provided in the embodiment of the present application can simulate SerDes channels with different attenuation ranges.
  • the first attenuation range corresponds to the first SerDes channel in the high attenuation range
  • the second attenuation range corresponds to the second SerDes channel in the higher attenuation range
  • the third attenuation range corresponds to the third SerDes channel in the medium attenuation range
  • the fourth attenuation range corresponds to Fourth SerDes channel for low attenuation range.
  • the adjustable attenuation circuit based on the RLGC circuit model provided in the embodiment of the present application further includes a twelfth transistor M12 and a thirteenth transistor M13 .
  • the drain of the twelfth transistor M12 is coupled to the input terminal 321 of the first impedance circuit 32
  • the drain of the thirteenth transistor M13 is coupled to the output terminal 332 of the second impedance circuit 33
  • the source of the twelfth transistor M12 Both the sources of the thirteenth transistor M13 and the twelfth transistor M13 are grounded; the gates of the twelfth transistor M12 and the thirteenth transistor M12 are both connected to the signal controller.
  • the level input to the gate of the twelfth transistor M12 through the signal controller is opposite to the level input to the gate of the tenth transistor M10, and the level input to the gate of the thirteenth transistor M13 through the signal controller The input level is opposite to the level input to the gate of the eleventh transistor M11.
  • the twelfth transistor M12 and the thirteenth transistor M13 are used to conduct the AC voltage of the attenuation adjustable circuit to ground when the second attenuation adjustment circuit 35 works independently.
  • the tenth transistor M10 and the eleventh transistor M11 when the output level of the output terminal SR3 of the signal controller is low level, that is, when the third attenuation adjustment circuit is in a non-working state, the tenth transistor M10 and the eleventh transistor M11 have AC voltage (at this time , the tenth transistor M10 and the eleventh transistor M11 have AC voltage equivalent to a large capacitance), since the gate input of the twelfth transistor M12 and the thirteenth transistor M13 is a high level, therefore, the twelfth transistor M12 and the thirteenth transistor M13 can conduct the AC voltage to the ground, so that the output terminal of the third attenuation adjustment circuit does not output a signal, that is, the third attenuation adjustment circuit does not interfere with other attenuation adjustment circuits (the first attenuation adjustment circuit 34). output signal.
  • the function of the twelfth transistor M12 and the thirteenth transistor M13 is to improve the isolation of the third attenuation adjustment circuit.
  • the twelfth transistor M12 and the thirteenth transistor M13 may be N-channel MOS transistors with the same parameters.
  • the gate of the twelfth transistor M12 and the gate of the thirteenth transistor M13 are coupled together and connected to the output terminal SK3 of the signal controller, or connected to the above-mentioned SR3 through an inverter, the output terminal of the inverter is SR3B, and the output The level of the terminal SR3B is opposite to the level of the output terminal SR3.
  • the signal controller is used to provide digital control signals to the adjustable attenuation circuit to control the operation of the first attenuation adjustment circuit, the second attenuation adjustment circuit and the third attenuation adjustment circuit.
  • the working state of the attenuation adjustment circuit includes working state or non-working state.
  • the attenuation adjustable circuit can simulate SerDes channels with different attenuation ranges .
  • Table 1 below is an example of the corresponding relationship between the working status of each attenuation adjustment circuit and the applicable SerDes channel.
  • SerDes channel The first attenuation adjustment circuit Second attenuation adjustment circuit
  • the third attenuation adjustment circuit First SerDes channel non-working state non-working state working state Second SerDes channel non-working state working state working state Third SerDes channel working state non-working state working state Fourth SerDes channel working state non-working state non-working state
  • the attenuation ranges of the first SerDes channel, the second SerDes channel, the third SerDes channel, and the fourth SerDes channel decrease sequentially.
  • the adjustable attenuation circuit based on the RLGC circuit model provided by the embodiment of the present application can adjust the adjustable attenuation circuit according to the demand for the attenuation value in practical applications, so that the attenuation value can reach the expected value.
  • the SerDes channel can simulate the SerDes channel with different attenuation ranges by controlling the working state of each adjustment circuit in the attenuation adjustable circuit, and the attenuation adjustable circuit has good applicability.
  • the embodiment of the present application also provides an adjustable attenuation chip, which can include multiple RLGC-based circuits as described in the above embodiments
  • the attenuation adjustable circuit of the model wherein, the plurality of attenuation adjustable circuits are divided into multiple groups of attenuation adjustable circuits, and the multiple groups of attenuation adjustable circuits are symmetrically arranged.
  • the adjustable attenuation chip provided by the embodiment of the present application further includes a signal controller, and each adjustable attenuation circuit in the above-mentioned plurality of adjustable attenuation circuits is connected to the The signal controller is connected, and the signal controller is used to provide digital control signals for the multiple attenuation adjustable circuits, so as to control the working states of the multiple attenuation adjustable circuits, and adjust the attenuation value of the attenuation adjustable circuits.
  • the signal controller controls different output terminals (such as SR1, SR2, SR3) of the signal controller through different communication protocols (such as but not limited to IIC and other communication protocols) to provide digital control signals for the attenuation adjustable circuit, so that Each attenuation adjustment circuit in the above-mentioned attenuation adjustable circuit is in the working state or inactive state, and the attenuation value of the attenuation adjustable circuit is adjusted through different output terminals (such as SW1, SW2, SC1 to SCN).
  • different output terminals such as SW1, SW2, SC1 to SCN.
  • the adjustable attenuation chip provided in the embodiment of the present application is a multi-channel adjustable attenuation chip.
  • the number of adjustable attenuation circuits in the adjustable attenuation chip can be set according to actual needs, and is not specifically limited in the embodiment of the present application.
  • the number of adjustable attenuation circuits is M, and M is a positive integer greater than or equal to 2.
  • the adjustable attenuation chip may be a 24-channel chip, that is, the adjustable attenuation chip includes 24 adjustable attenuation circuits as shown in FIG. 23 .
  • the attenuation adjustable chip provided by the embodiment of the present application can be applied to the scenario where multiple SerDes work in parallel, for example, the scenario where multiple SerDes channels transmit signals at the same time, and the above-mentioned signal controller outputs independent control signals to adjust the attenuation values of different SerDes channels respectively . It can be seen that each attenuation adjustable circuit in the attenuation adjustable chip can work independently without affecting each other, and the attenuation adjustable chip has high integration and small area.
  • the multiple adjustable attenuation circuits in the adjustable attenuation chip are divided into multiple groups of adjustable attenuation circuits, and the multiple groups of adjustable attenuation circuits symmetrically placed on the package substrate.
  • the attenuation adjustable chip includes 24 attenuation adjustable circuits, divide the 24 attenuation adjustable circuits into 4 groups on average, each group includes 6 attenuation adjustable circuits, and place the 4 groups of attenuation adjustable circuits symmetrically on the package substrate. Then, multiple groups of adjustable attenuation circuits are respectively wired to package the adjustable attenuation chip.
  • FIG. 26 shows a packaging effect diagram of an adjustable attenuation chip.
  • the above-mentioned packaging method for the adjustable attenuation chip is a miniaturized multi-DIE packaging technology, and each group of the above-mentioned adjustable attenuation circuits can be called a DIE.
  • This packaging method can not only reduce the packaging wiring
  • the length of the chip reduces the attenuation value (insertion loss) caused by the package wiring to the signal, and all the indicators of the attenuation adjustable chip are up to the standard, such as isolation and crosstalk, all meet the expected indicators.
  • the packaging method of the attenuation adjustable chip provided by the embodiment of the present application, the above-mentioned 24 attenuation can be included.
  • the attenuation adjustable chip of the tuning circuit is packaged.
  • the package area of the attenuation adjustable chip is 16 millimeters (mm) ⁇ 16mm.
  • the length of the longest trace in the package is less than 5mm, and the attenuation value of the package trace is less than 1dB.
  • the attenuation value of the entire attenuation adjustable chip after packaging is less than 3dB.
  • the impedance of the package wiring is 90 ohms, and the error is ⁇ 8%, the near-end crosstalk is less than -50dB, and the far-end crosstalk is less than -50dB.

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Abstract

一种基于RLGC电路模型的衰减可调电路及芯片，涉及电子技术领域，该衰减可调电路包括：开关电容阵列电路、第一阻抗电路以及第二阻抗电路；其中，第一阻抗电路的输入端耦合至衰减可调电路的输入端，第一阻抗电路的输出端连接第二阻抗电路的输入端，第二阻抗电路的输出端耦合至衰减可调电路的输出端，第一阻抗电路的输出端和第二阻抗电路的输入端分别连接开关电容阵列电路的第一端，开关电容阵列电路的第二端接地；第一阻抗电路和第二阻抗电路包括电感元件和电阻元件，开关电容阵列电路包括电容元件和开关元件。该开关电容阵列电路，用于在第一衰减范围内调节衰减可调电路的衰减值，该衰减可调电路能够满足不同的衰减需求，具有较好的适用性。

Description

基于RLGC电路模型的衰减可调电路及芯片
本申请要求于2021年05月21日提交国家知识产权局、申请号为202110560611.1、申请名称为“基于RLGC电路模型的衰减可调电路及芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电子技术领域，尤其涉及一种基于RLGC电路模型的衰减可调电路及芯片。
背景技术
串行器/解串器(serializer/deserializer，简称SerDes)是一种具有高速传输功能的接口器件，在发送端通过串行器将低速并行信号转换为高速串行信号，然后通过传输媒介(例如光缆或铜线等)将该串行信号传输至接收端，在接收端通过解串器将高速串行信号再转换为低速并行信号。
上述串行信号的传输媒介称为SerDes信道，目前，对SerDes进行测试的过程中，采用归一环回绕线板模拟SerDes信道，以测试SerDes的性能。
然而，对于多种相同类型的待测单板，每种待测单板中包括多个SerDes，对于相同位置的SerDes，各种待测单板的SerDes信道的长度可能不同，不同的SerDes信道使得信号的衰减程度可能不同，上述采用归一环回绕线板对SerDes信道进行模拟，该归一环回绕线板对SerDes信道的衰减模拟是固定的，因此，该归一环回绕线板不能适用于各种待测单板的SerDes信道的最大施加应力要求，采用归一环回绕线板对SerDes信道进行模拟，其适用性较差。
发明内容
本申请实施例提供一种基于RLGC电路模型的衰减可调电路及芯片，能够满足不同的衰减需求，具有较好的适用性。
为达到上述目的，本申请实施例采用如下技术方案：
第一方面，本申请实施例提供一种基于RLGC电路模型的衰减可调电路，包括：开关电容阵列电路、第一阻抗电路以及第二阻抗电路。其中，第一阻抗电路的输入端耦合至衰减可调电路的输入端，第一阻抗电路的输出端连接第二阻抗电路的输入端，第二阻抗电路的输出端耦合至衰减可调电路的输出端，第一阻抗电路的输出端和第二阻抗电路的输入端分别连接开关电容阵列电路的第一端，开关电容阵列电路的第二端接地。其中，第一阻抗电路和第二阻抗电路包括电感元件和电阻元件，开关电容阵列电路包括电容元件和开关元件。在该衰减可调电路中，开关电容阵列电路，用于在第一衰减范围内调节衰减可调电路的衰减值。
本申请实施例提供的基于RLGC电路模型的衰减可调电路，通过控制衰减可调电路的开关电容阵列，可以实现对该电路的衰减值的调节，由于该衰减可调电路的衰减值可以在第一衰减范围内进行调节，因此，在实际应用中可以根据对衰减值的需求调节衰减可调电路，使其衰减值达到预期的值，具有较好的适用性。
进一步的，由于本申请实施例提供的基于RLGC电路模型的衰减可调电路可以用于对不同衰减范围的SerDes信道进行模拟，因此无需针对每一种SerDes信道分别设计或开发一种测试工具板，能够极大地节约成本。
一种可能的实现方式中，上述开关电容阵列电路，具体用于通过调节衰减可调电路的电容值和电导值，在第一衰减范围内调节衰减可调电路的衰减值。
可以理解的是，在RLGC电路模型中，可以通过调节电路中的各个参数，例如电阻值、电感值、电导值或电容值中的至少一项来调节电路的衰减值，在本申请实施例提供的基于RLGC电路模型的衰减可调电路中，通过调整衰减可调电路中的电容值和电导值来调节衰减可调电路的衰减值。
一种可能的实现方式中，开关电容阵列电路由N个电容元件以及N个开关元件形成的N个开关电容模块并联组成，第i个开关电容模块的第一端耦合至开关电容阵列电路的第一端，第i个开关电容模块的第二端耦合至开关电容阵列电路的第二端；N为大于或等于2的正整数，i为1，2，……，N中的任意一个值。其中，N个电容元件中的第i个电容元件与N个开关元件中的第i个开关元件串联形成开关电容阵列电路的第i个开关电容模块。该N个开关元件，用于控制N个电容元件中的一个或多个电容元件接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值。
一种可能的实现方式中，上述N个开关元件为N个晶体管；N个晶体管中的第i个晶体管的漏极连接第i个电容元件的第一端，第i个晶体管的源极耦合至第i个开关电容模块的第二端，第i个晶体管的栅极连接信号控制器，第i个电容的第二端耦合至开关电容模块的第一端。
一种可能的实现方式中，上述第一阻抗电路包括第一电阻元件和第一电感元件，第一电阻元件和第一电感元件并联。其中，第一电阻元件的第一端和第一电感元件的第一端耦合至第一阻抗电路的输入端，第一电阻元件的第二端和第一电感元件的第二端耦合至第一阻抗电路的输出端。
一种可能的实现方式中，第二阻抗电路包括第二电阻元件和第二电感元件，第二电阻元件和第二电感元件并联。其中，第二电阻元件的第一端和第二电感元件的第一端耦合至第二阻抗电路的输入端，第二电阻元件的第二端和第二电感元件的第二端耦合至第二阻抗电路的输出端。
本申请实施例中，通过信号控制器控制N个晶体管导通或者截止，使得N个电容接入电路，或者不接入电路，通过控制接入电路的电容数量，从而在第一衰减范围内对衰减可调电路的衰减值进行调节。具体的，该衰减可调电路可以等效为一个二端口网络，计算二端口网络的S参数矩阵，根据S参数矩阵与电路的插入损耗之间的计算关系，得到衰减可调电路的插入损耗，该插入损耗即为衰减可调电路的衰减值。
一种可能的实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第一衰减调节电路，该第一衰减调节电路的输入端耦合至衰减可调电路的输入端，第一衰减调节电路的输出端耦合至衰减可调电路的输出端，第一衰减调节电路包括电感元件和开关元件。第一衰减调节电路和开关电容阵列电路，用于在第二衰减范围内调节衰减可调电路的衰减值；其中，第一衰减调节电路，用于调节衰减可调电路的电感值和电阻值，开关电容阵列电路，用于调节衰减可调电路的电容值和电导值。
一种可能的实现方式中，上述第一衰减调节电路包括第三电感元件、第一开关元件和第二开关元件，其中，第一开关元件、第三电感元件和第二开关元件依次串联。第一开关元件和第二开关元件，用于控制第三电感元件接入衰减可调电路或者不接入衰减可调电路，以调节该衰减可调电路的电感值和电阻值。
一种可能的实现方式中，上述开关元件为晶体管，且第一开关元件为第一晶体管，第二开关元件为第二晶体管。其中，第一晶体管的漏极耦合至第一衰减调节电路的输入端，第一晶体管的源极连接第三电感元件的第一端，第二晶体管的源极连接第三电感元件的第二端，第二晶体管的漏极耦合至第一衰减调节电路的输出端；第一晶体管的栅极和第二晶体管的栅极连接信号控制器。
上述第一晶体管和第二晶体管是参数相同的N沟道的MOS晶体管。
本申请实施例中，在第一晶体管和第二晶体管导通的情况下，通过信号控制器控制N个晶体管导通或者截止，使得N个电容接入电路，或者不接入电路，通过控制接入电路的电容数量，从而在第二衰减范围内对衰减可调电路的衰减值进行调节。具体的，该衰减可调电路可以等效为一个二端口网络，计算二端口网络的S参数矩阵，根据S参数矩阵与电路的插入损耗之间的计算关系，得到衰减可调电路的插入损耗，该插入损耗即为衰减可调电路的衰减值。
一种可能的实现方式中，第一衰减调节电路还包括第三晶体管和第四晶体管；其中，第三晶体管的漏极连接第一晶体管的源极，第四晶体管的漏极连接第二晶体管的源极，第三晶体管的源极和第四晶体管的源极均接地，第三晶体管的栅极和第四晶体管的栅极均连接信号控制器。通过信号控制器向第三晶体管的栅极输入的电平与向第一晶体管的栅极输入的电平相反，通过信号控制器向第四晶体管的栅极输入的电平与向第二晶体管的栅极输入的电平相反。第三晶体管和第四晶体管，用于在第一衰减调节电路不接入衰减可调电路的情况下，将第一衰减调节电路的交流电压导地。
本申请实施例中，当信号控制器通过其输出端向第一衰减调节电路输入的电平为低电平，即第一衰减调节电路处于非工作态时，第一晶体管和第二晶体管有交流电压(此时，第一晶体管和第二晶体管相当于大的电容)，此时，由于第三晶体管和第四晶体管的栅极输入的是高电平，因此，该第三晶体管和第四晶体管可以将交流电压导地，从而使得第一衰减调节电路的输出端不输出信号，能够使得第一衰减调节电路不干扰电路的其他部分的输出信号。综上，第三晶体管和第四晶体管的作用是提升第一衰减调节电路的隔离度。
一种可能的实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第二衰减调节电路，该第二衰减调节电路的输入端耦合至衰减可调电路的输入端，第二衰减调节电路的输出端耦合至衰减可调电路的输出端，第二衰减调节电路包括电感元件、电容元件以及开关元件。第二衰减调节电路和开关电容阵列电路，用于在第三衰减范围内调节衰减可调电路的衰减值；其中，第二衰减调节电路，用于调节衰减可调电路的电感值和电阻值，或者调节衰减可调电路的电感值、电阻值、电容值以及电导值；开关电容阵列电路，用于调节衰减可调电路的电容值和电导值。
一种可能的实现方式中，上述第二衰减调节电路包括第四电感元件、第三开关元件、第四开关元件、第一开关电容模块以及第二开关电容模块。其中，第三开关元件 的第一端耦合至衰减可调电路的输入端，第三开关元件的第二端连接第四电感元件的第一端和第一开关电容模块的第一端，第一开关电容模块的第二端接地；第四开关元件的第一端耦合至衰减可调电路的输出端，第四开关元件的第二端连接第四电感元件的第二端和第二开关电容模块的第一端，第二开关电容模块的第二端接地。第三开关元件和第四开关元件，用于控制第四电感元件接入衰减可调电路或者不接入衰减可调电路，以调节衰减可调电路的电感值和电阻值。
一种可能的实现方式中，上述第一开关电容模块由第一电容元件和第五开关元件串联形成，第二开关电容模块由第二电容元件和第六开关元件串联形成。其中，第五开关元件，用于控制第一电容元件接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值；第六开关元件，用于控制第二电容元件接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值。
一种可能的实现方式中，上述第五开关元件和第六开关元件为晶体管，并且第五开关元件为第五晶体管，第六开关元件为第六晶体管；第三开关元件和第四开关元件为晶体管，并且第三开关元件为第七晶体管，第四开关元件为第八晶体管。其中，第七晶体管的漏极耦合至第二衰减调节电路的输入端，第七晶体管的源极连接第四电感元件的第一端；第四电感元件的第二端连接第八晶体管的源极，第八晶体管的漏极耦合至第二衰减调节电路的输出端；第七晶体管的栅极和第八晶体管的栅极连接信号控制器。第五晶体管的漏极连接第一电容元件的第一端，第一电容元件的第二端连接第七晶体管的源极，第六晶体管的漏极连接第二电容元件的第一端，第二电容元件的第二端连接第八晶体管的源极，第五晶体管的源极和第六晶体管的源极均接地，第五晶体管的栅极和第六晶体管的栅极分别连接信号控制器。
本申请实施例中，在第一晶体管和第二晶体管截止，第七晶体管和第八晶体管导通的情况下，通过信号控制器控制N个晶体管导通或者截止，使得N个电容接入电路，或者不接入电路，通过控制接入电路的电容数量，并且通过该信号控制器控制第五晶体管和第六晶体管导通或者截止，使得第一电容和第二电容接入电路，或者不接入电路，从而在第三衰减范围内对衰减可调电路的衰减值进行调节。具体的，该衰减可调电路可以等效为一个二端口网络，计算二端口网络的S参数矩阵，根据S参数矩阵与电路的插入损耗之间的计算关系，得到衰减可调电路的插入损耗，该插入损耗即为衰减可调电路的衰减值。
一种可能的实现方式中，上述第二衰减调节电路还包括第九晶体管；第九晶体管的源极接地，第九晶体管的漏极连接第四电感元件的第二端，第九晶体管的栅极连接信号控制器；通过信号控制器向第九晶体管的栅极输入的电平与向第八晶体管的栅极输入的电平相反。第九晶体管，用于在第二衰减调节电路处于不接入衰减可调电路的情况下，将第二衰减调节电路的交流电压导地。
本申请实施例中，当第二衰减调节电路的控制端的输入电平为低电平，即第二衰减调节电路处于非工作态时，第二衰减调节电路中的第七晶体管和第八晶体管有交流电压(此时，第七晶体管和第八晶体管相当于大的电容)，由于第九晶体管栅极输入的是高电平，因此，该第九晶体管可以将交流电压导地，从而使得第二衰减调节电路的输出端不输出信号，即使得第二衰减调节电路不干扰其他衰减调节电路的输出信号。 综上，第九晶体管的作用是提升第二衰减调节电路的隔离度。
一种可能的实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第七开关元件和第八开关元件；第七开关元件和第八开关元件，用于控制第二衰减调节电路是否独立工作。当第七开关元件和第八开关元件未导通时，衰减可调电路中仅包括第二衰减调节电路，该第二衰减调节电路独立工作；该第二衰减调节电路，用于在第四衰减范围内调节衰减可调电路的衰减值。
一种可能的实现方式中，上述第七开关元件和第八开关元件为晶体管，并且第七开关元件为第十晶体管，第八开关元件为第十一晶体管。其中，第十晶体管的漏极耦合至衰减可调电路的输入端，第十晶体管的源极耦合至第一阻抗电路的输入端和第一衰减调节电路的输入端，第十一晶体管的漏极耦合至衰减可调电路的输出端，第十一晶体管的源极耦合至第二阻抗电路的输出端和第一衰减调节电路的输出端；第十晶体管的栅极和第十一晶体管的栅极连接信号控制器。
本申请实施例中，在第一晶体管和第二晶体管截止，第十晶体管和第十一晶体管截止，第七晶体管和第八晶体管导通的情况下，通过该信号控制器控制第五晶体管和第六晶体管导通或者截止，使得第一电容和第二电容接入电路，或者不接入电路，从而在第一衰减范围内对衰减可调电路的衰减值进行调节。具体的，该衰减可调电路可以等效为一个二端口网络，计算二端口网络的S参数矩阵，根据S参数矩阵与电路的插入损耗之间的计算关系，得到衰减可调电路的插入损耗，该插入损耗即为衰减可调电路的衰减值。
一种可能的实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第十二晶体管和第十三晶体管。其中，第十二晶体管的漏极耦合至第一阻抗电路的输入端，第十三晶体管的漏极耦合至第二阻抗电路的输出端，第十二晶体管的源极和第十三晶体管的源极均接地；第十二晶体管的栅极与第十三晶体管的栅极均连接信号控制器；通过信号控制器向第十二晶体管的栅极输入的电平与向第十晶体管的栅极输入的电平相反，通过信号控制器向第十三晶体管的栅极输入的电平与向第十一晶体管的栅极输入的电平相反。第十二晶体管和第十三晶体管，用于在第二衰减调节电路独立工作情况下，将衰减可调电路的交流电压导地。
本申请实施例中，当第十晶体管和第十一晶体管截止时，第十晶体管和第十一晶体管有交流电压(此时，第十晶体管和第十一晶体管有交流电压相当于大的电容)，由于第十二晶体管和第十三晶体管的栅极输入的是高电平，因此，该第十二晶体管和第十三晶体管可以将交流电压导地，从而使得第一方面所述的衰减可调电路(可以称为第三衰减调节电路)的输出端不输出信号，即使得第三衰减调节电路不干扰其他衰减调节电路(第一衰减调节电路)的输出信号。综上，第十二晶体管和第十三晶体管的作用是提升第三衰减调节电路的隔离度。
第二方面，本申请实施例提供一种衰减可调芯片，包括：多个第一方面及其可能的实现方式中任意之一所述的衰减可调电路，该多个衰减可调电路分为多组衰减可调电路，该多组衰减可调电路对称排布。
本申请实施例提供的衰减可调芯片可以适用于多个SerDes并行工作的场景，例如多个SerDes信道同时传输信号的场景，该衰减可调芯片中的每一个衰减可调电路可以 独立工作，互不影响，并且衰减可调芯片的集成度高，面积小。
一种可能的实现方式中，本申请实施例提供的衰减可调芯片还包括信号控制器；该信号控制器用于为多个衰减可调电路提供数字控制信号，以控制多个衰减可调电路的工作状态。
本申请实施例提供的对衰减可调芯片的封装方法是一种小型化的多DIE合封技术，上述每一组衰减可调电路可以称为一个DIE，该封装方法不但可以减小封装走线的长度，使得封装走线对信号造成的衰减值(即插入损耗)减小，而且该衰减可调芯片的各项指标均达标，例如隔离度、串扰都达到预期指标。
附图说明
图1为本申请实施例提供的一种RLGC电路模型和二端口网络的结构示意图；
图2为本申请实施例提供的一种SerDes测试原理示意图；
图3为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图一；
图4为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图二；
图5为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图三；
图6为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图四；
图7为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图五；
图8为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的等效电路图一；
图9为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图六；
图10为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图七；
图11为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图八；
图12为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的等效电路图二；
图13为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图九；
图14为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十；
图15为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十一；
图16为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十二；
图17为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十三；
图18为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的等效电路图三；
图19为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十四；
图20为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十五；
图21为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十六；
图22为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的等效电路图四；
图23为本申请实施例提供的一种基于RLGC电路模型的衰减可调电路的结构示意图十七；
图24为本申请实施例提供的一种衰减可调芯片的结构示意图一；
图25为本申请实施例提供的一种衰减可调芯片的结构示意图二；
图26为本申请实施例提供的一种衰减可调芯片的封装效果示意图。
具体实施方式
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一阻抗电路、第二阻抗电路等是用于区别不同的阻抗电路，而不是用于描述阻抗电路的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例提供的基于RLGC电路模型的衰减可调电路可用于模拟传输信道，在本申请实施例中，以该衰减可调电路用于模拟SerDes信道为例进行说明。
首先对本申请实施例提供的基于RLGC电路模型的衰减可调电路及芯片中涉及的一些概念做解释说明。
RLGC电路模型：是一种用于等效传输线的一种电路模型，RLGC电路模型包括四个分布参数，分别是电阻(R)、电感(L)、电导(G)以及电容(C)，在一种实现方式中，可以利用微元法将传输线切割为长度为dz的无穷多个RLGC小单元，该RLGC小单元的衰减特性与传输线的衰减特性基本相同。示例性的，图1中的(a)是一种RLGC小单元的结构以及与传输线的等效示意图，当使用RLGC电路模拟一段传输线时，多个RLGC小单元串联之后可以模拟该传输线，具体参考图1中的(b)。
应理解，信号经SerDes测试电路(该SerDes测试电路为SerDes信道的一部分) 进行传输的过程中，SerDes测试电路对信号具有一定的衰减作用，在SerDes测试电路的输入端匹配的情况下，SerDes测试电路对信号造成的衰减值等于SerDes测试电路的插入损耗，而电路的插入损耗与电路中各元器件的阻抗(直流阻抗或交流阻抗)有关。SerDes测试电路可以等效为二端口网络，基于该二端口网络，能够计算出SerDes测试电路的插入损耗。
二端口网络：参考图1中的(c)，对二端口网络进行简要的介绍，二端口网络的一端的电压可以为v 1，电流为i 1，另一个端口的电压为v 2，电流为i 2，电流i 1和电流i 2的方向参考图1中的(c)。应理解，二端口网络可以通过不同参数进行描述，例如二端口网络可以通过Z参数、Y参数或A参数进行描述。
通过Z参数描述图1中的(c)所示的二端口网络如下：
Figure PCTCN2022079957-appb-000001
通过Y参数描述图1中的(c)所示的二端口网络如下：
Figure PCTCN2022079957-appb-000002
通过A参数描述图1中的(c)所示的二端口网络如下：
Figure PCTCN2022079957-appb-000003
其中，
Figure PCTCN2022079957-appb-000004
为Z参数矩阵(即阻抗矩阵)，
Figure PCTCN2022079957-appb-000005
为Y参数矩阵(即导纳矩阵)，
Figure PCTCN2022079957-appb-000006
为A参数矩阵(即上述的ABCD转移矩阵)。
可以理解的是，上述Z参数矩阵、Y参数矩阵以及ABCD转移矩阵均可以与S参数矩阵(即散射矩阵)进行转换。上述S参数矩阵记为
Figure PCTCN2022079957-appb-000007
其中，S参数矩阵的元素S 11表示正向反射系数，可以反映输入端的匹配情况，S 22表示反向反射系数，可以反映输出端的匹配情况，S 21表示正向功率传输系数，可以反映增益或者衰减情况，S 12表示反向功率传输系数，用于反映隔离度。
对于一个二端口网络，该二端口网络的插入损耗可以通下述公式(1)计算。
IL＝20log|S 21|    公式(1)
其中，IL表示插入损耗，S 21是上述S参数矩阵中的元素。
应理解，二端口网络的端口匹配条件是：20log|S 11|满足预设的条件，例如20log|S 11|＜-10dB。
综上描述可知，针对不同的二端口网络，计算出该二端口网络的S参数矩阵之后，能够根据公式(1)计算得到该二端口网络的插入损耗，即衰减值。
需要说明的是，本申请实施例提供的基于RLGC电路模型的衰减可调电路可以等效为二端口网络，可选地，可以通过上述A参数、Z参数或Y参数表示二端口网络，进而将A参数、Z参数或Y参数转换为S参数，即可得到衰减可调电路的插入损耗。而对于一个电路，该电路的ABCD转移矩阵、Z参数矩阵以及Y参数矩阵均与RLGC 模型电路中的电阻、电感、电导以及电容的值具有直接的关系，因此本申请实施例提供基于RLGC衰减可调电路可通过调节电路的一种或多种元器件的值实现对电路的衰减值的调节。
SerDes：串行器/解串器的简称，使用SerDes进行信号传输是一种主流的时分多路复用(TDM)、点对点(P2P)的串行通信技术。在发送端将多路低速并行信号转换成高速串行信号，经过传输媒介(光缆或铜线等)，最后在接收端将高速串行信号重新转换成低速并行信号。这种点对点的串行通信技术可以充分利用传输媒介的信道容量，减少所需的传输信道和器件引脚数目，能够提升信号的传输速度，从而显著降低通信成本。
通过SerDes进行信号传输的过程中，信号从发送端到达接收端所经过的路径(路径中包括传输媒介)称为信道(channel)，也可以称为SerDes信道，SerDes信道中可以包括PCB走线，过孔，电缆，连接器等元件。信号通过SerDes信道进行传输时，会带来信号的衰减、反射以及串扰等问题，使得信号受损。其中，信号的衰减问题对于信号的完整性的影响较为明显。
本申请实施例中，对SerDes进行测试指的是对SerDes的衰减性能进行测试，即通过SerDes传输信号的过程中，对信号造成的衰减情况进行测试。例如，测试该SerDes能达到的极限衰减值等。
应理解，对SerDes进行测试时，测试的对象通常是一个待测单板，该待测单板上包括一些芯片等器件。例如，如图2中的(a)所示，待测单板中包括交换芯片，交换芯片中包括一个或多个SerDes，图2中的(a)以交换芯片包括一个SerDes为例进行说明，对该待测单板中的SerDes进行测试时，将测试板(测试板中包括用于模拟SerDes信道的测试芯片)与待测单板对接，其中，对于每一个SerDes，在待测单板中，还包括连接SerDes与测试板的PCB传输线、连接器等元件，在测试板中也包括连接器、PCB传输线等。
需要说明的是，连接SerDes与测试芯片的PCB传输线、连接器等元件也属于SerDes信道的一部分，在信号传输过程中，也会引起信号衰减；并且测试板中的测试芯片的封装走线也会引起信号衰减。若待测单板包括多个SerDes时，在待测单板上，对于不同SerDes，连接SerDes与测试板的元件可能不同，或PCB传输线的长度可能不同等等，使得不同的SerDes对信号造成的衰减程度不同。
综上，参考图2中的(b)，可以理解的是，通过SerDes信道传输信号的过程中，在SerDes信道中对信号造成的衰减可以包括两部分：第一部分衰减是连接SerDes与测试芯片的PCB传输线、连接器等元件导致的信号衰减，第二部分衰减是测试芯片导致的衰减。也就是说，整个SerDes信道对信号造成的衰减值是上述第一部分衰减对应的衰减值和第二部分衰减对应的衰减值之和。上述第一部分衰减对应的衰减值通常是固定的；上述测试芯片导致的衰减可以包括两个方面，第一方面是测试芯片中的测试电路导致的衰减，第二方面是测试芯片中对测试电路进行封装(布线)导致的衰减，即封装衰减，图2中的(b)示意了封装衰减，在现有的测试芯片中，测试芯片本身对信道造成的衰减值也是固定的，即衰减值不可调节。
在一种实现方式中，对不同待测单板中的SerDes信道进行模拟时，需针对不同的SerDes定制不同的测试板(包括测试芯片)，成本较高。
在另一种实现方式中，对不同待测单板中的SerDes信道进行模拟时，使用同一种测试板(即归一环回绕线板)，该测试板无法适用于不同待测单板的SerDes信道的最大施加应力要求，即测试板的适用性较低。
基于现有技术中用于模拟传输信道的测试板的衰减值不可调的的问题，本申请实施例提供一种基于RLGC电路模型的衰减可调电路及芯片，在该衰减可调电路中，通过衰减可调电路中的开关电容阵列，能够在一定的衰减范围内调节该衰减可调电路的衰减值。在一种应用中，该衰减可调电路可以用于模拟不同衰减值的SerDes信道，具有较好的适用性。
应理解，本申请实施例提供的基于RLGC电路模型的衰减可调电路用于模拟SerDes信道时，该衰减可调电路的输入端连接串行器的输出端，即串行器将多路串行信号转换为并行信号之后，将输出的并行信号输入至衰减可调电路，衰减可调电路的输出端连接解串器，即经衰减可调电路输出的并行信号输入至解串器的输入端，从而解串器将并行信号转换为多路串行信号。
下面对本申请实施例提供的基于RLGC电路模型的衰减可调电路及芯片进行详细地介绍。
如图3所示，本申请实施例提供一种基于RLGC电路模型的衰减可调电路，包括：开关电容阵列电路31、第一阻抗电路32、第二阻抗电路33。其中，第一阻抗电路32的输入端321耦合至衰减可调电路的输入端，第一阻抗电路32的输出端连接第二阻抗电路33的输入端331，第二阻抗电路33的输出端332耦合至衰减可调电路的输出端，第一阻抗电路32的输出端322和第二阻抗电路33的输入端331分别连接开关电容阵列电路31的第一端311，开关电容阵列电路31的第二端312接地。上述第一阻抗电路32和第二阻抗电路33包括电感元件和电阻元件，开关电容阵列电路31包括电容元件和开关元件。
上述开关电容阵列电路31，用于在第一衰减范围内调节衰减可调电路的衰减值。
在本申请实施例提供的基于RLGC电路模型的衰减可调电路可以等效为一个二端口网络，基于上述实施例中描述的在二端口网络的计算插入损耗的方法可以计算得到该衰减可调电路的插入损耗，衰减可调电路的插入损耗即为衰减可调电路的衰减值。本申请实施例中，通过控制衰减可调电路的开关电容阵列，可以实现对该电路的衰减值的调节，由于该衰减可调电路的衰减值可以在第一衰减范围内进行调节，如此该衰减可调电路能够模拟第一衰减范围内的不同衰减值的传输信道，具有较好的适用性。
进一步的，由于本申请实施例提供的基于RLGC电路模型的衰减可调电路可以用于对不同衰减范围的SerDes信道进行模拟，因此无需针对每一种SerDes信道分别设计或开发一种测试工具板，能够极大地节约成本。
可选地，本申请实施例中，上述开关电容阵列电路具体用于通过调节衰减可调电路的电容值和电导值，在第一衰减范围内调节衰减可调电路的衰减值。
可以理解的是，在RLGC电路模型中，可以通过调节电路中的各个参数，例如电阻值、电感值、电导值或电容值中的至少一项来调节电路的衰减值，在本申请实施例提供的基于RLGC电路模型的衰减可调电路中，通过调整衰减可调电路中的电容值和电导值来调节衰减可调电路的衰减值。可选地，由于电导值通常很小，对电路的衰减 值的影响较小，电导值也可以忽略不计。
参考图4，在一种实现方式中，开关电容阵列电路31由N个电容元件以及N个开关元件形成的N个开关电容模块并联组成。其中，第i个开关电容模块31-i的第一端耦合至开关电容阵列电路31的第一端311，第i个开关电容模块的第二端耦合至开关电容阵列电路31的第二端312；N为大于或等于2的正整数，i为1，2，……，N中的任意一个值。
结合图4，如图5所示，上述N个电容元件中的第i个电容元件与N个开关元件中的第i个开关元件串联形成开关电容阵列电路31的第i个开关电容模块，可选地，N个电容元件为电容。
本申请实施例中，上述N个开关元件，用于控制N个电容元件中的一个或多个电容元件接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值。
参考图6，在一种实现方式中，上述图5中的N个开关元件为N个晶体管，该N个晶体管中的第i个晶体管M'1的漏极连接第i个电容元件的第一端，该第i个晶体管的源极耦合至第i个开关电容模块31-i的第二端，第i个晶体管的栅极连接信号控制器，第i个电容的第二端耦合至开关电容模块31-i的第一端。
具体的，上述N个晶体管中的第i个晶体管M'i的栅极连接信号控制器的输出端SCi，通过信号控制器的输出端SCi输出的控制信号用于控制第i个晶体管M'i导通或截止，从而控制第i个电容C'i接入电路或者不接入电路。例如，当信号控制器的输出端SCi的电平为高电平时，第i个晶体管M'i导通，第i个电容C'i接入电路；当信号控制器的输出端SCi的电平为低电平时，第i个晶体管M'i截止，第i个电容C'i不接入电路。
参考图7，在一种实现方式中，上述第一阻抗电路32包括第一电阻元件R1和第一电感元件L1，第一电阻元件R1和第一电感元件L1并联。其中，第一电阻元件R1的第一端和第一电感元件L1的第一端耦合至第一阻抗电路32的输入端321，第一电阻元件R1的第二端和第一电感元件L1的第二端耦合至第一阻抗电路32的输出端321。
进一步的，参考图7，上述第二阻抗电路33包括第二电阻元件R2和第二电感元件L2，第二电阻元件R1和第二电感元件L2并联。其中，第二电阻元件R2的第一端和第二电感元件L2的第一端耦合至第二阻抗电路33的输入端331，第二电阻元件R2的第二端和第二电感元件L2的第二端耦合至第二阻抗电路33的输出端332。
结合图7，可以理解的是，信号控制器的输出端SC1至输出端SCN输出的电平不作限定，具体根据实际需求控制输出端SC1至输出端SCN的电平。可知，输出端SC1至输出端SCN的作用类似于开关，通过控制该信号控制器的输出端SC1至输出端SCN的电平，控制晶体管M'1至M'N导通或者截止，使得电容C'1至C'N接入电路，或者不接入电路，通过控制电容C'1至C'N中接入电路的电容数量，对衰减可调电路的衰减值进行调节。
应理解，本申请实施例中，上述晶体管M'1至M'N相当于开关，并且当晶体管
M'1至M'N中的一个或多个导通时，每个晶体管具有一定的导通电路，如此，图7所示的衰减可调电路可以等效为图8所示的电路，在图8中，R' on1至R' onN分别是晶体管M'1至M'N的导通电阻，C' 1至C' N分别为电容C'1至电容C'N的电容值，L 1为第一电 感L1的电感值，L 2为第二电感L2的电感值，R 1为第一电阻的阻值，R 2为第二电阻的阻值。
本申请实施例中，图8所示的衰减可调电路的等效电路是一个二端口网络，通过控制开关SC1和SCN的状态为不同的状态，在第一衰减范围内对该电路的衰减值进行调节。示例性的，以开关SC1至SCN均闭合为例，下面介绍图8所示的等效电路的衰减值的计算过程。
首先，采用ABCD转移矩阵对图8所示的电路进行表示，ABCD转移矩阵的表示过程如下：
Figure PCTCN2022079957-appb-000008
需要说明的是，在上述表示公式中，当第i个晶体管导通时，对应的X i的取值为1，当第i个晶体管截止时，对应的X i取值为0。
其次，将上述ABCD转移矩阵归一化后转换为S参数矩阵。具体的，归一化的ABCD转移矩阵与S参数矩阵的转换公式如下：
Figure PCTCN2022079957-appb-000009
Figure PCTCN2022079957-appb-000010
Figure PCTCN2022079957-appb-000011
Figure PCTCN2022079957-appb-000012
最后，基于转换得到的S参数矩阵，采用上述公式(1)可以计算得到图8所示的等效电路的插入损耗，从而得到该衰减可调电路的衰减值。
结合图7，如图9所示，在一种实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第一衰减调节电路34，该第一衰减调节电路34的输入端341耦合至衰减可调电路的输入端，第一衰减调节电路34的输出端342耦合至衰减可调电路的输出端。该第一衰减调节电路34包括电感元件和开关元件。
本申请实施例中，第一衰减调节电路34和开关电容阵列电路31，用于在第二衰减范围内调节衰减可调电路的衰减值。其中，第一衰减调节电路34，用于调节衰减可调电路的电感值和电阻值；开关电容阵列电路31，用于调节衰减可调电路的电容值和电导值。
可以理解的是，上述通过调节衰减可调电路的电感值、电阻值、电容值以及电导值，来调节衰减可调电路的衰减值。
参考图10，在一种实现方式中，第一衰减调节电路34包括第三电感元件L3、第一开关元件S1和第二开关元件S2。其中，第一开关元件S1、第三电感元件L3和第二开关元件S2依次串联。第一开关元件S1和第二开关元件S2，用于控制第三电感元件L3接入衰减可调电路或者不接入衰减可调电路，以调节该衰减可调电路的电感值和 电阻值。
可选地，上述开关元件为晶体管，参考图11，第一开关元件S1为第一晶体管M1，第二开关元件S2为第二晶体管M2。其中，第一晶体管M1的漏极耦合至第一衰减调节电路34的输入端341，第一晶体管M1的源极连接第三电感元件L3的第一端，第二晶体管M2的源极连接第三电感元件L3的第二端，第二晶体管M2的漏极耦合至第一衰减调节电路34的输出端342；第一晶体管M1的栅极和第二晶体管M2的栅极连接信号控制器。
需要说明的是，上述第一晶体管M1和第二晶体管M2是参数相同的N沟道的金属氧化物半导体(metal oxide semiconductor，MOS)晶体管。
具体的，第一晶体管M1的栅极和第二晶体管M2的栅极连接信号控制器的输出端SR2，即信号控制器的输出端SR2的输出信号用于控制第一晶体管M1和第二晶体管M2导通或截止。当信号控制器输出高电平至输出端SR2，第一晶体管M1和第九晶体管M2均到导通，当信号控制器输出低电平至输出端SR2，第一晶体管M1和第二晶体管M2均截止。
结合图11，可以理解的是，信号控制器的输出端SC1至输出端SCN的作用类似于开关，通过信号控制器控制该信号控制器的输出端SC1至输出端SCN的电平，控制晶体管M'1至M'N导通或者截止，使得电容C'1至C'N接入电路，或者不接入电路，通过控制电容C'1至C'N中接入电路的电容数量，对衰减可调电路的衰减值进行调节。具体的，信号控制器的输出端SC1至输出端SCN输出的电平不作限定，具体根据实际需求控制输出端SC1至输出端SCN的电平。
应理解，本申请实施例中，上述第一晶体管M1、第二晶体管M2以及晶体管M'1至M'N相当于开关，并且当上述第一晶体管M1和第二晶体管M2导通，晶体管M'1至M'N中的一个或多个导通时，每个晶体管具有一定的导通电阻。如此，图11所示的衰减可调电路可以等效为图12所示的电路。在图12中，R' on1至R' onN分别是晶体管M'1至M'N的导通电阻，C' 1至C' N分别为电容C'1至电容C'N的电容值，L 1为第一电感L1的电感值，L 2为第二电感L2的电感值，R 1为第一电阻的阻值，R 2为第二电阻的阻值，R on1和R on2分别为第一晶体管M1的导通电阻和第二晶体管M2的导通电阻，L 3为第三电感L3的电感值。
图12所示的等效电路也是一个二端口网络，在第一晶体管M1和第二晶体管M2导通的情况下，通过控制SC1至SCN为不同的状态，在第二衰减范围内调节衰减可调电路的衰减值。以开关SC1至SCN均闭合为例，下面介绍图12所示的等效电路的衰减值的计算过程。
首先，确定图12所示的等效电路的参数矩阵。应理解，在图12中，第一衰减调节电路34是并联在原本的衰减可调电路(即图7所示的衰减可调电路)的两端。
需要说明的是，为了便于描述，在以下实施例中，将图7所示的衰减可调电路统称为第三衰减调节电路。
具体的，先分别确定第一衰减调节电路34和第三衰减调节电路对应的ABCD转移矩阵，表示过程如下：
Figure PCTCN2022079957-appb-000013
Figure PCTCN2022079957-appb-000014
其中，
Figure PCTCN2022079957-appb-000015
是第一衰减调节电路34对应的ABCD转移矩阵，
Figure PCTCN2022079957-appb-000016
是第三衰减调节电路对应的ABCD转移矩阵。
然后，将
Figure PCTCN2022079957-appb-000017
和
Figure PCTCN2022079957-appb-000018
分别转换为Z矩阵，将
Figure PCTCN2022079957-appb-000019
转换为矩阵Z 1，该矩阵Z 1与矩阵
Figure PCTCN2022079957-appb-000020
的维度相同；同理，也将
Figure PCTCN2022079957-appb-000021
转换矩阵Z 3，该矩阵Z 3与矩阵
Figure PCTCN2022079957-appb-000022
的维度相同。
计算图12所示的等效电路的Z参数矩阵，该等效电路的Z参数矩阵是第一衰减调节电路34对应的Z参数矩阵与第三衰减调节电路对应的Z参数矩阵之和。具体的，图12所示的等效电路的Z参数矩阵为：Z＝Z 1+Z 3。该Z参数矩阵为
Figure PCTCN2022079957-appb-000023
其次，将上述Z参数矩阵转换为S参数矩阵，Z参数矩阵与S参数矩阵的转换公式如下：
Figure PCTCN2022079957-appb-000024
Figure PCTCN2022079957-appb-000025
Figure PCTCN2022079957-appb-000026
Figure PCTCN2022079957-appb-000027
最后，基于转换得到的S参数矩阵，采用上述公式(1)可以计算得到图12所示的等效电路的插入损耗，从而得到该衰减可调电路的衰减值。
参考图13，在一种实现方式中，上述第一衰减调节电路34还包括第三晶体管M3和第四晶体管M4。其中，第三晶体管M3的漏极连接第一晶体管的源极，第四晶体管M4的漏极连接第二晶体管M2的源极，第三晶体管M3的源极和第四晶体管M4的源极均接地，第三晶体管M3的栅极和第四晶体管M4的栅极均连接信号控制器。需要说明的是，通过信号控制器向第三晶体管M3的栅极输入的电平与向第一晶体管M1的栅极输入的电平相反，通过信号控制器向第四晶体管M4的栅极输入的电平与向第二晶体管M2的栅极输入的电平相反。
第三晶体管M3和第四晶体管M4，用于在第一衰减调节电路34不接入衰减可调电路的情况下，将第一衰减调节电路34的交流电压导地。
本申请实施例中，当信号控制器通过其输出端SR2向第一衰减调节电路34输入的电平为低电平，即第一衰减调节电路34处于非工作态时，第一晶体管M1和第二晶体管M2有交流电压(此时，第一晶体管M1和第二晶体管M2相当于大的电容)，此时，由于第三晶体管M3和第四晶体管M4的栅极输入的是高电平，因此，该第三晶体管M3和第四晶体管M4可以将交流电压导地，从而使得第一衰减调节电路34的输出端不输出信号，能够使得第一衰减调节电路34不干扰第三衰减调节电路的输出信号。综上，第三晶体管M3和第四晶体管M4的作用是提升第一衰减调节电路34的隔离度。
可选地，第三晶体管M3和第四晶体管M4可以为参数相同的N沟道的MOS晶体管。第三晶体管M3和第四晶体管M4的栅极耦合在一起，并连接信号控制器的输出端SK2，或者通过反相器连接上述SR2，反相器的输出端为SR2B，输出端SR2B的电平与输出端SR2的电平相反。
结合图13，如图14所示，在一种实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第二衰减调节电路35，该第二衰减调节电路35的输入端351耦合至衰减可调电路的输入端，第二衰减调节电路35的输出端352耦合至衰减可调电路的输出端；第二衰减调节电路35包括电感元件、电容元件以及开关元件。
第二衰减调节电路35和开关电容阵列电路31，用于在第三衰减范围内调节衰减可调电路的衰减值。其中，第二衰减调节电路35，用于调节衰减可调电路的电感值和电阻值，或者调节衰减可调电路的电感值、电阻值、电容值以及电导值；开关电容阵列电路，用于调节衰减可调电路的电容值和电导值。
在图14所示的基于RLGC电路模型的衰减可调电路中，由于第二衰减调节电路35中包括电感元件、电容元件以及开关元件，因此，可以通过开关元件控制电感元件以及电容元件是否接入衰减可调电路，从而调节电路的电感值和电阻值，或者调节电路的电感值、电阻值、电容值以及电导值。可选地，由于电阻值和电导值通常很小，对电路的衰减值的影响较小，电阻值和电导值也可以忽略不计。
参考图15，上述第二衰减调节电路35包括第四电感元件L4、第三开关元件S3、第四开关元件S4、第一开关电容模块CS1以及第二开关电容模块CS2。其中，第三开关元件S3的第一端耦合至衰减可调电路的输入端，第三开关元件S3的第二端连接第四电感元件L4的第一端和第一开关电容模块CS1的第一端，第一开关电容模块CS1的第二端接地；第四开关元件S4的第一端耦合至衰减可调电路的输出端，第四开关元件S4的第二端连接第四电感元件L4的第二端和第二开关电容模块CS1的第一端，第二开关电容模块CS1的第二端接地。
第三开关元件S3和第四开关元件S4，用于控制第四电感元件L4接入衰减可调电路或者不接入衰减可调电路，以调节衰减可调电路的电感值和电阻值。
可选地，如图16所示，上述第一开关电容模块CS1由第一电容元件C1和第五开关元件S5串联形成，第二开关电容模块CS2由第二电容元件C2和第六开关元件S6串联形成。其中，第五开关元件S5，用于控制第一电容元件C1接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值；第六开关元件S6，用于控制第二 电容元件2接入或者不接入衰减调节电路，以调节衰减可调电路的电容值和电导值。
可以理解的是，上述第三开关元件S3、第四开关元件S4、第五开关元件S5、第六开关元件S6可以互相配合来调节衰减可调电路的电感值、电阻值、电容值和电导值。
可选地，如图17所示，上述第五开关元件S5和第六开关元件S6为晶体管，并且第五开关元件S5为第五晶体管M5，第六开关元件S6为第六晶体管M6；第三开关元件S3和第四开关元件S4为晶体管，并且第三开关元件为第七晶体管M7，第四开关元件为第八晶体管M8。
其中，第七晶体管M7的漏极耦合至第二衰减调节电路35的输入端351，第七晶体管M7的源极连接第四电感元件L4的第一端；第四电感元件L4的第二端连接第八晶体管M8的源极，第八晶体管M8的漏极耦合至第二衰减调节电路35的输出端352；第七晶体管M7的栅极和第八晶体管M98的栅极连接信号控制器。第五晶体管M5的漏极连接第一电容元件C1的第一端，第一电容元件C1的第二端连接第七晶体管M7的源极，第六晶体管M6的漏极连接第二电容元件C2的第一端，第二电容元件C2的第二端连接第八晶体管M8的源极，第五晶体管M5的源极和第六晶体管M6的源极均接地，第五晶体管M5的栅极和第六晶体管M6的栅极分别连接信号控制器。
需要说明的是，上述第七晶体管M7和第八晶体管M8是参数相同的N沟道的MOS晶体管。
具体的，第七晶体管M7和第八晶体管M8的栅极连接信号控制器的输出端SR1，即信号控制器的输出端SR1的输出信号用于控制第七晶体管M7和第八晶体管M8导通或截止。当信号控制器输出高电平至输出端SR1，第七晶体管M7和第八晶体管M8均到导通，当信号控制器输出低电平至输出端SR1，第七晶体管M7和第八晶体管M8均截止。
本申请实施例中，对于图17所示的衰减可调电路，当信号控制器输出高电平至输出端SR1，输出低电平至输出端SR2时，第一衰减调节电路34不接入该衰减可调电路，即第一衰减调节电路34不工作，第二衰减调节电路35和第三衰减调节电路处于工作态。图17所示的电路等效为图18所示的电路。
结合图17，可以理解的是，信号控制器的输出端SC1至输出端SCN的作用类似于开关，通过控制该信号控制器的输出端SC1至输出端SCN的电平，控制晶体管M'1至M'N导通或者截止，使得电容C'1至C'N接入电路，或者不接入电路，通过控制电容C'1至C'N中接入电路的电容数量，从而对衰减可调电路的衰减值进行调节。具体的，信号控制器的输出端SC1至输出端SCN输出的电平不作限定，具体根据实际需求控制输出端SC1至输出端SCN的电平。并且，信号控制器的输出端SW1和输出端SW2的作用类似于开关，通过控制该信号控制器的输出端SW1和输出端SW2的电平，控制第五晶体管M5和第六晶体管M6导通或者截止，使得第一电容C1和第二电容C2接入电路，或者不接入电路，从而对衰减可调电路的衰减值进行调节。
在图18中，R' on1至R' onN分别是晶体管M'1至M'N的导通电阻，C' 1至C' N分别为电容C'1至电容C'N的电容值，L 1为第一电感L1的电感值，L 2为第二电感L2的电感值，R 1为第一电阻的阻，R 2为第二电阻的阻值。R on7是第七晶体管M7的导通电阻，R on8是第八晶体管M8的导通电阻，L 4为第四电感L4的电感值，R on5是第五晶体管 M5的导通电阻，R on6是第六晶体管M6的导通电阻，C 1是第一电容C1的电容值，C 2是第二电容C2的电容值。
图18所示的等效电路也是一个二端口网络，通过控制SW1、SW2以及SC1至SCN为不同的状态，在第三衰减范围内对该电路的衰减值进行调节。示例性的，以开关SW1、SW2以及SC1至SCN均闭合为例，下面介绍图18所示的等效电路的衰减值的计算过程。
首先，确定图18所示的等效电路的参数矩阵。应理解，在图18中，第二衰减调节电路35和第三衰减调节电路并联，先分别确定第二衰减调节电路35和第三衰减调节电路对应的ABCD转移矩阵，表示过程如下：
Figure PCTCN2022079957-appb-000028
Figure PCTCN2022079957-appb-000029
其中，
Figure PCTCN2022079957-appb-000030
是第二衰减调节电路35对应的ABCD转移矩阵，
Figure PCTCN2022079957-appb-000031
是第三衰减调节电路对应的ABCD转移矩阵。
然后，将
Figure PCTCN2022079957-appb-000032
和
Figure PCTCN2022079957-appb-000033
分别转换为Z矩阵，将
Figure PCTCN2022079957-appb-000034
转换为矩阵Z 2，该矩阵Z 2与矩阵
Figure PCTCN2022079957-appb-000035
的维度相同；同理，也将
Figure PCTCN2022079957-appb-000036
转换矩阵Z 3，该矩阵Z 3与矩阵
Figure PCTCN2022079957-appb-000037
的维度相同。
图18所示的等效电路的Z参数矩阵为：Z＝Z 2+Z 3。该Z参数矩阵为
Figure PCTCN2022079957-appb-000038
其次，将上述Z参数矩阵转换为S参数矩阵，具体参考上述实施例的相关描述，此处不再赘述。
最后，基于转换得到的S参数矩阵，采用上述公式(1)可以计算得到图18所示的等效电路的插入损耗，从而得到该衰减可调电路的衰减值。
参考图19，在一种实现方式中，上述第二衰减调节电路35还包括第九晶体管M9，该第九晶体管M9的源极接地，第九晶体管M9的漏极连接第四电感元件L4的第二端，第九晶体管M9的栅极连接信号控制器。需要说明的是，通过信号控制器向第九晶体管M9的栅极输入的电平与向第八晶体管的栅极输入的电平相反。
第九晶体管M9，用于在第二衰减调节电路35处于不接入衰减可调电路的情况下，将第二衰减调节电路35的交流电压导地。
本申请实施例中，当第二衰减调节电路35的控制端的输入电平为低电平，即第二 衰减调节电路35处于非工作态时，第二衰减调节电路35中的第七晶体管M7和第八晶体管M8有交流电压(此时，第七晶体管M7和第八晶体管M8相当于大的电容)，由于第九晶体管M9栅极输入的是高电平，因此，该第九晶体管M9可以将交流电压导地，从而使得第二衰减调节电路35的输出端不输出信号，即使得第二衰减调节电路35不干扰其他衰减调节电路的输出信号。综上，第九晶体管M9的作用是提升第二衰减调节电路35的隔离度。
可选地，该第九晶体管M9的栅极可以连接信号控制器的输出端SK1，或者通过反相器连接上述SR1，反相器的输出端为SR1B，输出端SR1B的电平与输出端SR1的电平相反。
参考图20，在一种实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第七开关元件S7和第八开关元件S8。第七开关元件和第八开关元件，用于控制第二衰减调节电路35是否独立工作。当第七开关元件S7和第八开关元件S8未导通时，衰减可调电路中仅包括第二衰减调节电路35，第二衰减调节电路35独立工作。在这种情况下，第二衰减调节电路35，用于在第四衰减范围内调节衰减可调电路的衰减值。
本申请实施例中，第七开关元件S7和第八开关元件S8未导通时，上述第一衰减调节电路34和第三衰减调节电路均处于非工作态，第二衰减调节电路35独立工作，该第二衰减调节电路35也是一个RLGC电路模型，可以用于模拟第一衰减范围的SerDes信道。
可选地，结合图20，如图21所示，上述第七开关元件S7和第八开关元件S8为晶体管，并且第七开关元件S7为第十晶体管M10，第八开关元件S8为第十一晶体管M11。其中，第十晶体管M10的漏极耦合至衰减可调电路的输入端，第十晶体管M10的源极耦合至第一阻抗电路32的输入端321和第一衰减调节电路34的输入端341，第十一晶体管M11的漏极耦合至衰减可调电路的输出端，第十一晶体管M11的源极耦合至第二阻抗电路33的输出端331和第一衰减调节电路34的输出端342；第十晶体管M10的栅极和第十一晶体管M11的栅极连接信号控制器。
具体的，第十晶体管M10的栅极和第十一晶体管M11的栅极连接信号控制器的输出端SR3，即信号控制器的输出端SR3的输出信号用于控制第十晶体管M10的栅极和第十一晶体管M11导通或截止。当信号控制器输出高电平至输出端SR3时，第十晶体管M10的栅极和第十一晶体管M11均到导通，当信号控制器输出低电平至输出端SR3，第十晶体管M10的栅极和第十一晶体管M11均截止。
本申请实施例中，对于图21所示的衰减可调电路，在信号控制器输出低电平至输出端SR3时，高电平至输出端SR1的情况下，第一衰减调节电路34和第三衰减调节电路不接入该衰减可调电路，即第一衰减调节电路34和第三衰减调节电路处于非工作态，第二衰减调节电路35和第三衰减调节电路处于工作态，图21所示的电路等效为图22所示的电路。
可以理解的是，上述信号控制器的输出端SW1和输出端SW2的作用类似于开关，通过信号控制器控制该信号控制器的输出端SW1和输出端SW2的电平，使得第一电容C1和/或第二电容C2接入电路，或者不接入电路，从而对衰减可调电路的衰减值进 行调节。信号控制器的输出端SW1和输出端SW2输出的电平不作限定，具体根据实际需求控制输出端SW1和输出端SW2的电平。
在图22中，R on7是第七晶体管M7的导通电阻，R on8是第八晶体管M8的导通电阻，L 4为第四电感L4的电感值，R on5是第五晶体管M5的导通电阻，R on6是第六晶体管M6的导通电阻，C 1是第一电容C1的电容值，C 2是第二电容C2的电容值。
图22所示的等效电路是一个二端口网络，其中，开关SW1和SW2的状态可以为不同的状态，例如，SW1和SW2均打开，或者SW1闭合，SW2打开，或者SW1打开，SW2闭合，或者SW1和SW2均闭合。通过控制SW1和SW2为不同的状态，在第四衰减范围内对该电路的衰减值进行调节。示例性的，以开关SW1和SW2均闭合为例，下面介绍图22所示的等效电路的衰减值的计算过程。
首先，采用ABCD转移矩阵表示图22所示的电路，ABCD转移矩阵的表示过程如下：
Figure PCTCN2022079957-appb-000039
其次，将上述ABCD转移矩阵转归一化后换为S参数矩阵。具体参考上述实施例的描述，此处不再赘述。
最后，基于转换得到的S参数矩阵，采用上述公式(1)可以计算得到图22所示的等效电路的插入损耗，从而得到该衰减可调电路的衰减值。
需要说明的是，本申请实施例中，上述第一衰减范围、第二衰减范围、第三衰减范围以及第四衰减范围不同，对应的衰减范围依次减小，对应的衰减值依次减小。示例性的，第一衰减范围可以为10分贝(dB)以上，第二衰减范围可以为5-10dB，第三衰减范围可以为3-5dB，第四衰减范围可以为2-3dB。即上述第一衰减范围为高衰减范围，第二衰减范围为较高衰减范围，第三衰减范围为中衰减范围，第四衰减范围为低衰减范围。
相应地，本申请实施例提供的基于RLGC电路模型的衰减可调电路用于模拟不同的SerDes信道时，可以模拟不同衰减范围的SerDes信道。例如，第一衰减范围对应高衰减范围的第一SerDes信道，第二衰减范围对应较高衰减范围的第二SerDes信道，第三衰减范围对应中衰减范围的第三SerDes信道，第四衰减范围对应低衰减范围的第四SerDes信道。
参考图23，在一种实现方式中，本申请实施例提供的基于RLGC电路模型的衰减可调电路还包括第十二晶体管M12和第十三晶体管M13。其中，第十二晶体管M12的漏极耦合至第一阻抗电路32的输入端321，第十三晶体管M13的漏极耦合至第二阻 抗电路33的输出端332，第十二晶体管M12的源极和第十三晶体管M13的源极均接地；第十二晶体管M12的栅极与第十三晶体管M12的栅极均连接信号控制器。需要说明的是，通过信号控制器向第十二晶体管M12的栅极输入的电平与向第十晶体管M10的栅极输入的电平相反，通过信号控制器向第十三晶体管M13的栅极输入的电平与向第十一晶体管M11的栅极输入的电平相反。
第十二晶体管M12和第十三晶体管M13，用于在第二衰减调节电路35独立工作情况下，将衰减可调电路的交流电压导地。
本申请实施例中，当信号控制器的输出端SR3输出电平为低电平，即第三衰减调节电路处于非工作态时，第十晶体管M10和第十一晶体管M11有交流电压(此时，第十晶体管M10和第十一晶体管M11有交流电压相当于大的电容)，由于第十二晶体管M12和第十三晶体管M13的栅极输入的是高电平，因此，该第十二晶体管M12和第十三晶体管M13可以将交流电压导地，从而使得第三衰减调节电路的输出端不输出信号，即使得第三衰减调节电路不干扰其他衰减调节电路(第一衰减调节电路34)的输出信号。综上，第十二晶体管M12和第十三晶体管M13的作用是提升第三衰减调节电路的隔离度。
可选地，第十二晶体管M12和第十三晶体管M13可以为参数相同的N沟道的MOS晶体管。第十二晶体管M12的栅极和第十三晶体管M13的栅极耦合在一起，并连接信号控制器的输出端SK3，或者通过反相器连接上述SR3，反相器的输出端为SR3B，输出端SR3B的电平与输出端SR3的电平相反。
综上所述，可知，在本申请实施例中，信号控制器用于向衰减可调电路提供数字控制信号，以控制上述第一衰减调节电路、第二衰减调节电路以及第三衰减调节电路的工作状态，衰减调节电路的工作状态包括工作态或非工作态。
结合图23，可选地，当衰减可调电路的第一衰减调节电路、第二衰减调节电路以及第三衰减调节电路不同的工作状态时，该衰减可调电路可以模拟不同衰减范围的SerDes信道。如下表1为各个衰减调节电路的工作状态与适用的SerDes信道的对应关系的示例。
表1
SerDes信道 第一衰减调节电路 第二衰减调节电路 第三衰减调节电路
第一SerDes信道 非工作态 非工作态 工作态
第二SerDes信道 非工作态 工作态 工作态
第三SerDes信道 工作态 非工作态 工作态
第四SerDes信道 工作态 非工作态 非工作态
结合表1，当信号控制器的输出端SR2输出高电平时，第一衰减调节电路处于工作态，当信号控制器的输出端SR2输出低电平时，第一衰减调节电路处于非工作态；当信号控制器的输出端SR1输出高电平时，第二衰减调节电路处于工作态，当信号控制器的输出端SR1输出低电平时，第二衰减调节电路处于非工作态；当信号控制器的输出端SR3输出高电平时，第三衰减调节电路处于工作态，当信号控制器的输出端SR3输出低电平时，第三衰减调节电路处于非工作态。
本申请实施例中，上述第一SerDes信道、第二SerDes信道、第三SerDes信道以 及第四SerDes信道的衰减范围依次减小。
综上，本申请实施例提供的基于RLGC电路模型的衰减可调电路，可以根据实际应用中对衰减值的需求调节衰减可调电路，使其衰减值达到预期的值，如此，针对不同衰减范围的SerDes信道，可以通过控制衰减可调电路中的各个调节电路的工作状态，实现对不同衰减范围的SerDes信道进行模拟，该衰减可调电路具有较好的适用性。
基于上述实施例对衰减可调电路的描述，如图24所示，本申请实施例还提供一种衰减可调芯片，该衰减可调芯片可以包括多个如上述实施例所述的基于RLGC电路模型的衰减可调电路，其中，该多个衰减可调电路分为多组衰减可调电路，多组衰减可调电路对称排布。
结合图24，如图25所示，本申请实施例提供的衰减可调芯片还包括信号控制器，上述多个衰减可调电路中的每一个衰减可调电路按照图23所示的连接方式与信号控制器连接，该信号控制器用于为多个衰减可调电路提供数字控制信号，以控制多个衰减可调电路的工作状态，以调节衰减可调电路的衰减值。
例如，信号控制器通过不同的通信协议(例如包括但不限于IIC等通信协议)控制该信号控制器的不同的输出端(例如SR1、SR2、SR3)为衰减可调电路提供数字控制信号，使得上述衰减可调电路中的各个衰减调节电路处于工作态或者非工作态，并且通过不同的输出端(例如SW1、SW2、SC1至SCN)对衰减可调电路的衰减值进行调节。具体可以参考上述实施例的描述，此处不再详述。
本申请实施例提供的衰减可调芯片是一种多通道的衰减可调芯片，衰减可调芯片中的衰减可调电路的数量可以根据实际需求设定，本申请实施例不作具体限定。在图24中所示的衰减可调芯片中，衰减可调电路的数量为M，M为大于或等于2的正整数。
在一种实现方式中，衰减可调芯片可以为24通道的芯片，即衰减可调芯片包括24个如图23所示的衰减可调电路。
本申请实施例提供的衰减可调芯片可以适用于多个SerDes并行工作的场景，例如多个SerDes信道同时传输信号的场景，上述信号控制器输出独立的控制信号分别调节不同的SerDes信道的衰减值。可知，该衰减可调芯片中的每一个衰减可调电路可以独立工作，互不影响，并且衰减可调芯片的集成度高，面积小。
针对本申请实施例提供的衰减可调芯片，对衰减可调芯片进行封装时，将衰减可调芯片中的多个衰减可调电路分为多组衰减可调电路，该多组衰减可调电路对称地放置于封装基板上。例如，假设衰减可调芯片包括24个衰减可调电路，将24个衰减可调电路平均分为4组，每一组包括6个衰减可调电路，将该4组衰减可调电路对称地放置在封装基板上。然后，对多组衰减可调电路分别进行布线，以封装衰减可调芯片，图26示意的是一种衰减可调芯片的封装效果图。
可以理解的是，上述对衰减可调芯片的封装方法是一种小型化的多DIE合封技术，上述每一组衰减可调电路可以称为一个DIE，该封装方法不但可以减小封装走线的长度，使得封装走线对信号造成的衰减值(即插入损耗)减小，而且该衰减可调芯片的各项指标均达标，例如隔离度、串扰都达到预期指标。
通过实验研究，在封装基板上的引脚的距离为0.8mm(即ball pitch为0.8mm)的情况下，按照本申请实施例提供的衰减可调芯片的封装方法，对上述包含24个衰减可 调电路的衰减可调芯片进行封装，该衰减可调芯片的封装面积为16毫米(mm)×16mm，封装走线中的最长的走线的长度小于5mm，封装走线的衰减值小于1dB，封装后的整个衰减可调芯片的衰减值小于3dB。并且，封装走线的阻抗为90欧姆，并且误差为±8％，近端串扰小于-50dB，远端串扰小于-50dB。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种基于RLGC电路模型的衰减可调电路，其特征在于，包括：开关电容阵列电路、第一阻抗电路以及第二阻抗电路；
    其中，所述第一阻抗电路的输入端耦合至所述衰减可调电路的输入端，所述第一阻抗电路的输出端连接所述第二阻抗电路的输入端，所述第二阻抗电路的输出端耦合至所述衰减可调电路的输出端，所述第一阻抗电路的输出端和所述第二阻抗电路的输入端分别连接所述开关电容阵列电路的第一端，所述开关电容阵列电路的第二端接地；所述第一阻抗电路和所述第二阻抗电路包括电感元件和电阻元件，所述开关电容阵列电路包括电容元件和开关元件；
    所述开关电容阵列电路，用于在第一衰减范围内调节所述衰减可调电路的衰减值。
  2. 根据权利要求1所述的衰减可调电路，其特征在于，
    所述开关电容阵列电路，具体用于通过调节所述衰减可调电路的电容值和电导值，在所述第一衰减范围内调节所述衰减可调电路的衰减值。
  3. 根据权利要求1或2所述的衰减可调电路，其特征在于，
    所述开关电容阵列电路由N个电容元件以及N个开关元件形成的N个开关电容模块并联组成，所述第i个开关电容模块的第一端耦合至所述开关电容阵列电路的第一端，所述第i个开关电容模块的第二端耦合至所述开关电容阵列电路的第二端；N为大于或等于2的正整数，i为1，2，……，N中的任意一个值；其中，所述N个电容元件中的第i个电容元件与所述N个开关元件中的第i个开关元件串联形成所述开关电容阵列电路的第i个开关电容模块；
    所述N个开关元件，用于控制所述N个电容元件中的一个或多个电容元件接入或者不接入所述衰减调节电路，以调节所述衰减可调电路的电容值和电导值。
  4. 根据权利要求3所述的衰减可调电路，其特征在于，所述N个开关元件为N个晶体管；
    所述N个晶体管中的第i个晶体管的漏极连接所述第i个电容元件的第一端，所述第i个晶体管的源极耦合至所述第i个开关电容模块的第二端，所述第i个晶体管的栅极连接信号控制器，所述第i个电容的第二端耦合至所述开关电容模块的第一端。
  5. 根据权利要求1至4任一项所述的衰减可调电路，其特征在于，
    所述第一阻抗电路包括第一电阻元件和第一电感元件，所述第一电阻元件和所述第一电感元件并联；其中，所述第一电阻元件的第一端和所述第一电感元件的第一端耦合至所述第一阻抗电路的输入端，所述第一电阻元件的第二端和所述第一电感元件的第二端耦合至所述第一阻抗电路的输出端；
    所述第二阻抗电路包括第二电阻元件和第二电感元件，所述第二电阻元件和所述第二电感元件并联；其中，所述第二电阻元件的第一端和所述第二电感元件的第一端耦合至所述第二阻抗电路的输入端，所述第二电阻元件的第二端和所述第二电感元件的第二端耦合至所述第二阻抗电路的输出端。
  6. 根据权利要求1至5任一项所述的衰减可调电路，其特征在于，所述衰减可调电路还包括第一衰减调节电路，所述第一衰减调节电路的输入端耦合至所述衰减可调电路的输入端，所述第一衰减调节电路的输出端耦合至所述衰减可调电路的输出端； 所述第一衰减调节电路包括电感元件和开关元件；
    所述第一衰减调节电路和所述开关电容阵列电路，用于在第二衰减范围内调节所述衰减可调电路的衰减值；其中，所述第一衰减调节电路，用于调节所述衰减可调电路的电感值和电阻值，所述开关电容阵列电路，用于调节所述衰减可调电路的电容值和电导值。
  7. 根据权利要求6所述的衰减可调电路，其特征在于，
    所述第一衰减调节电路包括第三电感元件、第一开关元件和第二开关元件；其中，所述第一开关元件、所述第三电感元件和所述第二开关元件依次串联；
    所述第一开关元件和所述第二开关元件，用于控制所述第三电感元件接入所述衰减可调电路或者不接入所述衰减可调电路，以调节所述衰减可调电路的电感值和电阻值。
  8. 根据权利要求6或7所述的衰减可调电路，其特征在于，所述开关元件为晶体管，且所述第一开关元件为第一晶体管，所述第二开关元件为第二晶体管；
    其中，所述第一晶体管的漏极耦合至所述第一衰减调节电路的输入端，所述第一晶体管的源极连接所述第三电感元件的第一端，所述第二晶体管的源极连接所述第三电感元件的第二端，所述第二晶体管的漏极耦合至所述第一衰减调节电路的输出端；所述第一晶体管的栅极和所述第二晶体管的栅极连接所述信号控制器。
  9. 根据权利要求6至8任一项所述的衰减可调电路，其特征在于，所述第一衰减调节电路还包括第三晶体管和第四晶体管；其中，所述第三晶体管的漏极连接所述第一晶体管的源极，所述第四晶体管的漏极连接所述第二晶体管的源极，所述第三晶体管的源极和所述第四晶体管的源极均接地，所述第三晶体管的栅极和所述第四晶体管的栅极均连接所述信号控制器；通过所述信号控制器向所述第三晶体管的栅极输入的电平与向所述第一晶体管的栅极输入的电平相反，通过所述信号控制器向所述第四晶体管的栅极输入的电平与向所述第二晶体管的栅极输入的电平相反；
    所述第三晶体管和所述第四晶体管，用于在所述第一衰减调节电路不接入所述衰减可调电路的情况下，将所述第一衰减调节电路的交流电压导地。
  10. 根据权利要求1至9任一项所述的衰减可调电路，其特征在于，所述衰减可调电路还包括第二衰减调节电路，所述第二衰减调节电路的输入端耦合至所述衰减可调电路的输入端，所述第二衰减调节电路的输出端耦合至所述衰减可调电路的输出端；所述第二衰减调节电路包括电感元件、电容元件以及开关元件；
    所述第二衰减调节电路和所述开关电容阵列电路，用于在第三衰减范围内调节所述衰减可调电路的衰减值；其中，所述第二衰减调节电路，用于调节所述衰减可调电路的电感值和电阻值，或者调节所述衰减可调电路的电感值、电阻值、电容值以及电导值；所述开关电容阵列电路，用于调节所述衰减可调电路的电容值和电导值。
  11. 根据权利要求10所述的衰减可调电路，其特征在于，
    所述第二衰减调节电路包括第四电感元件、第三开关元件、第四开关元件、第一开关电容模块以及第二开关电容模块；其中，所述第三开关元件的第一端耦合至所述衰减可调电路的输入端，所述第三开关元件的第二端连接所述第四电感元件的第一端和所述第一开关电容模块的第一端，所述第一开关电容模块的第二端接地；所述第四 开关元件的第一端耦合至所述衰减可调电路的输出端，所述第四开关元件的第二端连接所述第四电感元件的第二端和所述第二开关电容模块的第一端，所述第二开关电容模块的第二端接地；
    所述第三开关元件和所述第四开关元件，用于控制所述第四电感元件接入所述衰减可调电路或者不接入所述衰减可调电路，以调节所述衰减可调电路的电感值和电阻值。
  12. 根据权利要求11所述的衰减可调电路，其特征在于，
    所述第一开关电容模块由第一电容元件和第五开关元件串联形成，所述第二开关电容模块由第二电容元件和第六开关元件串联形成；
    所述第五开关元件，用于控制所述第一电容元件接入或者不接入所述衰减调节电路，以调节所述衰减可调电路的电容值和电导值；
    所述第六开关元件，用于控制所述第二电容元件接入或者不接入所述衰减调节电路，以调节所述衰减可调电路的电容值和电导值。
  13. 根据权利要求12所述的衰减可调电路，其特征在于，所述第五开关元件和第六开关元件为晶体管，并且所述第五开关元件为第五晶体管，所述第六开关元件为第六晶体管；所述第三开关元件和第四开关元件为晶体管，并且所述第三开关元件为第七晶体管，所述第四开关元件为第八晶体管；
    其中，所述第七晶体管的漏极耦合至所述第二衰减调节电路的输入端，所述第七晶体管的源极连接所述第四电感元件的第一端；所述第四电感元件的第二端连接所述第八晶体管的源极，所述第八晶体管的漏极耦合至所述第二衰减调节电路的输出端；所述第七晶体管的栅极和所述第八晶体管的栅极连接所述信号控制器；
    所述第五晶体管的漏极连接所述第一电容元件的第一端，所述第一电容元件的第二端连接所述第七晶体管的源极，所述第六晶体管的漏极连接所述第二电容元件的第一端，所述第二电容元件的第二端连接所述第八晶体管的源极，所述第五晶体管的源极和所述第六晶体管的源极均接地，所述第五晶体管的栅极和所述第六晶体管的栅极分别连接所述信号控制器。
  14. 根据权利要求10至13任一项所述的衰减可调电路，其特征在于，所述第二衰减调节电路还包括第九晶体管；所述第九晶体管的源极接地，所述第九晶体管的漏极连接所述第四电感元件的第二端，所述第九晶体管的栅极连接所述信号控制器；通过所述信号控制器向所述第九晶体管的栅极输入的电平与向所述第八晶体管的栅极输入的电平相反；
    所述第九晶体管，用于在所述第二衰减调节电路处于不接入所述衰减可调电路的情况下，将所述第二衰减调节电路的交流电压导地。
  15. 根据权利要求10至14任一项所述的衰减可调电路，其特征在于，所述衰减可调电路还包括第七开关元件和第八开关元件；
    所述第七开关元件和所述第八开关元件，用于控制所述第二衰减调节电路是否独立工作；
    当所述第七开关元件和所述第八开关元件未导通时，所述衰减可调电路中仅包括所述第二衰减调节电路，所述第二衰减调节电路独立工作；所述第二衰减调节电路， 用于在第四衰减范围内调节所述衰减可调电路的衰减值。
  16. 根据权利要求10至14任一项所述的衰减可调电路，其特征在于，所述第七开关元件和所述第八开关元件为晶体管，并且所述第七开关元件为第十晶体管，所述第八开关元件为第十一晶体管；
    其中，所述第十晶体管的漏极耦合至所述衰减可调电路的输入端，所述第十晶体管的源极耦合至所述第一阻抗电路的输入端和所述第一衰减调节电路的输入端，所述第十一晶体管的漏极耦合至所述衰减可调电路的输出端，所述第十一晶体管的源极耦合至所述第二阻抗电路的输出端和所述第一衰减调节电路的输出端；所述第十晶体管的栅极和所述第十一晶体管的栅极连接所述信号控制器。
  17. 根据权利要求10至16任一项所述的衰减可调电路，其特征在于，所述衰减可调电路还包括第十二晶体管和第十三晶体管；其中，所述第十二晶体管的漏极耦合至所述第一阻抗电路的输入端，所述第十三晶体管的漏极耦合至所述第二阻抗电路的输出端，所述第十二晶体管的源极和所述第十三晶体管的源极均接地；所述第十二晶体管的栅极与所述第十三晶体管的栅极均连接所述信号控制器；通过所述信号控制器向所述第十二晶体管的栅极输入的电平与向所述第十晶体管的栅极输入的电平相反，通过所述信号控制器向所述第十三晶体管的栅极输入的电平与向所述第十一晶体管的栅极输入的电平相反；
    所述第十二晶体管和所述第十三晶体管，用于在所述第二衰减调节电路独立工作情况下，将所述衰减可调电路的交流电压导地。
  18. 一种衰减可调芯片，其特征在于，包括：多个如权利要求1至17任一项所述的衰减可调电路，所述多个衰减可调电路分为多组衰减可调电路，所述多组衰减可调电路对称排布。
  19. 根据权利要求18所述的衰减可调芯片，其特征在于，所述衰减可调芯片还包括信号控制器；
    所述信号控制器用于为所述多个衰减可调电路提供数字控制信号，以控制所述多个衰减可调电路的工作状态。
PCT/CN2022/079957 2021-05-21 2022-03-09 基于rlgc电路模型的衰减可调电路及芯片 WO2022242273A1 (zh)

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