WO2022242031A1 - 阵列基板、显示面板 - Google Patents

阵列基板、显示面板 Download PDF

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Publication number
WO2022242031A1
WO2022242031A1 PCT/CN2021/126090 CN2021126090W WO2022242031A1 WO 2022242031 A1 WO2022242031 A1 WO 2022242031A1 CN 2021126090 W CN2021126090 W CN 2021126090W WO 2022242031 A1 WO2022242031 A1 WO 2022242031A1
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Prior art keywords
substrate
orthographic projection
light
contact
sub
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PCT/CN2021/126090
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English (en)
French (fr)
Inventor
霍培荣
李波
刘鹏
张永强
徐敬义
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2022242031A1 publication Critical patent/WO2022242031A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • Liquid crystal displays occupy an important position in the display field, and have been widely used in products with display functions such as televisions, mobile phones, and computers. With the continuous improvement of user requirements, high pixel density (Pixels Per Inch, PPI) products will emerge. In order to have high-definition, thin and light product quality, liquid crystal displays need to meet the design requirements of small screen size, high pixel density, and high brightness of the backlight source. However, the light leakage current of the products meeting these requirements is very serious, which causes serious flicker (Flicker) phenomenon and greatly reduces the display quality.
  • Embodiments of the present application provide an array substrate and a display panel
  • an array substrate including a substrate and a plurality of sub-pixels arranged in an array arranged on the substrate; the sub-pixels include a light-shielding layer, a semiconductor layer and , gate layer, source-drain layer and pixel electrode layer;
  • the semiconductor layer includes a first contact portion, a first channel portion, a doped portion, a second channel portion, and a second contact portion connected in sequence;
  • the gate layer includes a first gate and a second gate;
  • the source-drain layer includes a first electrode and a second electrode;
  • the pixel electrode layer includes a pixel electrode; the first electrode is electrically connected to the first contact portion and the pixel electrode, and the second electrode is electrically connected to the pixel electrode.
  • the second contact portion is electrically connected;
  • first channel portion and the first gate overlap along a direction perpendicular to the substrate
  • second channel portion and the second gate overlap along a direction perpendicular to the substrate. direction overlap
  • the orthographic projection of the light-shielding layer on the substrate at least covers the orthographic projection of the first channel portion, the second channel portion and part of the first contact portion on the substrate.
  • the gate layer further includes gate lines
  • the first gate is a portion where the gate line overlaps the first channel portion along a direction perpendicular to the substrate
  • the second gate is a portion of the gate line that overlaps the first channel portion along a direction perpendicular to the substrate. a portion whose direction overlaps with the second channel portion;
  • the gate line extends along a first direction
  • the orthographic projection of the doped portion on the substrate is located on a first side of the orthographic projection of the gate line on the substrate
  • the orthographic projection of the second contact portion on the substrate is located on a second side of the orthographic projection of the grid line on the substrate, and the first side is opposite to the second side.
  • the light-shielding layer extends along the first direction, and the orthographic projection of the grid lines on the substrate is located within the orthographic projection of the light-shielding layer on the substrate.
  • the light-shielding layer includes at least an overlapping portion and a first portion, the overlapping portion extends along the first direction, and the orthographic projection on the substrate is the same as that of the gate line on the substrate.
  • the orthographic projections on the substrate are coincident, the orthographic projections of the first portion on the substrate are located on the second side of the orthographic projections of the gridlines on the substrate;
  • the first contact portion includes a first contact sub-portion and a first doped sub-portion, the first doped sub-portion is disposed between the first contact sub-portion and the first channel portion, the the first contact subpart is electrically connected to the first pole;
  • the orthographic projection of the first doped sub-portion on the substrate is located within the orthographic projection of the first portion on the substrate; and/or, the first contact sub-portion is located on the substrate
  • the orthographic projection on the base is within the orthographic projection of the first portion on the substrate.
  • the orthographic projection of the second contact portion on the substrate does not overlap with the orthographic projection of the first portion on the substrate, and the orthographic projection of the doped portion on the substrate The projection does not overlap with the orthographic projection of the light-shielding layer on the substrate.
  • the orthographic projection of the first contact sub-portion on the substrate is located within the orthographic projection of the first part on the substrate, and the first doped sub-portion is located on the substrate In the case where the orthographic projection on the base and the orthographic projection of the first portion on the substrate do not overlap, the first portion is not connected to the overlapping portion.
  • the second contact portion includes a second contact sub-portion and a second doped sub-portion, and the second doped sub-portion is disposed between the second contact sub-portion and the second channel portion Between, the second contact sub-part is electrically connected to the second pole;
  • At least part of the orthographic projection of the second doped sub-portion on the substrate is located within the orthographic projection of the first portion on the substrate.
  • the orthographic projection of the second contact subsection on the substrate does not overlap with the orthographic projection of the first part on the substrate.
  • the orthographic projection of the first doped sub-portion on the substrate is located within the orthographic projection of the first part on the substrate, and the first contact sub-portion is located on the substrate
  • the first portion extends along the first direction and is connected to the overlapping portion.
  • the length of the second doped subsection along the second direction is greater than the length of the first doped subsection along the second direction
  • the width of the first portion along the second direction is the same as the length of the first doped sub-section along the second direction, and the second direction is perpendicular to the first direction;
  • the orthographic projection on the substrate does not overlap with the orthographic projection of the light-shielding layer on the substrate.
  • the light-shielding layer further includes a second part, and the orthographic projection of the second part on the substrate is located on the first side of the orthographic projection of the grid lines on the substrate;
  • the orthographic projection of the second portion on the substrate partially overlaps the orthographic projection of the doped portion on the substrate, and the width of the second portion along the second direction is smaller than that of the first portion width along the second direction.
  • the orthographic projections of the first doped subsection and the second doped subsection on the substrate are located within the orthographic projection of the first part on the substrate, and the In the case where the orthographic projections of the first contact subsection, the second contact subsection and the doped section on the substrate do not overlap with the orthographic projection of the first part on the substrate, the The first part includes a first subsection and a second subsection, both of the first subsection and the second subsection are connected to the overlapping part, and the first doped subsection is on the substrate
  • the orthographic projection of the first subdivision on the substrate lies within the orthographic projection of the second doped subdivision on the substrate, and the orthographic projection of the second doped subdivision on the substrate lies within the second subdivision on the substrate within the orthographic projection on .
  • the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate, and the boundary shape of the orthographic projection of the light-shielding layer on the substrate is It is the same as the boundary shape of the orthographic projection of the semiconductor layer on the substrate.
  • the light-shielding layer includes a first light-shielding portion and a second light-shielding portion that are not connected, and the orthographic projection of the first light-shielding portion on the substrate at least covers the first grid on the substrate.
  • the orthographic projection on the substrate and the partial orthographic projection of the first contact portion on the substrate, the orthographic projection of the second light shielding portion on the substrate at least covers the second grid on the substrate. The orthographic projection on and the partial orthographic projection of the second contact portion on the substrate.
  • a display panel including an opposite color filter substrate and the above-mentioned array substrate;
  • the color filter substrate includes a black matrix
  • the black matrix on the substrate of the array substrate orthographically projects the orthographic projection of the light-shielding layer covering the array substrate on the substrate.
  • FIG. 1 is an energy level diagram of a semiconductor layer provided in an embodiment of the present application
  • FIG. 2 is a comparison diagram of leakage currents of an NMOS transistor and a PMOS transistor before and after illumination according to an embodiment of the present application;
  • Fig. 3 is a comparison diagram of leakage currents of different samples under different lighting environments provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a driving process provided by an embodiment of the present application.
  • Fig. 6a is a schematic structural diagram of another array substrate provided by the embodiment of the present application.
  • Fig. 6b is a schematic structural diagram of another array substrate provided in the embodiment of the present application.
  • Fig. a1 is a schematic structural diagram of a light-shielding layer provided by the embodiment of the present application
  • Fig. a2 is a schematic structural diagram of a semiconductor layer formed on the basis of Fig. a1
  • Fig. a3 is a structural schematic diagram of a gate line formed on the basis of Fig. a2 ;
  • Figure a4 is a schematic structural diagram of another light-shielding layer provided by the embodiment of the present application
  • Figure a4 is a schematic structural diagram of a semiconductor layer formed on the basis of Figure a5
  • Figure a6 is a structure with gate lines formed on the basis of Figure a5 schematic diagram
  • Figure 8a is a cross-sectional view along the CD direction of a3 figure in Figure 7a;
  • Figure 8b is a cross-sectional view along the CD direction of a6 figure in Figure 7b;
  • Fig. b1 is a schematic structural diagram of a light-shielding layer provided by the embodiment of the present application
  • Fig. b2 is a schematic structural diagram of a semiconductor layer formed on the basis of Fig. b1
  • Fig. b3 is a structural schematic diagram of a gate line formed on the basis of Fig. b2 ;
  • Fig. 10 is a sectional view along the CD direction of b3 diagram in Fig. 9;
  • Figure c1 is a schematic structural diagram of a light-shielding layer provided by the embodiment of the present application
  • Figure c2 is a schematic structural diagram of a semiconductor layer formed on the basis of Figure c1
  • Figure c3 is a structural schematic diagram of a gate line formed on the basis of Figure c2 ;
  • Fig. 12 is a sectional view along the CD direction of c3 diagram in Fig. 11;
  • Figure d1 is a schematic structural diagram of a light-shielding layer provided by the embodiment of the present application
  • Figure d2 is a schematic structural diagram of a semiconductor layer formed on the basis of Figure d1
  • Figure d3 is a structural schematic diagram of a gate line formed on the basis of Figure d2 ;
  • Fig. 14 is a cross-sectional view along the CD direction of d3 diagram in Fig. 13;
  • Figure e1 is a schematic structural diagram of a light-shielding layer provided by the embodiment of the present application
  • Figure e2 is a schematic structural diagram of a semiconductor layer formed on the basis of Figure e1
  • Figure e3 is a structural schematic diagram of a gate line formed on the basis of Figure e2 ;
  • Fig. 16 is a cross-sectional view along the CD direction of e3 diagram in Fig. 15;
  • a1 figure and a2 figure are two kinds of electron microscope pictures respectively;
  • FIG. 18 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or None to imply that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation should therefore not be construed as limiting the application.
  • the liquid crystal display panel includes a relative array substrate and a color filter substrate, and a liquid crystal arranged between the array substrate and the color filter substrate; since the liquid crystal cannot emit light, in order to realize the display, the liquid crystal display panel also includes a backlight, which can be arranged in the array The side of the substrate away from the color filter substrate. The light emitted by the backlight passes through the array substrate, liquid crystal, and color filter substrate in turn. Because the liquid crystal molecules will be twisted under the action of the electric field, the amount of light passing through can be changed, thereby realizing the display of different images.
  • the array substrate includes a plurality of sub-pixels arranged in an array, and the electric field generated by each sub-pixel is generally controlled by a thin film transistor, thereby controlling the deflection of the liquid crystal.
  • the semiconductor layer of a thin film transistor is easily affected by light, thereby generating leakage current.
  • TFT Thin Film Transistor
  • the Fermi level E Fi of the n-type semiconductor 100 is higher than the intrinsic Fermi level E F .
  • the carriers mainly come from the intrinsic excitation, and the Fermi level is close to the intrinsic Fermi level at this time.
  • the semiconductor is irradiated with light with photon energy h ⁇ Eg (band gap width), at this time the equilibrium condition is destroyed, and the semiconductor is in a non-equilibrium state deviated from the equilibrium state.
  • Ec represents the bottom of the conduction band, that is, the lowest energy level of the conduction band; Ev represents the top of the valence band.
  • the leakage current Ioff after illumination is greater than the leakage current Ioff before illumination; in Figure 2, the abscissa Vg represents the gate voltage of the transistor, and the ordinate Id represents the transistor gate voltage. drain-source current.
  • the main influencing variable of leakage current increase is illumination, and the intensity of illumination is positively correlated with the value of illumination leakage current.
  • the pixel density and the brightness of the backlight are designed to be very high, which leads to the serious light leakage current of high PPI products, and the light leakage current will cause flicker (Flicker) problem, Significantly reduces the display effect.
  • the array substrate includes a plurality of gate lines 101 and a plurality of data lines 102, the gate lines 101 are electrically connected to the gates of the TFTs 104 of each row of sub-pixels, and the data lines 102 are electrically connected to one electrode of the TFTs 104 of each column of sub-pixels. connection; in each sub-pixel, the other pole of the TFT 104 is electrically connected to the pixel electrode 103 .
  • the driving process of a sub-pixel TFT as an example, the principle of flickering is described.
  • the Vgate signal is input to the gate through the gate line; when the voltage of the Vgate signal is high, the TFT is turned on, and the data line outputs a positive polarity Vdata + signal to charge the TFT, so that the pixel electrode
  • the voltage becomes Vd + ; however, due to the existence of parasitic capacitance, the voltage of the pixel electrode will be pulled down by ⁇ Vp; then, the voltage of the Vgate signal becomes low level, and the TFT enters the holding phase.
  • the voltage of the pixel electrode remains at the charging voltage until the next charging; however, if affected by light, the TFT will generate a leakage current, so that the voltage of the pixel electrode will continue to decrease with the increase of the holding time.
  • the voltage of the Vgate signal is at a high level, the TFT is turned on, the data line outputs a negative polarity Vdata - signal, and the TFT is discharged and reversely charged, so that the voltage of the pixel electrode becomes Vd - ; but due to the existence of parasitic capacitance , the voltage of the pixel electrode will be pulled down by ⁇ Vp; then, the voltage of the Vgate signal becomes low level, and the TFT enters the holding phase.
  • the voltage of the pixel electrode will always maintain the charging voltage before the next charge; however, if affected by light, the TFT will generate a leakage current, so that the absolute value of the voltage of the pixel electrode will continue to decrease with the increase of the holding time.
  • the brightness of the sub-pixels is different between two adjacent frames, so that human eyes can recognize the flicker. If the column inversion driving method is used, there will be obvious shaking head and vertical lines in the actual use process, which will greatly reduce the display quality.
  • Vcom refers to the voltage of the common electrode, and the pixel electrode and the common electrode form an electric field to make the liquid crystal molecules twist.
  • the Vcom voltage can be (Vd + +Vd - )/2, but due to the existence of parasitic capacitance, the voltage of the pixel electrode will be pulled down by ⁇ Vp.
  • the Vcom voltage can be compensated, that is, the Vcom voltage shown in FIG. 5 can be used, and the voltage value is less than (Vd + +Vd - )/2.
  • the embodiment of the present application provides an array substrate, as shown in FIG.
  • the semiconductor layer includes a first contact portion 31, a first channel portion 123, a doped portion 124, a second channel portion 125, and a second contact portion 32 connected in sequence;
  • the gate layer includes a first gate 131 and a second gate 132;
  • the source and drain layers include a first pole 141 and a second pole 142;
  • One pole 141 is electrically connected to the first contact portion and the pixel electrode 15 respectively, and the second pole is electrically connected to the second contact portion.
  • the first pole 141 is electrically connected to the first contact sub-portion 121 of the first contact portion
  • the second pole 142 is electrically connected to the second contact sub-portion 127 of the second contact portion as an example for illustration.
  • the orthographic projection of the light-shielding layer on the substrate at least covers the orthographic projection of the first channel part, the second channel part and part of the first contact part on the substrate.
  • the orthographic projection of the light-shielding layer 11 on the substrate 1 covers at least the first channel portion 123, the second channel portion 125, and the first doped sub-portion 122 of the first contact portion on the substrate 1. Orthographic projection is used as an example to draw.
  • the material of the light-shielding layer may be an opaque metal material, such as molybdenum, aluminum, aluminum neodymium alloy and the like.
  • the shape of the light-shielding layer is not limited, and may be specifically determined according to the semiconductor layer and the gate layer.
  • the orthographic projection of the light-shielding layer on the substrate refers to the projection of the light-shielding layer on the substrate along a direction perpendicular to the substrate. The orthographic projections of the remaining film layers on the substrate are similar, and will not be described later.
  • the above-mentioned orthographic projection of the light-shielding layer on the substrate can cover the orthographic projection of part of the first contact portion on the substrate, or can also cover the orthographic projection of all the first contact portions on the substrate; of course, the light-shielding layer can also cover The orthographic projection of structures such as the second contact part and the doped part on the substrate.
  • the overall shape of the sequentially connected first contact portion, first channel portion, doped portion, second channel portion and second contact portion is not limited.
  • the overall shape may be straight, U-shaped, etc.; in consideration of saving space, the U-shape may be adopted.
  • the semiconductor layer may be an N-type semiconductor layer.
  • the above-mentioned array substrate may also include a plurality of gate lines 101 and a plurality of data lines 102 crossing each other, and the gate lines 101 are connected to the first gate G1 and the second gate of each row of sub-pixels 2 G2 is electrically connected, and the data line 102 is electrically connected to the second electrode C2 of each row of sub-pixels 105 ; in each sub-pixel, the first electrode C1 is electrically connected to the pixel electrode 103 .
  • the data line can be arranged on the same layer as the first pole and the second pole, and the data line is connected to the second pole; or, the second pole is the part where the data line overlaps with the second contact portion along a direction perpendicular to the substrate.
  • a gate insulating layer 21 is provided; an interlayer dielectric layer 22 may also be provided between the gate layer and the source-drain layer, and the first electrode 141 may be connected to the first contact through a first via hole penetrating the interlayer dielectric layer 22 and the gate insulating layer 21.
  • the second electrode 142 can be electrically connected to the second contact part through the second via hole penetrating the interlayer dielectric layer 22 and the gate insulating layer 21; a second insulating layer can also be arranged between the source drain layer and the pixel electrode layer 23.
  • the pixel electrode 15 can be electrically connected to the first electrode 141 through a via hole penetrating the second insulating layer 23; a common electrode layer can also be provided on the side of the pixel electrode layer away from the source and drain layers, and the common electrode layer can include a common electrode 25, An electric field can be formed between the common electrode 25 and the pixel electrode 15 to drive the liquid crystal to deflect.
  • the array substrate may also include other film layers and structures, and only the film layers and structures related to the invention are introduced here, and other structures can be obtained from related technologies, and will not be repeated here.
  • the above array substrate can be applied to TN (Twisted Nematic, twisted nematic) type, VA (Vertical Alignment, vertical alignment) type, IPS (In-Plane Switching, plane conversion) type or ADS (Advanced Super Dimension Switch, advanced super dimension field conversion) type liquid crystal display panels, and any products or components with display functions such as televisions, digital cameras, mobile phones, and tablet computers that include these liquid crystal display panels.
  • TN Transmission Nematic, twisted nematic
  • VA Vertical Alignment, vertical alignment
  • IPS In-Plane Switching, plane conversion
  • ADS Advanced Super Dimension Switch, advanced super dimension field conversion
  • the transistor formed by the semiconductor layer, the gate layer, and the source-drain layer is a top-gate double-gate transistor, and the double-gate transistor can be an LTPS (Low Temperature Poly-silicon, low temperature polysilicon) transistor, an oxide transistor, or a non-conductive transistor.
  • the crystalline silicon type transistor is not limited here. In large-size, high-PPI products, LTPS transistors are widely used.
  • the leakage current of a double-gate transistor is smaller than that of a single-gate transistor.
  • transistors can be divided into N-type transistors and P-type transistors.
  • An N-type transistor is taken as an example for description below.
  • An N-type transistor may include a gate, a source, and a drain, wherein the source and drain may be interchanged.
  • the low-level end is called the source
  • the high-level end is called the drain, and the current flows from the drain to the source.
  • N-type transistors When N-type transistors are applied to the display panel, when the positive frame is displayed (that is, driven by the positive polarity data signal Vdata + shown in Figure 5), the side of the pixel electrode is at a low potential, and the electrode of the transistor electrically connected to the pixel electrode is the source pole, the data line side is at a high potential, and the electrode of the transistor electrically connected to the data line is a drain.
  • the negative frame is displayed (that is , driven by the negative polarity data signal Vdata- shown in Figure 5)
  • the pixel electrode side is at a high potential
  • the electrode of the transistor electrically connected to the pixel electrode is a drain
  • the data line side is at a low potential
  • the electrode of the transistor electrically connected to the data line is the source.
  • the source and drain of the N-type transistor will change.
  • the positive frame leakage current is higher than the negative frame leakage current, and the "tail lift" of the cut-off region in the transfer characteristic curve is serious (indicating that the positive frame leakage current is serious).
  • the first pole is electrically connected to the first contact portion and the pixel electrode respectively, and the second pole may be electrically connected to the second contact portion and the data line respectively.
  • the first pole when it is driven by a positive polarity data voltage, the first pole may be called a source, and the second pole may be called a drain.
  • the principle of reducing the leakage current of the present application will be described below.
  • the region In the positive frame holding stage of the transistor, if the depletion region at the edge of the channel is illuminated, the region can be excited to generate electron-hole pairs, and some electrons can jump to the edge of the conduction band after gaining a certain energy (for example: energy greater than 2eV).
  • the present application provides a light-shielding layer, and the orthographic projection of the light-shielding layer on the substrate at least covers the first channel portion, the second channel portion, and part of the first contact portion, that is, the light-shielding layer shields at least the first channel portion, the second channel portion, and the second channel portion.
  • the light-shielding layer can block the light from the backlight source to the first channel part, the second channel part and part of the first contact part , which can reduce the number of electron-hole pairs generated by the first contact part due to illumination excitation, thereby reducing the number of electrons moving to the second contact part in the positive frame holding stage, thereby reducing the light leakage current and improving the leakage caused by the leakage current. Flickering problem.
  • the second gate 132 is a portion where the gate line 13 overlaps the second channel portion 125 along a direction perpendicular to the substrate.
  • the gate line 13 extends along the first direction OA, and the orthographic projection of the doped portion 124 on the substrate is located on the first side of the orthographic projection of the gate line 13 on the substrate.
  • the orthographic projections of the first contact portion 31 and the second contact portion 32 on the substrate are located on the second side of the orthographic projection of the gate line 13 on the substrate, and the first side is opposite to the second side.
  • the doped part, the first contact part, the second contact part, the first channel part and the second channel part may form a U shape as shown in figure a2 in FIG. 7a.
  • the above-mentioned first direction is not specifically limited, and may be the OA direction as shown in FIG. 7a.
  • figure a3 in FIG. 7a As shown in figure a3 in FIG. 7a, figure b3 in FIG. 9, and figure c3 in FIG. Located within the orthographic projection of the opaque layer on the substrate.
  • the process can be simplified and the number of patterning processes can be reduced.
  • the grid lines are mostly made of metal, and metal can reflect light, the light emitted by the backlight to the grid lines may be reflected to the semiconductor layer, thereby increasing the magnitude of the leakage current; in order to avoid this situation, the grid
  • the orthographic projection of the lines on the substrate is within the orthographic projection of the light-shielding layer on the substrate, so the light-shielding layer can shield the grid lines, prevent light from the backlight from hitting the grid lines, and further reduce leakage current.
  • the orthographic projection of the grid line on the substrate coincides with the orthographic projection of the first part 111 on the substrate, and the orthographic projection of the first part 111 on the substrate is located on the second side of the orthographic projection of the grid line 13 on the substrate.
  • the first contact portion 31 includes a first contact sub-portion 121 and a first doped sub-portion 122, and the first doped sub-portion 122 is disposed between the first contact sub-portion 121 and the first trench. Between the track parts 123 , as shown in FIGS. 8 a , 10 and 12 , the first contact sub-part 121 is electrically connected to the first pole 141 .
  • the orthographic projection of the first doped sub-portion on the substrate is located within the orthographic projection of the first part on the substrate; and/or, the orthographic projection of the first contact sub-portion on the substrate is located within the orthographic projection of the first part on the substrate within the orthographic projection of .
  • the ion doping concentration of the first contact sub-portion is greater than the ion doping concentration of the first doped sub-portion; the first contact sub-portion belongs to a heavily doped region and is used for electrical connection with the first electrode; The first doped sub-section belongs to a lightly doped region (LDD region).
  • the ion doping concentration of the doping portion may be the same as that of the first doping sub-portion.
  • the above-mentioned light-shielding layer at least includes an overlapping portion and a first portion means: the light-shielding layer includes an overlapping portion and a first portion; at this time, the overlapping portion can block the light from the backlight source to the grid line, and the first portion can block the light from the backlight source to the second grid line.
  • the light-shielding layer may also include parts other than the overlapping part and the first part, for example: the second part 112 shown in Figure 7b, the orthographic projection of the second part on the substrate is located at the The second part overlaps the orthographic projection of the doping part on the substrate; at this time, the second part can block part of the light from the backlight source to the doping part.
  • the above-mentioned orthographic projection of the first doped sub-portion on the substrate is located within the orthographic projection of the first part on the substrate; and/or, the orthographic projection of the first contact sub-portion on the substrate is located within the orthographic projection of the first part on the substrate.
  • the first one as shown in FIGS. 7 a , 7 b , and 11 , the orthographic projection of the first doped sub-portion 122 on the substrate is located within the orthographic projection of the first portion 111 on the substrate.
  • the first part can block the light from the backlight source to the first doped sub-part. Since the first doped subsection is close to the first channel section, it is very easy to generate hole-electron pairs under the excitation of light; after the first part is shielded, it can block the light from the backlight source to the first doped subsection, thereby greatly The number of hole-electron pairs generated by light excitation is reduced, thereby reducing the number of electrons moving to the second contact part in the positive frame holding phase, and finally reducing light leakage current.
  • the first part may cover the first contact subsection, or may not cover the first contact subsection, which is not limited here.
  • the second type is that the orthographic projection of the first contact sub-portion 121 on the substrate is located within the orthographic projection of the first portion 111 on the substrate.
  • the first part can block the light from the backlight source to the first contact sub-part. Since the first contact part is excited by light, hole-electron pairs will also be generated; after the first part is shielded, the light emitted from the backlight to the first contact part can be blocked, thereby greatly reducing the hole-electron pairs generated by light excitation. Quantity, and then reduce the number of electrons moving to the second contact part in the positive frame holding phase, and finally reduce the light leakage current.
  • the first portion may block the first doped sub-section, or may not block the first doped sub-section, which is not limited here.
  • the orthographic projections of the first doped subsection and the first contact subsection on the substrate are both within the orthographic projection of the first part on the substrate.
  • the first part can shield the first doped subsection and the first contact subsection at the same time, and can block the light emitted by the backlight to the first doped subsection and the first contact subsection, thereby greatly reducing the holes generated by illumination excitation.
  • the number of electron pairs thereby reducing the number of electrons moving to the second contact portion in the positive frame holding phase, and finally reducing the light leakage current.
  • the above-mentioned orthographic projection of the second contact portion on the substrate may be located within the orthographic projection of the first portion on the substrate, or, the orthographic projection of the second contact portion on the substrate is not intersecting the orthographic projection of the first portion on the substrate Stacking is not limited here and needs to be selected according to the actual design situation.
  • the second contact portion is not blocked.
  • the orthographic projection of the second contact portion 127 on the substrate does not overlap with the orthographic projection of the first portion 111 on the substrate, and the orthographic projection of the doped portion 124 on the substrate and the light-shielding The orthographic projections of layer 11 on the substrate do not overlap.
  • the light-shielding layer does not shield the second contact portion and the doped portion, and the area of the light-shielding layer can be reduced, which is beneficial to saving space.
  • the orthographic projection of the first contact subportion on the substrate is located within the orthographic projection of the first part on the substrate, and the orthographic projection of the first doped subportion on the substrate is the same as that of the first part on the substrate.
  • the first part is not connected to the overlapping part.
  • the structure of the light-shielding layer may be as shown in figure a of FIG. 9 , including a disjointed first portion 111 and an overlapping portion 110 . In this structure, referring to FIG. 9 and FIG.
  • the first part 111 covers the first contact sub-section 121
  • the overlapping part 110 covers the gate line 13
  • the second contact portion 32 and the first doped sub-portion 122 are not designed to be shielded.
  • the orthographic projection of the second channel portion 125 on the substrate 1 coincides with the partial orthographic projection F1 of the overlapping portion 110 on the substrate 1, and the orthographic projection of the first channel portion 123 on the substrate 1
  • the projection coincides with the partial orthographic projection F2 of the overlapping portion 110 on the substrate 1
  • the orthographic projection F3 of the first contact sub-portion 121 on the substrate 1 is located within the orthographic projection F4 of the first portion 111 on the substrate 1 .
  • part of the second contact portion is blocked.
  • the second contact portion 32 includes a second contact subsection 127 and a second doped subsection 126, and the second doped subsection 126 is disposed on the second contact subsection 127. and the second channel portion 125, as shown in FIGS.
  • the partial orthographic projection lies within the orthographic projection of the first portion 111 on the substrate 1 .
  • the ion doping concentration of the second contact sub-portion is greater than the ion doping concentration of the second doped sub-portion; the second contact sub-portion belongs to a heavily doped region and is used for electrical connection with the second electrode; The second doped sub-section belongs to a lightly doped region (LDD region).
  • LDD region lightly doped region
  • At least part of the orthographic projection of the above-mentioned second doped sub-portion on the substrate is located within the orthographic projection of the first part on the substrate, including: as shown in FIG. 7a and 8a, the second doped sub-portion 126 on the substrate 1 Part of the orthographic projection is located within the orthographic projection of the first portion 111 on the substrate 1; or, as shown in FIGS. within the orthographic projection on 1.
  • At least part of the orthographic projection of the second contact subsection on the substrate may be located within the orthographic projection of the first part on the substrate, that is, the first part may at least partially cover the second contact subsection.
  • the orthographic projection of the second contact subportion 127 on the substrate 1 does not overlap with the orthographic projection of the first part 111 on the substrate 1, that is, does not block the second contact subportion. , there is no limitation here.
  • the above-mentioned first part can at least block part of the light emitted from the backlight to the second doped sub-section, thereby reducing the number of hole-electron pairs generated by the second doped sub-section under illumination excitation, thereby reducing the location of the second doped sub-section.
  • the number of electrons in the position thereby further reducing the light leakage current.
  • the orthographic projection of the second contact subsection on the substrate does not overlap with the orthographic projection of the first part on the substrate. That is, the first part does not block the second contact sub-portion, which can reduce the design area of the first part.
  • the orthographic projection of the first doped sub-portion on the substrate is located within the orthographic projection of the first part on the substrate, and the orthographic projection of the first contact sub-portion on the substrate is within the When the orthographic projections on the substrate do not overlap, as shown in FIGS. 7 a , 7 b and 11 , the first portion 111 extends along the first direction OA and is connected to the overlapping portion 110 .
  • the length L1 of the second doped sub-portion 126 along the second direction OB is greater than the length L2 of the first doped sub-portion 122 along the second direction OB; thus, The second contact sub-portions 127 and the first contact sub-portions 121 are alternately arranged along the second direction OB, which can further save space.
  • the width L3 of the first portion 111 along the second direction OB is the same as the length L2 of the first doped sub-section 122 along the second direction OB, and the second direction OB is the same as the first direction OA.
  • the direction is vertical; referring to FIG. 8 a , the orthographic projection of the doped portion 124 on the substrate 1 does not overlap with the orthographic projection of the light shielding layer 11 on the substrate 1 .
  • the light-shielding layer 11 shown in FIG. 7 a is an asymmetric structure, that is, the light-shielding layer is arranged asymmetrically on both sides of the grid lines. Specifically, the first portion 111 of the light-shielding layer 11 is disposed in the area corresponding to the second side of the gate line 13, the overlapping portion 110 is disposed in the area corresponding to the gate line 13, and the area corresponding to the first side of the gate line is not provided with a light-shielding layer.
  • the orthographic projection of the second channel portion 125 on the substrate 1 coincides with the partial orthographic projection E2 of the overlapping portion 110 on the substrate 1, and the orthographic projection of the first channel portion 123 on the substrate 1
  • the projection coincides with the partial orthographic projection E4 of the overlapping portion 110 on the substrate 1
  • the orthographic projection of the first doped sub-part 122 on the substrate 1 is within the orthographic projection of the first part 111 on the substrate 1
  • the orthographic projection of the part of the heterogeneous part 126 on the substrate 1 is within the orthographic projection of the first part 111 on the substrate 1 .
  • E1 and E5 are partial orthographic projections of the first portion 111 on the substrate 1, respectively.
  • the second portion 112 of the light shielding layer 11 is disposed in a region corresponding to the first side of the gate line 13 , and the second portion 112 can shield part of the doped portion 124 .
  • the orthographic projection E9 of the second portion 112 on the substrate 1 overlaps with the orthographic projection of the doped portion 124 on the substrate 1.
  • the second portion 112 along The width h2 of the second direction OB is smaller than the width h1 of the first portion 111 along the second direction OB.
  • the above-mentioned second portion may extend along the first direction OA as shown in FIG. 7 b and be connected to the overlapping portion 110 .
  • the light-shielding layer shown in FIG. 7b is an asymmetric structure, that is, the light-shielding layer is arranged asymmetrically on both sides of the grid lines. Specifically, as shown in a6 in FIG. Corresponding to the area on the first side of the gate line 13 , the width h2 of the second portion 112 along the second direction OB is smaller than the width h1 of the first portion 111 along the second direction OB. Referring to FIG.
  • the orthographic projection of the second channel portion 125 on the substrate 1 coincides with the partial orthographic projection E8 of the overlapping portion 110 on the substrate 1 , and the orthographic projection of the first channel portion 123 on the substrate 1
  • the projection coincides with the partial orthographic projection E12 of the overlapping portion 110 on the substrate 1
  • the orthographic projection of the first doped sub-part 122 on the substrate 1 is within the orthographic projection of the first portion 111 on the substrate 1
  • the part of the orthographic projection of the second part 124 on the substrate 1 is within the orthographic projections E9 and E11 of the second part 112 on the substrate 1, and the part of the orthographic projection of the second doped sub-part 126 on the substrate 1 is located in the first part 111.
  • the orthographic projection of the first doped subsection 122 on the substrate 1 lies within the orthographic projection of the first portion 111 on the substrate 1 .
  • E7 and E13 are partial orthographic projections of the first portion 111 on the substrate 1 , respectively.
  • the light-shielding layer shown in FIG. 7a is an extreme design of an asymmetric structure, that is, no second part is provided.
  • the difference between the width of the first part along the second direction and the width of the second part along the second direction can be 2 microns, of course, the higher the difference, the stronger the improvement effect.
  • the above-mentioned asymmetric light-shielding layer can well reduce the leakage current. Based on the same type of transistors, the flicker value and leakage current of the first part and the second part of the transistor with different widths are detected, and Table 1 and Table 2 can be obtained.
  • the first column represents different samples (a total of 20 samples)
  • the second column FLK represents the flicker value
  • LS represents the width of the light-shielding layer along the second direction
  • Gate represents the width of the gate line along the second direction
  • Up represents The width of the second part of the light-shielding layer along the second direction
  • Down represents the width of the first part of the light-shielding layer along the second direction.
  • Figure a1 and figure a2 in Figure 17 are two kinds of electron microscope pictures, wherein the distance between the dotted lines is the width of the first part of the light-shielding layer along the second direction OA, and the width of the first part of the light-shielding layer in figure a1 along the second direction is greater than For the width of the first part of the light-shielding layer along the second direction in the figure a2, the FLK value of the figure a1 in FIG.
  • Figure a1 and a2 in Figure 17 include two transistors and three data lines 102, wherein the area of the small circle on the data line is the second electrode 142, and the area of the large circle between the two data lines 102 is the first electrode 142. electrode 141 .
  • the first column represents different samples (two groups of 15 samples in total)
  • LS represents the width of the light-shielding layer along the second direction
  • Gate represents the width of the gate line along the second direction
  • Up represents the second part of the light-shielding layer The width along the second direction
  • Down represents the width of the first part of the light-shielding layer along the second direction
  • IOFF@20000nit represents the leakage current under light irradiation with a brightness of 20000 nit. It can be drawn from Table 2 that the average leakage current of the second group of 8 samples is 25% higher than that of the first group of 7 samples.
  • the Up values of 7 samples are all smaller than the Down values; in the second group, the Up values of 8 samples are all greater than the Down values.
  • the actual product verification shows that the above-mentioned asymmetric light-shielding layer can effectively reduce the leakage current, especially the design in which the width of the second part along the second direction of the light-shielding layer is smaller than the width of the first part along the second direction.
  • Another structure of the light-shielding layer is provided below.
  • the orthographic projection of the first doped subsection and the second doped subsection on the substrate is located within the orthographic projection of the first part on the substrate, and the first contact subsection, the second contact subsection and
  • the first part includes a first subsection and a second subsection, and both the first subsection and the second subsection Connected to the overlapping portion
  • the orthographic projection of the first doped sub-section on the substrate is located within the orthographic projection of the first sub-section on the substrate
  • the orthographic projection of the second doped sub-section on the substrate is located within the second sub-section Partially within the orthographic projection on the substrate.
  • the first subsection of the light-shielding layer can block the light from the backlight to the first doped subsection
  • the second subsection can block the light from the backlight to the second doped subsection
  • the overlapping part can block the light from the backlight to the second doped subsection.
  • the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate, and the boundary shape of the orthographic projection of the light-shielding layer on the substrate and the shape of the semiconductor layer on the substrate Orthographic projections have the same boundary shape. As shown in FIG. 13 and FIG.
  • the first contact subsection 121, the first doped subsection 122, the first channel section 123, the doped section 124, the second channel section 125, the second doped section The orthographic projections of the miscellaneous subsection 126 and the second contact subsection 127 on the substrate 1 are respectively H8, H7, H6, H5, H4, H3 and H2, all located within the orthographic projection H1 of the light shielding layer 11 on the substrate 1 .
  • the light-shielding layer can block the light from the backlight source to the semiconductor layer, and can block the light from the backlight source to the first grid and the second grid; the light-shielding layer of this structure does not need to cover the entire grid line, and the design area is small.
  • the orthographic projection of 113 on the substrate 1 at least covers the orthographic projection of the first grid 131 on the substrate 1 and the partial orthographic projection of the first contact portion 31 on the substrate 1, and the second light shielding portion 112 is on the substrate 1
  • the orthographic projection of at least covers the orthographic projection of the second grid 132 on the substrate 1 and part of the orthographic projection of the second contact portion 32 on the substrate 1 .
  • the above-mentioned orthographic projection of the first light-shielding portion on the substrate at least covers the orthographic projection of the first grid on the substrate and part of the orthographic projection of the first contact portion on the substrate includes: the orthographic projection of the first light-shielding portion on the substrate
  • the projection covers the orthographic projection of the first gate on the substrate and the partial orthographic projection of the first contact portion on the substrate; for example, if the first contact portion includes the first contact sub-section and the first doped sub-section, the second
  • the orthographic projection of a light-shielding portion on the substrate can cover at least part of the orthographic projection of the first contact sub-portion or the first doping sub-portion on the substrate.
  • the orthographic projection of the first light-shielding portion 113 on the substrate covers the orthographic projection of the first light-shielding portion 113 on the substrate
  • the orthographic projection of the first doped sub-portion 122 on the substrate is shown as an example.
  • the orthographic projection of the first light shielding portion on the substrate covers the orthographic projection of the first gate on the substrate and all the orthographic projections of the first contact portion on the substrate.
  • the orthographic projection of the first light shielding portion on the substrate may also cover the orthographic projection other than the orthographic projection of the first grid and the first contact portion on the substrate.
  • the above-mentioned orthographic projection of the second light-shielding portion on the substrate at least covers the orthographic projection of the second grid on the substrate and part of the orthographic projection of the second contact portion on the substrate includes: the orthographic projection of the second light-shielding portion on the substrate
  • the projection covers the orthographic projection of the second gate on the substrate and the partial orthographic projection of the second contact portion on the substrate; for example, if the second contact portion includes a second contact sub-section and a second doped sub-section, the first
  • the orthographic projection of the second light-shielding portion on the substrate can cover at least part of the orthographic projection of the second contact sub-portion or the second doping sub-portion on the substrate.
  • the partial orthographic projection of the second doped sub-portion 126 on the substrate is shown as an example.
  • the orthographic projection of the second light shielding portion on the substrate covers the orthographic projection of the second gate on the substrate and all the orthographic projections of the second contact portion on the substrate.
  • the orthographic projection of the second light shielding portion on the substrate may also cover the orthographic projection other than the orthographic projections of the second grid and the second contact portion on the substrate.
  • the orthographic projection J6 of the first channel portion 123 on the substrate 1, the orthographic projection J7 of the first doped sub-portion 122 on the substrate 1, and the portion of the doped portion 124 on the substrate 1 The orthographic projection J5 is located in the orthographic projection J8 of the first light-shielding portion 113 on the substrate 1, the orthographic projection J3 of the second channel portion 125 on the substrate 1, and the second doped sub-portion 126 are on the substrate 1
  • the partial orthographic projection J2 of the doped portion 124 on the substrate 1 and the partial orthographic projection J4 of the doping portion 124 on the substrate 1 are both located within the orthographic projection J1 of the second light shielding portion 112 on the substrate 1 .
  • the length of the second doped sub-section along the second direction may be greater than the length of the first doped sub-section along the second direction, and the width of the second doped sub-section in the second light shielding section along the first direction is the same as that of the first doped sub-section.
  • a doped sub-section has the same length along the second direction. In this way, the second contact sub-portions and the first contact sub-portions are alternately arranged along the second direction, which can further save space; meanwhile, while ensuring the reduction of leakage current, the area of the light-shielding layer is further reduced.
  • the embodiment of the present application also provides a display panel, as shown in FIG. 18 , which includes an opposite color filter substrate 40 and the aforementioned array substrate 41;
  • the orthographic projection M on the substrate 411 covers the orthographic projection N of the light shielding layer 412 of the array substrate 41 on the substrate 411 .
  • the area corresponding to the black matrix in the array substrate belongs to the non-opening area, and setting the light-shielding layer in the non-opening area can reduce the leakage current and improve the flicker phenomenon without reducing the opening ratio, thereby improving product quality and user experience.
  • the color filter substrate 40 may also be a base 402 , and the black matrix 401 may be disposed on the base 402 , of course, it may also include other structures such as a color filter layer.
  • the display panel may further include a liquid crystal 42 disposed between the color filter substrate 40 and the array substrate 41 to form a liquid crystal display panel.
  • the type of the display panel is not limited, it can be TN (Twisted Nematic, twisted nematic) type, VA (Vertical Alignment, vertical orientation) type, IPS (In-Plane Switching, plane switching) type or ADS (Advanced Super Dimension Switch, advanced ultra-dimensional field conversion) type and other liquid crystal display panels, as well as any products or components with display functions such as TVs, digital cameras, mobile phones, and tablet computers that include these liquid crystal display panels.
  • TN Transmission Nematic, twisted nematic
  • VA Vertical Alignment, vertical orientation
  • IPS In-Plane Switching, plane switching
  • ADS Advanced Super Dimension Switch, advanced ultra-dimensional field conversion

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Abstract

本申请提供了一种阵列基板、显示面板，涉及显示技术领域，该阵列基板能够大幅降低光照漏电流，大幅改善光照漏电流导致的闪烁问题。阵列基板包括阵列排布的多个子像素；子像素包括依次层叠设置在衬底上的遮光层、半导体层、栅极层、源漏层和像素电极层；半导体层包括依次相连的第一接触部、第一沟道部、掺杂部、第二沟道部和第二接触部；栅极层包括第一栅极和第二栅极；源漏层包括第一极和第二极；遮光层在衬底上的正投影至少覆盖第一沟道部、第二沟道部和部分第一接触部在衬底上的正投影。

Description

阵列基板、显示面板
相关申请的交叉引用
本申请要求在2021年05月20日提交中国专利局、申请号为202110554410.0、名称为“一种阵列基板、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板。
背景技术
液晶显示器在显示领域占据重要地位，目前已广泛应用于电视、手机、电脑等具有显示功能的产品中。随着用户要求的不断提升，高高像素密度(Pixels Per Inch，PPI)产品随之产生。为了具备高清、轻薄的产品品质，液晶显示器需要满足屏幕尺寸小、像素密度高、背光源亮度高的设计要求。但是满足这些要求的产品的光照漏电流情况非常严重，进而引发严重的闪烁(Flicker)现象，大幅降低显示品质。
发明内容
本申请的实施例提供一种阵列基板、显示面板，
本申请的实施例采用如下技术方案：
一方面，提供了一种阵列基板，包括衬底以及设置在所述衬底上的阵列排布的多个子像素；所述子像素包括依次层叠设置在所述衬底上的遮光层、半导体层、栅极层、源漏层和像素电极层；
所述半导体层包括依次相连的第一接触部、第一沟道部、掺杂部、第二沟道部和第二接触部；所述栅极层包括第一栅极和第二栅极；所述源漏层包括第一极和第二极；所述像素电极层包括像素电极；所述第一极分别与所述第一接触部和所述像素电极电连接，所述第二极与所述第二接触部电连接；
其中，所述第一沟道部和所述第一栅极沿垂直于所述衬底的方向交叠，所述第二沟道部和所述第二栅极沿垂直于所述衬底的方向交叠；
所述遮光层在所述衬底上的正投影至少覆盖所述第一沟道部、所述第二沟道部和部分所述第一接触部在衬底上的正投影。
可选的，所述栅极层还包括栅线；
所述第一栅极为所述栅线沿垂直于所述衬底的方向与所述第一沟道部交叠的部分，所述第二栅极为所述栅线沿垂直于所述衬底的方向与所述第二 沟道部交叠的部分；
所述栅线沿第一方向延伸，所述掺杂部在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的第一侧，所述第一接触部和所述第二接触部在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的第二侧，所述第一侧和所述第二侧相对。
可选的，所述遮光层沿所述第一方向延伸，所述栅线在所述衬底上的正投影位于所述遮光层在所述衬底上的正投影以内。
可选的，所述遮光层至少包括交叠部分和第一部分，所述交叠部分沿所述第一方向延伸、且在所述衬底上的正投影与所述栅线在所述衬底上的正投影重合，所述第一部分在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的所述第二侧；
所述第一接触部包括第一接触子部和第一掺杂子部，所述第一掺杂子部设置在所述第一接触子部和所述第一沟道部之间，所述第一接触子部与所述第一极电连接；
其中，所述第一掺杂子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内；和/或，所述第一接触子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内。
可选的，所述第二接触部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠，所述掺杂部在所述衬底上的正投影与所述遮光层在所述衬底上的正投影不交叠。
可选的，在所述第一接触子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内、且所述第一掺杂子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分与所述交叠部分不相连。
可选的，所述第二接触部包括第二接触子部和第二掺杂子部，所述第二掺杂子部设置在所述第二接触子部和所述第二沟道部之间，所述第二接触子部与所述第二极电连接；
其中，所述第二掺杂子部在所述衬底上的至少部分正投影位于所述第一部分在所述衬底上的正投影以内。
可选的，所述第二接触子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠。
可选的，在所述第一掺杂子部在所述衬底上的正投影位于所述第一部分 在所述衬底上的正投影以内、且所述第一接触子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分沿所述第一方向延伸、且与所述交叠部分相连。
可选的，所述第二掺杂子部沿第二方向的长度大于所述第一掺杂子部沿第二方向的长度；
所述第一部分沿所述第二方向的宽度与所述第一掺杂子部沿所述第二方向的长度相同，所述第二方向与所述第一方向垂直；所述掺杂部在所述衬底上的正投影与所述遮光层在所述衬底上的正投影不交叠。
可选的，所述遮光层还包括第二部分，所述第二部分在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的所述第一侧；
所述第二部分在所述衬底上的正投影与所述掺杂部在所述衬底上的正投影部分交叠，且所述第二部分沿第二方向的宽度小于所述第一部分沿所述第二方向的宽度。
可选的，在所述第一掺杂子部和所述第二掺杂子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内，且所述第一接触子部、所述第二接触子部和所述掺杂部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分包括第一子部分和第二子部分，所述第一子部分和所述第二子部分均与所述交叠部分相连，所述第一掺杂子部在所述衬底上的正投影位于所述第一子部分在所述衬底上的正投影以内，所述第二掺杂子部在所述衬底上的正投影位于所述第二子部分在所述衬底上的正投影以内。
可选的，所述半导体层在所述衬底上的正投影位于所述遮光层在所述衬底上的正投影以内，且所述遮光层在所述衬底上的正投影的边界形状和所述半导体层在所述衬底上的正投影的边界形状相同。
可选的，所述遮光层包括不相连的第一遮光部和第二遮光部，所述第一遮光部在所述衬底上的正投影至少覆盖所述第一栅极在所述衬底上的正投影以及所述第一接触部在所述衬底上的部分正投影，所述第二遮光部在所述衬底上的正投影至少覆盖所述第二栅极在所述衬底上的正投影以及所述第二接触部在所述衬底上的部分正投影。
另一方面，提供了一种显示面板，包括相对的彩膜基板和上述的阵列基板；
其中，所述彩膜基板包括黑矩阵，所述黑矩阵在所述阵列基板的衬底上 正投影覆盖所述阵列基板的遮光层在所述衬底上的正投影。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种半导体层的能级图；
图2为本申请实施例提供的一种NMOS晶体管和PMOS晶体管在光照前后的漏电流对比图；
图3为本申请实施例提供的一种不同样本在不同光照环境下的漏电流对比图；
图4为本申请实施例提供的一种阵列基板的结构示意图；
图5为本申请实施例提供的一种驱动过程示意图；
图6a为本申请实施例提供的另一种阵列基板的结构示意图；
图6b为本申请实施例提供的又一种阵列基板的结构示意图；
图7a中，图a1为本申请实施例提供的一种遮光层的结构示意图，图a2在图a1基础上形成有半导体层的结构示意图，图a3在图a2基础上形成有栅线的结构示意图；
图7b中，图a4为本申请实施例提供的另一种遮光层的结构示意图，图a4在图a5基础上形成有半导体层的结构示意图，图a6在图a5基础上形成有栅线的结构示意图；
图8a为沿图7a中a3图CD方向的截面图；
图8b为沿图7b中a6图CD方向的截面图；
图9中，图b1为本申请实施例提供的一种遮光层的结构示意图，图b2在图b1基础上形成有半导体层的结构示意图，图b3在图b2基础上形成有栅线的结构示意图；
图10为沿图9中b3图CD方向的截面图；
图11中，图c1为本申请实施例提供的一种遮光层的结构示意图，图c2在图c1基础上形成有半导体层的结构示意图，图c3在图c2基础上形成有 栅线的结构示意图；
图12为沿图11中c3图CD方向的截面图；
图13中，图d1为本申请实施例提供的一种遮光层的结构示意图，图d2在图d1基础上形成有半导体层的结构示意图，图d3在图d2基础上形成有栅线的结构示意图；
图14为沿图13中d3图CD方向的截面图；
图15中，图e1为本申请实施例提供的一种遮光层的结构示意图，图e2在图e1基础上形成有半导体层的结构示意图，图e3在图e2基础上形成有栅线的结构示意图；
图16为沿图15中e3图CD方向的截面图；
图17中，a1图和a2图分别为两种电镜图；
图18为本申请实施例提供的一种显示面板的结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本申请的实施例中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
液晶显示面板包括相对的阵列基板和彩膜基板、以及设置在阵列基板和彩膜基板之间的液晶；由于液晶不能发光，为了实现显示，液晶显示面板还包括背光源，背光源可以设置在阵列基板远离彩膜基板的一侧。背光源发出的光线依次经过阵列基板、液晶和彩膜基板，由于液晶分子在电场作用下会发生扭转，从而能够改变光线的通过量，进而实现不同画面的显示。阵列基板包括阵列排布的多个子像素，一般通过薄膜晶体管控制每个子像素产生的电场，进而控制液晶的偏转。
但是薄膜晶体管(Thin Film Transistor，TFT)的半导体层容易受到光照影响，进而产生漏电流。以n型半导体为例进行说明，参考图1所示，n型半导体100的费米能级E Fi在本征费米能级E F之上。当受到外界光照时，载流子主要来自于本征激发，此时费米能级与本征费米能级接近。在一定温度下，采用光子能量hν≥Eg(禁带宽度)的光照射半导体，这时平衡态条件被破坏，半导体处于偏离平衡态的非平衡态。光照前，半导体中电子浓度为n0；光照后，非平衡态半导体中电子浓度n＝n0+δn，其中，δn为光生载流子。图1中，Ec表示导带底，即导带的最低能级；Ev表示价带顶。
参考图2所示，无论是NMOS晶体管还是PMOS晶体管，光照后的漏电流I off均大于光照前的漏电流I off；图2中，横坐标Vg表示晶体管的栅极电压，纵坐标Id表示晶体管的漏源电流。另外，漏电流增加主要影响变量为光照，而光照强度与光照漏电流的数值成正相关。采用不同规格的四个TFT分别在黑暗环境(Dark)、6500nit光照环境P1和20000nit光照环境P2下测试漏电流，得到如图3所示的测试结果图。从图3可以得出，任一个样本中，随着光照亮度的增大，漏电流也随之增大，且光照亮度越大，漏电流也越大。
高PPI产品中(例如：1000PPI、1200PPI等)，像素密度、背光源亮度都设计的非常高，从而导致高PPI产品的光照漏电流情况非常严重，而光照漏电流会导致闪烁(Flicker)问题，大幅降低显示效果。
参考图4所示，阵列基板包括多条栅线101和多条数据线102，栅线101与每行子像素的TFT104的栅极电连接，数据线102与每列子像素的TFT104的一极电连接；各子像素中，TFT104的另一极与像素电极103电连接。以一个子像素的TFT的驱动过程为例，说明产生闪烁的原理。参考图5所示，在奇数帧内，通过栅线向栅极输入Vgate信号；Vgate信号的电压为高电平时，TFT打开，数据线输出正极性Vdata +信号，向TFT充电，使得像素电极的电压变为Vd +；但是由于寄生电容的存在，像素电极的电压会被拉低△Vp；接着，Vgate信号的电压变为低电平，TFT进入保持阶段。理想状态下，在下次充电前，像素电极的电压始终保持充电电压；但是，若受到光照影响，TFT会产生漏电流，从而使得像素电极的电压随保持时间的增长而不断降低。
在下一偶数帧时，Vgate信号的电压为高电平，TFT打开，数据线输出负极性Vdata -信号，TFT放电完成反向充电，使得像素电极的电压变为Vd -； 但是由于寄生电容的存在，像素电极的电压会被拉低△Vp；接着，Vgate信号的电压变为低电平，TFT进入保持阶段。理想状态下，在下次充电前，像素电极的电压始终保持充电电压；但是，若受到光照影响，TFT会产生漏电流，从而使得像素电极的电压绝对值随保持时间的增长而不断降低。由于在保持阶段中漏电流的存在，导致子像素在相邻两帧间的亮度形成差异，从而使得人眼识别到闪烁。若采用列反转驱动方式，在实际使用过程中会出现明显的摇头竖纹，大幅降低显示品质。
另外，图5中，Vcom指的是公共电极的电压，像素电极和公共电极形成电场，以使得液晶分子发生扭转。Vcom电压可以是(Vd ++Vd -)/2，但是由于寄生电容的存在，像素电极的电压会被拉低△Vp。为了保证液晶分子的压差不变，可以对Vcom电压进行补偿，即可采用图5所示的Vcom电压，该电压值小于(Vd ++Vd -)/2。
基于上述，本申请实施例提供了一种阵列基板，参考图6a所示，包括衬底1以及设置在衬底1上的阵列排布的多个子像素2；子像素包括依次层叠设置在衬底上的遮光层、半导体层、栅极层、源漏层和像素电极层。
参考图7a中a2图所示，半导体层包括依次相连的第一接触部31、第一沟道部123、掺杂部124、第二沟道部125和第二接触部32；参考图7a中a3图所示，栅极层包括第一栅极131和第二栅极132；参考图8a所示，源漏层包括第一极141和第二极142；像素电极层包括像素电极15；第一极141分别与第一接触部和像素电极15电连接，第二极与第二接触部电连接。(图8a中以第一极141与第一接触部的第一接触子部121电连接，第二极142与第二接触部的第二接触子部127电连接为例进行绘示。)
其中，参考图8a所示，第一沟道部123和第一栅极131沿垂直于衬底1的方向交叠，第二沟道部125和第二栅极132沿垂直于衬底1的方向交叠；遮光层在衬底上的正投影至少覆盖第一沟道部、第二沟道部和部分第一接触部在衬底上的正投影。(图8a中以遮光层11在衬底1上的正投影至少覆盖第一沟道部123、第二沟道部125、第一接触部的第一掺杂子部122在衬底1上的正投影为例进行绘示。)
上述遮光层的材料可以是不透光的金属材料，例如：钼、铝、铝钕合金等等。该遮光层的形状不做限定，具体可以根据半导体层和栅极层确定。遮光层在衬底上的正投影是指：遮光层沿垂直于衬底的方向在衬底上的投影。其余膜层在衬底上的正投影与此类似，后续不再说明。
上述遮光层在衬底上的正投影可以覆盖部分第一接触部在衬底上的正投影，或者，还可以覆盖全部第一接触部在衬底上的正投影；当然，遮光层还可以覆盖第二接触部、掺杂部等结构在衬底上的正投影。
上述半导体层中，依次相连的第一接触部、第一沟道部、掺杂部、第二沟道部和第二接触部的整体形状不做限定。示例的，该整体形状可以是直条状、U形等等；考虑到节省空间，可以采用U形。该半导体层可以是N型半导体层。
参考图6a和图6b所示，上述阵列基板还可以包括相互交叉的多条栅线101和多条数据线102，栅线101与每行子像素2的第一栅极G1和第二栅极G2电连接，数据线102与每行子像素105的第二极C2电连接；各子像素中，第一极C1与像素电极103电连接。其中，数据线可以与第一极和第二极同层设置，且数据线与第二极相连；或者，第二极为数据线沿垂直于衬底的方向与第二接触部交叠的部分。
当然，各子像素中，为了避免相邻两层之间互相影响，参考图8a所示，遮光层和半导体层之间还可以设置第一绝缘层20；半导体层和栅极层之间还可以设置栅绝缘层21；栅极层和源漏层之间还可以设置层间介质层22，第一极141可以通过贯穿层间介质层22和栅绝缘层21的第一过孔与第一接触部电连接，第二极142可以通过贯穿层间介质层22和栅绝缘层21的第二过孔与第二接触部电连接；源漏层和像素电极层之间还可以设置第二绝缘层23，像素电极15可以通过贯穿第二绝缘层23的过孔与第一极141电连接；像素电极层远离源漏层的一侧还可以设置公共电极层，公共电极层可以包括公共电极25，公共电极25和像素电极15之间可以形成电场，以驱动液晶偏转。当然，该阵列基板还可以包括其它膜层和结构，这里仅介绍与发明点相关的膜层和结构，其它结构可以从相关技术中获得，此处不再赘述。
上述阵列基板可以应用于TN(Twisted Nematic，扭曲向列)型、VA(Vertical Alignment，垂直取向)型、IPS(In-Plane Switching，平面转换)型或ADS(Advanced Super Dimension Switch，高级超维场转换)型等液晶显示面板中、以及包括这些液晶显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件中。
上述半导体层、栅极层和源漏层形成的晶体管为顶栅双栅型晶体管，该双栅型晶体管可以是LTPS(Low Temperature Poly-silicon，低温多晶硅)型晶体管、氧化物型晶体管，或者非晶硅型晶体管，这里不做限定。在大尺寸、 高PPI产品中，LTPS型晶体管应用较多。双栅型晶体管的漏电流小于单栅型晶体管的漏电流。
按照晶体管的特性，可以将晶体管分为N型晶体管和P型晶体管。下面以N型晶体管为例进行说明。N型晶体管可以包括栅极、源极和漏极，其中，源极和漏极可以互换。在N型晶体管中，将低电平一端称为源极，高电平一端称为漏极，电流从漏极流向源极。将N型晶体管应用到显示面板中，在正帧显示时(即采用图5所示的正极性数据信号Vdata +驱动)，像素电极侧处于低电位，与像素电极电连接的晶体管的电极为源极，数据线侧处于高电位，与数据线电连接的晶体管的电极为漏极。在负帧显示时(即采用图5所示的负极性数据信号Vdata -驱动)，像素电极侧处于高电位，与像素电极电连接的晶体管的电极为漏极，数据线侧处于低电位，与数据线电连接的晶体管的电极为源极。即采用不同极性的数据信号驱动时，N型晶体管的源漏极会发生变化。N型晶体管中，正帧漏电流高于负帧漏电流，并且在转移特性曲线中截止区的“翘尾”严重(说明正帧漏电流情况严重)。
上述第一极和第二极中，第一极分别与第一接触部和像素电极电连接，第二极可以分别与第二接触部和数据线电连接。若为N型晶体管，采用正极性数据电压驱动时，第一极可以称为源极，第二极可以称为漏极。下面说明本申请减少漏电流的原理。在晶体管的正帧保持阶段，若沟道边缘耗尽区受到光照，则该区域能够激发产生电子空穴对，部分电子获得一定能量(例如:大于2eV的能量)后能够跃迁至导带边缘。这些高能载流子可以轻易扩散而不受势能限制，并沿与偏压(栅极电压)所形成的电场方向移动，空穴往沟道流动而电子则朝向漏极端，进而使得源漏极之间的高电场主要集中在漏极端。若能够减少从源极端向漏极端移动的电子数量，则可减少漏电流的大小。因此，本申请通过设置遮光层，遮光层在衬底上的正投影至少覆盖第一沟道部、第二沟道部和部分第一接触部，即遮光层至少遮挡第一沟道部、第二沟道部和部分第一接触部；那么将该阵列基板应用于液晶显示面板时，遮光层能够遮挡背光源射向第一沟道部、第二沟道部和部分第一接触部的光线，这样可以减少第一接触部因光照激发产生的电子空穴对数量，从而减少在正帧保持阶段向第二接触部移动的电子数量，进而降低了光照漏电流，改善了因漏电流导致的闪烁问题。
可选的，为了尽可能地提高开口率，参考图7a中a2和a3图所示，栅极层还包括栅线13；第一栅极131为栅线13沿垂直于衬底的方向与第一沟 道部123交叠的部分，第二栅极132为栅线13沿垂直于衬底的方向与第二沟道部125交叠的部分。
参考图7a中a2和a3图所示，栅线13沿第一方向OA方向延伸，掺杂部124在衬底上的正投影位于栅线13在衬底上的正投影的第一侧，第一接触部31和第二接触部32在衬底上的正投影位于栅线13在衬底上的正投影的第二侧，第一侧和第二侧相对。
上述掺杂部、第一接触部、第二接触部、第一沟道部和第二沟道部可以形成如图7a中a2图所示的U形。上述第一方向不做具体限定，可以是如图7a所示的OA方向。
在一个或多个实施例中，参考图7a中a3图、图9中b3图、图11中c3图所示，遮光层沿第一方向OA方向延伸，栅线13在衬底上的正投影位于遮光层在衬底上的正投影以内。
这样一方面可以简化工艺，减少构图工艺次数。另一方面，由于栅线多采用金属制作，而金属能够反射光线，那么背光源射向栅线的光线有可能被反射至半导体层，进而增大漏电流的大小；为了避免此种情况，栅线在衬底上的正投影位于遮光层在衬底上的正投影以内，则遮光层能够遮挡栅线，防止背光源的光线射向栅线，进一步降低漏电流的大小。
进一步可选的，为了便于制作，参考图7a、9和11所示，遮光层11至少包括交叠部分110和第一部分111，交叠部分110沿第一方向OA方向延伸、且在衬底上的正投影与栅线在衬底上的正投影重合，第一部分111在衬底上的正投影位于栅线13在衬底上的正投影的第二侧。
参考图7a、9和11所示，第一接触部31包括第一接触子部121和第一掺杂子部122，第一掺杂子部122设置在第一接触子部121和第一沟道部123之间，参考图8a、10和12所示，第一接触子部121与第一极141电连接。
其中，第一掺杂子部在衬底上的正投影位于第一部分在衬底上的正投影以内；和/或，第一接触子部在衬底上的正投影位于第一部分在衬底上的正投影以内。
上述第一接触部中，第一接触子部的离子掺杂浓度大于第一掺杂子部的离子掺杂浓度；第一接触子部属于重掺杂区，用于与第一极电连接；第一掺杂子部属于轻掺杂区(LDD区)。掺杂部的离子掺杂浓度可以与第一掺杂子部的离子掺杂浓度相同。
上述遮光层至少包括交叠部分和第一部分是指：遮光层包括交叠部分和 第一部分；此时，交叠部分可以遮挡背光源射向栅线的光线，第一部分可以遮挡背光源射向第一掺杂子部和/或第一接触子部的光线。或者，遮光层还可以包括除交叠部分和第一部分以外的部分，例如：图7b所示的第二部分112，第二部分在衬底上的正投影位于栅线在衬底上的正投影的第一侧，第二部分与掺杂部在衬底上的正投影部分交叠；此时，第二部分可以遮挡背光源射向掺杂部的部分光线。
上述第一掺杂子部在衬底上的正投影位于第一部分在衬底上的正投影以内；和/或，第一接触子部在衬底上的正投影位于第一部分在衬底上的正投影以内包括三种情况：
第一种，参考图7a、7b、11所示，第一掺杂子部122在衬底上的正投影位于第一部分111在衬底上的正投影以内。
这样，第一部分可以遮挡背光源射向第一掺杂子部的光线。由于第一掺杂子部靠近第一沟道部，在光照激发下，极易产生空穴电子对；采用第一部分遮挡后，能够阻挡背光源射向第一掺杂子部的光线，从而大幅降低光照激发产生的空穴电子对数量，进而减小在正帧保持阶段向第二接触部移动的电子数量，最终降低光照漏电流。
此时，第一部分可以遮挡第一接触子部，或者，也可以不遮挡第一接触子部，这里不做限定。
第二种，参考图9所示，第一接触子部121在衬底上的正投影位于第一部分111在衬底上的正投影以内。
这样，第一部分可以遮挡背光源射向第一接触子部的光线。由于第一接触子部在光照激发下，也会产生空穴电子对；采用第一部分遮挡后，能够阻挡背光源射向第一接触子部的光线，从而大幅降低光照激发产生的空穴电子对数量，进而减小在正帧保持阶段向第二接触部移动的电子数量，最终降低光照漏电流。
此时，第一部分可以遮挡第一掺杂子部，或者，也可以不遮挡第一掺杂子部，这里不做限定。
第三种，第一掺杂子部和第一接触子部在衬底上的正投影均位于第一部分在衬底上的正投影以内。
这样，第一部分可以同时遮挡第一掺杂子部和第一接触子部，能够阻挡背光源射向第一掺杂子部和第一接触子部的光线，从而大幅降低光照激发产生的空穴电子对数量，进而减小在正帧保持阶段向第二接触部移动的电子数 量，最终降低光照漏电流。
上述第二接触部在衬底上的正投影可以位于第一部分在衬底上的正投影以内，或者，第二接触部在衬底上的正投影与第一部分在衬底上的正投影不交叠，这里不做限定，需要根据实际设计情况选择。
下面进一步根据第二接触部的遮挡情况，提供不同的结构。
第一种，第二接触部未被遮挡。
可选的，参考图9所示，第二接触部127在衬底上的正投影与第一部分111在衬底上的正投影不交叠，掺杂部124在衬底上的正投影与遮光层11在衬底上的正投影不交叠。
这样，遮光层对第二接触部和掺杂部不做遮挡，能够减少遮光层的面积，有利于节省空间。
进一步可选的，在第一接触子部在衬底上的正投影位于第一部分在衬底上的正投影以内、且第一掺杂子部在衬底上的正投影与第一部分在衬底上的正投影不交叠的情况下，第一部分与交叠部分不相连。遮光层的结构可以如图9中a图所示，包括不相连的第一部分111和交叠部分110。该结构中，结合图9和图10，第一部分111遮挡第一接触子部121，交叠部分110遮挡栅线13、第一沟道部123和第二沟道部125，掺杂部124、第二接触部32和第一掺杂子部122不做遮挡设计。参考图10所示，第二沟道部125在衬底1上的正投影与交叠部分110在衬底1上的部分正投影F1重合，第一沟道部123在衬底1上的正投影与交叠部分110在衬底1上的部分正投影F2重合，第一接触子部121在衬底1上的正投影F3位于第一部分111在衬底1上的正投影F4以内。
第二种，第二接触部的部分被遮挡。
可选的，参考图7a、7b、11所示，第二接触部32包括第二接触子部127和第二掺杂子部126，第二掺杂子部126设置在第二接触子部127和第二沟道部125之间，参考图8a、8b、12所示，第二接触子部127与第二极142电连接；其中，第二掺杂子部126在衬底1上的至少部分正投影位于第一部分111在衬底1上的正投影以内。
上述第二接触部中，第二接触子部的离子掺杂浓度大于第二掺杂子部的离子掺杂浓度；第二接触子部属于重掺杂区，用于与第二极电连接；第二掺杂子部属于轻掺杂区(LDD区)。第二掺杂子部、掺杂部和第一掺杂子部三者的离子掺杂浓度可以相同。
上述第二掺杂子部在衬底上的至少部分正投影位于第一部分在衬底上的正投影以内包括：结合图7a和8a所示，第二掺杂子部126在衬底1上的部分正投影位于第一部分111在衬底1上的正投影以内；或者，结合图11和12所示，第二掺杂子部126在衬底1上的全部正投影位于第一部分111在衬底1上的正投影以内。
上述第二接触子部在衬底上的至少部分正投影可以位于第一部分在衬底上的正投影以内，即第一部分至少可以遮挡部分第二接触子部。或者，参考图8a、8b、12所示，第二接触子部127在衬底1上的正投影与第一部分111在衬底1上的正投影不交叠，即不遮挡第二接触子部，这里不做限定。
上述第一部分至少可以遮挡背光源射向第二掺杂子部的部分光线，从而可以减少第二掺杂子部在光照激发下产生的空穴电子对数量，进而减少第二掺杂子部所在位置的电子数量，从而进一步降低光照漏电流。
进一步可选的，第二接触子部在衬底上的正投影与第一部分在衬底上的正投影不交叠。即第一部分不遮挡第二接触子部，这样能够减小第一部分的设计面积。
为了简化结构，便于实现，在第一掺杂子部在衬底上的正投影位于第一部分在衬底上的正投影以内、且第一接触子部在衬底上的正投影与第一部分在衬底上的正投影不交叠的情况下，参考图7a、7b和11所示，第一部分111沿第一方向OA方向延伸、且与交叠部分110相连。
进一步可选的，参考图7a中a2图所示，第二掺杂子部126沿第二方向OB方向的长度L1大于第一掺杂子部122沿第二方向OB方向的长度L2；这样，第二接触子部127和第一接触子部121沿第二方向OB方向交错设置，可以进一步节省空间。
参考图7a中a2图所示，第一部分111沿第二方向OB方向的宽度L3与第一掺杂子部122沿第二方向OB方向的长度L2相同，第二方向OB方向与第一方向OA方向垂直；参考图8a所示，掺杂部124在衬底1上的正投影与遮光层11在衬底1上的正投影不交叠。
如图7a所示的遮光层11属于非对称结构，即遮光层在栅线两侧的设置不对称。具体的，该遮光层11的第一部分111设置在对应栅线13第二侧的区域，交叠部分110设置在对应栅线13的区域，而对应栅线第一侧的区域未设置遮光层。参考图8a所示，第二沟道部125在衬底1上的正投影与交叠部分110在衬底1上的部分正投影E2重合，第一沟道部123在衬底1上 的正投影与交叠部分110在衬底1上的部分正投影E4重合，第一掺杂子部122在衬底1上的正投影在第一部分111在衬底1上的正投影以内，第二掺杂子部126在衬底1上的部分正投影在第一部分111在衬底1上的正投影以内。图8a中，E1和E5分别是第一部分111在衬底1上的部分正投影。
由于制作精度的限制，可选的，参考图7b所示，遮光层还包括第二部分112，第二部分112在衬底上的正投影位于栅线13在衬底上的正投影的第一侧。即遮光层11的第二部分112设置在对应栅线13第一侧的区域，该第二部分112可以遮挡部分掺杂部124。
参考图8b所示，第二部分112在衬底1上的正投影E9与掺杂部124在衬底1上的正投影部分交叠，参考图7b中a6图所示，第二部分112沿第二方向OB方向的宽度h2小于第一部分111沿第二方向OB方向的宽度h1。
上述第二部分可以如图7b所示沿第一方向OA方向延伸、且与交叠部分110相连。如图7b所示的遮光层属于非对称结构，即遮光层在栅线两侧的设置不对称。具体的，参考图7b中a6所示，该遮光层11的第一部分111设置在对应栅线13第二侧的区域，交叠部分110设置在对应栅线13的区域，第二部分112设置在对应栅线13第一侧的区域，且第二部分112沿第二方向OB方向的宽度h2小于第一部111分沿第二方向OB方向的宽度h1。参考图8b所示，第二沟道部125在衬底1上的正投影与交叠部分110在衬底1上的部分正投影E8重合，第一沟道部123在衬底1上的正投影与交叠部分110在衬底1上的部分正投影E12重合，第一掺杂子部122在衬底1上的正投影与位于第一部分111在衬底1上的正投影以内，掺杂部124在衬底1上的部分正投影在第二部分112在衬底1上的正投影E9和E11以内，第二掺杂子部126在衬底1上的部分正投影位于第一部分111在衬底1上的正投影E7以内，第一掺杂子部122在衬底1上的正投影位于第一部分111在衬底1上的正投影以内。图8b中，E7和E13分别是第一部分111在衬底1上的部分正投影。
图7a所示的遮光层为非对称结构的极限设计，即不设置第二部分。这里对于第一部分沿第二方向的宽度与第二部分沿第二方向的宽度的差值不做限定，示例的，第一部分沿第二方向的宽度与第二部分沿第二方向的宽度的差值可以在2微米，当然差值越高，改善效果越强。
需要说明的是，上述非对称遮光层能够很好地降低漏电流。基于同类型晶体管，对具有不同宽度的第一部分和第二部分的晶体管的闪烁值和漏电流 进行检测，可以得到表一和表二。
表一
NO. FLK LS Gate Up Down
#1 3.5％ 5.36 2.80 0.90 1.74
#2 4.1％ 5.24 2.89 1.09 1.31
#3 4.6％ 5.27 3.28 0.93 1.27
#4 4.6％ 5.27 3.30 0.92 1.38
#5 4.6％ 4.94 3.16 1.03 1.18
#6 4.1％ 5.23 2.93 0.73 1.62
#7 3.5％ 5.14 2.99 0.71 1.53
#8 3.2％ 5.16 2.92 0.84 1.54
#9 3.3％ 5.17 2.96 0.36 1.83
#10 3.4％ 5.21 2.90 0.77 1.53
#11 3.5％ 5.10 2.87 0.94 1.40
#12 7.1％ 5.39 3.08 1.35 1.00
#13 8.1％ 5.22 2.85 1.32 1.04
#14 8.8％ 4.95 2.75 1.33 0.89
#15 9.1％ 5.18 2.86 1.54 0.80
#16 9.9％ 5.06 2.88 1.36 0.88
#17 9.0％ 5.22 2.99 1.54 0.63
#18 10.8％ 5.12 2.95 1.35 0.86
#19 9.4％ 4.98 3.14 1.65 0.08
#20 8.9％ 4.87 2.89 1.24 0.85
表一中，第一列表示不同的样本(总共20个样本)，第二列FLK表示闪烁值，LS表示遮光层沿第二方向的宽度，Gate表示栅线沿第二方向的宽度，Up表示遮光层的第二部分沿第二方向的宽度，Down表示遮光层的第一部分沿第二方向的宽度。从表一中可以得出，样本1-11中，Up值均小于Down值，相应的闪烁值均小于5％，远远小于行业的管控要求10％；而样本12-20中，Up值均大于Down值，相应的闪烁值均大于7％。实际产品验证得出：上述非对称遮光层能够有效改善闪烁问题，尤其是遮光层中第二部分沿第二方向的宽度小于第一部分沿第二方向的宽度的设计。图17中a1图和a2图是两种电镜图，其中虚线之间的距离即为遮光层的第一部分沿第二方向OA方向的宽度，a1图遮光层的第一部分沿第二方向的宽度大于a2图中遮光层的第一部分沿第二方向的宽度，图17中a1图的FLK值为3.5％，图17中a2图的FLK值为7.8％。图17中a1图和a2图中包括两个晶体管、三条数据线102，其中，数据线上的小圆圈所在区域为第二电极142，两条数据线102之间的大圆圈所在区域为第一电极141。
表二
Figure PCTCN2021126090-appb-000001
表二中，第一列表示不同的样本(两组总共15个样本)，LS表示遮光层沿第二方向的宽度，Gate表示栅线沿第二方向的宽度，Up表示遮光层的第二部分沿第二方向的宽度，Down表示遮光层的第一部分沿第二方向的宽度，IOFF@20000nit表示在亮度为20000nit的光线照射下的漏电流。从表二中可以得出，第二组8个样本的漏电流平均值比第一组7个样本的漏电流平均值高25％。第一组中，7个样本的Up值均小于Down值；第二组中，8个样本的Up值均大于Down值。实际产品验证得出：上述非对称遮光层能够有效降低漏电流，尤其是遮光层中第二部分沿第二方向的宽度小于第一部分沿第二方向的宽度的设计。
下面再提供一种遮光层的结构。
可选的，在第一掺杂子部和第二掺杂子部在衬底上的正投影位于第一部分在衬底上的正投影以内，且第一接触子部、第二接触子部和掺杂部在衬底上的正投影与第一部分在衬底上的正投影不交叠的情况下，第一部分包括第一子部分和第二子部分，第一子部分和第二子部分均与交叠部分相连，第一掺杂子部在衬底上的正投影位于第一子部分在衬底上的正投影以内，第二掺 杂子部在衬底上的正投影位于第二子部分在衬底上的正投影以内。
这样，遮光层的第一子部分可以阻挡背光源射向第一掺杂子部的光线，第二子部分可以阻挡背光源射向第二掺杂子部的光线，交叠部分可以阻挡射向栅线、第一沟道部和第二沟道部的光线；该结构中，第一部分的面积较小，有利于实现高PPI产品。
在一个或多个实施例中半导体层在衬底上的正投影位于遮光层在衬底上的正投影以内，且遮光层在衬底上的正投影的边界形状和半导体层在衬底上的正投影的边界形状相同。结合图13和图14所示，半导体层中，第一接触子部121、第一掺杂子部122、第一沟道部123、掺杂部124、第二沟道部125、第二掺杂子部126、第二接触子部127在衬底1上的正投影分别为H8、H7、H6、H5、H4、H3和H2，均位于遮光层11在衬底1上的正投影H1以内。
这样，遮光层可以阻挡背光源射向半导体层的光线，同时可以阻挡背光源射向第一栅极和第二栅极的光线；该结构的遮光层无需遮挡整条栅线，设计面积小。
在一个或多个实施例中，为了尽可能地减少遮光层的面积，结合图15和16所示，遮光层11包括不相连的第一遮光部113和第二遮光部112，第一遮光部113在衬底1上的正投影至少覆盖第一栅极131在衬底1上的正投影以及第一接触部31在衬底1上的部分正投影，第二遮光部112在衬底1上的正投影至少覆盖第二栅极132在衬底1上的正投影以及第二接触部32在衬底1上的部分正投影。
上述第一遮光部在衬底上的正投影至少覆盖第一栅极在衬底上的正投影以及第一接触部在衬底上的部分正投影包括：第一遮光部在衬底上的正投影覆盖第一栅极在衬底上的正投影以及第一接触部在衬底上的部分正投影；示例的，若第一接触部包括第一接触子部和第一掺杂子部，第一遮光部在衬底上的正投影可以覆盖第一接触子部或者第一掺杂子部在衬底上的至少部分正投影，图15以第一遮光部113在衬底上的正投影覆盖第一掺杂子部122在衬底上的正投影为例进行绘示。或者，第一遮光部在衬底上的正投影覆盖第一栅极在衬底上的正投影以及第一接触部在衬底上的全部正投影。或者，第一遮光部在衬底上的正投影还可以覆盖除第一栅极和第一接触部在衬底上的正投影以外的正投影。
上述第二遮光部在衬底上的正投影至少覆盖第二栅极在衬底上的正投 影以及第二接触部在衬底上的部分正投影包括：第二遮光部在衬底上的正投影覆盖第二栅极在衬底上的正投影以及第二接触部在衬底上的部分正投影；示例的，若第二接触部包括第二接触子部和第二掺杂子部，第二遮光部在衬底上的正投影可以覆盖第二接触子部或者第二掺杂子部在衬底上的至少部分正投影，图15以第二遮光部32在衬底上的正投影覆盖第二掺杂子部126在衬底上的部分正投影为例进行绘示。或者，第二遮光部在衬底上的正投影覆盖第二栅极在衬底上的正投影以及第二接触部在衬底上的全部正投影。或者，第二遮光部在衬底上的正投影还可以覆盖除第二栅极和第二接触部在衬底上的正投影以外的正投影。图16中，第一沟道部123在衬底1上的正投影J6、第一掺杂子部122在在衬底1上的正投影J7、掺杂部124在在衬底1上的部分正投影J5均位于第一遮光部113在衬底1上的正投影J8内，第二沟道部125在衬底1上的正投影J3、第二掺杂子部126在在衬底1上的部分正投影J2、掺杂部124在在衬底1上的部分正投影J4均位于第二遮光部112在衬底1上的正投影J1内。
上述第二掺杂子部沿第二方向的长度可以大于第一掺杂子部沿第二方向的长度，第二遮光部中遮挡第二掺杂子部的部分沿第一方向的宽度与第一掺杂子部沿第二方向的长度相同。这样，第二接触子部和第一接触子部沿第二方向交错设置，可以进一步节省空间；同时在保证降低漏电流的同时，进一步地减少遮光层的面积。
本申请实施例还提供了一种显示面板，参考图18所示，包括相对的彩膜基板40和上述的阵列基板41；其中，彩膜基板40包括黑矩阵401，黑矩阵401在阵列基板41的衬底411上的正投影M覆盖阵列基板41的遮光层412在衬底411上的正投影N。
需要说明的是，阵列基板中与黑矩阵对应的区域属于非开口区，将遮光层设置在非开口区，可以在不降低开口率的情况下，降低漏电流并改善闪烁现象，提升产品品质和用户体验。图18中，彩膜基板40还可以基底402，黑矩阵401可以设置在基底402上，当然还可以包括彩膜层等其它结构。显示面板还可以包括设置在彩膜基板40和阵列基板41之间的液晶42，以形成液晶显示面板。
该显示面板的类型不做限定，其可以是TN(Twisted Nematic，扭曲向列)型、VA(Vertical Alignment，垂直取向)型、IPS(In-Plane Switching，平面转换)型或ADS(Advanced Super Dimension Switch，高级超维场转换) 型等液晶显示面板、以及包括这些液晶显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，其中，包括衬底以及设置在所述衬底上的阵列排布的多个子像素；所述子像素包括依次层叠设置在所述衬底上的遮光层、半导体层、栅极层、源漏层和像素电极层；
    所述半导体层包括依次相连的第一接触部、第一沟道部、掺杂部、第二沟道部和第二接触部；所述栅极层包括第一栅极和第二栅极；所述源漏层包括第一极和第二极；所述像素电极层包括像素电极；所述第一极分别与所述第一接触部和所述像素电极电连接，所述第二极与所述第二接触部电连接；
    其中，所述第一沟道部和所述第一栅极沿垂直于所述衬底的方向交叠，所述第二沟道部和所述第二栅极沿垂直于所述衬底的方向交叠；
    所述遮光层在所述衬底上的正投影至少覆盖所述第一沟道部、所述第二沟道部和部分所述第一接触部在衬底上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述栅极层还包括栅线；
    所述第一栅极为所述栅线沿垂直于所述衬底的方向与所述第一沟道部交叠的部分，所述第二栅极为所述栅线沿垂直于所述衬底的方向与所述第二沟道部交叠的部分；
    所述栅线沿第一方向延伸，所述掺杂部在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的第一侧，所述第一接触部和所述第二接触部在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的第二侧，所述第一侧和所述第二侧相对。
  3. 根据权利要求2所述的阵列基板，其中，所述遮光层沿所述第一方向延伸，所述栅线在所述衬底上的正投影位于所述遮光层在所述衬底上的正投影以内。
  4. 根据权利要求3所述的阵列基板，其中，所述遮光层至少包括交叠部分和第一部分，所述交叠部分沿所述第一方向延伸、且在所述衬底上的正投影与所述栅线在所述衬底上的正投影重合，所述第一部分在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的所述第二侧；
    所述第一接触部包括第一接触子部和第一掺杂子部，所述第一掺杂子 部设置在所述第一接触子部和所述第一沟道部之间，所述第一接触子部与所述第一极电连接；
    其中，所述第一掺杂子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内；和/或，所述第一接触子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内。
  5. 根据权利要求4所述的阵列基板，其中，所述第二接触部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠，所述掺杂部在所述衬底上的正投影与所述遮光层在所述衬底上的正投影不交叠。
  6. 根据权利要求5所述的阵列基板，其中，在所述第一接触子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内、且所述第一掺杂子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分与所述交叠部分不相连。
  7. 根据权利要求4所述的阵列基板，其中，所述第二接触部包括第二接触子部和第二掺杂子部，所述第二掺杂子部设置在所述第二接触子部和所述第二沟道部之间，所述第二接触子部与所述第二极电连接；
    其中，所述第二掺杂子部在所述衬底上的至少部分正投影位于所述第一部分在所述衬底上的正投影以内。
  8. 根据权利要求7所述的阵列基板，其中，所述第二接触子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠。
  9. 根据权利要求8所述的阵列基板，其中，在所述第一掺杂子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内、且所述第一接触子部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分沿所述第一方向延伸、且与所述交叠部分相连。
  10. 根据权利要求9所述的阵列基板，其中，所述第二掺杂子部沿第二方向的长度大于所述第一掺杂子部沿所述第二方向的长度；
    所述第一部分沿所述第二方向的宽度与所述第一掺杂子部沿所述第二方向的长度相同，所述第二方向与所述第一方向垂直；所述掺杂部在所述衬底上的正投影与所述遮光层在所述衬底上的正投影不交叠。
  11. 根据权利要求9所述的阵列基板，其中，所述遮光层还包括第二部分，所述第二部分在所述衬底上的正投影位于所述栅线在所述衬底上的正投影的所述第一侧；
    所述第二部分在所述衬底上的正投影与所述掺杂部在所述衬底上的正投影部分交叠，且所述第二部分沿第二方向的宽度小于所述第一部分沿所述第二方向的宽度。
  12. 根据权利要求8所述的阵列基板，其中，在所述第一掺杂子部和所述第二掺杂子部在所述衬底上的正投影位于所述第一部分在所述衬底上的正投影以内，且所述第一接触子部、所述第二接触子部和所述掺杂部在所述衬底上的正投影与所述第一部分在所述衬底上的正投影不交叠的情况下，所述第一部分包括第一子部分和第二子部分，所述第一子部分和所述第二子部分均与所述交叠部分相连，所述第一掺杂子部在所述衬底上的正投影位于所述第一子部分在所述衬底上的正投影以内，所述第二掺杂子部在所述衬底上的正投影位于所述第二子部分在所述衬底上的正投影以内。
  13. 根据权利要求2所述的阵列基板，其中，所述半导体层在所述衬底上的正投影位于所述遮光层在所述衬底上的正投影以内，且所述遮光层在所述衬底上的正投影的边界形状和所述半导体层在所述衬底上的正投影的边界形状相同。
  14. 根据权利要求2所述的阵列基板，其中，所述遮光层包括不相连的第一遮光部和第二遮光部，所述第一遮光部在所述衬底上的正投影至少覆盖所述第一栅极在所述衬底上的正投影以及所述第一接触部在所述衬底上的部分正投影，所述第二遮光部在所述衬底上的正投影至少覆盖所述第二栅极在所述衬底上的正投影以及所述第二接触部在所述衬底上的部分正投影。
  15. 一种显示面板，其中，包括相对的彩膜基板和权利要求1-14任一项所述的阵列基板；
    其中，所述彩膜基板包括黑矩阵，所述黑矩阵在所述阵列基板的衬底上正投影覆盖所述阵列基板的遮光层在所述衬底上的正投影。
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