WO2022239620A1 - パッケージ - Google Patents

パッケージ Download PDF

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Publication number
WO2022239620A1
WO2022239620A1 PCT/JP2022/018467 JP2022018467W WO2022239620A1 WO 2022239620 A1 WO2022239620 A1 WO 2022239620A1 JP 2022018467 W JP2022018467 W JP 2022018467W WO 2022239620 A1 WO2022239620 A1 WO 2022239620A1
Authority
WO
WIPO (PCT)
Prior art keywords
package
electronic component
plate
wiring
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/018467
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
洋平 森山
敦司 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2023520948A priority Critical patent/JPWO2022239620A1/ja
Publication of WO2022239620A1 publication Critical patent/WO2022239620A1/ja
Priority to US18/504,850 priority patent/US20240072010A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This embodiment relates to a package on which electronic components are mounted.
  • the electronic components After being mounted on the package, the electronic components are mounted on the circuit board. Electronic components are electrically connected to peripheral components mounted on the circuit board through wiring arranged on the circuit board.
  • the heat generated by the electronic components can be efficiently released to the outside of the package.
  • a package larger than the electronic component is used in order to improve the heat radiation performance of the electronic component.
  • the peripheral components are placed outside the area where the package is mounted on the circuit board, using a large package increases the distance between the electronic components and the peripheral components. As a result, the wiring of the circuit board electrically connecting the electronic component and the peripheral component becomes long. As the size of the package is increased in order to improve the heat dissipation property of the package, the wiring for connecting to the electronic component becomes longer and the parasitic inductance of the wiring increases.
  • the purpose of this embodiment is to increase the heat dissipation of a package on which an electronic component is mounted, and to reduce the length of the wiring connected to the electronic component on the wiring board on which the package is mounted.
  • a package includes a first portion in which a mounting area for mounting an electronic component is defined, and a second portion connected to the first portion.
  • the area of the second portion is larger than that of the first portion in a plan view seen from the surface normal direction of the surface where the first portion and the second portion are connected.
  • FIG. 1 is a schematic diagram showing the configuration of a package according to the first embodiment.
  • FIG. 2 is a schematic diagram showing connections between the electronic components mounted on the package and the wiring arranged on the wiring board according to the first embodiment.
  • FIG. 3 is a schematic diagram showing the configuration of a package of a comparative example.
  • FIG. 4 is a schematic diagram showing a heat diffusion region.
  • FIG. 5 is another schematic diagram showing a heat diffusion region.
  • FIG. 6 is a schematic diagram for explaining the size of the package according to the first embodiment.
  • FIG. 7 is a schematic diagram showing a model for explaining heat diffusion.
  • FIG. 8 is a schematic diagram showing the configuration of a package according to a modification of the first embodiment.
  • FIG. 9 is a schematic diagram showing the configuration of a package according to the second embodiment.
  • FIG. 10 is a schematic diagram showing an example of arrangement of support columns of a package according to the second embodiment.
  • a package 1 according to the first embodiment can mount an electronic component 100, and has a first portion 11 and a second portion 12 connected to the first portion 11, as shown in FIG.
  • the first part 11 and the second part 12 of the package 1 may be integrated.
  • the entire structure in which the first portion 11 and the second portion 12 are connected is referred to as a mounting portion 10 .
  • the electronic component 100 is a transistor or the like formed on a semiconductor substrate.
  • a package 1 mounted with a transistor formed on a gallium nitride (GaN) substrate is mounted on the surface of the wiring substrate 2 .
  • GaN gallium nitride
  • FIG. 1 shows a state in which an electronic component 100 is mounted in a mounting area inside the first portion 11 .
  • plane view in a plan view (hereinafter simply referred to as “plan view”) of the plane where the first portion 11 and the second portion 12 are connected, the first portion 11 Also, the area of the second portion 12 is large.
  • the area in plan view is also simply referred to as "area".
  • the normal direction of the surface where the first portion 11 and the second portion 12 are connected is defined as the Z-axis direction.
  • a plane perpendicular to the Z-axis direction is defined as the XY plane, the left-right direction of FIG. 1 is defined as the X-axis direction, and the direction perpendicular to the paper surface is defined as the Y-axis direction.
  • the package 1 is mounted on the wiring board 2 with the first portion 11 facing the wiring board 2 .
  • the package 1 is configured such that the electronic component 100 can be electrically connected to the wiring arranged on the wiring substrate 2 .
  • the electronic component 100 and the wiring arranged on the wiring substrate 2 are electrically connected via terminals (not shown) arranged on the package 1 .
  • the first portion 11 has a first plate 111 and a second plate 112 that are spaced apart and face each other.
  • the first plate 111 faces the wiring board 2 .
  • a second plate 112 is connected to the second portion 12 .
  • Electronic component 100 is mounted in a hollow portion between first plate 111 and second plate 112 .
  • a mounting area is set on the surface of the second plate 112 facing the first plate 111 , and the electronic component 100 is bonded to the second plate 112 .
  • Both sides of the second portion 12 are defined by a first surface 121 connected to the first portion 11 and a second surface 122 facing the first surface 121 .
  • the first surface 121 is thermally connected to the mounting area of the first portion 11 .
  • the first surface 121 of the second portion 12 and the mounting area are thermally connected.
  • the electronic component 100 may be soldered to the mounting area of the first portion 11 to thermally connect the first surface 121 and the mounting area.
  • the electronic component 100 may be bonded to the mounting area of the first portion 11 with an adhesive having thermal conductivity.
  • the mounting portion 10 By forming the mounting portion 10 from a material with good thermal conductivity, the heat generated by the electronic component 100 can be efficiently dissipated from the second surface 122 of the second portion 12 to the outside of the mounting portion 10 . Therefore, a metal material may be used for the mounting portion 10 .
  • copper which has high thermal conductivity, may be used as the material of the mounting portion 10 .
  • the thermal conductivity of the mounting portion 10 is approximately 400 W/(m ⁇ K).
  • lightweight aluminum may be used as the material for the mounting portion 10 .
  • the area of the second portion 12 is larger than the first portion 11 including the mounting area in a plan view. Heat can be effectively dissipated from the portion 12. - ⁇
  • the mounting area is surrounded by the first plate 111, the second plate 112, and the side plate 113 connecting the first plate 111 and the second plate 112.
  • electronic component 100 is also in contact with side plate 113 of first portion 11 , heat generated in electronic component 100 is more efficiently transferred to first portion 11 than when electronic component 100 is in contact only with second plate 112 . from to the second portion 12 .
  • the first portion 11 is arranged in the center of the first surface 121 of the second portion 12, for example.
  • heat generated in electronic component 100 spreads evenly from the region of first surface 121 contacting first portion 11 toward second surface 122 . while propagating through the second portion 12 . Evenly spreading the heat generated in the electronic component 100 allows the entire second portion 12 to be used for heat propagation.
  • the electronic component 100 mounted on the package 1 is electrically connected to the wiring arranged on the wiring board 2 via terminals (not shown) arranged on the surface of the first portion 11, for example.
  • the peripheral component 3 is, for example, a driving device that drives the electronic component 100 when the electronic component 100 is an active element such as a transistor.
  • the peripheral component 3 is a passive component added to the electronic component 100, such as a chip capacitor or a resistive element.
  • the peripheral component 3 is a gate driver (GD) that drives the transistor.
  • FIG. 2 shows an example of connection between the electronic component 100 and wiring arranged on the wiring board 2 when the electronic component 100 is a transistor having a drain electrode D, a source electrode S, and a gate electrode G.
  • a drain electrode D of the electronic component 100 is electrically connected to a drain wiring 201 arranged on the wiring board 2 .
  • a source electrode S of the electronic component 100 is electrically connected to a ground wiring GND arranged on the wiring board 2 .
  • the gate electrode G of the electronic component 100 is electrically connected to the GD as the peripheral component 3 through wiring arranged on the wiring substrate 2 .
  • GD is connected to an oscillator circuit 31 and a power supply circuit 32 arranged on the wiring board 2 .
  • a capacitor C is connected between the wiring connecting the GD and the power supply circuit 32 and the ground wiring GND.
  • the mounting portion 10 has a mesa shape in which the first portion 11 protrudes from the second portion 12 in a side view seen from a direction perpendicular to a plane where the first portion 11 and the second portion 12 are connected.
  • the thickness of the first portion 11 along the Z-axis direction (hereinafter simply referred to as “thickness”) is between the second portion 12 and the wiring board 2 . ) is provided. Therefore, the peripheral component 3 can be arranged between the second portion 12 and the wiring board 2 as shown in FIG. Therefore, according to the package 1, when the package 1 is arranged on the wiring board 2, the wiring of the wiring board 2 connecting the electronic component 100 and the peripheral component 3 can be shortened.
  • the peripheral component 3 can be arranged between the second portion 12 and the wiring board 2 . Therefore, the wiring connecting the electronic component 100 mounted on the package 1 and the peripheral component 3 is shorter than the wiring connecting the electronic component 100 mounted on the package 1a and the peripheral component 3 . Therefore, according to the package 1, it is possible to suppress an increase in the parasitic inductance of the wiring.
  • the package 1 shown in FIG. 1 has an insulating thermally conductive sheet 20 arranged on the second surface 122 of the second portion 12 .
  • the heat conductive sheet 20 faces the first portion 11 with the second portion 12 interposed therebetween.
  • the package 1 has a heat sink 30 arranged on the thermally conductive sheet 20 and facing the second portion 12 with the thermally conductive sheet 20 interposed therebetween.
  • the heat generated by the electronic component 100 propagates to the heat sink 30 via the mounting portion 10 and the heat conductive sheet 20 .
  • the heat sink 30 releases heat propagated from the thermally conductive sheet 20 to the outside of the package 1 .
  • a sheet-like member with high thermal conductivity such as a resin sheet is used for the thermally conductive sheet 20 .
  • the thermal conductivity of the thermally conductive sheet 20 is, for example, approximately several W/(m ⁇ K).
  • a silicone sheet or the like is used for the heat conductive sheet 20 .
  • a material with high thermal conductivity such as metal is used as the material of the heat sink 30 .
  • copper or aluminum is used for the material of the heat sink 30 .
  • the heat sink 30 made of aluminum has a thermal conductivity of about 200 W/(m ⁇ K).
  • the hatched heat diffusion region 200 extends only to a partial region of the second surface 122 of the second portion 12 . do not have. That is, even if the area of the heat conductive sheet is increased, if the heat diffusion area 200 on the second surface 122 is narrow, the heat dissipation effect of the heat generated in the electronic component 100 is reduced.
  • a condition for setting the thickness of the second portion 12 so that the heat diffusion region 200 covers substantially the entire surface of the second surface 122 is hereinafter also referred to as a “setting condition”.
  • the size of the mounting portion 10 will be examined as a setting condition for realizing high thermal conductivity in the package 1 .
  • the size of the first portion 11 and the size of the second portion 12 are defined as shown in FIG.
  • the length of the side in the X-axis direction is also referred to as "width”
  • the length of the side in the Y-axis direction is also referred to as “depth”
  • the length of the side in the Z-axis direction is also referred to as "height”.
  • the size of the first portion 11 is Wm1 in width, dm1 in depth, and hm1 in height.
  • the size of the second portion 12 is width Wm2, depth dm2, and height hm2.
  • Width Wm1, depth dm1, and height hm1 are greater than the width, depth, and height of electronic component 100, respectively.
  • the height hm1 is greater than the height of the peripheral component 3 .
  • the width Wm2 and depth dm2 of the second portion 12 are equal to the width and depth of the thermally conductive sheet 20, respectively. Therefore, the height hm2 at which the heat diffusion region 200 spreads over the range of the width Wm2 and the depth dm2 may be determined as a setting condition.
  • the peripheral component 3 can be arranged between the first portion 11 and between the second portion 12 and the wiring board 2 in plan view. As a result, for the plurality of electronic components 100 mounted on the package 1, the wiring connecting each electronic component 100 and the peripheral component 3 can be shortened.
  • FIG. 9 shows a package 1 according to a second embodiment.
  • the package 1 shown in FIG. 9 further comprises struts 40 arranged on the second portion 12 in the remaining area of the area where the first portion 11 is arranged.
  • the strut 40 extends in the normal direction of the plane where the first portion 11 and the second portion 12 are connected. Part of the post 40 penetrates the wiring board 2 and is fixed to the wiring board 2 .
  • Other configurations of the package 1 shown in FIG. 9 are the same as those of the first embodiment shown in FIG.
  • the second portion 12 may be distorted if the wiring board 2 is connected only with the first portion 11 of the package 1. If the second portion 12 is distorted, the electronic component 100 may be separated from the mounting area or damaged. In particular, when the size of electronic component 100 is small, the relative area of second portion 12 to first portion 11 is large, and second portion 12 is likely to be distorted. For example, if the electronic component 100 is a semiconductor device formed on a GaN substrate, the size of the first portion 11 is designed to be small in order to reduce parasitic inductance.
  • the package 1 having the struts 40 for example, as shown in FIG. 10, four struts 40 are arranged in the outer edge region of the first surface 121 of the second portion 12 so as to surround the first portion 11. .
  • One end of the post 40 is connected to the second portion 12 and the other end is connected to the wiring board 2 . Therefore, according to the package 1 having the struts 40 , it is possible to prevent the second portion 12 from being distorted. As a result, it is possible to prevent the electronic component 100 from being detached from the mounting area and the electronic component 100 from being damaged due to the strain generated in the second portion 12 .
  • the arrangement of the struts 40 shown in FIG. 10 is an example, and the position or number of the struts 40 can be set arbitrarily.
  • the package 1 according to the second embodiment is substantially the same as the first embodiment, and duplicate descriptions are omitted.
  • the package 1 having the configuration in which the heat conductive sheet 20 is arranged between the mounting portion 10 and the heat sink 30 is shown above, but the package 1 does not have the heat conductive sheet 20 and the heat sink 30 is arranged on the mounting portion 10. You may
  • the above shows the case where the first portion 11 is arranged in the center of the first surface 121 of the second portion 12 .
  • the first portion 11 can be arranged at any position on the first surface 121 of the second portion 12 .
  • the position of the first portion 11 relative to the second portion 12 may be adjusted according to the position of the peripheral component 3 arranged on the wiring board 2 or the like.
  • this embodiment includes various embodiments not described here.
  • Appendix (Appendix 1) A package capable of mounting an electronic component, a first portion in which a mounting area for mounting the electronic component is defined; a second portion connected to the first portion; A package, wherein the area of the second portion is larger than that of the first portion in a plan view seen from a surface normal direction of a surface connecting the first portion and the second portion.
  • Appendix 2 the first portion having spaced apart first and second plates; The mounting area is set on a surface of the second plate facing the first plate, the second plate is connected to the second portion; A package as described in Appendix 1.
  • the first portion has a side plate connecting the first plate and the second plate, the electronic component arranged in the mounting area is in contact with the side plate; A package as described in Appendix 2.
  • the first portion 11 and the second portion are parallelepiped-shaped, Assuming that the width Wm1 and depth dm1 of the first portion 11 and the width Wm2, depth dm2 and height hm2 of the second portion 12, Wm2 ⁇ Wm1+2 ⁇ hm2 dm2 ⁇ dm1+2 ⁇ hm2
  • the heat diffusion area is substantially the entire second surface, and high thermal conductivity can be achieved.
  • the first portion 11 and the second portion are parallelepiped-shaped, The first portion 11 has a width Wm1 and a depth dm1, and the second portion 12 has a width Wm2, a depth dm2 and a height hm2.
  • hm2 ⁇ (Wm2 ⁇ Wm1)/2 ⁇ sin ⁇ /cos ⁇ hm2 ⁇ (dm2 ⁇ dm1)/2 ⁇ sin ⁇ /cos ⁇ The package according to Appendix 7, satisfying the relationship:
  • the heat diffusion area is substantially the entire second surface, and high thermal conductivity can be achieved.
  • Appendix 11 A package configured to be mountable on the surface of a wiring board, Further comprising a post arranged in a region of the second portion remaining in the region where the first portion is arranged and extending in the direction normal to the surface; 11. The package according to any one of appendices 1 to 10, wherein one end of the support is connected to the second portion and the other end is connected to the wiring board facing the first portion.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2022/018467 2021-05-13 2022-04-21 パッケージ Ceased WO2022239620A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2023520948A JPWO2022239620A1 (https=) 2021-05-13 2022-04-21
US18/504,850 US20240072010A1 (en) 2021-05-13 2023-11-08 Package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-081690 2021-05-13
JP2021081690 2021-05-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/504,850 Continuation US20240072010A1 (en) 2021-05-13 2023-11-08 Package

Publications (1)

Publication Number Publication Date
WO2022239620A1 true WO2022239620A1 (ja) 2022-11-17

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ID=84029566

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/018467 Ceased WO2022239620A1 (ja) 2021-05-13 2022-04-21 パッケージ

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US (1) US20240072010A1 (https=)
JP (1) JPWO2022239620A1 (https=)
WO (1) WO2022239620A1 (https=)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294740A (ja) * 2005-04-07 2006-10-26 Denso Corp 電子装置
JP2007329204A (ja) * 2006-06-06 2007-12-20 Otsuka Denki Kk 熱拡散装置および電子機器
JP2008218669A (ja) * 2007-03-02 2008-09-18 Nec Electronics Corp 半導体装置
JP2011096826A (ja) * 2009-10-29 2011-05-12 Fujitsu Ltd 半導体モジュール
JP2012204632A (ja) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
WO2021066024A1 (ja) * 2019-09-30 2021-04-08 京セラ株式会社 蓋体、電子部品収容用パッケージ及び電子装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815486B2 (en) * 2002-04-12 2004-11-09 Dow Corning Corporation Thermally conductive phase change materials and methods for their preparation and use
US7360586B2 (en) * 2003-07-31 2008-04-22 Fujitsu Limited Wrap around heat sink apparatus and method
US20050088092A1 (en) * 2003-10-17 2005-04-28 Myoung-Kon Kim Plasma display apparatus
US7449775B1 (en) * 2006-05-22 2008-11-11 Sun Microsystems, Inc. Integrated thermal solution for electronic packages with materials having mismatched coefficient of thermal expansion
JP5898919B2 (ja) * 2011-10-31 2016-04-06 新光電気工業株式会社 半導体装置
US10375859B2 (en) * 2013-06-26 2019-08-06 Molex, Llc Ganged shielding cage with thermal passages
US11330738B1 (en) * 2020-12-23 2022-05-10 Xilinx, Inc. Force balanced package mounting

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294740A (ja) * 2005-04-07 2006-10-26 Denso Corp 電子装置
JP2007329204A (ja) * 2006-06-06 2007-12-20 Otsuka Denki Kk 熱拡散装置および電子機器
JP2008218669A (ja) * 2007-03-02 2008-09-18 Nec Electronics Corp 半導体装置
JP2011096826A (ja) * 2009-10-29 2011-05-12 Fujitsu Ltd 半導体モジュール
JP2012204632A (ja) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
WO2021066024A1 (ja) * 2019-09-30 2021-04-08 京セラ株式会社 蓋体、電子部品収容用パッケージ及び電子装置

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US20240072010A1 (en) 2024-02-29
JPWO2022239620A1 (https=) 2022-11-17

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