WO2022237001A1 - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
WO2022237001A1
WO2022237001A1 PCT/CN2021/113623 CN2021113623W WO2022237001A1 WO 2022237001 A1 WO2022237001 A1 WO 2022237001A1 CN 2021113623 W CN2021113623 W CN 2021113623W WO 2022237001 A1 WO2022237001 A1 WO 2022237001A1
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layer
conductive layer
bit line
conductive
etched
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PCT/CN2021/113623
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English (en)
French (fr)
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李昇
金星
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长鑫存储技术有限公司
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Priority to US17/520,786 priority Critical patent/US20220367477A1/en
Publication of WO2022237001A1 publication Critical patent/WO2022237001A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor device and a method for forming the same.
  • Dynamic random access memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each storage unit usually includes a capacitor and a transistor. The source of the transistor is connected to the capacitor through the storage node contact (Node Contact, NC) and the landing pad (Landing Pad, LP), so as to read the data information stored in the capacitor. Alternatively, data information is written into a capacitor for storage.
  • NC storage node contact
  • LP landing pad
  • a contact hole is defined by forming two intersecting mask patterns, and a conductive material is filled in the contact hole to form a storage node contact; secondly, a landing pad is formed on the storage node contact through a patterning process.
  • the process of forming storage node contacts and landing pads in related technologies requires advanced exposure technology to form finer patterns, which is a severe challenge for high exposure rates.
  • the formation process of the storage node contact and the landing pad in the related art has many steps, the process is relatively complicated, and the manufacturing cost of the semiconductor device is relatively high.
  • An embodiment of the present application provides a method for forming a semiconductor device, the method comprising: providing a semiconductor substrate, the semiconductor substrate including a plurality of bit line structures arranged at intervals along a first direction; The surface is filled with a conductive material to form a conductive layer covering the surface of the bit line structure, the top surface of the conductive layer is beyond the top surface of the bit line structure; the conductive layer is etched to form a plurality of mutually independent first A conductive layer and a second conductive layer located on each of the first conductive layers.
  • the embodiment of the present application also provides a semiconductor device, the semiconductor device is formed by the method for forming the above-mentioned semiconductor device, and the semiconductor device includes: a semiconductor substrate on which a plurality of active region; a bit line structure, the bit line structure includes a bit line contact layer, a bit line metal layer and a bit line mask layer; the bit line metal layer intersects with the active region through the bit line contact layer; the The bit line structure is arranged at intervals along the first direction; the first conductive layer and the second conductive layer, the first conductive layer is connected to the capacitor through the second conductive layer; A first structure with a first predetermined height on the first conductive layer and a second structure with a second predetermined height located on a part of the bit line structure; the first predetermined height is greater than the predetermined height the second preset height.
  • FIG. 1 is an optional schematic flow chart of a method for forming a semiconductor device provided in an embodiment of the present application
  • FIGS. 2a-2e are schematic flow charts for forming a conductive layer provided in the embodiment of the present application.
  • 3a-3k, 4a-4g are schematic flow charts for forming the first conductive layer and the second conductive layer provided by the embodiment of the present application;
  • 5a and 5b are schematic diagrams of an optional structure of the semiconductor device provided by the embodiment of the present application.
  • FIG. 1 is an optional schematic flow chart of the method for forming a semiconductor device provided in the embodiment of the present application. As shown in FIG. 1 , the method includes the following steps:
  • Step S101 providing a semiconductor substrate, where the semiconductor substrate includes a plurality of bit line structures arranged at intervals along a first direction.
  • the material of the semiconductor substrate can be selected from silicon (Si), silicon germanium alloy (SiGe), silicon carbide (SiC), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), zinc oxide (ZnO) , gallium oxide (Ga 2 O 3 ) or lithium aluminate (LiAlO 2 ), etc. Since the Si substrate is cheap, easy to be doped, and easy to react to form a heterogeneous isolation layer, therefore, Si is selected as the substrate in the embodiment of the present application.
  • the semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; under the condition of ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the first Three directions.
  • the direction of the top surface and the bottom surface of the substrate that is, the plane where the substrate is located
  • the arrangement direction of a plurality of bit line structures can be defined as A first direction
  • a planar direction of the semiconductor substrate may be determined based on the first direction and the second direction.
  • the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • the bit line structure includes a bit line contact layer, a bit line metal layer and a bit line mask layer sequentially formed on the semiconductor substrate.
  • the semiconductor substrate includes at least one bit line structure.
  • Step S102 filling the surface of the bit line structure with a conductive material to form a conductive layer covering the surface of the bit line structure.
  • the top surface of the conductive layer exceeds the top surface of the bit line structure.
  • the conductive material may be any metal material or semiconductor material, and the conductive material may also be a mixed material of multiple metal materials, a mixed material of multiple semiconductor materials, or a mixed material of metal materials and semiconductor materials.
  • the conductive material includes a first conductive material and a second conductive material; the conductive layer includes a first initial conductive layer and a second initial conductive layer.
  • Step S103 etching the conductive layer to form a plurality of mutually independent first conductive layers and a second conductive layer located on each of the first conductive layers.
  • the semiconductor device may be a DRAM
  • the first conductive layer may be a storage node contact
  • the second conductive layer may be a landing pad
  • a plurality of mutually independent first conductive layers and a second conductive layer located on each first conductive layer can be formed by directly etching the conductive layer, thereby forming a semiconductor device.
  • the device in this way, can greatly simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device.
  • Figures 2a-2e are schematic flow charts for forming a conductive layer provided by the embodiment of the present application
  • Figures 3a-3k, 4a-4g are schematic flow charts for forming the first conductive layer and the second conductive layer provided by the embodiment of the present application.
  • FIG. 2a-2e, FIG. 3a-3k and FIG. 4a-4g are schematic structural diagrams during the formation process of the semiconductor device, to further describe in detail the method for forming the semiconductor device provided by the embodiment of the present application.
  • step S101 is performed to provide a semiconductor substrate, where the semiconductor substrate includes a plurality of bit line structures arranged at intervals along a first direction.
  • FIG. 2a is a schematic cross-sectional structure diagram of a semiconductor substrate including multiple bit line structures provided by an embodiment of the present application.
  • the semiconductor substrate 200 includes four bit line structures 201 arranged along the X-axis direction, each The bit line structure 201 includes a bit line contact layer 2011 , a bit line metal layer 2012 and a bit line mask layer 2013 stacked in sequence along the Z-axis direction.
  • the bit line mask layer 2013 is used as an etching mask to form the bit line metal layer 2012 .
  • the material of the bit line metal layer includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • the material of the bit line contact layer 2011 may be polysilicon
  • the bit line metal layer 2012 includes a metal tungsten layer 2012-1 and a titanium-containing metal layer 2012-2.
  • the titanium-containing metal layer may be a composite layer of a titanium nitride layer and a titanium metal layer.
  • FIG. 2a only exemplarily shows a limited number of bit line structures, and in an actual manufacturing process, the semiconductor substrate includes multiple bit line structures.
  • the semiconductor substrate 200 includes a plurality of active regions (not shown in the figure) out), the bit line contact layer 2011 intersects with the active region in the semiconductor substrate, and a bit line metal layer 2012 is formed above the bit line contact layer 2011, so that the bit line metal layer and the active area can be realized area electrical connection.
  • bit line contact layer and the bit line metal layer in the bit line structure is described as follows:
  • the active region includes at least a bit line contact region forming a bit line contact layer; the bit line contact layer and the bit line metal layer are formed by the following methods:
  • Step S10 forming a first dielectric layer on the surface of the semiconductor substrate, the first dielectric layer is used to protect the active region in the semiconductor substrate.
  • the first dielectric layer may be a silicon dioxide layer.
  • Step S11 etching the first dielectric layer and the active region, and forming a bit line contact hole in the bit line contact area.
  • Step S12 filling the bit line contact hole with a bit line contact material to form an initial bit line contact layer.
  • Step S13 sequentially depositing a metal layer and a bit line mask layer on the surface of the first dielectric layer.
  • Step S14 etching the metal layer and the initial bit line contact layer through the bit line mask layer to form the bit line contact layer and the bit line metal layer.
  • the semiconductor substrate 200 further includes: a second dielectric layer 202 located on the surface of the bit line structure 201, and the second dielectric layer 202 is used to isolate the bit line structure and other structures subsequently formed around the bit line structure, such as storage node contacts and landing pads.
  • the material of the second dielectric layer includes any one of the following: silicon nitride, silicon oxide and silicon oxynitride.
  • step S102 is performed to fill the surface of the bit line structure with a conductive material to form a conductive layer covering the surface of the bit line structure.
  • step S102 includes the following steps:
  • Step S1021 filling the surface of the bit line structure with a first conductive material to form the first initial conductive layer covering the surface of the bit line structure.
  • the surface of the bit line structure 201 is filled with a first conductive material to form a first initial conductive layer 203 covering the bit line structure 201 and the surface of the second dielectric layer 202 .
  • the first conductive material may be polysilicon, and the top surface 203 - 1 of the first initial conductive layer 203 protrudes beyond the top surface of the bit line structure 201 .
  • Step S1022 etching back the first initial conductive layer to expose a part of the bit line mask layer of the bit line structure.
  • the first initial conductive layer 203 is etched back using a dry etching process to reduce the height of the first initial conductive layer 203 in the Z-axis direction and expose part of the bit line structure 201.
  • the dry etching process includes plasma etching, reactive ion etching or ion milling.
  • Step S1023 filling the surface of the first initial conductive layer after etching back with a second conductive material to form the second initial conductive layer covering the surface of the part of the bit line mask layer.
  • the top surface of the second initial conductive layer is beyond the top surface of the bit line mask layer.
  • the surface of the first initial conductive layer 203 is filled with a second conductive material to form a second initial conductive layer 204 covering part of the surface of the bit line mask layer 2013 .
  • the second conductive material may be metal W, and the top surface 204 - 1 of the second initial conductive layer 204 is beyond the top surface of the bit line mask layer 2013 .
  • the method for forming the semiconductor device may further include:
  • Step S1024 performing chemical mechanical polishing or etching back on the second initial conductive layer.
  • the purpose of performing chemical mechanical polishing (CMP) or etching back on the second initial conductive layer is to make the second initial conductive layer have a flat surface, which is convenient for subsequent polishing on the second initial conductive layer. Grow other structures or layers.
  • CMP chemical mechanical polishing
  • the top surface 204-1 of the second initial conductive layer 204 still exceeds the top surface of the bit line mask layer 2013, and the second initial There is a preset height difference between the top surface 204 - 1 of the conductive layer 204 and the top surface of the bit line mask layer 2013 .
  • the preset height difference may be 10-80 nanometers.
  • step S103 is performed to etch the conductive layer to form a plurality of mutually independent first conductive layers and a first conductive layer located on each of the first conductive layers. Two conductive layers.
  • step S103 may include the following steps:
  • Step S1031 along the third direction, sequentially perform the first etching treatment on the first initial conductive layer and the second initial conductive layer to form a first etched conductive layer independent of each other along the second direction and along the second initial conductive layer.
  • the conductive layer is etched in a second direction independent of each other.
  • Step S1032 performing a second etching process on the second etched conductive layer along the third direction to form a plurality of mutually independent first conductive layers and a first conductive layer located on each of the first conductive layers.
  • Two conductive layers wherein, the second direction is perpendicular to the first direction, the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate is located, and the third direction is vertical on the plane where the semiconductor substrate is located.
  • the first etching process may include the following steps:
  • Step S20 forming a first mask layer with a first mask pattern on the surface of the second initial conductive layer.
  • the first mask layer includes a first hard mask layer, a first anti-reflection layer and a first photoresist layer stacked in sequence.
  • Step S20 is formed by the following steps:
  • Step S201 forming a first hard mask layer, a first anti-reflection layer, and a first photoresist layer on the surface of the second initial conductive layer; wherein, the first photoresist layer has a first initial mask pattern.
  • the first hard mask layer may be a spin-on-carbon layer
  • the first anti-reflection layer may be a silicon oxynitride layer.
  • the first hard mask layer, the first anti-reflection layer and the first photoresist layer can be formed by any suitable deposition process, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical Vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD).
  • a first hard mask layer 205, a first anti-reflection layer 206 and a first photoresist layer 207 are sequentially formed on the surface of the second initial conductive layer 204, constituting the first mask layer .
  • the first photoresist layer 207 has a first initial mask pattern, and the first initial mask pattern consists of a plurality of stripe patterns 2071 arranged in parallel along the X-axis direction.
  • Step S202 forming an isolation layer on the surface of the first photoresist layer having the first initial mask pattern.
  • an isolation layer 208 is formed on the surface of the first photoresist layer 207 having the first initial mask pattern.
  • the isolation layer material may be silicon oxide.
  • Step S203 sequentially etching the isolation layer and the first initial mask pattern, retaining the isolation layer on the sidewall of the first initial mask pattern, and forming an isolation sidewall pattern.
  • the isolation layer 208 and the first initial mask pattern are sequentially etched by a dry etching process, and the isolation layer 208 located on the sidewall of each striped pattern 2071 in the first initial mask pattern is retained, so that The isolation sidewall pattern 2081 is formed.
  • Step S204 etching the first anti-reflection layer and the first hard mask layer through the isolation spacer pattern to form the first mask layer with the first mask pattern.
  • the isolation spacer pattern is the first mask pattern, and after the isolation spacer pattern is formed, the first mask layer having the first mask pattern is formed, A subsequent first etching process can be performed by isolating the spacer pattern.
  • Step S21 sequentially etching the second initial conductive layer and the first initial conductive layer through the first mask layer, so as to transfer the first mask pattern to the second initial conductive layer And in the first initial conductive layer, the first etched conductive layers independent of each other along the second direction and the second etched conductive layers independent of each other along the second direction are formed.
  • Figure 3e is a schematic diagram of the three-dimensional structure of the first etched conductive layer and the second etched conductive layer provided by the embodiment of the present application
  • Figure 3f is a schematic diagram of the cross-sectional structure along AA' in Figure 3e
  • Figure 3g is a schematic diagram of the first etched conductive layer formed The top view of the etched conductive layer and the second etched conductive layer, as shown in FIGS. 3e-3g, after etching the second initial conductive layer 204 and the first initial conductive layer 203 through the first mask layer, a The first etched conductive layer 203' which is independent of each other along the Y-axis direction and the second etched conductive layer 204' which is mutually independent along the Y-axis direction.
  • any adjacent two first etched conductive layers A first etching trench is formed between them, and a second etching trench is formed between any two adjacent second etching conductive layers.
  • a first etch trench T1 is formed between any two adjacent first etched conductive layers 203 ′, and a first etched trench T1 is formed between any adjacent two second etched conductive layers 204 'A second etched trench T2 is formed between them.
  • the method for forming the semiconductor device may further include:
  • Step S30 filling the first etched trench between any adjacent two first etched conductive layers and the second etched trench between any adjacent two second etched conductive layers A contact isolation material is used to form a storage contact isolation layer.
  • the first etched trench T1 between any adjacent two first etched conductive layers 203' and any adjacent two second etched conductive layers 204' The storage contact isolation material is filled in the second etched trench T2, forming the storage contact isolation layer 209, the top surface 209-1 of the storage contact isolation layer 209 is beyond the top surface 204 of the second etched conductive layer '-1.
  • the storage contact isolation material may be silicon nitride.
  • the storage contact isolation material will be filled during the filling process.
  • a gap is generated, and the generated gap can be used as an air gap between adjacent first conductive layers, so that the critical dimension (Critical Dimension, CD) of the first etched trench can be reduced, and correspondingly, the size of the first conductive layer will be The larger the resistance of the first conductive layer, the smaller the resistance-capacitance delay (Rc) will be.
  • CD Critical Dimension
  • Rc resistance-capacitance delay
  • Step S31 performing etching on the storage contact isolation layer to remove the storage contact isolation layer located on the top surface of the second etched conductive layer.
  • the storage contact isolation layer 209 is etched along the Z-axis direction by using a dry etching process until the top surface 204'-1 of the second etched conductive layer is exposed.
  • the second etching process is performed on the second etched conductive layer along the third direction to form a plurality of independent first conductive layers and each of the first conductive layers.
  • the second conductive layer above the layer includes: performing partial etching on the second etched conductive layer above the bit line mask layer along the third direction, exposing part of the bit line A mask layer, forming the first conductive layer and the second conductive layer on each of the first conductive layers which are independent from each other along the first direction.
  • the second etching process may include the following steps:
  • Step S22 forming a second mask layer with a second mask pattern on the surface of the second etched conductive layer and the surface of the storage contact isolation layer.
  • the second mask layer includes a second hard mask layer, a second anti-reflection layer and a second photoresist layer stacked in sequence.
  • Step S22 can be formed by the following steps:
  • Step S221 sequentially depositing and forming a second hard mask layer, a second anti-reflection layer and a second photoresist layer on the surfaces of the second etched conductive layer and the storage contact isolation layer.
  • the second hard mask layer is the same as the first hard mask layer
  • the second anti-reflection layer is the same as the first anti-reflection layer
  • the second photoresist layer is the same as the first anti-reflection layer.
  • a photoresist layer is the same.
  • a second hard mask layer 210, a second anti-reflection layer 211 and a second optical layer are sequentially deposited on the surface of the second etched conductive layer 204' and the surface of the storage contact isolation layer 209. resist layer 212 .
  • the second photoresist layer 212 has a second mask pattern; the second mask pattern includes a plurality of sub-patterns 2121 arranged in parallel along the X-axis direction; each of the sub-patterns 2121 is in contact with the The extending direction in a plane parallel to the semiconductor substrate has an included angle B with the first direction, and the included angle B is not equal to 90 degrees, for example, the included angle B may be 60 degrees or 120 degrees.
  • each sub-pattern and the second etched conductive layer have a pinched diamond-shaped area, and the diamond-shaped area is used to form a subsequent second conductive layer.
  • each of the sub-patterns 2121 and the second etched conductive layer 204 ′ has a pinched diamond-shaped region C.
  • Step S222 sequentially etching the second anti-reflection layer and the second hard mask layer through each of the sub-patterns to form the second mask layer with the second mask pattern.
  • the second mask pattern is used to perform the subsequent second etching process.
  • Step S23 using the second mask pattern to etch and remove part of the second etched conductive layer above the bit line mask layer, and the remaining second etched conductive layer forms the first Two conductive layers.
  • the second etching conductive layer 204 is etched through a second mask pattern to form a second conductive layer 204′′ on each of the first conductive layers 203′′.
  • the method for forming a semiconductor device may further include: after forming the second conductive layer, forming a capacitor on the surface of the second conductive layer.
  • forming a capacitor on the surface of the second conductive layer may include the following steps:
  • Step S40 filling an insulating material between any two adjacent second conductive layers to form an insulating layer.
  • Step S41 sequentially depositing a first electrode layer, a dielectric layer and a second electrode layer on the surface of the second conductive layer and the surface of the insulating layer to form the capacitor.
  • the material of the first electrode layer and the second electrode layer may include any one of the following: metal, doped semiconductor, conductive metal oxide and conductive metal nitride.
  • the method for forming a semiconductor device may further include: before forming the bit line structure, forming a word line structure inside the active region.
  • a transistor is formed in the active region of the semiconductor device provided by the embodiment of the present application, the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening of the transistor Or close, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • the embodiment of the present application provides a new semiconductor device formation process.
  • a new semiconductor device formation process By directly etching the conductive layer, a plurality of independent first conductive layers and a second conductive layer located on each first conductive layer are formed, and then The method of forming a semiconductor device is simple and ingenious, which greatly simplifies the process flow and production cost.
  • the method for forming a semiconductor device provided in the embodiment of the present application does not require advanced exposure technology, and the process is simple and easy for mass production.
  • the embodiment of the present application further provides a semiconductor device, and the semiconductor device is formed by the method for forming the semiconductor device provided in the above embodiment.
  • 5a and 5b are schematic structural diagrams of an optional semiconductor device provided by the embodiment of the present application.
  • the semiconductor device 30 includes: a semiconductor substrate 300, a bit line structure 301, a first conductive layer 303, second conductive layer 304 and capacitor.
  • a semiconductor substrate 300 on which a plurality of active regions (not shown) arranged at intervals are formed.
  • bit line structure 301 includes a bit line contact layer 3011, a bit line metal layer 3012 and a bit line mask layer 3013; the bit line metal layer 3012 communicates with the The source regions intersect; the bit line structures 301 are arranged at intervals along the first direction.
  • the first direction may be the X-axis direction
  • the bit line structures 301 are arranged at intervals along the X-axis direction.
  • the semiconductor device 30 may further include a dielectric layer 302 located on the surface of the bit line structure 301 , and the dielectric layer 302 is used to protect the bit line structure 301 .
  • the first conductive layer may be a storage node contact
  • the second conductive layer may be a landing pad
  • the second conductive layer 304 includes a first structure with a first preset height h1 located on a part of the first conductive layer 303 and a first structure with a first predetermined height h1 located on a part of the bit line structure.
  • the semiconductor device 30 further includes: a storage contact isolation layer 309; the storage contact isolation layer 309 is located between any two adjacent first conductive layers 303, and is located at any Between two adjacent second conductive layers 304 .
  • the semiconductor device 30 further includes: an air gap 3091; the air gap 3091 is located in the storage contact isolation layer arranged in sequence along the second direction; wherein, the first The two directions are perpendicular to the first direction, and the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate 300 is located.
  • the second direction is the Y-axis direction.
  • the air gap 3091 is composed of a first part and a second part; the first part of the air gap 3091 is located at the storage contact isolation between two adjacent first conductive layers 303 In the layer, the second part of the air gap is located in the storage contact isolation layer between the adjacent two second conductive layers 304 corresponding to the adjacent two first conductive layers.
  • the first part and the second part are equal in size. In other embodiments, the sizes of the first portion and the second portion may also be unequal.
  • the height difference between the overlap of the first part and the second part of the air gap and the metal tungsten layer in the bit line structure is smaller than a preset height value, so that the adjacent Connections between first conductive layers and reduction of connections between adjacent second conductive layers.
  • the air gap 3091 has a third preset height h3 along the third direction; the storage contact isolation layer has a fourth preset height h4 along the third direction; The fourth preset height is greater than the third preset height, and the difference between the fourth preset height h4 and the third preset height h3 is smaller than the preset difference; wherein, the first The three directions are perpendicular to the plane where the semiconductor substrate is located. In the embodiment of the present application, there is no specific limitation on the magnitude of the preset difference.
  • the third direction is perpendicular to the first direction and the second direction, and the third direction is the Z-axis direction.
  • the semiconductor device 30 further includes an insulating layer 305 located between two adjacent second conductive layers 304, and the insulating layer is used to make the second conductive layer have a flat surface. The surface is convenient for the subsequent formation of capacitors on the second conductive layer.
  • the material of the insulating layer 305 may be silicon dioxide.
  • the capacitor includes: a first electrode layer 306 , a dielectric layer 307 and a second electrode layer 308 .
  • the material of the first electrode layer 306 and the second electrode layer 308 includes any one of the following: metal, doped semiconductor, conductive metal oxide and conductive metal nitride;
  • the material of the dielectric layer 307 includes Any of the following: materials with hazel oxide, zirconia, aluminum oxide, lanthanum oxide, tantalum oxide, titanium dioxide, and perovskite structures.
  • the semiconductor device provided in the embodiment of the present application is similar to the method for forming the semiconductor device provided in the above-mentioned embodiment.
  • the technical features not disclosed in detail in the embodiment of the present application please refer to the above-mentioned embodiment for understanding, and details will not be repeated here.
  • An embodiment of the present application provides a semiconductor device, because the semiconductor device has air in the storage contact isolation layer between adjacent first conductive layers and in the storage contact isolation layer between adjacent second conductive layers. In this way, the critical dimension of the storage contact isolation layer between adjacent first conductive layers can be reduced, so that the size of the first conductive layer increases, thereby reducing the resistance of the first conductive layer, and reducing the resistance-capacitance delay, so that The prepared semiconductor devices have excellent electrical properties.
  • the disclosed devices and methods may be implemented in non-target ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.

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Abstract

本申请实施例提供一种半导体器件及其形成方法，其中，所述方法包括：提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的位线结构；在所述位线结构的表面填充导电材料，形成覆盖于所述位线结构表面的导电层，所述导电层的顶表面超出于所述位线结构的顶表面；刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层。

Description

半导体器件及其形成方法
相关申请的交叉引用
本申请基于申请号为202110524592.7、申请日为2021年5月13日、发明名称为“半导体器件及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体器件及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每一个存储单元通常包括电容器和晶体管，晶体管的源极通过存储节点接触(Node Contact，NC)和着陆焊盘(Landing Pad，LP)与电容器连接，进而实现读取存储在电容器中的数据信息，或者，将数据信息写入电容器中进行存储。
相关技术中，首先，通过形成两个彼此相交的掩膜图案来定义一接触孔，并在接触孔中填充导电材料，形成存储节点接触；其次，在存储节点接触之上通过构图工艺形成着陆焊盘，由此可见，相关技术中形成存储节点接触和着陆焊盘的过程需要高级的曝光技术来形成更加精细的图案，这对高曝光率是一个严峻的挑战。另外，相关技术中的存储节点接触和着陆焊盘的形成过程步骤繁多，工艺较为复杂，半导体器件的制造成本较高。
发明内容
本申请实施例提供一种半导体器件的形成方法，所述方法包括：提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的位线结构；在所述位线结构的表面填充导电材料，形成覆盖于所述位线结构表面的导电层，所述导电层的顶表面超出于所述位线结构的顶表面；刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层。
本申请实施例还提供一种半导体器件，所述半导体器件通过上述半导体器件的形成方法形成，所述半导体器件包括：半导体衬底，所述半导体衬底上形成有多个间隔排布的有源区；位线结构，所述位线结构包括位线接触层、位线金属层和位线掩膜层；所述位线金属层通过所述位线接触层与所述有源区相交；所述位线结构沿第一方向间隔排布；第一导电层和第二导电层，所述第一导电层通过所述第二导电层连接至电容器；其中，所述第二导电层包括位于部分第一导电层之上的、具有第一预设高度的第一结构和位于部分所述位线结构之上的、具有第二预设高度的第二结构；所述第一预设高度大于所述第二预设高度。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本申请实施例提供的半导体器件的形成方法的一种可选的流程示意图；
图2a～2e为本申请实施例提供的形成导电层的流程示意图；
图3a～3k、4a～4g为本申请实施例提供的形成第一导电层和第二导电层的流程示意图；
图5a和5b为本申请实施例提供的半导体器件的一种可选的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对发明的具体技术方案做进一步详细描述。以下实施例用于说明本申请，但不用来限制本申请的范围。
在后续的描述中，使用用于表示元件的诸如“模块”或“单元”的后缀仅为了有利于本申请的说明，其本身没有特定的意义。因此，“模块”或“单元”可以混合地使用。
本申请实施例提供一种半导体器件的形成方法，图1为本申请实施例提供的半导体器件的形成方法的一种可选的流程示意图，如图1所示，所述方法包括以下步骤：
步骤S101、提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的位线结构。
这里，所述半导体衬底的材料可以选择硅(Si)、硅锗合金(SiGe)、碳化硅(SiC)、氧化铝(Al 2O 3)、氮化铝(AlN)、氧化锌(ZnO)、氧化镓(Ga 2O 3)或铝酸锂(LiAlO 2)等中的任意一种。由于Si衬底价格低廉，且易于掺杂，同时易于发生反应生成异质的隔离层，因此，本申请实施例中选择Si作为衬底。
所述半导体衬底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义垂直衬底顶表面和底表面的方向为第三方向。在衬底顶表面和底表面(即衬底所在的平面)方向上，定义两彼此相交(例如彼此垂直)的第一方向和第二方向，例如，可以定义多个位线结构的排列方向为第一方向，基于所述第一方向和所述第二方向可以确定所述半导体衬底的平面方向。这里，所述第一方向、所述第二方向和所述第三方向两两垂直。本申请实施例中，定义所述第一方向为X轴方向，定义所述第二方向为Y轴方向，定义所述第三方向为Z轴方向。
在一些实施例中，位线结构包括依次形成于所述半导体衬底上的位线接触层、位线金属层和位线掩膜层。本申请实施例中，所述半导体衬底包括至少一个位线结构。
步骤S102、在所述位线结构的表面填充导电材料，形成覆盖于所述位线结构表面的导电层。
其中，所述导电层的顶表面超出于所述位线结构的顶表面。
这里，所述导电材料可以是任意一种金属材料或者半导体材料，所述导电材料还可以是多种金属材料的混合材料、多种半导体材料的混合材料或者金属材料和半导体材料的混合材料。本申请实施例中，所述导电材料包括第一导电材料和第二导电材料；所述导电层包括第一初始导电层和第二初始导电层。
步骤S103、刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第 一导电层之上的第二导电层。
本申请实施例中，所述半导体器件可以是DRAM，所述第一导电层可以是存储节点接触，所述第二导电层可以是着陆焊盘。
本申请实施例提供的半导体器件的形成方法，由于可以通过直接刻蚀导电层，形成多个相互独立的第一导电层和位于每一第一导电层之上的第二导电层，进而形成半导体器件，如此，能够极大地简化半导体器件的制备工艺流程，降低半导体器件的制造成本。
图2a～2e为本申请实施例提供的形成导电层的流程示意图，图3a～3k、4a～4g为本申请实施例提供的形成第一导电层和第二导电层的流程示意图。接下来请参考图2a～2e、图3a～3k和图4a～4g中半导体器件形成过程中的结构示意图，对本申请实施例提供的半导体器件的形成方法进行进一步地详细说明。
首先，可以参考图2a，执行步骤S101、提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的位线结构。
图2a为本申请实施例提供的包含多个位线结构的半导体衬底的剖面结构示意图，如图2a所示，半导体衬底200包括4个沿X轴方向排列的位线结构201，每一位线结构201包括沿Z轴方向依次堆叠的位线接触层2011、位线金属层2012和位线掩膜层2013。所述位线掩膜层2013用于作为刻蚀掩膜版形成所述位线金属层2012。所述位线金属层的材料包括：钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。本申请实施例中，所述位线接触层2011的材料可以为多晶硅，所述位线金属层2012包括金属钨层2012-1和含钛金属层2012-2。例如，所述含钛金属层可以是氮化钛层和金属钛层的复合层。
需要说明是，图2a中仅仅示例性地示出了有限个数的位线结构，在实际制备过程中，半导体衬底包括多个位线结构。
下面，对所述位线结构与所述半导体衬底之间的位置关系进行如下说明：请继续参见图2a，所述半导体衬底200包括多个间隔排布的有源区(图中未示出)，所述位线接触层2011与半导体衬底中的有源区相交，且所述位线接触层2011的上方形成有位线金属层2012，如此，可以实现位线金属层与有源区的电连接。
接下来，对位线结构中位线接触层和所述位线金属层的形成过程进行如下说明：
在一些实施例中，所述有源区至少包括一形成位线接触层的位线接触区；所述位线接触层和所述位线金属层通过以下方式形成：
步骤S10、在所述半导体衬底的表面形成第一介质层，所述第一介质层用于保护所述半导体衬底中的有源区。
这里，所述第一介质层可以是二氧化硅层。
步骤S11、刻蚀所述第一介质层和所述有源区，在所述位线接触区形成位线接触孔。
步骤S12、在所述位线接触孔中填充位线接触材料，形成初始位线接触层。
步骤S13、在所述第一介质层的表面依次沉积形成金属层和位线掩膜层。
步骤S14、通过所述位线掩膜层，刻蚀所述金属层和所述初始位线接触层，形成所述位线接触层和所述位线金属层。
在一些实施例中，请继续参见图2a，所述半导体衬底200还包括：位于所述位线结构201表面的第二介质层202，所述第二介质层202用于隔离所述位线结构和后续在位线结构周围形成的其它结构，例如，存储节点接触和着陆焊盘。这里，所述第二介质层的材料包括以下任意一种：氮化硅、氧化硅和氮氧化硅。
接下来，可以参考图2b～2e，执行步骤S102、在所述位线结构的表面填充导电材 料，形成覆盖于所述位线结构表面的导电层。
在一些实施例中，步骤S102包括以下步骤：
步骤S1021、在所述位线结构的表面填充第一导电材料，形成覆盖于所述位线结构表面的所述第一初始导电层。
如图2b所示，在位线结构201的表面填充第一导电材料，形成覆盖于位线结构201和第二介质层202表面的第一初始导电层203。这里，所述第一导电材料可以是多晶硅，所述第一初始导电层203的顶表面203-1超出于位线结构201的顶表面。
步骤S1022、对所述第一初始导电层进行回刻，以暴露出所述位线结构的部分位线掩膜层。
如图2c所示，采用干法刻蚀工艺对第一初始导电层203进行回刻处理，以减小第一初始导电层203在Z轴方向上的高度，暴露出位线结构201的部分位线掩膜层2013。
这里，所述干法刻蚀工艺包括等离子体刻蚀、反应离子刻蚀或者离子铣。
步骤S1023、在回刻后的所述第一初始导电层的表面填充第二导电材料，形成覆盖于所述部分位线掩膜层表面的所述第二初始导电层。
其中，所述第二初始导电层的顶表面超出于所述位线掩膜层的顶表面。
如图2d所示，在第一初始导电层203的表面填充第二导电材料，形成覆盖于部分位线掩膜层2013表面的第二初始导电层204。这里，所述第二导电材料可以是金属W，所述第二初始导电层204的顶表面204-1超出于位线掩膜层2013的顶表面。
在一些实施例中，在形成所述第二初始导电层之后，所述半导体器件的形成方法还可以包括：
步骤S1024、对所述第二初始导电层进行化学机械抛光处理或者回刻处理。
本申请实施例中，对第二初始导电层进行化学机械抛光(Chemical Mechanical Polishing，CMP)或者回刻处理的目的是使得第二初始导电层具有平整的表面，便于后续在第二初始导电层上生长其他结构或膜层。
如图2e所示，对第二初始导电层204进行CMP或者回刻处理之后，第二初始导电层204的顶表面204-1仍然超出于位线掩膜层2013的顶表面，且第二初始导电层204的顶表面204-1与位线掩膜层2013的顶表面之间具有预设高度差。在一些实施例中，所述预设高度差可以是10～80纳米。
接下来，可以参考图3a～3k、图4a～4g，执行步骤S103、刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层。
在一些实施例中，步骤S103可以包括以下步骤：
步骤S1031、沿第三方向，对所述第一初始导电层和所述第二初始导电层依次进行第一刻蚀处理，形成沿第二方向相互独立的第一刻蚀导电层和沿所述第二方向相互独立的第二刻蚀导电层。
步骤S1032、沿所述第三方向，对所述第二刻蚀导电层进行第二刻蚀处理，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层；其中，所述第二方向垂直于所述第一方向，所述第二方向与所述第一方向构成的平面平行于所述半导体衬底所在的平面，所述第三方向垂直于所述半导体衬底所在的平面。
在一些实施例中，所述第一刻蚀处理过程可以包括以下步骤：
步骤S20、在所述第二初始导电层的表面形成具有第一掩膜图案的第一掩膜层。
这里，所述第一掩膜层包括依次堆叠的第一硬掩膜层、第一抗反射层和第一光刻胶层。步骤S20通过以下步骤形成：
步骤S201、在所述第二初始导电层的表面形成第一硬掩膜层、第一抗反射层和第 一光刻胶层；其中，所述第一光刻胶层具有第一初始掩膜图案。
这里，所述的第一硬掩模层可以是旋涂碳层，所述第一抗反射层可以是氮氧化硅层。本申请实施例中，第一硬掩膜层、第一抗反射层和第一光刻胶层可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、原子层沉积(Atomic Layer Deposition，ALD)。
如图3a和3b所示，在第二初始导电层204的表面依次形成了第一硬掩模层205、第一抗反射层206和第一光刻胶层207，构成了第一掩膜层。其中，第一光刻胶层207具有第一初始掩膜图案，所述第一初始掩膜图案由多个沿X轴方向平行排列的条状图案2071。
步骤S202、在具有所述第一初始掩膜图案的所述第一光刻胶层的表面形成隔离层。
如图3c所示，在具有第一初始掩膜图案的第一光刻胶层207的表面形成了隔离层208。这里，所述隔离层材料可以是氧化硅。
步骤S203、对所述隔离层和所述第一初始掩膜图案依次进行刻蚀，保留位于所述第一初始掩膜图案侧壁的隔离层，形成隔离侧墙图案。
如图3d所示，采用干法刻蚀工艺对隔离层208和第一初始掩膜图案依次进行刻蚀，保留位于第一初始掩膜图案中每一条状图案2071侧壁的隔离层208，从而形成了隔离侧墙图案2081。
步骤S204、通过所述隔离侧墙图案，刻蚀所述第一抗反射层和所述第一硬掩膜层，以形成具有所述第一掩膜图案的所述第一掩膜层。
本申请实施例中，所述隔离侧墙图案即为所述第一掩膜图案，形成了隔离侧墙图案之后，即形成了具有所述第一掩膜图案的所述第一掩膜层，通过隔离侧墙图案可以进行后续的第一刻蚀处理过程。
步骤S21、通过所述第一掩膜层，依次刻蚀所述第二初始导电层和所述第一初始导电层，以实现将所述第一掩膜图案转移至所述第二初始导电层和所述第一初始导电层中，形成沿所述第二方向相互独立的所述第一刻蚀导电层和沿所述第二方向相互独立的所述第二刻蚀导电层。
图3e为本申请实施例提供的形成第一刻蚀导电层和第二刻蚀导电层的三维结构示意图，图3f为图3e中沿A-A'的剖面结构示意图，图3g为形成第一刻蚀导电层和第二刻蚀导电层的俯视图，结合图3e～3g所示，通过第一掩膜层刻蚀所述第二初始导电层204和第一初始导电层203之后，形成了沿Y轴方向相互独立的第一刻蚀导电层203'和沿Y轴方向相互独立的第二刻蚀导电层204'。
在一些实施例中，在形成沿Y轴方向相互独立的第一刻蚀导电层和沿Y轴方向相互独立的第二刻蚀导电层之后，在任意相邻的两个第一刻蚀导电层之间形成了第一刻蚀沟槽，并且在任意相邻的两个第二刻蚀导电层之间形成了第二刻蚀沟槽。例如，请继续参见图3f，在任意相邻的两个第一刻蚀导电层203'之间形成了第一刻蚀沟槽T1，并且在任意相邻的两个第二刻蚀导电层204'之间形成了第二刻蚀沟槽T2。
在一些实施例中，在形成所述第二方向相互独立的所述第一刻蚀导电层和沿所述第二方向相互独立的所述第二刻蚀导电层之后，且在所述第二刻蚀处理之前，所述半导体器件的形成方法还可以包括：
步骤S30、在任意相邻的两个第一刻蚀导电层之间的第一刻蚀沟槽和任意相邻的两个第二刻蚀导电层之间的第二刻蚀沟槽中填充存储接触隔离材料，形成存储接触隔离层。
如图3h和3i所示，在任意相邻的两个第一刻蚀导电层203'之间的第一刻蚀沟槽 T1和任意相邻的两个第二刻蚀导电层204'之间的第二刻蚀沟槽T2中填充存储接触隔离材料，形成了存储接触隔离层209，所述存储接触隔离层209的顶表面209-1超出于所述第二刻蚀导电层的顶表面204'-1。
这里，所述存储接触隔离材料可以是氮化硅。
本申请实施例中，由于第一刻蚀沟槽T1和第二刻蚀沟槽T2具有较大的深宽比(深宽比大于10:1)，因此，存储接触隔离材料的填充过程中会产生缝隙，产生的缝隙可以作为相邻第一导电层之间的空气隙，如此，能够缩小第一刻蚀沟槽的关键尺寸(Critical Dimension，CD)，相应地，第一导电层的尺寸会增大，进而第一导电层的电阻越小，电阻-电容延迟(Rc)也会减小。例如，请继续参见图3h和3i，在形成存储接触隔离层209时，形成了位于所述存储接触隔离层中的空气隙2091。
步骤S31、对所述存储接触隔离层进行刻蚀处理，去除位于所述第二刻蚀导电层顶表面的所述存储接触隔离层。
如图3j和3k所示，采用干法刻蚀工艺，沿Z轴方向对存储接触隔离层209进行刻蚀处理，直至暴露出所述第二刻蚀导电层的顶表面204'-1为止。
在一些实施例中，所述沿所述第三方向，对所述第二刻蚀导电层进行第二刻蚀处理，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层，包括：沿所述第三方向，对所述位线掩膜层之上的所述第二刻蚀导电层进行部分刻蚀处理，暴露出部分所述位线掩膜层，形成沿所述第一方向相互独立的所述第一导电层和位于每一所述第一导电层之上的所述第二导电层。
在一些实施例中，所述第二刻蚀处理过程可以包括以下步骤：
步骤S22、在所述第二刻蚀导电层的表面和所述存储接触隔离层的表面形成具有第二掩膜图案的第二掩膜层。
这里，所述第二掩膜层包括依次堆叠的第二硬掩膜层、第二抗反射层和第二光刻胶层。步骤S22可以通过以下步骤形成：
步骤S221、在所述第二刻蚀导电层和所述存储接触隔离层的表面，依次沉积形成第二硬掩膜层、第二抗反射层和第二光刻胶层。
这里，所述第二硬掩模层与所述第一硬掩模层相同，所述第二抗反射层与所述第一抗反射层相同，所述第二光刻胶层与所述第一光刻胶层相同。
如图4a～4c所示，在第二刻蚀导电层204'的表面和所述存储接触隔离层209的表面依次沉积形成第二硬掩膜层210、第二抗反射层211和第二光刻胶层212。其中，所述第二光刻胶层212具有第二掩膜图案；所述第二掩膜图案包括多个沿X轴方向平行排列的子图案2121；每一所述子图案2121在与所述半导体衬底平行的平面内的延伸方向，与所述第一方向具有一夹角B，所述夹角B不等于90度，例如，所述夹角B可以为60度或120度。
本申请实施例中，每一所述子图案与所述第二刻蚀导电层存在一夹断的菱形区域，所述菱形区域用于形成后续的第二导电层。例如，图4d中每一所述子图案2121与所述第二刻蚀导电层204'存在一夹断的菱形区域C。
步骤S222、通过每一所述子图案，依次刻蚀所述第二抗反射层和所述第二硬掩膜层，以形成具有所述第二掩膜图案的所述第二掩膜层。
本申请实施例中，通过第二掩膜图案用于进行后续的第二刻蚀处理过程。
步骤S23、通过所述第二掩膜图案，刻蚀去除部分位于所述位线掩膜层之上的所述第二刻蚀导电层，保留的所述第二刻蚀导电层形成所述第二导电层。
如图4e～4g所示，通过第二掩膜图案刻蚀所述第二刻蚀导电层204形成位于每一第一导电层203”之上的第二导电层204”。
在一些实施例中，所述半导体器件的形成方法还可以包括：在形成所述第二导电层之后，在所述第二导电层的表面形成电容器。
在一些实施例中，所述在所述第二导电层的表面形成电容器可以包括以下步骤：
步骤S40、在任意相邻的两个第二导电层之间填充绝缘材料，形成绝缘层。
步骤S41、在所述第二导电层的表面和所述绝缘层的表面依次沉积第一电极层、介电层和第二电极层，以形成所述电容器。
这里，所述第一电极层和所述第二电极层的材料可以包括以下任意一种：金属、掺杂半导体、导电金属氧化物和导电金属氮化物。
在一些实施例中，所述半导体器件的形成方法还可以包括：在形成所述位线结构之前，形成位于所述有源区内部的字线结构。
本申请实施例提供的半导体器件的有源区中形成有一晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
本申请实施例提供了一种新的半导体器件的形成工艺，通过直接刻蚀导电层，形成多个相互独立的第一导电层和位于每一第一导电层之上的第二导电层，进而形成半导体器件，方法简单巧妙，极大的简化工艺流程及生产成本。另外，本申请实施例提供的半导体器件的形成方法不需要高级的曝光技术，工艺简便，易于大规模生产。
除此之外，本申请实施例还提供一种半导体器件，所述半导体器件通过上述实施例提供的半导体器件的形成方法形成。图5a和5b为本申请实施例提供的半导体器件的一种可选的结构示意图，如图5a和5b所示，所述半导体器件30包括：半导体衬底300、位线结构301、第一导电层303、第二导电层304和电容器。
半导体衬底300，所述半导体衬底上形成有多个间隔排布的有源区(图中未示出)。
位线结构301，所述位线结构301包括位线接触层3011、位线金属层3012和位线掩膜层3013；所述位线金属层3012通过所述位线接触层3011与所述有源区相交；所述位线结构301沿第一方向间隔排布。
这里，所述第一方向可以为X轴方向，所述位线结构301沿X轴方向间隔排布。
在一些实施例中，所述半导体器件30还可以包括位于所述位线结构301表面的介质层302，所述介质层302用于保护所述位线结构301。
第一导电层303和第二导电层304，所述第一导电层303通过所述第二导电层304连接至电容器。
在一些实施例中，所述第一导电层可以是存储节点接触，所述第二导电层可以是着陆焊盘。
请继续参见图5a，所述第二导电层304包括位于部分第一导电层303之上的、具有第一预设高度h1的第一结构和位于部分所述位线结构之上的、具有第二预设高度h2的第二结构；所述第一预设高度h1大于所述第二预设高度h2。
请继续参见图5b，在一些实施例中，所述半导体器件30还包括：存储接触隔离层309；所述存储接触隔离层309位于任意相邻两个第一导电层303之间，且位于任意相邻两个第二导电层304之间。
在一些实施例中，请继续参见图5b，所述半导体器件30还包括：空气隙3091；所述空气隙3091位于沿第二方向依次排列的所述存储接触隔离层中；其中，所述第二方向垂直于所述第一方向，所述第二方向与所述第一方向构成的平面平行于所述半导体衬底300所在的平面。这里，所述第二方向为Y轴方向。
在一些实施例中，请继续参见图5b，所述空气隙3091由第一部分和第二部分组 成；所述空气隙3091的第一部分位于相邻两个第一导电层303之间的存储接触隔离层中，所述空气隙的第二部分位于与所述相邻两个第一导电层对应的相邻两个第二导电层304之间的存储接触隔离层中。
本申请实施例中，所述第一部分和所述第二部分的大小相等。在其它实施例中，所述第一部分和所述第二部分的大小也可以不相等。
本申请实施例中，所述空气隙的第一部分和第二部分的交叠处与所述位线结构中的金属钨层之间的高度差小于一预设高度值，如此，可以减少相邻第一导电层之间的连接和减少相邻第二导电层之间的连接。
在一些实施例中，请继续参见图5b，所述空气隙3091沿第三方向的具有第三预设高度h3；所述存储接触隔离层沿所述第三方向具有第四预设高度h4；所述第四预设高度大于所述第三预设高度，且所述第四预设高度h4与所述第三预设高度h3之间的差值小于预设差值；其中，所述第三方向垂直于所述半导体衬底所在的平面。本申请实施例中，对预设差值的大小不进行具体限定。
这里，所述第三方向与所述第一方向和所述第二方向两两相互垂直，所述第三方向为Z轴方向。
在一些实施例中，请继续参见图5a和5b，所述半导体器件30还包括位于相邻两个第二导电层304之间绝缘层305，所述绝缘层用于使得第二导电层具有平整的表面，便于后续在第二导电层之上形成电容器。所述绝缘层305的材料可以是二氧化硅。
本申请实施例中，请继续参见图5a和5b，所述电容器包括：第一电极层306、介电层307和第二电极层308。这里，所述第一电极层306和所述第二电极层308的材料包括以下任意一种：金属、掺杂半导体、导电金属氧化物和导电金属氮化物；所述介电层307的材料包括以下任意一种：氧化哈、氧化锆、三氧化二铝、三氧化二镧、三氧化二钽、二氧化钛和钙钛矿结构的材料。
本申请实施例提供的半导体器件与上述实施例提供的半导体器件的形成方法类似，对于本申请实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
本申请实施例提供一种半导体器件，由于所述半导体器件具有位于相邻第一导电层之间的存储接触隔离层中、且位于相邻第二导电层之间的存储接触隔离层中的空气隙，如此，能够缩小相邻第一导电层之间存储接触隔离层的关键尺寸，使得第一导电层的尺寸增大，进而使得第一导电层的电阻降低，电阻-电容延迟减小，使得所制备的半导体器件具有优异的电性能。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的一些实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种半导体器件的形成方法，包括：
    提供半导体衬底，所述半导体衬底包括多个沿第一方向间隔排布的位线结构；
    在所述位线结构的表面填充导电材料，形成覆盖于所述位线结构表面的导电层，所述导电层的顶表面超出于所述位线结构的顶表面；
    刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层。
  2. 根据权利要求1所述的方法，其中，所述导电材料包括第一导电材料和第二导电材料；所述导电层包括第一初始导电层和第二初始导电层；
    所述在所述位线结构的表面填充导电材料，形成覆盖于所述位线结构表面的导电层，包括：
    在所述位线结构的表面填充第一导电材料，形成覆盖于所述位线结构表面的所述第一初始导电层；
    对所述第一初始导电层进行回刻，以暴露出所述位线结构的部分位线掩膜层；
    在回刻后的所述第一初始导电层的表面填充第二导电材料，形成覆盖于所述部分位线掩膜层表面的所述第二初始导电层，所述第二初始导电层的顶表面超出于所述位线掩膜层的顶表面。
  3. 根据权利要求2所述的方法，其中，所述刻蚀所述导电层，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层，包括：
    沿第三方向，对所述第一初始导电层和所述第二初始导电层依次进行第一刻蚀处理，形成沿第二方向相互独立的第一刻蚀导电层和沿所述第二方向相互独立的第二刻蚀导电层；
    沿所述第三方向，对所述第二刻蚀导电层进行第二刻蚀处理，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层；
    其中，所述第二方向垂直于所述第一方向，所述第二方向与所述第一方向构成的平面平行于所述半导体衬底所在的平面，所述第三方向垂直于所述半导体衬底所在的平面。
  4. 根据权利要求3所述的方法，其中，所述沿所述第三方向，对所述第二刻蚀导电层进行第二刻蚀处理，形成多个相互独立的第一导电层和位于每一所述第一导电层之上的第二导电层，包括：
    沿所述第三方向，对所述位线掩膜层之上的所述第二刻蚀导电层进行部分刻蚀处理，暴露出部分所述位线掩膜层，形成沿所述第一方向相互独立的所述第一导电层和位于每一所述第一导电层之上的所述第二导电层。
  5. 根据权利要求3所述的方法，其中，所述第一刻蚀处理包括：
    在所述第二初始导电层的表面形成具有第一掩膜图案的第一掩膜层；
    通过所述第一掩膜层，依次刻蚀所述第二初始导电层和所述第一初始导电层，以实现将所述第一掩膜图案转移至所述第二初始导电层和所述第一初始导电层中，形成沿所述第二方向相互独立的所述第一刻蚀导电层和沿所述第二方向相互独立的所述第二刻蚀导电层。
  6. 根据权利要求5所述的方法，其中，所述第一掩膜层包括依次堆叠的第一硬掩膜层、第一抗反射层和第一光刻胶层；
    所述在所述第二初始导电层的表面形成具有第一掩膜图案的第一掩膜层，包括：
    在所述第二初始导电层的表面形成第一硬掩膜层、第一抗反射层和第一光刻胶层； 其中，所述第一光刻胶层具有第一初始掩膜图案；
    在具有所述第一初始掩膜图案的所述第一光刻胶层的表面形成隔离层；
    对所述隔离层和所述第一初始掩膜图案依次进行刻蚀，保留位于所述第一初始掩膜图案侧壁的隔离层，形成隔离侧墙图案；
    通过所述隔离侧墙图案，刻蚀所述第一抗反射层和所述第一硬掩膜层，以形成具有所述第一掩膜图案的所述第一掩膜层。
  7. 根据权利要求6所述的方法，其中，所述方法还包括：
    在形成沿所述第二方向相互独立的所述第一刻蚀导电层和沿所述第二方向相互独立的所述第二刻蚀导电层之后，且在所述第二刻蚀处理之前，在任意相邻的两个第一刻蚀导电层之间的第一刻蚀沟槽和任意相邻的两个第二刻蚀导电层之间的第二刻蚀沟槽中填充存储接触隔离材料，形成存储接触隔离层；
    对所述存储接触隔离层进行刻蚀处理，去除位于所述第二刻蚀导电层顶表面的所述存储接触隔离层。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    在所述第一刻蚀沟槽和所述第二刻蚀沟槽中填充所述存储接触隔离材料时，形成位于所述存储接触隔离层中心的空气隙。
  9. 根据权利要求7所述的方法，其中，所述存储接触隔离材料包括氮化硅。
  10. 根据权利要求7所述的方法，其中，所述第二刻蚀处理包括：
    在所述第二刻蚀导电层的表面和所述存储接触隔离层的表面形成具有第二掩膜图案的第二掩膜层；
    通过所述第二掩膜图案，刻蚀去除部分位于所述位线掩膜层之上的所述第二刻蚀导电层，保留的所述第二刻蚀导电层形成所述第二导电层。
  11. 根据权利要求10所述的方法，其中，所述第二掩膜层包括依次堆叠的第二硬掩膜层、第二抗反射层和第二光刻胶层；
    所述在所述第二刻蚀导电层的表面和所述存储接触隔离层的表面形成具有第二掩膜图案的第二掩膜层，包括：
    在所述第二刻蚀导电层和所述存储接触隔离层的表面，依次沉积形成第二硬掩膜层、第二抗反射层和第二光刻胶层；其中，所述第二光刻胶层具有第二掩膜图案；所述第二掩膜图案包括多个沿所述第一方向平行排列的子图案；每一所述子图案在与所述半导体衬底平行的平面内的延伸方向，与所述第一方向具有一夹角，所述夹角不等于90度；
    通过每一所述子图案，依次刻蚀所述第二抗反射层和所述第二硬掩膜层，以形成具有所述第二掩膜图案的所述第二掩膜层。
  12. 一种半导体器件，所述半导体器件通过上述权利要求1至11任一项提供的半导体器件的形成方法形成，包括：
    半导体衬底，所述半导体衬底上形成有多个间隔排布的有源区；
    位线结构，所述位线结构包括位线接触层、位线金属层和位线掩膜层；所述位线金属层通过所述位线接触层与所述有源区相交；所述位线结构沿第一方向间隔排布；
    第一导电层和第二导电层，所述第一导电层通过所述第二导电层连接至电容器；
    其中，所述第二导电层包括位于部分第一导电层之上的、具有第一预设高度的第一结构和位于部分所述位线结构之上的、具有第二预设高度的第二结构；所述第一预设高度大于所述第二预设高度。
  13. 根据权利要求12所述的半导体器件，还包括：存储接触隔离层；
    所述存储接触隔离层位于任意相邻两个第一导电层之间，且位于任意相邻两个第 二导电层之间。
  14. 根据权利要求13所述的半导体器件，还包括：空气隙；
    所述空气隙位于沿第二方向依次排列的所述存储接触隔离层中；
    其中，所述第二方向垂直于所述第一方向，所述第二方向与所述第一方向构成的平面平行于所述半导体衬底所在的平面。
  15. 根据权利要求14所述的半导体器件，其中，所述空气隙由第一部分和第二部分组成；
    所述空气隙的第一部分位于相邻两个第一导电层之间的存储接触隔离层中，所述空气隙的第二部分位于与所述相邻两个第一导电层对应的相邻两个第二导电层之间的存储接触隔离层中。
  16. 根据权利要求14所述的半导体器件，其中，所述空气隙沿第三方向的具有第三预设高度；所述存储接触隔离层沿所述第三方向具有第四预设高度；
    所述第四预设高度大于所述第三预设高度，且所述第四预设高度与所述第三预设高度之间的差值小于预设差值；
    其中，所述第三方向垂直于所述半导体衬底所在的平面。
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