WO2022233240A1 - 功率半导体器件的封装结构与功率模块 - Google Patents

功率半导体器件的封装结构与功率模块 Download PDF

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Publication number
WO2022233240A1
WO2022233240A1 PCT/CN2022/088349 CN2022088349W WO2022233240A1 WO 2022233240 A1 WO2022233240 A1 WO 2022233240A1 CN 2022088349 W CN2022088349 W CN 2022088349W WO 2022233240 A1 WO2022233240 A1 WO 2022233240A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
welding
pin
package structure
base island
Prior art date
Application number
PCT/CN2022/088349
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English (en)
French (fr)
Inventor
李高显
党晓波
王锁海
Original Assignee
苏州汇川技术有限公司
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Publication date
Application filed by 苏州汇川技术有限公司 filed Critical 苏州汇川技术有限公司
Publication of WO2022233240A1 publication Critical patent/WO2022233240A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Definitions

  • the present application relates to the technical field of packaging structures, and in particular, to a packaging structure of a power semiconductor device and a power module.
  • the collector of the IGBT is soldered on the base island of the lead frame through soft solder, the gate is connected to the first pin of the lead frame through an aluminum wire, and the emitter is connected through the aluminum wire and the lead frame.
  • the third pins of the lead frame are connected, and then the lead frame is mounted on the substrate to form a corresponding power module.
  • the commonly used substrate is FR-4 plate, which is designed with via holes, and the heat is dissipated to the radiator through the thermally conductive insulating material, but the thermal resistance of this heat dissipation path is high, so the power module has the problem of poor heat dissipation.
  • the main purpose of the present application is to provide a packaging structure of a power semiconductor device and a power module, which aims to solve the technical problem of poor heat dissipation capability of the power module in the prior art.
  • a packaging structure of a power semiconductor device proposed in the present application includes:
  • the lead frame includes a base island area, the base island area supports a plastic package, and at least a part of one end face of the base island region is bent along the direction toward the plastic package to form at least one soldering pin.
  • one end of the welding leg away from the base island region is bent to form a welding portion.
  • one end of the welding leg away from the base island region is bent in a direction away from the plastic package to form the welding portion.
  • the molding body has a first side surface facing the welding leg
  • One end of the welding leg away from the base island area is bent along the length direction of the first side surface to form a welding portion.
  • the plurality of welding legs are arranged symmetrically with each other.
  • both ends of the first side surface are respectively connected with a second side surface and a third side surface;
  • the welding leg includes a first welding leg and a second welding leg, the first welding leg is disposed close to the second side surface, and the second welding leg is disposed close to the third side surface;
  • One end of the welding portion of the first welding leg away from the second welding leg protrudes from the second side surface, and one end of the welding portion of the second welding leg away from the first welding leg protrudes from the third side surface.
  • the plurality of welding legs are arranged in parallel and spaced apart from each other.
  • the package structure further includes:
  • pins there are at least two pins, one end of the pins is arranged in the plastic package, and the other end extends away from the soldering pins.
  • the present application also provides a power module, including:
  • the above-mentioned package structure of a power semiconductor device wherein the solder pins of the package structure are fixedly connected to the substrate, and the plastic body of the package structure is attached to the substrate, so that the lead frame of the package structure is disposed on the side of the plastic package away from the substrate.
  • the technical solution of the present application is to form at least one soldering pin by bending at least part of one end face of the base island region of the lead frame in the direction toward the plastic package, so that when the package structure is mounted on the substrate through the soldering pin, the package
  • the plastic packaging body of the structure is attached to the substrate, and the lead frame with higher thermal conductivity is disposed on the side of the plastic packaging body away from the substrate, thereby improving the heat dissipation capability of the power module.
  • FIG. 1 is a front view of an embodiment of a packaging structure of a power semiconductor device of the present application, wherein a perspective treatment is performed on a plastic packaging body in the figure;
  • FIG. 2 is a side view of an embodiment of the packaging structure of the power semiconductor device of the present application.
  • FIG. 3 is a schematic structural diagram of an embodiment of a packaging structure of a power semiconductor device of the present application
  • FIG. 4 is a schematic structural diagram of another embodiment of the packaging structure of the power semiconductor device of the present application.
  • FIG. 5 is a schematic structural diagram of another embodiment of the packaging structure of the power semiconductor device of the present application.
  • FIG. 6 is a schematic structural diagram of still another embodiment of the packaging structure of the power semiconductor device of the present application.
  • the terms “connected”, “fixed” and the like should be understood in a broad sense, for example, “fixed” may be a fixed connection, a detachable connection, or an integrated; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be an internal communication between two elements or an interaction relationship between the two elements, unless otherwise explicitly defined.
  • “fixed” may be a fixed connection, a detachable connection, or an integrated; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be an internal communication between two elements or an interaction relationship between the two elements, unless otherwise explicitly defined.
  • an embodiment of the present application provides a packaging structure for a power semiconductor device.
  • the packaging structure is integrally fixed to a substrate by means of welding feet formed by bending on a lead frame, and a plastic sealing body of the packaging structure is attached to the substrate.
  • the lead frame with higher thermal conductivity is disposed on the side of the plastic package away from the substrate, which reduces the thermal resistance of the heat dissipation path, thereby improving the heat dissipation capability of the power module.
  • the packaging structure of the power semiconductor device of the present application may be a TO-263 packaging structure or other packaging structures such as TO-252.
  • the packaging structure of the semiconductor device is a TO-263 packaging structure.
  • the following also takes the packaging structure of the semiconductor device as an example for description. According to the content disclosed in this embodiment, those of ordinary skill in the art can easily think of the specific structure when the packaging structure of the power semiconductor device is TO-252 or other packaging structures.
  • the package structure of the power semiconductor device may include a plastic package and a lead frame.
  • the lead frame 10 includes a base island region 12 , the base island region 12 supports a plastic package 20 , and at least a portion of one end surface of the base island region 12 is bent in a direction toward the plastic package 20 to form at least one solder pin 14 .
  • the package structure may include a lead frame 10 , a plastic package 20 , a first semiconductor chip 41 , a second semiconductor chip 42 , a first lead 31 and a second lead 32 .
  • the lead frame 10 is configured in a flat plate shape, and a base island region 12 is formed on one surface of the lead frame 10 . In the length direction of the lead frame 10 , the two ends of the base island region 12 are the pin end 13 and the welding end 11 respectively.
  • the first semiconductor chip 41 is a three-terminal active device, the front side of the first semiconductor chip 41 has an output terminal and a control terminal, the back side of the first semiconductor chip 41 has an input terminal, and the input terminal is welded to the base island region 12 of the lead frame 10 , The output terminal is electrically connected to the first pin 31 through a bonding wire, and the control terminal is electrically connected to the second pin 32 through a bonding wire.
  • the second semiconductor chip 42 is a two-terminal active device, the front side of the second semiconductor chip 42 has an output terminal, the back side of the second semiconductor chip 42 has an input terminal, the input terminal is welded to the base island region 12 , and the output terminal is electrically connected to the second pin 32 .
  • the first semiconductor chip 41 , the second semiconductor chip 42 , the bonding wires, the part of the first lead 31 and the part of the second lead 32 are packaged on the lead frame 10 by the plastic package 20 . Both the first lead 31 and the second lead 32 extend from the side of the lead end 13 to the outside of the plastic package 20 along the length of the lead frame 10 .
  • the lead frame 10 is generally made of metal material, such as copper alloy material.
  • the molding body 20 is generally made of epoxy molding material.
  • At least a part of the surface of the welding end 11 is bent along the direction toward the plastic package 20 to form at least one welding leg 14 .
  • all or part of the surface of the welding end 11 may be bent in the direction toward the plastic package 20 to form a welding leg 14 , or a plurality of parts of the surface may be bent to form a plurality of welding legs 14 . It can be determined according to the actual situation, which is not limited in the embodiments of this specification.
  • a plastic package space is defined between the soldering pins 14 and the base island region 12 , and the plastic package 20 is located in the plastic package space. Therefore, when the package structure is mounted on the substrate, the package structure can be soldered on the substrate through at least one soldering pin 14.
  • the plastic package 20 is located between the lead frame 10 and the substrate, so that the metal lead frame 10 is far away from the substrate. And contact with the outside world, can better dissipate heat to the air, so as to improve the overall heat dissipation capacity of the power module.
  • the solder pins 14 may extend to protrude from a surface of the plastic package 20 away from the base island region 12 , so as to facilitate the soldering of the solder pins 14 and the substrate.
  • the package structure of this embodiment further includes a third lead 33 , and the third lead 33 is located between the first lead 31 and the second lead 32 .
  • one end of the welding leg 14 away from the base island region 12 is bent to form the welding portion 141 .
  • soldering portion 141 one end of the soldering pin 14 away from the base island region 12 is bent to form a soldering portion 141 , and the soldering portion 141 has a larger soldering area to facilitate adjustment of the position of the package structure and the substrate to accurately solder the package structure.
  • the larger welding area also makes the welding between the welding pins 14 and the substrate more stable.
  • one end of the welding leg 14 away from the base island region 12 is bent in a direction away from the plastic package 20 to form the welding portion 141 .
  • the lead frame 10 is integrally formed with a zigzag-like structure, and the welding portion 141 extends in a direction away from the pin end 13 .
  • the welding area formed when the welding portion 141 is welded to the substrate is far away from the plastic package 20 , so that the shape and internal structure of the plastic package 20 can be prevented from being affected by the soldering.
  • the plurality of soldering legs 14 are arranged in parallel with each other and at intervals.
  • the number of welding pins 14 can be set to two. It is easy to understand that more welding pins 14 may be provided, which is not limited in this embodiment.
  • the plastic package 20 has a first side surface 21 facing the welding leg 14 .
  • One end of the welding leg 14 away from the base island region 12 is bent along the length direction of the first side surface 21 to form a welding portion 141 .
  • the direction from the pin end 13 to the solder end 11 is the length direction of the lead frame 10 , and the direction perpendicular to it is the width direction of the lead frame 10 .
  • the first side surface 21 extends along the width direction of the lead frame 10 .
  • the welding portion 141 formed by the welding leg 14 extends along the length direction of the first side surface 21 , that is, the width direction of the lead frame 10 .
  • the bonding area formed when the solder pins 14 and the substrate are soldered extends along the width direction of the lead frame 10 , so that the solder pins 14 and the substrate can be more firmly attached, and the lead frame 10 can be prevented from shaking and loosening in the width direction.
  • the bonding area formed when the soldering pins 14 and the substrate are welded extends along the width direction of the lead frame 10 , so that the soldering pins 14 are closely attached to the plastic package 20 and the space occupied by the package structure on the substrate is reduced.
  • the plurality of welding legs 14 are arranged symmetrically with each other.
  • the number of soldering pins 14 may be two, and the two soldering pins 14 are arranged symmetrically along the width direction of the lead frame 10 .
  • two ends of the first side surface 21 are respectively connected with a second side surface 22 and a third side surface 23 .
  • the welding leg 14 includes a first welding leg 14 a and a second welding leg 14 b , the first welding leg 14 a is disposed close to the second side surface 22 , and the second welding leg 14 b is disposed close to the third side surface 23 .
  • the second side surface 22 and the third side surface 23 are disposed opposite to each other.
  • One end of the welding portion 141 of the first welding leg 14a away from the second welding leg 14b protrudes from the second side surface 22, and one end of the welding portion 141 of the second welding leg 14b away from the first welding leg 14a protrudes from the third side surface . Both of them protrude from the corresponding side surfaces of the plastic package 20 to facilitate the operation and positioning during welding.
  • the plastic package 20 is disposed toward the substrate.
  • the solder pins 14 There is a gap with the plastic body 20 .
  • the aforementioned bending to form the welding leg 14 and one end of the welding leg 14 to bend to form the welding portion 141 may be bent to form a right angle, or may be bent to form an acute angle. This is not limited.
  • the present application also provides a power module, including: a substrate; and the above-mentioned packaging structure of a power semiconductor device.
  • solder pins 14 of the package structure are fixedly connected to the substrate, and the plastic package 20 of the package structure is attached to the substrate, so that the lead frame 10 of the package structure is disposed on the side of the plastic package 20 away from the substrate.
  • the specific structure of the package structure refers to the above-mentioned embodiments. Since the power module adopts all the technical solutions of the above-mentioned embodiments, it has at least all the functions brought by the technical solutions of the above-mentioned embodiments, and will not be repeated here.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请公开一种功率半导体器件的封装结构与功率模块，属于封装结构技术领域。功率半导体器件的封装结构包括：塑封体20；以及引线框架10，引线框架10包括基岛区12，基岛区12承载塑封体20，基岛区12的一端端面的至少部分沿朝向塑封体20的方向弯折形成至少一个焊接脚14。本申请提供的功率半导体器件的封装结构提高了功率模块的散热能力。

Description

功率半导体器件的封装结构与功率模块
本申请要求于2021年5月7号申请的、申请号为202120964363.2的中国专利申请的优先权，其全部内容通过引用结合于此。
技术领域
本申请涉及封装结构技术领域，具体涉及一种功率半导体器件的封装结构与功率模块。
 背景技术
对于IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）器件，IGBT的集电极通过软焊料焊接在引线框架的基岛上，栅极通过铝线和引线框架的第一管脚相连，发射极通过铝线和引线框架的第三管脚相连接，然后通过将引线框架贴装于基板上，组成相应的功率模块。目前常用的基板为FR-4板材，板材上设计有过孔，通过导热绝缘材料散热至散热器，但这种散热路径热阻较高，因此功率模块存在散热能力不好的问题。
 技术问题
本申请的主要目的是提供一种功率半导体器件的封装结构与功率模块，旨在解决现有技术中功率模块存在散热能力不好的技术问题。
 技术解决方案
为实现上述目的，本申请提出的一种功率半导体器件的封装结构，包括：
塑封体；以及
引线框架，引线框架包括基岛区，基岛区承载塑封体，基岛区的一端端面的至少部分沿朝向塑封体的方向弯折形成至少一个焊接脚。
在一实施方式中，焊接脚远离基岛区的一端弯折形成焊接部。
在一实施方式中，焊接脚远离基岛区的一端沿远离塑封体的方向弯折形成焊接部。
在一实施方式中，塑封体具有朝向焊接脚的第一侧面；
焊接脚远离基岛区的一端沿第一侧面的长度方向弯折形成焊接部。
在一实施方式中，多个焊接脚彼此对称设置。
在一实施方式中，第一侧面的两端分别连接有第二侧面和第三侧面；
焊接脚包括第一焊接脚与第二焊接脚，第一焊接脚靠近第二侧面设置，第二焊接脚靠近第三侧面设置；
其中，第一焊接脚的焊接部远离第二焊接脚的一端凸出于第二侧面，第二焊接脚的焊接部远离第一焊接脚的一端凸出于第三侧面。
在一实施方式中，多个焊接脚彼此平行且间隔设置。
在一实施方式中，焊接脚与塑封体之间存在间隙。
在一实施方式中，封装结构还包括：
至少2个引脚，引脚的一端设置于塑封体内，另一端沿远离焊接脚的方向延伸。
第二方面，本申请还提供了一种功率模块，包括：
基板；以及
上述的功率半导体器件的封装结构；其中，封装结构的焊接脚固定连接于基板，且封装结构的塑封体与基板贴合，以使封装结构的引线框架设置于塑封体背离基板的一侧。
 有益效果
本申请技术方案通过采用在引脚框架的基岛区的一端端面的至少部分沿朝向所述塑封体的方向弯折形成至少一个焊接脚，从而在封装结构通过焊接脚安装至基板上时，封装结构的塑封体与所述基板贴合，而导热能力更高的引线框架设置于所述塑封体背离基板的一侧，从而提高了功率模块的散热能力。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请功率半导体器件的封装结构一实施例的主视图，其中，图中对塑封体做了透视处理；
图2为本申请功率半导体器件的封装结构一实施例的侧视图；
图3为本申请功率半导体器件的封装结构一实施例的结构示意图；
图4为本申请功率半导体器件的封装结构另一实施例的结构示意图；
图5为本申请功率半导体器件的封装结构又一实施例的结构示意图；
图6为本申请功率半导体器件的封装结构再一实施例的结构示意图。
附图标号说明：
标号 名称 标号 名称
10 引线框架 11 焊接端
12 基岛区 13 引脚端
14 焊接脚 141 焊接部
20 塑封体 21 第一侧面
22 第二侧面 31 第一引脚
32 第二引脚 33 第三引脚
41 第一半导体芯片 42 第二半导体芯片
14a 第一焊接脚 14b 第二焊接脚
23 第三侧面    
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
在本申请中，除非另有明确的规定和限定，术语“连接”、“固定”等应做广义理解，例如，“固定”可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义，包括三个并列的方案，以“A和/或B”为例，包括A方案、或B方案、或A和B同时满足的方案。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
相关技术中，对于IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）器件，塑封体贴装于引线框架基岛区上，然后引线框架贴装于基板上，组成相应的功率模块，但是正如前所述散热路径热阻较高，限制了功率模块的散热能力，和系统过载能力。为此，本申请实施例提供了一种功率半导体器件的封装结构，通过引线框架上弯折形成的焊接脚将封装结构整体固定至基板上，且封装结构的塑封体与所述基板贴合，而导热能力更高的引线框架设置于所述塑封体背离基板的一侧，降低了散热路径热阻，从而提高了功率模块的散热能力。
下面结合一些具体实施例进一步阐述本申请的发明构思。
需要说明的是，本申请功率半导体器件的封装结构可以为TO-263封装结构或者TO-252等其他封装结构。本实施例中，半导体器件的封装结构为TO-263封装结构。下文也以半导体器件的封装结构为例进行说明，根据本实施例公开的内容，本领域普通技术人员易于想到当该功率半导体器件的封装结构为TO-252或者其他封装结构时的具体结构。
本实施例中，功率半导体器件的封装结构可以包括塑封体以及引线框架。
引线框架10包括基岛区12，基岛区12承载塑封体20，基岛区12的一端端面的至少部分沿朝向塑封体20的方向弯折形成至少一个焊接脚14。
在一个实施例中，参阅图1，封装结构可以包括引线框架10、塑封体20、第一半导体芯片41、第二半导体芯片42、第一引脚31和第二引脚32。引线框架10构造为平板状，其一侧表面形成有基岛区12。在引线框架10长度方向上，基岛区12的两端分别为引脚端13和焊接端11。第一半导体芯片41为三端有源器件，第一半导体芯片41的正面具有输出端和控制端，第一半导体芯片41的背面具有输入端，输入端与引线框架10的基岛区12焊接，输出端通过键合线电性连接至第一引脚31，控制端通过键合线电性连接至第二引脚32。第二半导体芯片42为二端有源器件，第二半导体芯片42的正面具有输出端，第二半导体芯片42的背面具有输入端，输入端与基岛区12焊接，输出端通过键合线电性连接至第二引脚32。第一半导体芯片41、第二半导体芯片42、键合线、第一引脚31的部分和第二引脚32的部分通过塑封体20封装于引线框架10。第一引脚31和第二引脚32均从引脚端13侧沿引线框架10长度方延伸至塑封体20外。引线框架10一般采用金属材料制成，如由铜合金材质制成。塑封体20一般采用环氧塑封材料制成。
而焊接端11的至少部分表面沿朝向塑封体20的方向弯折形成至少一个焊接脚14。在一些实施例中，可以是焊接端11的全部或者部分表面沿朝向塑封体20的方向弯折形成一个焊接脚14，还可以是多个部分的表面弯折形成多个焊接脚14，具体的可以根据实际情况确定，本说明书实施例对此不作限定。焊接脚14和基岛区12之间限定出塑封体空间，塑封体20位于该塑封体空间内。从而在将该封装结构安装于基板上时，封装结构可通过至少一个焊接脚14焊接在基板上，此时，塑封体20位于引线框架10和基板之间，从而金属材质的引线框架10远离基板并与外界接触，可更好地将热量散发至空气中，以提高功率模块整体的散热能力。
值得一提的是，参阅图2，焊接脚14可延伸至凸出于塑封体20远离基岛区12的一侧表面，以利于焊接脚14与基板的焊接。
此外，参阅图5和图6，在一些其他的实施例中，本实施例的封装结构还包括第三引脚33，第三引脚33位于第一引脚31和第二引脚32之间。
在一实施例中，焊接脚14远离基岛区12的一端弯折形成焊接部141。
参阅图2至图6，焊接脚14远离基岛区12的一端弯折形成焊接部141，焊接部141的焊接面积更大，以方便调整封装结构和基板的位置，以将封装结构准确焊接。同时，焊接面积更大还使得焊接脚14与基板的焊接更加稳定。
作为本实施例的一种选择，焊接脚14远离基岛区12的一端沿远离塑封体20的方向弯折形成焊接部141。
参阅图2和图5，引线框架10整体形成一类似于Z字结构，焊接部141沿远离引脚端13的方向延伸。此时，封装结构焊接至基板上时，焊接部141与基板焊接时形成的焊接区远离塑封体20，从而可避免焊接影响塑封体20的外形和内部结构。
此时，多个焊接脚14彼此平行且间隔设置。参阅图2和图5，如焊接脚14可设置为2个。容易理解的，焊接脚14还可设置为更多个，本实施例对此并不限定。
作为本实施例的另一种选择，塑封体20具有朝向焊接脚14的第一侧面21。焊接脚14远离基岛区12的一端沿第一侧面21的长度方向弯折形成焊接部141。
参阅图4和图6，引脚端13至焊接端11的方向为引线框架10的长度方向，与其垂直的方向即为引线框架10的宽度方向。第一侧面21即沿引线框架10的宽度方向延伸。此时，焊接脚14形成的焊接部141沿第一侧面21的长度方向，也即是引线框架10的宽度方向延伸。
本实施例中，焊接脚14与基板焊接时形成的焊接区沿引线框架10的宽度方向延伸，从而可使得焊接脚14与基板更加牢固，避免引线框架10在其宽度方向上可摇晃松动。且焊接脚14与基板焊接时形成的焊接区沿引线框架10的宽度方向延伸，可使得焊接脚14紧贴塑封体20，减少封装结构在基板上所占的空间。
此时，多个焊接脚14彼此对称设置。参阅图4和图6，焊接脚14可设置为2个，2个焊接脚14沿引线框架10的宽度方向左右对称设置。
在一实施例中，第一侧面21的两端分别连接有第二侧面22和第三侧面23。
焊接脚14包括第一焊接脚14a与第二焊接脚14b，第一焊接脚14a靠近第二侧面22设置，第二焊接脚14b靠近第三侧面23设置。
参阅图4和图6，在引线框架10的宽度方向上，第二侧面22和第三侧面23相对设置。其中，第一焊接脚14a的焊接部141远离第二焊接脚14b的一端凸出于第二侧面22，第二焊接脚14b的焊接部141远离第一焊接脚14a的一端凸出于第三侧面。两者均凸出塑封体20上的相应侧面，以便于焊接时的操作与定位。
在一实施例中，焊接脚14与塑封体20之间存在间隙。
参阅图1和图2，本实施例中，焊接脚14焊接至基板时，塑封体20朝向基板设置，为了避免焊接脚14的焊接过程中影响塑封体20的外表面以及内部结构，焊接脚14与塑封体20之间存在间隙。
值得一提的是，前述的弯折形成焊接脚14，以及焊接脚14的一端弯折形成焊接部141可以是弯折后形成一直角，还可以是弯折后形成一锐角，本实施例对此并不限定。
第二方面，本申请还体提供了一种功率模块，包括：基板；以及上述的功率半导体器件的封装结构。
其中，封装结构的焊接脚14固定连接于基板，且封装结构的塑封体20与基板贴合，以使封装结构的引线框架10设置于塑封体20背离基板的一侧。
该封装结构的具体结构参照上述实施例，由于本功率模块采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有功能，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (10)

  1. 一种功率半导体器件的封装结构，包括：塑封体、引线框架、第一半导体芯片、第二半导体芯片和第一引脚、第二引脚；
    所述引线框架包括基岛区，所述基岛区承载所述塑封体，所述基岛区的一端端面的至少部分沿朝向所述塑封体的方向弯折形成至少一个焊接脚，所述焊接脚远离所述基岛区的一端弯折形成焊接部；
    所述第一半导体芯片、所述第二半导体芯片的输入端与所述基岛区焊接，所述第一半导体芯片的输出端通过键合线电性连接至所述第一引脚、所述第二半导体芯片的输出端通过键合线电性连接至所述第二引脚；
    所述第一引脚和第二引脚的一端均设置于所述塑封体内，所述第一引脚和第二引脚的另一端均沿远离所述焊接脚的方向弯折延伸。
  2. 根据权利要求1所述的封装结构，其中，在所述引线框架的长度方向上，所述基岛区的两端分别为所述焊接脚、所述第一引脚和所述第二引脚；
    所述第一半导体芯片为三端有源器件，所述第一半导体芯片的正面具有输出端和控制端，所述第一半导体芯片的背面具有输入端，所述第一半导体芯片的输出端通过键合线电性连接至第一引脚，所述第一半导体芯片的控制端通过键合线电性连接至第二引脚；
    所述第二半导体芯片为二端有源器件，所述第二半导体芯片的正面具有输出端，背面具有输入端，所述第二半导体芯片的输出端通过键合线电性连接至第二引脚。
  3. 根据权利要求2所述的封装结构，其中，所述封装结构还包括：
    第三引脚，所述第三引脚位于所述第一引脚和所述第二引脚之间。
  4. 根据权利要求1所述的封装结构，其中，所述焊接脚远离所述基岛区的一端沿远离所述塑封体的方向弯折形成所述焊接部。
  5. 根据权利要求1所述的封装结构，其中，所述塑封体具有朝向所述焊接脚的第一侧面；
    所述焊接脚远离所述基岛区的一端沿所述第一侧面的长度方向弯折形成所述焊接部。
  6. 根据权利要求5所述的封装结构，其中，当所述焊接脚为多个时，多个所述焊接脚彼此对称设置。
  7. 根据权利要求6所述的封装结构，其中，所述第一侧面的两端分别连接有第二侧面和第三侧面；
    所述焊接脚包括第一焊接脚与第二焊接脚，所述第一焊接脚靠近所述第二侧面设置，所述第二焊接脚靠近所述第三侧面设置；
    其中，所述第一焊接脚的焊接部远离所述第二焊接脚的一端凸出于所述第二侧面，所述第二焊接脚的焊接部远离所述第一焊接脚的一端凸出于所述第三侧面。
  8. 根据权利要求1至5任一项所述的封装结构，其中，当所述焊接脚为多个时，多个所述焊接脚彼此平行且间隔设置。
  9. 根据权利要求1所述的封装结构，其中，所述焊接脚与所述塑封体之间存在间隙。
  10. 一种功率模块，包括：
    基板；以及
    功率半导体器件的封装结构；其中，所述封装结构的焊接脚固定连接于所述基板，且所述封装结构的塑封体与所述基板贴合，以使所述封装结构的引线框架设置于所述塑封体背离基板的一侧。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842556A (zh) * 2011-06-21 2012-12-26 万国半导体(开曼)股份有限公司 双面外露的半导体器件及其制作方法
CN206806330U (zh) * 2017-05-10 2017-12-26 深圳市三联盛科技股份有限公司 一种应用于sot23半导体封装的集成电路
CN107785345A (zh) * 2017-11-17 2018-03-09 上海晶丰明源半导体股份有限公司 引线框架、引线框架阵列及封装体
CN214505484U (zh) * 2021-05-07 2021-10-26 苏州汇川技术有限公司 功率半导体器件的封装结构与功率模块

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102842556A (zh) * 2011-06-21 2012-12-26 万国半导体(开曼)股份有限公司 双面外露的半导体器件及其制作方法
CN206806330U (zh) * 2017-05-10 2017-12-26 深圳市三联盛科技股份有限公司 一种应用于sot23半导体封装的集成电路
CN107785345A (zh) * 2017-11-17 2018-03-09 上海晶丰明源半导体股份有限公司 引线框架、引线框架阵列及封装体
CN214505484U (zh) * 2021-05-07 2021-10-26 苏州汇川技术有限公司 功率半导体器件的封装结构与功率模块

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