CN206806330U - 一种应用于sot23半导体封装的集成电路 - Google Patents

一种应用于sot23半导体封装的集成电路 Download PDF

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CN206806330U
CN206806330U CN201720513635.0U CN201720513635U CN206806330U CN 206806330 U CN206806330 U CN 206806330U CN 201720513635 U CN201720513635 U CN 201720513635U CN 206806330 U CN206806330 U CN 206806330U
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integrated circuit
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lead frame
sot23
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陈林
郑天凤
朱仕镇
韩壮勇
朱文锋
吴富友
刘志华
刘群英
朱海涛
张团结
王鹏飞
曹丙平
周贝贝
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Shenzhen Sanlian Polytron Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型涉及半导体封装技术领域，尤其涉及一种应用于SOT23半导体封装的集成电路，包括引线框架、倒装芯片和塑封体，所述倒装芯片上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，所述倒装芯片的连接凸点与引线框架上的焊盘电连接，并倒装在引线框架上。直接焊接可以明显降低电阻、电感和寄生电容值，并减少芯片内部的阻性损耗和开关损耗，更好地降低发热量，所有的引脚都可以当做散热片来提高散热效率，不易形成芯片中间热点现象。采用倒装封装的集成电路体积小，负载能力高，成本低廉，非常适用于机顶盒、计算机接口设备、LCD显示器和电视等电子产品。

Description

一种应用于SOT23半导体封装的集成电路
技术领域
本实用新型涉及半导体封装技术领域，尤其涉及一种应用于SOT23半导体封装的集成电路。
背景技术
在电信通信及电脑等消费性电子产品的蓬勃发展下，广泛应用于其上的电源供应器及电源转换器重要性也随之增加，不仅在体积重量上要轻薄短小，在效能及使用寿命上也要更好更长。目前的电源转换器，大多设计将所有的元件平面铺设在同一单芯片上或使用多个芯片组合,但最后皆封装于同一个封装引线框架上。如图1所示，传统的SOT-23封装是以打线的方式将芯片和引线框架连接起来的，所用的连线一般是25-38um的金线或铜线，受到线径的限制，此种封装不能通过太大的电流，也不能很好地实现热传导的效果，应用范围受到限制。
实用新型内容
本实用新型的目的在于提供一种有效降低封装的热阻和电阻，具有更好的电性表现和优化的散热能力的应用于SOT23半导体封装的集成电路。
本实用新型是这样实现的：一种应用于SOT23半导体封装的集成电路，包括引线框架、倒装芯片和塑封体，所述倒装芯片上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，所述倒装芯片的连接凸点与引线框架上的焊盘电连接，并倒装在引线框架上。
其中，所述倒装芯片上的连接凸点为铜柱，所述引线框架表面覆盖有绝缘层，所述绝缘层上设有多个开口，以使引线框架相应的引脚部分暴露出来，所述开口与铜柱位置相对应。
其中，所述铜柱直径为50-100μm。
其中，所述绝缘层厚度为10μm。
本实用新型的有益效果为：所述应用于SOT23半导体封装的集成电路，包括引线框架、倒装芯片和塑封体，所述倒装芯片上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，形成电源降压器，所述倒装芯片的连接凸点与引线框架上的焊盘电连接，并倒装在引线框架上，直接焊接可以明显降低电阻、电感和寄生电容值，并减少芯片内部的阻性损耗和开关损耗，更好地降低发热量，所有的引脚都可以当做散热片来提高散热效率，不易形成芯片中间热点现象。采用倒装封装的集成电路体积小，负载能力高，成本低廉，非常适用于机顶盒、计算机接口设备、LCD显示器和电视等电子产品。
附图说明
图1是现有技术中SOT23封装的电源降压器集成电路的结构示意图；
图2是本实用新型所述应用于SOT23半导体封装的集成电路实施例的结构示意图；
图3是本实用新型所述应用于SOT23半导体封装的集成电路实施例的剖面示意图。
其中，1、引线框架；11、绝缘层；12、开口；13、焊盘；2、金线；3、芯片；4、塑封体；5、倒装芯片；51、连接凸点。
具体实施方式
为了使本实用新型的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本实用新型，并不用于限定本实用新型。
作为本实用新型所述应用于SOT23半导体封装的集成电路实施例，如图2和图3所示，包括引线框架1、倒装芯片5和塑封体4，所述倒装芯片5上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，所述倒装芯片5的连接凸点51与引线框架1上的焊盘13电连接，并倒装在引线框架1上。
所述应用于SOT23半导体封装的集成电路，包括引线框架1、倒装芯片5和塑封体4，所述倒装芯片5上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，形成电源降压器，所述倒装芯片5的连接凸点51与引线框架1上的焊盘13电连接，并倒装在引线框架1上，直接焊接可以明显降低电阻、电感和寄生电容值，并减少倒装芯片5内部的阻性损耗和开关损耗，更好地降低发热量，所有的引脚都可以当做散热片来提高散热效率，不易形成芯片中间热点现象。采用倒装封装的集成电路体积小，负载能力高，可以达到3.5A的输出，成本低廉，非常适用于机顶盒、计算机接口设备、LCD显示器和电视等电子产品。
在本实施例中，所述倒装芯片5上的连接凸点51为铜柱，所述引线框架1表面覆盖有绝缘层11，所述绝缘层11上设有多个开口12，以使引线框架1相应的引脚部分暴露出来，所述开口12与铜柱位置相对应。开口12处暴露出来的引脚部分与铜柱焊接，绝缘层11可以阻止焊料从焊接位置流走，避免因熔融的焊料从焊接位置流失而引起铜柱与引脚部分的不良接触，可以增加焊料的量，以增加铜柱和引线框架之间焊接强度。
在本实施例中，所述铜柱直径优选值为50-100μm；所述绝缘层厚度优选值为10μm。
以上所述仅为本实用新型的较佳实施例而已，并不用以限制本实用新型，凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本实用新型的保护范围之内。

Claims (4)

1.一种应用于SOT23半导体封装的集成电路，其特征在于，包括引线框架、倒装芯片和塑封体，所述倒装芯片上具有集成电路，至少包含两个串联的功率场效应晶体管和一个控制回路芯片，所述倒装芯片的连接凸点与引线框架上的焊盘电连接，并倒装在引线框架上。
2.根据权利要求1所述应用于SOT23半导体封装的集成电路，其特征在于，所述倒装芯片上的连接凸点为铜柱，所述引线框架表面覆盖有绝缘层，所述绝缘层上设有多个开口，以使引线框架相应的引脚部分暴露出来，所述开口与铜柱位置相对应。
3.根据权利要求2所述应用于SOT23半导体封装的集成电路，其特征在于，所述铜柱直径为50-100μm。
4.根据权利要求2所述应用于SOT23半导体封装的集成电路，其特征在于，所述绝缘层厚度为10μm。
CN201720513635.0U 2017-05-10 2017-05-10 一种应用于sot23半导体封装的集成电路 Active CN206806330U (zh)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2022233240A1 (zh) * 2021-05-07 2022-11-10 苏州汇川技术有限公司 功率半导体器件的封装结构与功率模块

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022233240A1 (zh) * 2021-05-07 2022-11-10 苏州汇川技术有限公司 功率半导体器件的封装结构与功率模块

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