WO2022228948A1 - Galliumnitrid auf silizium halbleiterbauelement mit rückseiten- und vereinzelungs-graben im siliziumsubstrat, sowie verfahren zum herstellen desselben - Google Patents
Galliumnitrid auf silizium halbleiterbauelement mit rückseiten- und vereinzelungs-graben im siliziumsubstrat, sowie verfahren zum herstellen desselben Download PDFInfo
- Publication number
- WO2022228948A1 WO2022228948A1 PCT/EP2022/060320 EP2022060320W WO2022228948A1 WO 2022228948 A1 WO2022228948 A1 WO 2022228948A1 EP 2022060320 W EP2022060320 W EP 2022060320W WO 2022228948 A1 WO2022228948 A1 WO 2022228948A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- membrane
- semiconductor component
- cavern
- substrate
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title description 18
- 229910002601 GaN Inorganic materials 0.000 title description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 14
- 229910052710 silicon Inorganic materials 0.000 title description 14
- 239000010703 silicon Substances 0.000 title description 14
- 239000012528 membrane Substances 0.000 claims abstract description 110
- 238000000926 separation method Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000003631 wet chemical etching Methods 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 21
- 238000000708 deep reactive-ion etching Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000003550 marker Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Definitions
- Transistors based on gallium nitride offer the possibility of realizing components with lower on-resistances and at the same time higher breakdown voltages than comparable components based on silicon or silicon carbide.
- GaN transistors are primarily known for what are known as high-electron mobility transistors (HEMTs), in which the current flow takes place laterally on the top side of the substrate through a two-dimensional electron gas that forms the transistor channel.
- HEMTs high-electron mobility transistors
- Such lateral components can be produced by heteroepitaxy of the functional GaN layers on silicon wafers.
- vertical devices in which the current flows from the front of the substrate to the back of the substrate, are more advantageous in terms of both the size and the electric field distribution inside the device.
- Such a component cannot be produced directly using heteroepitaxial GaN layers on silicon (Si), since insulating intermediate layers (a so-called buffer) are required to adapt the lattice mismatch between GaN and Si and to reduce the substrate curvature.
- the buffer itself is mechanically strained in such a way that it just compensates for the strain of the GaN layers at room temperature. Because the buffer one is an insulator, the current flow from the front of the substrate to the back of the substrate is prevented by the buffer.
- Native GaN substrates are also known on which the required additional epitaxial GaN layers of the device can be grown without the need for an insulating buffer.
- GaN substrates are small (typically 50 mm in diameter) and expensive.
- the following III-V nitride semiconductor layers are grown epitaxially on the silicon substrate 61 or generally the carrier substrate: the insulating buffer 13, a highly doped contact semiconductor layer with n conductivity 14, the lightly doped n conductive drift layer 15, a p-conductive body layer 16 and a highly doped n-conductive source contact layer 17.
- Source contact layer 17 and body layer 16 are penetrated by a trench (trench), the side walls and bottom of which are separated from gate electrode 21 by a gate dielectric 22 .
- Source contact layer 17 and body layer 16 are contacted by a source electrode 41 which is separated from gate electrode 21 by an insulating layer 31 .
- the silicon substrate 61 and the buffer 13 are removed by a rear-side trench 51, which ends in the highly doped contact semiconductor layer with n-type conductivity 14. This is through a rear drain electrode 52 is contacted.
- a conductive channel is formed in the body layer 16 by applying a gate voltage to the gate electrode 21, through which a current flow from the source electrode 41 to the drain electrode 52 is permitted.
- the drain electrode 52 can consist of several metallic layers.
- FIG. 2A and FIG. 2B show, in schematic cross-sectional views, a method customary in the related art for dicing a wafer with a multiplicity of transistor chips into individual chips.
- FIG.2A illustrates the transistor chip before dicing
- FIG.2B illustrates the transistor chip after dicing.
- the transistor chips can be picked off a carrier 71 in order to be further processed using standard methods of assembly and connection technology.
- markings so-called saw ditches 72, are applied on the front side in an area outside the active transistor area (for example the area which includes the source electrode 41 and/or the rear side trench 51).
- markings so-called saw ditches 72
- FIG. 2A may be an etch in which portions of the insulating layer 31 have been removed.
- additional layers are provided as a marking, for example in the form of a metallization that is not electrically connected to the source electrode 41 .
- the marking of the sawing ditch 72 serves as a marker for the subsequent sawing or separating process.
- the wafer 61 is applied to a so-called sawing film 71 (dice tape or bluetape), which is clamped in a frame.
- the wafer 61 is then singulated along the sawing grooves 72 using a diamond-coated saw blade, so that a wider sawing street is created and isolated chips then remain on the sawing foil 71 , which are then picked off by the sawing foil 71 be able.
- the same sawing line can also be sawed several times to different depths, or different saw blades can also be used for different depths.
- the chips are separated conventionally by a laser, or by a so-called stealth-dice process, in which a kind of predetermined breaking point is created by the laser, at which the sawing film is subsequently expanded laterally 71 break the chips in two.
- the membrane semiconductor component according to the invention with the features according to claim 1 has the advantage of reducing costs when dicing the membrane semiconductor components.
- the thickness to be sawn for separating the membrane semiconductor component is clearly reduced by the second rear side cavern in the outside area.
- laterally narrower sawing streets can be realized, which means that less wafer area is lost for sawing and costs can be saved.
- the membrane semiconductor component can enable saw-free singulation processes.
- the dicing of membrane semiconductor devices can be carried out in a safe, reliable and faster manner.
- Saw-free processes can be based, for example, on breaking through lateral expansion or pressurization of a predetermined separation point.
- backside chipping can be reduced or avoided by means of the membrane semiconductor component.
- Backside chipping is a breaking out of the sawing groove on the back of the wafer, which occurs in a classic sawing process.
- FIG. 1 is a schematic representation of a related art membrane transistor
- FIGS. 2A and 2B are schematic representations of a related art vertical field effect transistor
- FIG. 3A to FIG. 8 are schematic representations of a membrane semiconductor component according to various aspects.
- any vertical power semiconductor components can be produced using this technology, such as Schottky diodes, pn -Diodes, Vertical- Diffusion MOSFETS (VDMOS), Current- Aperture Vertical Electron Transistors (CAVETs), vGroove Vertical High Electron Mobility Transistors (vHEMTs) or Fin Field Effect Transistors (FinFETs).
- VDMOS Vertical- Diffusion MOSFETS
- CAVETs Current- Aperture Vertical Electron Transistors
- vHEMTs vGroove Vertical High Electron Mobility Transistors
- Fin Field Effect Transistors Fin Field Effect Transistors
- FIG. 3A shows a schematic cross-sectional view of a membrane semiconductor device 100 according to various embodiments.
- FIG. 3B illustrates a schematic top view of the membrane semiconductor device 100 illustrated in FIG. 3A.
- the dashed line in FIG. 3A shown area.
- the membrane semiconductor component 100 has a (second) rear side cavern 81 .
- the second rear side cavern 81 is also referred to below as a saw cavern 81 .
- the (first) rear side cavern 51 is arranged for the drain contact 52 below or essentially below the active area of the membrane semiconductor component 100 . In other words: the first rear side cavern 51 is arranged in the area in which switchable transistor channels are formed.
- the saw cavern 81 is arranged outside the active area, for example in the outer area 92 outside the membrane area 91.
- the saw cavity 81 can be arranged circumferentially around the active area 91, as shown in FIG. 4A and FIG.4B.
- the sawing cavern 81 can be formed, for example, in the same process step as the rear side cavern 51.
- the sawing cavern 81 can be made, for example, by a dry chemical plasma etching process (referred to as deep reactive ion etching (DRIE) for example) without generating additional costs. With plasma etching, structures that can be etched in the same process step do not generate any additional costs.
- the second rear-side cavern 81 or the sawing cavern 81 can be formed by means of an etching process.
- the etching process can be a wet chemical etching process or a dry chemical etching process, for example DRIE.
- the second rear side cavern 81 can have the form of a trench or a blind hole with a side wall in the substrate 61, for example.
- the second rear side cavern 81 can be a blind hole, a plurality of blind holes spaced apart from one another, a trench or a combination thereof in the substrate 61 .
- the side wall of the blind hole or trench in the substrate 61 can be the boundary of the second rear side cavern 81 (optionally covered by the drain electrode 52).
- the side wall for example the substrate 61 and/or the drain electrode 52 on the surface of the side wall, can have a ripple structure, for example a periodic ripple pattern.
- the periodic ripple pattern can be produced, for example, by a dry chemical etching process, for example DRIE.
- the second rear cavern 81 can thus clearly be free of saw marks.
- the intended separation point 98 can be separated by means of an etching process.
- the etching process can be a wet chemical etching process or a dry chemical etching process, for example DRIE.
- DRIE dry chemical etching process
- the saw cavern 81 can have a width, for example a lateral dimension, which is in a range from approximately 20 ⁇ m to approximately 100 ⁇ m.
- the etch rate can decrease as the aspect ratio of the structure to be etched increases. With narrow saw caverns 81, therefore, a Forming the rear side cavern 51 may require an additional and/or prolonged etching process.
- the substrate 61 for example a wafer
- the substrate 61 can be stabilized on the front side during the singulation, for example by temporary bonding, on a temporary carrier, for example a carrier wafer. This may be necessary in the case when there is no continuous connection between the individual chips by means of the silicon substrate 61 due to the saw cavity 81 .
- a temporary carrier for example a carrier wafer.
- the membrane semiconductor component 100 has an outer area 92 and a membrane area 82 . At least part of a substrate 61 is arranged in the outer area 92 .
- the substrate 61 is structured in such a way that a first rear side cavern 51 is set up in the membrane area 82 .
- the first rear side cavern 51 is free of substrate 61.
- At least one active area is arranged in the membrane area 82.
- the active region can have, for example, at least one control electrode 21, one source electrode 41 and/or a pn junction.
- the membrane semiconductor component 100 also has a predetermined separation point 98 which has a second rear side cavern 81 in the outer area 82 .
- the second rear side cavern 81 is free of substrate 61.
- a filling material can be arranged in the first rear side cavern 51 .
- the backfill material can be electrically and thermally conductive.
- the second rear cavern 81 is free of backfill material.
- the drain electrode 52 can be arranged in the first rear side cavity 51 and in the second rear side cavity 81 .
- the drain electrode 52 can be arranged in the first rear side cavern 51 .
- the second rear side cavern 81 can be free of drain electrode 52.
- the intended separation point 98 can be set up free of metal.
- the intended separation point 98 can also have one or more layers 13 , 14 , 15 , 16 , 17 , 31 on or above the second rear side cavern 81 .
- the one layer 13, 14, 15, 16, 17, 31 or the plurality of layers 13, 14, 15, 16, 17, 31 can each comprise or be formed from a material which is optically transparent or translucent.
- a membrane semiconductor device structure may include a first membrane semiconductor device 100 and a second membrane semiconductor device 100 with a common substrate 61 .
- Each of the first and second membrane semiconductor devices 100 may have a membrane area 82 and have an outer area 92 between the first and second membrane semiconductor devices 100 .
- the substrate 61 can be structured in such a way that a first rear-side cavern 51 is set up in the membrane region 82 of the first and second membrane semiconductor component 100, with the first rear-side cavern 51 being free of substrate 61 and with at least one active region in the membrane region 82 of the first and second membrane semiconductor component 100 is arranged and the active region has at least one control electrode 21 .
- the membrane semiconductor component structure has a predetermined separation point 98, which has a second rear side cavern 81 in the outer region 82 between the first and second membrane semiconductor component 100, the second rear side cavern 81 being free of substrate 61.
- FIG. 4A and FIG. 4B illustrate schematic cross-sectional views of the membrane semiconductor component 100 before (FIG. 4A) and after (FIG. 4B) singulation in a sawing or chip singulation process according to various embodiments.
- the wafer 61 with the membrane semiconductor components 100 spaced apart by saw cavities 81 is clearly applied to a saw tape 71 .
- a non-illustrated, optionally front-applied, temporary support substrate may be removed.
- the saw caverns 81 can be optically recognizable from the front.
- gallium nitride layers 14, 15, 16, 17 and the insulation layer 31 can be or be designed to be essentially transparent in the visible spectral range.
- the saw caverns 81 can form an optical contrast to the substrate 61 .
- the saw cavern 81 can thus serve as a position marker.
- the layers 14, 15, 16, 17, 31 remaining above the saw cavity 81 which can have a thickness of a few micrometers, can be cut in the form of a flat cut (in FIG illustrated by the arrow) are severed.
- the cutting area can have the same lateral dimension as the saw cavity 81 or a different lateral dimension than the saw cavity 81 , for example it can be narrower or wider than the saw cavity 81 .
- the risk of so-called backside chipping when producing the diaphragm semiconductor component 100 is reduced.
- the low thickness of the layers 14, 15, 16, 17, 31 above the saw cavity 81 makes it possible for the multiple traversing of each saw path with different strokes or different saw blade diameters, which is usual to reduce backside chipping, to become optional.
- the membrane semiconductor device 100 can thus simplify the sawing process. As a result, the process time and the costs of sawing can be reduced.
- FIG. 5A-5B and FIG.6A-6B illustrate schematic cross-sectional views of the membrane semiconductor device 100 before (FIG.5A, FIG.6A) and after (FIG.5B, FIG.6B) singulation in a sawing or chip singulation process according to various embodiments .
- the membrane semiconductor component 100 can be formed in such a way that the region of the saw cavity 81 remains free of the drain electrode 52, as illustrated in FIG. 5A-FIG. 6B.
- Metals can be relatively soft materials compared to semiconductor materials. As a result, the saw blade of a wafer saw can be used when separating contaminated, e.g. smeared. In addition, when sawing through the drain electrode 52 with a small thickness of the semiconductor layers 14, 15, 16, 17 there is the risk of an electrical short circuit between the drain electrode 52 on the rear side and the source electrode 41 and/or the gate electrode 21 to generate on the front.
- the drain electrode 52 can be removed from the area of the saw cavity 81 or the drain electrode 52 can be structured in such a way that the area of the saw cavity 81 and/or the area laterally around the saw cavity 81 remains free of the metal of the rear-side contact , for example the drain electrode 52, and/or the front-side contact, for example the source electrode 41 and/or the gate electrode 21.
- the structured formation of the drain electrode 52 can take place, for example, by means of a shadow mask process in a sputtering process .
- the structured formation of, for example, the drain electrode 52 can take place by selective etching of the drain electrode 52 in the area of the saw cavities 81 . Since this means that there is no metal in the area of the saw cavities 81, there is no risk of a short circuit and wear on the saw blade is reduced.
- the membrane semiconductor component 100 can be formed in such a way that the first rear side cavern 51 is partially or completely filled with a filling material 53, as illustrated in FIG. 6A-FIG. 6B. This can enable low electrical and thermal drain resistance as well as high stability of the wafer and the final chips.
- the saw caverns 81 can remain free of backfill material 53.
- a selective filling of the rear side cavern 51 with filling material 53 can be done, for example, by filling with a metal paste, for example copper, a solder or a selective thickening by means of electroplating (by lithographic masking or selective application of the electrical seed layer (seed layer).
- a metal paste for example copper, a solder or a selective thickening by means of electroplating (by lithographic masking or selective application of the electrical seed layer (seed layer).
- FIG. 7A and FIG.7B illustrate schematic cross-sectional views of the membrane semiconductor device 100 in alternatives to the sawing process Chip singulation processes according to various embodiments.
- the membrane semiconductor components can be separated by breaking up the layers above the second rear side cavity 81 .
- the membrane semiconductor component 100 can be arranged on a laterally deformable carrier 71, for example a so-called sawing tape 71, which is laterally deformed for singulation, for example laterally expanded (illustrated in FIG. 7A by means of the arrows 99 pointing outward). Due to the deformation of the carrier 71, the layers 13, 14, 15, 16, 17, 31, which can have a thickness of a few micrometers, are broken up over the second cavity 81 on the rear side. The membrane semiconductor component 100 can then be removed from the carrier 71 in individual form.
- the first rear side cavern 51 can be filled with a backfill material (not shown, but see for example FIG.6A, FIG.6B) to mechanically seal the active area of the membrane semiconductor device (also referred to as the membrane area) during the lateral expansion of the carrier 71 to stabilize.
- the second rear-side cavern 81 can remain free of filling material 53, which simplifies the isolation.
- ) can correspond to overpressure (P1>P2) or underpressure (P1 ⁇ P2).
- the layers 13, 14, 15, 16, 17, 31 above the second rear side cavity 81 can be severed by means of the pressure difference, as a result of which the membrane semiconductor components 100 can be isolated.
- FIG. 8 illustrates a schematic cross-sectional view of the membrane semiconductor device 100 in an alternative die singulation process to the sawing process according to various embodiments.
- the membrane semiconductor component 100 while the membrane semiconductor component 100 is still bonded to the front side of the carrier wafer 62, be isolated.
- This can be carried out, for example, with a dedicated wafer saw in the saw cavity 81, or alternatively with a dry or wet chemical etching process in the second rear side cavity 81.
- This allows the remaining layers to be severed above the second rear side cavity 81 and a gap 82 is formed. This enables increased stability since the membrane semiconductor component 100 is connected to the carrier wafer 62 .
- the width of the breaking edges can be set, for example, by the aspect ratio of the dry or wet chemical etching for the silicon substrate 61 and the layers 14 , 15 , 16 , 17 containing gallium nitride and the insulating layer 31 .
- the membrane semiconductor component can cause the width of the break edges to be predetermined only by the aspect ratio of a dry chemical etch or a wet chemical etch of the etch for the silicon substrate 61 and the layers 14, 15, 16, 17 containing gallium nitride and the insulating layer 31.
- the width of the breaking edge can thus be independent of the width of an optionally usable saw blade.
- the second rear side cavern 81 can also be formed in parallel or simultaneously for the entire wafer. Depending on the process parameters, backside chipping can be reduced or avoided.
- the temporary connection of the membrane semiconductor component 100 to the carrier wafer 62 can be selectively removed from the carrier wafer 62 by means of a laser during the picking of the membrane semiconductor component 100 from the carrier wafer 62 or can be carried out over the entire surface using another conventional method.
- the rear side of the substrate 61 can be applied to a carrier 71 before the debonding from the carrier wafer 62 and the membrane semiconductor component 100 can then be detached from the carrier wafer 62 .
- the individual membrane semiconductor components 100 can then be removed from the carrier 71 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202280045715.1A CN117581379A (zh) | 2021-04-27 | 2022-04-20 | 在硅衬底中具有后侧沟道和分离沟道的硅基氮化镓半导体构件以及用于其制造的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102021204159.0 | 2021-04-27 | ||
DE102021204159.0A DE102021204159A1 (de) | 2021-04-27 | 2021-04-27 | Membran-halbleiterbauelement und verfahren zum herstellen desselben |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022228948A1 true WO2022228948A1 (de) | 2022-11-03 |
Family
ID=81654697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2022/060320 WO2022228948A1 (de) | 2021-04-27 | 2022-04-20 | Galliumnitrid auf silizium halbleiterbauelement mit rückseiten- und vereinzelungs-graben im siliziumsubstrat, sowie verfahren zum herstellen desselben |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN117581379A (de) |
DE (1) | DE102021204159A1 (de) |
WO (1) | WO2022228948A1 (de) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008128160A1 (en) * | 2007-04-12 | 2008-10-23 | Massachusetts Institute Of Technology | Hemts based on si/nitride structures |
US20130062996A1 (en) * | 2011-09-12 | 2013-03-14 | Texas Instruments Incorporated | Mems device fabricated with integrated circuit |
US20150060942A1 (en) * | 2013-09-03 | 2015-03-05 | Renesas Electronics Corporation | Semiconductor device |
US20150270356A1 (en) * | 2014-03-20 | 2015-09-24 | Massachusetts Institute Of Technology | Vertical nitride semiconductor device |
US20190027426A1 (en) * | 2017-07-20 | 2019-01-24 | Nuvoton Technology Corporation | Nitride semiconductor device |
US10797681B1 (en) * | 2019-07-25 | 2020-10-06 | Zhuhai Crystal Resonance Technologies Co., Ltd. | Method of fabricating novel packages for electronic components |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006022377B4 (de) | 2006-05-12 | 2016-03-03 | Robert Bosch Gmbh | Mikromechanische Vorrichtung und Verfahren zur Herstellung einer mikromechanischen Vorrichtung |
US8436371B2 (en) | 2007-05-24 | 2013-05-07 | Cree, Inc. | Microscale optoelectronic device packages |
DE102008002307A1 (de) | 2008-06-09 | 2009-12-10 | Robert Bosch Gmbh | Herstellungsverfahren für ein mikromechanisches Bauelement, entsprechender Bauelementverbund und entsprechendes mikromechanisches Bauelement |
US9402138B2 (en) | 2012-10-12 | 2016-07-26 | Infineon Technologies Ag | MEMS device and method of manufacturing a MEMS device |
-
2021
- 2021-04-27 DE DE102021204159.0A patent/DE102021204159A1/de active Pending
-
2022
- 2022-04-20 CN CN202280045715.1A patent/CN117581379A/zh active Pending
- 2022-04-20 WO PCT/EP2022/060320 patent/WO2022228948A1/de active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008128160A1 (en) * | 2007-04-12 | 2008-10-23 | Massachusetts Institute Of Technology | Hemts based on si/nitride structures |
US20130062996A1 (en) * | 2011-09-12 | 2013-03-14 | Texas Instruments Incorporated | Mems device fabricated with integrated circuit |
US20150060942A1 (en) * | 2013-09-03 | 2015-03-05 | Renesas Electronics Corporation | Semiconductor device |
US20150270356A1 (en) * | 2014-03-20 | 2015-09-24 | Massachusetts Institute Of Technology | Vertical nitride semiconductor device |
US20190027426A1 (en) * | 2017-07-20 | 2019-01-24 | Nuvoton Technology Corporation | Nitride semiconductor device |
US10797681B1 (en) * | 2019-07-25 | 2020-10-06 | Zhuhai Crystal Resonance Technologies Co., Ltd. | Method of fabricating novel packages for electronic components |
Also Published As
Publication number | Publication date |
---|---|
CN117581379A (zh) | 2024-02-20 |
DE102021204159A1 (de) | 2022-10-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102013107632B4 (de) | Verfahren zum Herstellen von Halbleitervorrichtungen mittels Ionenimplantation | |
DE102005041793B4 (de) | Top Drain MOSgated Einrichtung und Herstellungsprozess dafür | |
DE102009061851B3 (de) | Halbleiterbauelement mit Kanalstoppgraben | |
DE102012110133B4 (de) | Ein Halbleiterbauelement mit einem Durchkontakt und Herstellungsverfahren dafür | |
DE102012103369B4 (de) | Ein Verfahren zum Ausbilden eines Halbleiterbauelements und ein Halbleiterbauelement | |
DE102014106823B9 (de) | Verfahren zur Herstellung von Halbleiterbauelementen mit einem Glassubstrat und Halbleiterbauelemente mit Glassubstrat | |
DE112016002613T5 (de) | Leistungs-Halbleiterbauelement | |
DE112019000863T5 (de) | Halbleitervorrichtung | |
DE102014114235B3 (de) | Verfahren zum Bilden eines Transistors, Verfahren zum Strukturieren eines Substrates und Transistor | |
DE102014107295A1 (de) | Halbleitervorrichtung, verfahren zum herstellen einer halbleitervorrichtung und integrierte schaltung | |
DE102013105035A1 (de) | Verfahren zum Herstellen eines optoelektronischen Halbleiterchips | |
DE102013112646B4 (de) | Verfahren für die spannungsreduzierte Herstellung von Halbleiterbauelementen | |
DE112017000947T5 (de) | Verbindungshalbleitervorrichtung und herstellungsverfahren für dieverbindungshalbleitervorrichtung | |
DE102014101859A1 (de) | Superjunction-Halbleitervorrichtung mit Überkompensationszonen | |
DE102017119568B4 (de) | Siliziumkarbidbauelemente und Verfahren zum Herstellen von Siliziumkarbidbauelementen | |
DE102011004475B4 (de) | Herstellungsverfahren für eine Halbleitereinrichtung mit isoliertem Gate | |
DE102016104968B3 (de) | Verfahren zum herstellen von halbleitervorrichtungen mit transistorzellen, halbleitervorrichtung und mikroelektromechanische vorrichtung | |
DE102013107380B4 (de) | Ein Verfahren zum Ausbilden eines Halbleiterbauelements | |
DE102016104757B4 (de) | Halbleitertransistor und Verfahren zum Bilden des Halbleitertransistors | |
DE102011088732B4 (de) | Verfahren zum Herstellen eines Stöpsels in einem Halbleiterkörper | |
DE102011010248B3 (de) | Ein Verfahren zum Herstellen eines Halbleiterbausteins | |
DE102014116834B4 (de) | Halbleitereinzelchip aufweisend eine Maskierungsstruktur, die Teil von Chip-Vereinzelung-Schnittfugengebieten ist und diese definiert, Verfahren zum Ausbildung eines Halbleiterchips sowie zugehöriger Wafer | |
DE102017106202B4 (de) | Verfahren zum herstellen einer halbleitervorrichtung, umfassend eine ätzung eines halbleitermaterials | |
WO2022228948A1 (de) | Galliumnitrid auf silizium halbleiterbauelement mit rückseiten- und vereinzelungs-graben im siliziumsubstrat, sowie verfahren zum herstellen desselben | |
DE102014106747A1 (de) | Halbleitervorrichtung, integrierte schaltung und verfahren zum herstellen einer halbleitervorrichtung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22723613 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202280045715.1 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 18557201 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 22723613 Country of ref document: EP Kind code of ref document: A1 |