WO2022227565A1 - 中断控制器、中断控制方法、芯片、计算机设备以及介质 - Google Patents

中断控制器、中断控制方法、芯片、计算机设备以及介质 Download PDF

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Publication number
WO2022227565A1
WO2022227565A1 PCT/CN2021/134628 CN2021134628W WO2022227565A1 WO 2022227565 A1 WO2022227565 A1 WO 2022227565A1 CN 2021134628 W CN2021134628 W CN 2021134628W WO 2022227565 A1 WO2022227565 A1 WO 2022227565A1
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interrupt
target
signal
interrupt signal
sent
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PCT/CN2021/134628
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English (en)
French (fr)
Inventor
孙守乐
戴亮
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上海阵量智能科技有限公司
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Publication of WO2022227565A1 publication Critical patent/WO2022227565A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/36—Arbitration

Definitions

  • the present disclosure relates to the field of computer technology, and in particular, to an interrupt controller, an interrupt control method, a chip, a computer device, and a storage medium.
  • Embodiments of the present disclosure provide at least an interrupt controller, an interrupt control method, a chip, a computer device, and a storage medium.
  • an embodiment of the present disclosure provides an interrupt controller, including: an interrupt arbitration module connected to a plurality of interrupt connection devices, and a plurality of interrupt interface modules respectively connected to corresponding interrupt receiving devices;
  • the interrupt interface module is respectively connected with the interrupt arbitration module, and can use different communication protocols to perform data transmission with the corresponding interrupt receiving device; wherein, the interrupt arbitration module is used to interrupt the to-be-sent from the interrupt sending device.
  • the signal is arbitrated, the target interrupt signal is obtained, and the target interrupt signal is sent to the corresponding target interrupt interface module; a plurality of the interrupt interface modules are used as the target interrupt interface module, in response to receiving the interrupt arbitration.
  • the target interrupt signal sent by the module sends an interrupt instruction to the interrupt receiving device connected to the target interrupt interface module based on the target interrupt signal.
  • the interrupt sending device when the interrupt sending device needs to send an interrupt signal to the interrupt receiving device, it only needs to send the interrupt signal to the interrupt controller, and the interrupt sending device does not need to switch the interface, thereby reducing the complexity of the process of sending the interrupt signal by the interrupt sending device . At the same time, it can solve the problem of insufficient communication flexibility of a single interface module, making the application scenarios changeable.
  • the interrupt arbitration module is used to: use the currently received interrupt signal sent by the interrupt sending device as the to-be-sent interrupt signal, and/or, remove the historical target from the historical interrupt signal.
  • Other interrupt signals other than the interrupt signal are used as the interrupt signal to be sent; wherein, the historical interrupt signal is the interrupt signal sent by the interrupt sending device received by the interrupt arbitration module in the historical data processing cycle, and the historical interrupt signal is sent by the interrupt sending device.
  • the target interrupt signal is the target interrupt signal determined in the historical data processing cycle.
  • the interrupt arbitration module when the interrupt arbitration module performs arbitration on the interrupt signal to be sent, it is configured to, based on at least one of the following priorities, determine the target interrupt signal from the interrupt signal to be sent: the The first priority corresponding to the interrupt signal to be sent, the second priority corresponding to the plurality of interrupt interface modules respectively, and the third priority of the interrupt sending device corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module when determining the target interrupt signal from the to-be-sent interrupt signal based on the first priority corresponding to the to-be-sent interrupt signal, is used to: At least one to-be-sent interrupt signal with the highest first priority is determined from the to-be-sent interrupt signals as the target interrupt signal; or, based on the scheduling sequence of the plurality of interrupt interface modules, the In the interface module, one or more target interrupt interface modules are determined, and the target interrupt signal is determined according to the first priority from the interrupt signals to be sent corresponding to each of the target interrupt interface modules.
  • the interrupt signal with the highest priority among all the interrupt signals sent by the interrupt sending device is sent first, so that the interrupt receiving device can receive and process the more important interrupt signals first.
  • the security of task processing with sequential order can be improved.
  • the interrupt receiving devices corresponding to the multiple interrupt interface modules can all receive the target interrupt signal and perform data processing, thereby improving the utilization rate of computing power.
  • the interrupt arbitration module when determining the target interrupt signal from the to-be-sent interrupt signals based on the second priorities corresponding to the plurality of interrupt interface modules respectively, uses In: determining one or more of the target interrupt interface modules from the plurality of interrupt interface modules based on the respective second priorities of the plurality of interrupt interface modules; from the to-be-sent interrupt signals, determining A target interrupt signal corresponding to each of the target interrupt interface modules.
  • the interrupt arbitration module when determining a target interrupt signal corresponding to the target interrupt interface module from the to-be-sent interrupt signal, is used to: from the to-be-sent interrupt signal , determine the first candidate interrupt signal corresponding to the target interrupt interface module; based on the receiving order of the first candidate interrupt signal, or the first priority corresponding to the first candidate interrupt signal In the first candidate interrupt signal, the target interrupt signal is determined.
  • a corresponding target interrupt signal can be preferentially sent to a more important interrupt interface module among the plurality of interrupt interface modules, so that the more important interrupt interface module can preferentially process the corresponding target interrupt signal.
  • the interrupt arbitration module determines the target interrupt signal from the interrupt signal to be sent. , used to: determine one or more target interrupt sending devices from the interrupt sending devices corresponding to the interrupt signal to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent; In sending the interrupt signal, the target interrupt signal corresponding to each target interrupt sending device is determined.
  • the interrupt arbitration module when determining a target interrupt signal corresponding to the target interrupt sending device from the to-be-sent interrupt signal, is configured to: from the to-be-sent interrupt signal , determine a second candidate interrupt signal corresponding to the target interrupt sending device; based on at least one of the following, from the second candidate interrupt signal, determine the target interrupt signal: the second candidate The first priority corresponding to the interrupt signal, the second priority corresponding to the interrupt interface module respectively, and the receiving order of the second candidate interrupt signal.
  • the more important interrupt sending device among the multiple interrupt sending devices can preferentially send the corresponding target interrupt signal, so that the more important interrupt sending device can preferentially send the corresponding target interrupt signal.
  • the interrupt arbitration module when arbitrating the interrupt signal to be sent, is configured to: determine at least two target interrupts from a plurality of the interrupt interface modules based on the interrupt signal to be sent. An interface module; for each of the at least two target interrupt interface modules, determine a target interrupt signal corresponding to the interrupt interface module from the interrupt signals to be sent corresponding to the interrupt interface module.
  • the interrupt controller can also send corresponding target interrupt signals to multiple interrupt interface modules at the same time, so as to improve efficiency, improve the utilization rate of multiple interrupt interface modules, and improve the computing power of multiple interrupt receiving devices for processing interrupt signals utilization.
  • the interrupt controller further includes: a mask register; the mask register is used to receive an interrupt to be masked identifier issued by the interrupt receiving device; the interrupt arbitration module is used for The interrupt signal to be sent of the interrupt sending device is arbitrated, and when the target interrupt signal is obtained, it is used for: reading the mask interrupt identifier from the mask register, and based on the mask interrupt identifier, from the to-be-sent interrupt A masked interrupt signal corresponding to the masked interrupt identifier and a non-maskable interrupt signal other than the masked interrupt signal are determined in the signal; the non-maskable interrupt signal is arbitrated to obtain the target interrupt signal.
  • the interrupt controller further includes a suspending register; the interrupt arbitration module is further configured to, after determining the non-maskable interrupt signal from the interrupt signal to be sent, screen the interrupt signal to be masked. Stored in the hanging register; after receiving the unmasking interrupt identifier issued by the interrupt receiving device, based on the unmasking interrupt identifier, read the unmasking interrupt identifier corresponding to the unmasking interrupt identifier from the hanging register The interrupt signal is used as the to-be-sent interrupt signal.
  • the interrupt interface module includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module corresponding to PCIe includes: a data packet integration module, a message signal interrupt table register. , and interrupt mapping register file; Described interrupt mapping register file, for storing the mapping relation information between interrupt signal and data address to mark; Described message signal interrupt table register, for storing described data address to mark corresponding The data address pair; the data address pair includes: an instruction and a processing data register address indicated by the instruction; the data packet integration module sends an interrupt to the corresponding interrupt receiving device based on the target interrupt signal When the instruction is used, based on the received target interrupt signal, the target data address pair identifier corresponding to the target interrupt signal is determined from the interrupt mapping register file; using the target data address pair identifier, from the message In the signal interrupt table register, read the target data address pair; use PCIe to integrate the target data address pair, generate an interrupt data packet, and send the interrupt data packet to the interrupt receiving device corresponding to
  • an embodiment of the present disclosure further provides an interrupt controller, including: an interrupt arbitration module and an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module is connected to the interrupt arbitration module The interrupt arbitration module is used to arbitrate the interrupt signal to be sent, obtain the target interrupt signal, and send the target interrupt signal to the corresponding target interrupt interface module; the interrupt interface module is used to respond to receiving the interrupt arbitration The target interrupt signal sent by the module sends an interrupt instruction to the interrupt receiving device connected to the target interrupt interface module based on the target interrupt signal.
  • an interrupt controller including: an interrupt arbitration module and an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module is connected to the interrupt arbitration module The interrupt arbitration module is used to arbitrate the interrupt signal to be sent, obtain the target interrupt signal, and send the target interrupt signal to the corresponding target interrupt interface module; the interrupt interface module is used to respond to receiving the interrupt arbitration The target interrupt signal sent by the module sends an interrupt instruction to the interrupt receiving device connected to the target interrupt interface module based on
  • the interrupt controller includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe;
  • the interrupt interface module includes: a data packet integration module, a message signal interrupt table register, and an interrupt Mapping register file;
  • the interrupt mapping register file is used to store the mapping relationship information between the interrupt signal and the data address pair identifier;
  • the message signal interrupt table register is used to store the data address corresponding to the data address pair identifier Right;
  • the data address pair includes: an instruction and a processing data register address indicated by the instruction;
  • the data packet integration module is used to determine, based on the received target interrupt signal, from the interrupt mapping register file and The target data address pair identifier corresponding to the target interrupt signal; using the target data address pair identifier, read the target data address pair from the message signal interrupt table register; use PCIe to perform the target data address pair. integration, generate an interrupt data packet, and send the interrupt data packet to the interrupt receiving device corresponding to the target interrupt interface module.
  • an embodiment of the present disclosure further provides an interrupt control method, which is applied to an interrupt controller, where the interrupt controller includes: an interrupt arbitration module connected to a plurality of interrupt sending devices, and respectively connected to corresponding interrupt receiving devices a plurality of interrupt interface modules; a plurality of the interrupt interface modules are respectively connected with the interrupt arbitration module, and can use different communication protocols to perform data transmission with the corresponding interrupt receiving device; the interrupt control method includes: The interrupt arbitration module arbitrates the interrupt signal to be sent from the interrupt sending device, obtains the target interrupt signal, and sends the target interrupt signal to the corresponding target interrupt interface module; the interrupt interface module is used as the target interrupt interface. module, in response to receiving the target interrupt signal sent by the interrupt arbitration module, send an interrupt instruction to the corresponding interrupt receiving device based on the target interrupt signal.
  • the interrupt control method further includes: the interrupt arbitration module determines the currently received interrupt signal sent by the interrupt sending device as the to-be-sent interrupt signal, and/or, interrupts the history.
  • the other interrupt signals in the signal except the historical target interrupt signal are used as the interrupt signal to be sent; wherein, the historical interrupt signal is the interrupt signal sent by the interrupt sending device received by the interrupt arbitration module in the historical data processing cycle,
  • the historical target interrupt signal is a target interrupt signal determined in the historical data processing cycle.
  • the interrupt arbitration module performs arbitration on interrupt signals to be sent, including determining a target interrupt signal from the interrupt signals to be sent based on at least one of the following priorities: The first priority level corresponding to the signal, the second priority level corresponding to the plurality of interrupt interface modules respectively, and the third priority level of the interrupt sending device corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module determines the target interrupt signal from the interrupt signal to be sent based on the first priority corresponding to the interrupt signal to be sent, including: the interrupt arbitration The module determines at least one to-be-sent interrupt signal with the highest first priority from the to-be-sent interrupt signals as the target interrupt signal; In the interrupt interface module, one or more target interrupt interface modules are determined, and the target interrupt signal is determined according to the first priority from the interrupt signals to be sent corresponding to each of the target interrupt interface modules.
  • the interrupt arbitration module determines the target interrupt signal from the to-be-sent interrupt signals based on second priorities corresponding to the plurality of interrupt interface modules respectively, including: the The interrupt arbitration module determines one or more target interrupt interface modules from the multiple interrupt interface modules based on the respective second priorities of the multiple interrupt interface modules; A target interrupt signal corresponding to each of the target interrupt interface modules.
  • the interrupt arbitration module determines a target interrupt signal corresponding to the target interrupt interface module from the to-be-sent interrupt signals, including: the interrupt arbitration module interrupts from the to-be-sent interrupt signal. In the signal, determine the first candidate interrupt signal corresponding to the target interrupt interface module; based on the receiving order of the first candidate interrupt signal, or the first priority corresponding to the first candidate interrupt signal, respectively, From the first candidate interrupt signals, the target interrupt signal is determined.
  • the interrupt arbitration module determines the target interrupt signal from the interrupt signal to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent, including: The interrupt arbitration module determines one or more target interrupt sending devices from the interrupt sending devices corresponding to the interrupt signal to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent; Among the interrupt signals to be sent, a target interrupt signal corresponding to each target interrupt sending device is determined.
  • the interrupt arbitration module determines the target interrupt signal corresponding to the target interrupt sending device from the to-be-sent interrupt signals, including: the interrupt arbitration module interrupts the to-be-sent interrupt signal.
  • a second candidate interrupt signal corresponding to the target interrupt sending device is determined; based on at least one of the following, from the second candidate interrupt signal, determine the target interrupt signal: the second device The first priority corresponding to the interrupt signal, the second priority corresponding to the interrupt interface module respectively, and the receiving order of the second candidate interrupt signal are selected.
  • the interrupt arbitration module performs arbitration on the interrupt signal to be sent, including: the interrupt arbitration module determines at least two interrupt interface modules from a plurality of the interrupt interface modules based on the interrupt signal to be sent. A target interrupt interface module; for each interrupt interface module in the at least two target interrupt interface modules, from the interrupt signals to be sent corresponding to the interrupt interface module, determine a target interrupt signal corresponding to the interrupt interface module.
  • the interrupt controller further includes a mask register.
  • the interrupt control method further includes: receiving, by the mask register, an interrupt to be masked identifier issued by the interrupt receiving device.
  • the interrupt arbitration module performs arbitration on the interrupt signal to be sent from the interrupt sending device to obtain the target interrupt signal, including: the interrupt arbitration module reads the mask interrupt identifier from the mask register, and based on the The masked interrupt identifier, the masked interrupt signal corresponding to the masked interrupt identifier and the non-masked interrupt signal other than the masked interrupt signal are determined from the interrupt signals to be sent; the non-masked interrupt signal is arbitrated to obtain the Target interrupt signal.
  • the interrupt controller further includes a hanging register; the interrupt control method further includes: after the interrupt arbitration module determines the masked interrupt signal from the interrupt signal to be sent, The masked interrupt signal is stored in the suspending register; after receiving the unmasking interrupt identifier issued by the interrupt receiving device, based on the unmasking interrupt identifier, read and unmask from the suspending register The interrupt signal corresponding to the interrupt identifier is used as the interrupt signal to be sent.
  • the interrupt interface module includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module corresponding to PCIe includes: a data packet integration module, a message signal interrupt table register. , and an interrupt mapping register file; the interrupt control method further comprises: the interrupt mapping register file stores the mapping relationship information between the interrupt signal and the data address pair identifier; the message signal interrupt table register stores the data address pair Identifies the corresponding data address pair; the data address pair includes: an instruction and a processing data register address indicated by the instruction; the data packet integration module, based on the received target interrupt signal, extracts the data from the interrupt mapping register file from the interrupt mapping register file.
  • an embodiment of the present disclosure further provides an interrupt control method, which is applied to an interrupt controller, where the interrupt controller includes: an interrupt arbitration module and an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the The interrupt interface module corresponding to PCIe is connected with the interrupt arbitration module; the interrupt control method includes: the interrupt arbitration module arbitrates the interrupt signal to be sent from the interrupt sending device, obtains the target interrupt signal, and interrupts the corresponding target The interface module sends a target interrupt signal; when the interrupt interface module acts as a target interrupt interface module, in response to receiving the target interrupt signal sent by the interrupt arbitration module, the interrupt interface module connects to the target interrupt interface module based on the target interrupt signal The interrupt receiving device sends the interrupt command.
  • the interrupt controller includes: an interrupt arbitration module and an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the The interrupt interface module corresponding to PCIe is connected with the interrupt arbitration module; the interrupt control method includes: the interrupt arbitration module arbitrates the interrupt signal to be sent from the interrupt sending device, obtain
  • the interrupt control method is applied to the interrupt controller, and the interrupt controller includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module corresponding to the PCIe It includes: a data packet integration module, a message signal interrupt table register, and an interrupt mapping register file; the interrupt control method includes: the interrupt mapping register file stores the mapping relationship information between the interrupt signal and the data address pair identifier; the The message signal interrupt table register stores the data address pair corresponding to the data address pair identifier; the data address pair includes: an instruction and a processing data register address indicated by the instruction; the data packet integration module is based on the received target interrupt signal, determine the target data address pair identifier corresponding to the target interrupt signal from the interrupt mapping register file; use the target data address pair identifier to read the target from the message signal interrupt table register A data address pair; the target data address pair is integrated by PCIe, an interrupt data packet is generated, and the interrupt data packet is sent to the interrupt receiving device corresponding to the target interrupt interface module.
  • the interrupt controller includes an
  • an optional implementation manner of the present disclosure further provides a chip, including the interrupt controller according to any one of the first aspect, or the interrupt controller according to any one of the second aspect.
  • an optional implementation manner of the present disclosure further provides a computer device, including an instruction memory and the interrupt controller according to any one of the first aspect or the second aspect, or the chip according to the fifth aspect.
  • an optional implementation manner of the present disclosure further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program executes any one of the third aspect or the fourth aspect when the computer program is run. steps in a possible implementation.
  • FIG. 1 shows a schematic diagram of an interrupt controller provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of an interrupt controller processing an interrupt signal provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of processing an interrupt signal by another interrupt controller provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of processing an interrupt signal by another interrupt controller provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of processing an interrupt signal by another interrupt controller provided by an embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of another interrupt controller provided by an example of the present disclosure
  • FIG. 7 shows a schematic diagram of an interrupt controller applied to PCIe provided by an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of an interrupt interface module under the PCIe communication protocol in an interrupt controller provided by an example of the present disclosure
  • FIG. 9 shows a schematic diagram of an interrupt signal transmission path between multiple interrupt sending devices and multiple interrupt receiving devices provided by an embodiment of the present disclosure
  • FIG. 10 shows a flowchart of an interrupt control method provided by an embodiment of the present disclosure
  • FIG. 11 shows a flowchart of another interrupt control method provided by an embodiment of the present disclosure.
  • the interrupt sending device can usually send the interrupt signal to the interrupt receiving device by means of bus transmission. If different interrupt receiving devices and interrupt sending devices use different communication protocols when communicating , then the interrupt sending device needs to frequently switch the interface according to the communication protocol used by the interrupt receiving device to be sent when sending the interrupt signal to different interrupt receiving devices, which makes the process of sending the interrupt signal complicated.
  • the process of judging the communication protocol between the interrupt sending device and the corresponding interrupt receiving device, determining the communication interface, and sending an interrupt signal to the communication interface needs to occupy the computing resources of the interrupt sending device.
  • the process of sending an interrupt instruction to an interrupt receiving device based on an interrupt signal is simply referred to as sending an interrupt signal to the interrupt receiving device.
  • the present disclosure provides an interrupt controller.
  • the interrupt sending device can send the When the interrupt receiving device using different communication protocols sends the interrupt signal, it only needs to send the interrupt signal to the interrupt controller, and the interrupt sending device does not need to switch the interface, thereby reducing the complexity of the process of sending the interrupt signal by the interrupt sending device.
  • the interrupt arbitration module in the interrupt controller determines the specific interrupt interface module to which the interrupt signal is to be sent, and uses the determined interrupt interface module to send the interrupt signal to the corresponding interrupt receiving device, there is no need to occupy the interrupt The computing resources of the sending device.
  • the interrupt controller provided by the embodiments of the present disclosure can be connected to only one interrupt sending device, so that the interrupt sending device can use a dedicated interrupt controller to send an interrupt signal to the interrupt receiving device; when connecting an interrupt sending device with an interrupt When the controller is connected, the two can be connected through an interface, or the two can be connected through a circuit. It is also possible to set multiple input ports on the interrupt controller, and connect to different interrupt sending devices through multiple input ports. Different interrupt sending devices can respectively send interrupt signals to the same or different interrupt receivers through the same interrupt controller. equipment.
  • FIG. 1 is a schematic diagram of the interrupt controller provided by the embodiment of the present disclosure
  • the interrupt controller includes: The interrupt arbitration module 110 and a plurality of interrupt interface modules 120 respectively connected to the interrupt arbitration module 110 .
  • the interrupt arbitration module 110 is used to arbitrate the interrupt signal to be sent from the interrupt sending device, obtain the target interrupt signal, and send the target interrupt signal to the corresponding target interrupt interface module;
  • the interrupt interface module 120 is used as a target interrupt interface module, in response to receiving the target interrupt signal sent by the interrupt arbitration module 110, based on the target interrupt signal to the interrupt receiving device connected to the target interrupt interface module Send interrupt command.
  • the multiple interrupt interface modules 120 may include, for example, interrupt interface modules 120 that respectively adopt multiple different communication protocols, and the communication protocols may include, for example, at least two of the following: a high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe ) protocol, Serial Peripheral Interface (SPI) protocol, I2C bus (Inter-Integrated Circuit, I2C) protocol, Universal Serial Bus (Universal Serial Bus, USB) protocol, and Ethernet (Ethernet) protocol.
  • the multiple interrupt interface modules 120 include, for example, at least two of a PCIe interface, an SPI interface, an I2C interface, a USB interface, and an Ethernet interface.
  • the interrupt interface module 120 that adopts a certain communication protocol is referred to as the interrupt interface module 120 corresponding to the communication protocol.
  • any communication protocol only needs to correspond to one interrupt interface module, and there is no need to set a plurality of corresponding interrupt interface modules 120 for one communication protocol.
  • FIG. 1 an interrupt interface module 120-0 corresponding to the PCIe communication protocol, an interrupt interface module 120-1 corresponding to the SPI communication protocol, and an interrupt interface module 120-2 corresponding to the I2C communication protocol are shown.
  • the number of interrupt interface modules 120 corresponding to one communication protocol may be set by those skilled in the art according to actual conditions, which is not specifically limited in the embodiment of the present disclosure.
  • the interrupt signal to be sent may include, for example, an interrupt signal currently received by the interrupt arbitration module 110 and sent by the interrupt sending device.
  • the interrupt sending device sends the interrupt signal to the interrupt arbitration module 110, it can send the interrupt signal to the interrupt arbitration module 110 in the interrupt controller one by one in an orderly manner according to the actual situation, according to its own data processing cycle or data processing sequence, or in the interrupt controller. Multiple interrupt signals are sent to the interrupt arbitration module 110 in one data processing cycle or one time slice of the data processing sequence.
  • the interrupt arbitration module 110 determines the interrupt signal to be sent, for example, the following methods may be adopted: determine the interrupt signal currently received and sent by the interrupt sending device as the interrupt signal to be sent, and/or remove the historical target from the historical interrupt signal The interrupt signal other than the interrupt signal is used as the interrupt signal to be sent.
  • the interrupt newly received by the interrupt arbitration module 110 can be
  • the signals are all interrupt signals to be sent, and the interrupt signals sent by the interrupt sending device may include, for example, interrupt signal a, interrupt signal b, . . . , interrupt signal i, and interrupt signal j.
  • interrupt signal sent by the interrupt sending device may include, for example, interrupt signals corresponding to N different communication protocols (hereinafter also referred to as N kinds of interrupt signals), and each interrupt signal may include M (N and M are both positive integers)
  • N kinds of interrupt signals may include M (N and M are both positive integers)
  • M are both positive integers
  • the number of interrupt signals of different types can be the same or different.
  • the interrupt sending device In other arbitration cycles except the first arbitration cycle, that is, the arbitration cycle in which the interrupt signal sent by the interrupt sending device is not received for the first time, because there may be an interrupt signal sent by the interrupt sending device to the interrupt controller in the historical data processing cycle , and these interrupt signals are not sent to the corresponding interrupt receiving device in the historical data processing cycle. Therefore, when determining the interrupt signal to be sent, the interrupt sending device must also send the historical interrupt signal in the historical data processing cycle. Other interrupt signals other than the historical target interrupt signal are also determined as the interrupt signal to be sent, wherein the historical target interrupt signal is the target interrupt signal determined and completed in the historical data processing cycle.
  • the historical interrupt signal as the interrupt signal to be sent may include, for example, an interrupt signal that is masked in the historical data processing cycle but unmasked in the current data processing cycle.
  • It may also include: an interrupt signal sent by the interrupt sending device to the interrupt arbitration module 110 in the current data processing cycle, but not sent to the interrupt receiving device in the previous arbitration cycle because it was not determined as the target interrupt signal.
  • the interrupt controller may include a status register, where the status register is used to store status information of the interrupt signal. The interrupt controller can poll or clear the information held in the status register as needed.
  • the interrupt arbitration module 110 arbitrates the interrupt signal to be sent, for example, based on at least one of the following priorities, from the interrupt signal to be sent, determine the target interrupt signal: the first priority corresponding to the interrupt signal to be sent, a plurality of interrupts
  • the interface module 120 corresponds to the second priority and the third priority of the interrupt sending device corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module 110 determines the target interrupt signal from the interrupt signal to be sent, for example, at least one of the following methods (A), (B), and (C) may be adopted:
  • the interrupt arbitration module 110 determines the target interrupt signal from the interrupt signals to be sent based on the first priority corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module 110 uses the first priority to determine the target interrupt signal, the following manner (A1) or (A2) may be adopted:
  • (A1) Based on the first priority corresponding to the interrupt signal to be sent, at least one interrupt signal to be sent with the highest first priority is determined from the interrupt signals to be sent as the target interrupt signal.
  • the first priority may be predetermined, for example, a first priority 0 corresponding to the interrupt signal a, a first priority 1 corresponding to the interrupt signal b, . . . , and a first priority 9 corresponding to the interrupt signal j , and determine the order of priority from low to high as the first priority 0, the first priority 1, the first priority 2, ..., the first priority 9, that is, the first priority 0 has the lowest priority , the first priority 9 has the highest priority.
  • the interrupt arbitration module 110 may determine a target interrupt signal to send to the interrupt interface module 120 according to the corresponding first priorities.
  • the interrupt arbitration module 110 may receive multiple interrupt signals with different first priorities, for example, simultaneously receive the interrupt signal a to the interrupt signal c. At this time, since the first priority of the interrupt signal c is higher, the interrupt arbitration module 110 first uses the interrupt signal c as the target interrupt signal, and uses the interrupt interface module 120 corresponding to the interrupt signal c as the target interrupt interface module, such as an interrupt The interface module 120-0 then sends the interrupt signal c to the interrupt interface module 120-0.
  • the interrupt arbitration module 110 receives the interrupt signal a sent by the interrupt sending device 200-2, and the interrupt sending device 200-1 sends the interrupt signal a. After the interrupt signal b and the interrupt signal c sent by the sending device 200-0 are interrupted, the interrupt signal c is sent as the target interrupt signal to the interrupt interface module 120-0 corresponding to the interrupt signal c.
  • the interrupt signal with the highest priority among all the interrupt signals sent by the interrupt sending device is sent first, so that the interrupt receiving device can receive and process the more important interrupt signals first.
  • a higher priority can be set for a task that needs to be processed first, and a lower priority can be set for other tasks that need to be processed. In this way, it can be ensured that more important tasks are prioritized.
  • the interrupt arbitration module 110 may also receive multiple interrupt signals with the same first priority.
  • the target interrupt signals may be determined according to the time sequence in which the interrupt signals are received, for example, an interrupt signal that receives an earlier interrupt signal is determined as the target interrupt signal.
  • the plurality of interrupt interface modules 120 may include an interrupt interface module 120-0, an interrupt interface module 120-1, and an interrupt interface module 120-2.
  • the interrupt signals sent to each interrupt interface module 120 respectively include: sending interrupt signal h, interrupt signal i, and interrupt signal j to interrupt interface module 120-0; sending interrupt signal e and interrupt signal f to interrupt interface module 120-1 , and interrupt signal g; send interrupt signal a, interrupt signal b, interrupt signal c, and interrupt signal d to the interrupt interface module 120-2.
  • the scheduling sequence of the multiple interrupt interface modules 120 can be determined, for example, according to the importance of each interrupt receiving device corresponding to the multiple interrupt interface modules 120 .
  • the interrupt receiving device 300-2 undertakes relatively important data processing tasks, and when the interrupt receiving device 300-0 undertakes the simplest data processing task, it can be determined that the scheduling sequence of the three interrupt interface modules 120 is the interrupt interface module 120-2 ⁇ Interrupt interface module 120-1 ⁇ interrupt interface module 120-0.
  • the interrupt interface module 120-2 is firstly used as the target interrupt interface module.
  • the interrupt signal to be sent corresponding to the interrupt interface module 120-2 that is, the interrupt signal a, the interrupt signal b, the interrupt signal c, and the interrupt signal d, can also be determined, and the interrupt signal with the highest first priority is also That is, the interrupt signal d is determined as the target interrupt signal.
  • the interrupt signal d can be used as the target interrupt signal and sent to the interrupt receiving device 300-2 by using the interrupt interface module 120-2.
  • the interrupt receiving device 300 - 2 receives the interrupt signal d, that is, the sending process indicated by 1 in FIG. 3 .
  • the interrupt arbitration module 110 may continue to perform the process according to the scheduling sequence of the interrupt interface module 120. Polling, that is, determining the interrupt interface module 120-1 as the target interrupt interface module, and determining the target interrupt signal among the multiple interrupt signals corresponding to the interrupt interface module 120-1.
  • the interrupt signal g with the highest first priority can be determined as the target interrupt signal , and use the interrupt interface module 120-1 to send it to the interrupt receiving device 300-1; then, for a plurality of interrupt signals to be sent corresponding to the interrupt interface module 120-0, that is, the interrupt signal h, the interrupt signal i, the interrupt signal For the signal j, the interrupt signal j with the highest first priority may be determined as the target interrupt signal, and sent to the interrupt receiving device 300-0 by using the interrupt interface module 120-0.
  • the sending process indicated by 1 corresponds to the interrupt receiving device 300-2 that first receives the interrupt signal d
  • the sending process indicated by 2 corresponds to the interrupt receiving device 300-1 and then receives the interrupt signal g
  • the sending process indicated by 3 The process-corresponding interrupt receiving device 300-0 finally receives the interrupt signal j.
  • the target interrupt signal can be determined according to all received interrupt signals to be sent.
  • the importance of the multiple interrupt interface modules 120 can be determined according to the scheduling sequence of the multiple interrupt interface modules 120, and the corresponding interrupts with the highest priority are sent to the multiple interrupt interface modules 120 in turn in a polling manner. signal, so that the more important interrupt interface module 120 among the multiple interrupt interface modules 120 can receive the corresponding target interrupt signal first, and then other interrupt interface modules 120 can also receive the corresponding target interrupt signal according to the degree of importance; It can be ensured that the interrupt receiving devices 300 corresponding to the multiple interrupt interface modules 120 can receive the target interrupt signal and perform data processing, improve the utilization rate of the multiple interrupt interface modules 120, and improve the calculation of the interrupt signal processing by the multiple interrupt receiving devices 300. power utilization.
  • the interrupt arbitration module 110 determines the target interrupt signal from the interrupt signals to be sent based on the second priorities corresponding to the plurality of interrupt interface modules 120 respectively.
  • the interrupt arbitration module 110 when the interrupt arbitration module 110 uses the second priority to determine the target interrupt signal, it may determine one or more interrupt interface modules 120 based on the second priority corresponding to the multiple interrupt interface modules 120 respectively. target interrupt interface modules 120; from the interrupt signals to be sent, determine the target interrupt signal corresponding to each target interrupt interface module 120.
  • the second priority may be predetermined, for example, the second priority 0 is determined for the interrupt interface module 120-0, the second priority 1 is determined for the interrupt interface module 120-1, and the corresponding second priority is determined for the interrupt interface module 120-2.
  • the second priority 2 that is, the interrupt interface module with the highest priority is the interrupt interface module 120-2, followed by the interrupt interface module 120-1, and the interrupt interface module with the lowest priority is the interrupt interface module 120-0.
  • the multiple interrupt interface modules 120 include the interrupt interface module 120-0 to the interrupt interface module 120-2, the highest priority can be determined. is the second priority level 2, and the corresponding interrupt interface module is the interrupt interface module 120-2, which is determined as the target interrupt interface module.
  • the target interrupt signal corresponding to the target interrupt interface module is determined from the plurality of interrupt signals to be sent.
  • the target interrupt signal corresponding to the target interrupt interface module can be determined in the following manner: from the interrupt signals to be sent, the first candidate interrupt signal corresponding to the target interrupt interface module is determined; based on the reception of the first candidate interrupt signal The sequence, or the first priority corresponding to the first candidate interrupt signal respectively, determines the target interrupt signal from the first candidate interrupt signal.
  • the interrupt signals to be sent include interrupt signal a to interrupt signal j, and the determined first interrupt interface module 120-2 corresponds to the target interrupt interface module 120-2.
  • the alternative interrupt signals may include a plurality of interrupt signals sent by the interrupt sending device 200-2: interrupt signal a, interrupt signal b, interrupt signal c, and interrupt signal d.
  • the first candidate interrupt signal may be all interrupt signals to be sent, or part of the interrupt signals that need to be transmitted by the target interrupt interface module.
  • the part of the interrupt signal is, for example, an interrupt signal to be transmitted to a specific interrupt receiving device connected to the target interrupt interface module.
  • any one of the following methods (B1) or (B2) may be adopted:
  • the receiving sequence of the first candidate interrupt signal may be interrupt signal a ⁇ interrupt signal b ⁇ interrupt signal c ⁇ interrupt signal d.
  • the interrupt signal a received first can be used as the target interrupt signal. In this way, it can be ensured that the interrupt signal received by the interrupt arbitration module 110 earlier among the plurality of first candidate interrupt signals is sent to the interrupt receiving device for processing, so as to prevent stagnation.
  • FIG. 4 another schematic diagram of an interrupt controller processing an interrupt signal according to an embodiment of the present disclosure is provided.
  • the interrupt sending device 200-2 sends the interrupt signal a ⁇ interrupt signal d to the interrupt arbitration module 110 in sequence, and the interrupt arbitration module 110 determines the target interrupt signal as the interrupt signal a according to the receiving sequence of the first candidate interrupt signal,
  • the interrupt signal a is sent to the interrupt receiving device 300-2 corresponding to the interrupt signal a.
  • the first priority corresponding to the first candidate interrupt signal includes: the interrupt signal a corresponds to the first priority 0, the interrupt signal b corresponds to the first priority 1, and the interrupt signal c corresponds to the first priority
  • the priority level 2 and the interrupt signal d correspond to the first priority level 3.
  • the first priority with the highest priority, that is, priority 3 may be determined, and the corresponding interrupt signal d may be used as the target interrupt signal.
  • the interrupt arbitration module 110 determines the target interrupt signal from the interrupt signals to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module 110 uses the third priority to determine the target interrupt signal, based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent, from the interrupt sending device corresponding to the interrupt signal to be sent, One or more target interrupt sending devices are determined; from the interrupt signals to be sent, a target interrupt signal corresponding to each target interrupt sending device is determined.
  • the third priority may be predetermined, for example, including determining the corresponding third priority 0 for the interrupt sending device 200-0, determining the corresponding third priority 1 for the interrupt sending device 200-1, and determining the corresponding third priority for the interrupt sending device 200-2. Three priority 2. Then, among the interrupt sending device 200-0 to the interrupt sending device 200-2, the highest priority is the third priority 2, and the corresponding interrupt sending device is the interrupt sending device 200-2. At this time, it can be determined that the interrupt sending device 200-2 is the target interrupt sending device.
  • the corresponding target interrupt signal can be determined according to the target interrupt sending device.
  • the target interrupt signal may be determined in the following manner: from the interrupt signals to be sent, a second candidate interrupt signal corresponding to the target interrupt sending device is determined; based on at least one of the following, from the second candidate interrupt signal , and determine the target interrupt signal: the first priority corresponding to the second candidate interrupt signal, the second priority corresponding to the interrupt interface module 120 respectively, and the receiving order of the second candidate interrupt signal.
  • the interrupt arbitration module 110 may receive, for example, the interrupt signal a to the interrupt signal d sent by the interrupt sending device 200-2.
  • the target interrupt sending device that is, the interrupt sending device 200-2, and the corresponding interrupt signals a to d may be used as the second candidate interrupt signals.
  • determining the target interrupt signal from the second candidate interrupt signal for example, at least one of the following methods (C1), (C2), and (C3) may be adopted:
  • (C1) Determine the target interrupt signal from the second candidate interrupt signal according to the first priority corresponding to the second candidate interrupt signal.
  • using the first priority to determine the target interrupt signal from the second candidate interrupt signal, that is, from the interrupt signal a to the interrupt signal d, is similar to the methods (A1) and (A2) above. Repeat.
  • (C2) Determine the target interrupt signal from the second candidate interrupt signals according to the second priorities corresponding to the interrupt interface modules 120 respectively.
  • using the second priority to determine the target interrupt signal from the second candidate interrupt signal, that is, from the interrupt signal a to the interrupt signal d, is similar to the method of determining the target interrupt signal in the above (B), and the same here No longer.
  • (C3) according to the receiving sequence of the second candidate interrupt signal, determine the target interrupt signal from the second candidate interrupt signal.
  • the method of determining the target interrupt signal from the second candidate interrupt signal that is, from the interrupt signal a to the interrupt signal d, is similar to the method of determining the target interrupt signal in the above-mentioned determination (B1), and the same is not used here. Repeat.
  • the interrupt arbitration module 110 can preferentially send more important target interrupt signals to the corresponding interrupt interface module 120 first.
  • interrupt arbitration module 110 determines to send corresponding target interrupt signals to multiple interrupt interface modules 120 at the same time.
  • the interrupt arbitration module 110 may perform arbitration according to the following manner: based on the interrupt signal to be sent, from among the plurality of interrupt interface modules 120, at least two target interrupt interface modules 120 are determined; Each of the interrupt interface modules 120 in the system determines the target interrupt signal corresponding to the interrupt interface module 120 from the interrupt signals to be sent corresponding to the interrupt interface module 120 .
  • FIG. 5 another schematic diagram of an interrupt controller processing an interrupt signal according to an embodiment of the present disclosure is provided.
  • the interrupt interface module 120-0 corresponds to the first priority level
  • the interrupt interface module 120-1 corresponds to the first priority level 1
  • the interrupt interface module 120-2 corresponds to the first priority level 2, although the priority level is the highest
  • the interrupt interface module is the interrupt interface module 120-2, but the interrupt sending device 200-2 does not send an interrupt signal, that is, the interrupt interface module 120-2 has no corresponding interrupt signal, so it does not send an interrupt signal to the interrupt interface module 120-2.
  • both of the two interrupt interface modules 120 are used as target interrupt interface modules.
  • the target interrupt signal to be sent to the interrupt interface module 120-0 may be determined in a manner similar to the above (A1);
  • the target interrupt signal sent by the module 120-1 is the interrupt signal g.
  • the interrupt arbitration module 110 may be based on the first priority corresponding to the interrupt signal to be sent, the second priority corresponding to the multiple interrupt interface modules 120 respectively, and the interrupt sending device corresponding to the interrupt signal to be sent. At least one of the third priority levels of 200, at least two target interrupt interface modules are determined.
  • the interrupt arbitration module 110 may determine the interrupt signal with the highest priority and the second highest priority among the interrupt signals to be sent, and then The interrupt interface module 120 for transmitting the two interrupt signals serves as the target interrupt interface module.
  • the interrupt arbitration module 110 determines the specific processing process of the at least two target interrupt interface modules, which is similar to the solutions of the above-mentioned methods (A), (B), and (C), and will not be repeated here.
  • the interrupt receiving device may also issue a masking interrupt flag to the interrupt controller.
  • a masking interrupt flag For example, during the process of image data processing, when a certain image data to be processed is too large, it may be set at a preset value. The processing of the to-be-processed image data cannot be completed during the processing time, so the interrupt receiving device can issue a masked interrupt flag to the interrupt controller, and tasks corresponding to the masked interrupt include, for example, sending new to-be-processed image data.
  • the interrupt receiving device may not receive new image data to be processed first, but after the processing of the image data being processed is completed, send the unmasking interrupt flag to the interrupt controller to ensure that new image data to be processed is received again.
  • the interrupt receiving device does not have accumulated image data to be processed, data loss caused by overflow from the corresponding register is prevented, and errors caused by data mixing are reduced.
  • an example of the present disclosure further provides another interrupt controller, including a mask register 130 .
  • the interrupt receiving device 300 issues a mask interrupt identifier
  • the mask register 130 can receive the mask interrupt identifier.
  • the interrupt arbitration module 110 can read the mask interrupt flag from the mask register 130, and based on the mask interrupt flag, arbitrate the interrupt signal to be sent to obtain the target interrupt signal.
  • the interrupt controller receives the interrupt sending device 200-0 and sends the interrupt signal a to the interrupt signal e to the interrupt receiving device 300-0.
  • the interrupt receiving device 300-0 sends a masked interrupt flag to the interrupt controller, which may correspond to one interrupt signal, such as interrupt signal a; or correspond to multiple interrupt signals, such as interrupt signal d and interrupt signal e.
  • the interrupt receiving device 300-0 issues the masked interrupt identifier to the interrupt controller
  • the masked interrupt identifier is received by the mask register 130 in the interrupt controller, and then the interrupt arbitration module 110 reads the masked interrupt identifier from the mask register 130, A masked interrupt signal corresponding to the masked interrupt representation and a non-maskable interrupt signal other than the masked interrupt signal are determined from the interrupt signals to be sent.
  • the interrupt arbitration module 110 determines the non-maskable interrupt signal from the interrupt signal a to the interrupt signal e included in the interrupt signal to be sent, including the interrupt signal b to the interrupt signal. e, and then arbitrate the non-maskable interrupt signal to obtain the target interrupt signal.
  • the interrupt signal corresponding to the masked interrupt identifier includes the interrupt signal e and the interrupt signal f
  • the interrupt signal to be sent since the interrupt signal to be sent only includes the interrupt signal a to the interrupt signal e, but does not include the interrupt signal f, the non-maskable interrupt signal determined by the interrupt arbitration module 110
  • the interrupt signal includes the interrupt signal a to the interrupt signal d, and then the non-maskable interrupt signal is arbitrated to obtain the target interrupt signal.
  • the way that the interrupt arbitration module 110 arbitrates the non-maskable interrupt signal to obtain the target interrupt signal is the same as the way in which the interrupt arbitration module 110 determines the target interrupt signal in (A), (B), and (C) above. The method is similar and will not be repeated here.
  • a suspension register 140 may also be included for storing the masked interrupt signal. Specifically, after the interrupt arbitration module 110 determines the masked interrupt signal from the interrupt signals to be sent, the masked interrupt signal may be stored in the suspension register 140 . At this time, the masked interrupt signal is retained in the hanging register 140 until the masking register 130 receives the unmasking interrupt identifier sent by the interrupt receiving device, and the interrupt arbitration module 110 obtains the unmasking interrupt identifier from the masking register 130 and unmasks the interrupt based on this The flag, from the hanging register 140, obtains the interrupt signal corresponding to the unmasking interrupt flag as the interrupt signal to be sent.
  • Different communication protocols may correspond to different pending registers 140.
  • a dedicated register may be set for a certain communication protocol. For example, when the communication protocol includes PCIe, a pending bit array (Pending Bit Array, PBA) may be set as the PCIe corresponding. the hanging register.
  • the embodiments of the present disclosure also provide an interrupt controller applied to the high-speed serial computer expansion bus standard PCIe.
  • an interrupt controller applied to PCIe provided by an embodiment of the present disclosure includes: an interrupt arbitration module 710 and an interrupt interface module 720 corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module 720 Connected with the interrupt arbitration module 710; wherein,
  • the interrupt arbitration module 710 is used to arbitrate the interrupt signal to be sent from the interrupt sending device, obtain the target interrupt signal, and send the target interrupt signal to the corresponding target interrupt interface module;
  • the interrupt interface module 720 corresponding to PCIe is used as a target interrupt interface module, in response to receiving the target interrupt signal sent by the interrupt arbitration module 710, based on the target interrupt signal, to the interrupt receiving device connected to the target interrupt interface module to send an interrupt instruction to the device .
  • the interrupt interface module 720 corresponding to PCIe may further include a data packet integration module, a message signal interrupt table register, and an interrupt mapping register file.
  • the interrupt mapping register file is used to store the mapping relationship information between the interrupt signal and the data address pair identifier
  • the message signal interrupt table register is used to store the data address pair corresponding to the data address pair identifier; the data address pair includes: the instruction and the processing data register address indicated by the instruction;
  • the data packet integration module is used to determine the target corresponding to the target interrupt signal from the interrupt mapping register file based on the received target interrupt signal when sending an interrupt instruction to the interrupt receiving device connected to the target interrupt interface module based on the target interrupt signal Data address pair identification; using the target data address pair identification, read the target data address pair from the message signal interrupt table register; use PCIe to integrate the target data address pair, generate an interrupt packet, and send it to the corresponding interrupt interface module.
  • An interrupt receiving device sends an interrupt packet.
  • FIG. 8 is a schematic diagram of an interrupt interface module 720 under the PCIe communication protocol in an interrupt controller according to an embodiment of the present disclosure.
  • the interrupt interface module 720 under the PCIe communication protocol includes a data packet integration module 810, a message signal interrupt table register (Message Signaled Interrupt-X Table RAM, MSI-X Table RAM) 820, and an interrupt mapping register file 830 .
  • the interrupt receiving device can issue the mapping relationship information between the interrupt signal and the data address pair identifier to the interrupt mapping register file 830, for example, the interrupt signal a corresponds to pair0, the interrupt signal b corresponds to pair1, and the interrupt signal c corresponds to pair2 .
  • the data address pair corresponding to the data address pair identifier can also be issued to the message signal interrupt table register 820, for example, including the data address pair corresponding to pair0: 0X00-ABC, the data address pair corresponding to pair1: 0X01-DEF, corresponding to pair2
  • the data address pair 0X02-XYZ.
  • the data address pair includes the instruction and the register address of the data to be processed indicated by the instruction. For example, ABC, DEF, XYZ can correspond to different instructions, and 0X00, 0X01, and 0X02 can, for example, correspond to the register address of the pending data indicated by the instruction. .
  • the data packet integration module 810 determines the target data address pair identifier corresponding to the target interrupt signal from the interrupt mapping register file 830 based on the received target interrupt signal, for example, the interrupt signal a, For example, pair0; use the target data address pair to identify pair0, read the target data address pair 0X00-ABC from the message signal interrupt table register 820; use PCIe to integrate the target data address pair, such as adding header information, and then generate an interrupt data packets, and send the interrupt data packets to the interrupt receiving device corresponding to the interrupt interface module 720 .
  • FIG. 9 is a schematic diagram of an interrupt signal transmission path between multiple interrupt sending devices and multiple interrupt receiving devices according to an embodiment of the present disclosure.
  • three interrupt receiving devices are included, namely, interrupt receiving device 300-0, interrupt receiving device 300-1, and interrupt receiving device 300-2; and three interrupt sending devices are also included, which are interrupt sending device 200 respectively.
  • Each interrupt sending device includes a corresponding interrupt controller, including an interrupt controller 100-0 to an interrupt controller 100-2, and each interrupt sending device is integrally set with its internal interrupt controller.
  • each interrupt controller includes an interrupt interface module corresponding to the communication protocol used by the interrupt receiving device 300-0 to the interrupt receiving device 300-2, any interrupt sending device 200 can send an interrupt signal to the interrupt receiving device 300-0 to any one of the interrupt receiving device 300-2.
  • the interrupt sending device 200 can select the interrupt receiving device 300 that is the same as the previous interrupt signal, or the interrupt receiving device 300 that is different from the previous interrupt signal. device 300.
  • the writing order of each step does not mean a strict execution order but constitutes any limitation on the implementation process, and the specific execution order of each step should be based on its function and possible Internal logic is determined.
  • the embodiment of the present disclosure also provides an interrupt control method corresponding to the interrupt controller.
  • the control method reference may be made to the implementation of the interrupt controller, and the repetition will not be repeated.
  • an interrupt controller includes: an interrupt arbitration module connected to a plurality of interrupt sending devices; A plurality of interrupt interface modules connected to the corresponding interrupt receiving device; the plurality of interrupt interface modules are respectively connected with the interrupt arbitration module, and can use different communication protocols to perform data transmission with the corresponding interrupt receiving device; the interrupt control method includes:
  • the interrupt arbitration module arbitrates the interrupt signal to be sent from the interrupt sending device, obtains the target interrupt signal, and sends the target interrupt signal to the corresponding target interrupt interface module;
  • the interrupt interface module when used as the target interrupt interface module, sends an interrupt instruction to the corresponding interrupt receiving device based on the target interrupt signal in response to receiving the target interrupt signal sent by the interrupt arbitration module.
  • the interrupt control method further includes: the interrupt arbitration module determines the currently received interrupt signal sent by the interrupt sending device as the to-be-sent interrupt signal, and/or, interrupts the history The interrupt signals other than the historical target interrupt signal in the signal are used as the interrupt signal to be sent; wherein, the historical interrupt signal is the interrupt signal sent by the interrupt sending device received by the interrupt arbitration module in the historical data processing cycle, so The historical target interrupt signal is the target interrupt signal determined in the historical data processing cycle.
  • the interrupt arbitration module performs arbitration on interrupt signals to be sent, including determining a target interrupt signal from the interrupt signals to be sent based on at least one of the following priorities: The first priority level corresponding to the signal, the second priority level corresponding to the plurality of interrupt interface modules respectively, and the third priority level of the interrupt sending device corresponding to the interrupt signal to be sent.
  • the interrupt arbitration module determines the target interrupt signal from the interrupt signal to be sent based on the first priority corresponding to the interrupt signal to be sent, including: the interrupt arbitration The module determines at least one to-be-sent interrupt signal with the highest first priority from the to-be-sent interrupt signals as the target interrupt signal; In the interrupt interface module, one or more target interrupt interface modules are determined, and the target interrupt signal is determined according to the first priority from the interrupt signals to be sent corresponding to each of the target interrupt interface modules.
  • the interrupt arbitration module determines the target interrupt signal from the to-be-sent interrupt signals based on second priorities corresponding to the plurality of interrupt interface modules respectively, including: the The interrupt arbitration module determines one or more target interrupt interface modules from the multiple interrupt interface modules based on the respective second priorities of the multiple interrupt interface modules; A target interrupt signal corresponding to each of the target interrupt interface modules.
  • the interrupt arbitration module determines a target interrupt signal corresponding to the target interrupt interface module from the to-be-sent interrupt signals, including: the interrupt arbitration module interrupts from the to-be-sent interrupt signal. In the signal, determine the first candidate interrupt signal corresponding to the target interrupt interface module; based on the receiving order of the first candidate interrupt signal, or the first priority corresponding to the first candidate interrupt signal, respectively, From the first candidate interrupt signals, the target interrupt signal is determined.
  • the interrupt arbitration module determines the target interrupt signal from the interrupt signal to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent, including: The interrupt arbitration module determines one or more target interrupt sending devices from the interrupt sending devices corresponding to the interrupt signal to be sent based on the third priority of the interrupt sending device corresponding to the interrupt signal to be sent; Among the interrupt signals to be sent, a target interrupt signal corresponding to each target interrupt sending device is determined.
  • the interrupt arbitration module determines the target interrupt signal corresponding to the target interrupt sending device from the to-be-sent interrupt signals, including: the interrupt arbitration module interrupts the to-be-sent interrupt signal.
  • a second candidate interrupt signal corresponding to the target interrupt sending device is determined; based on the first priority corresponding to the second candidate interrupt signal, the second priority corresponding to the interrupt interface module, the at least one of the receiving sequences of the second candidate interrupt signals, and determine the target interrupt signal from the second candidate interrupt signals.
  • the interrupt arbitration module performs arbitration on the interrupt signal to be sent, including: the interrupt arbitration module determines at least two interrupt interface modules from a plurality of the interrupt interface modules based on the interrupt signal to be sent. A target interrupt interface module; for each interrupt interface module in the at least two target interrupt interface modules, from the interrupt signals to be sent corresponding to the interrupt interface module, determine a target interrupt signal corresponding to the interrupt interface module.
  • the interrupt controller further includes: a mask register; and the interrupt control method further includes: the mask register receives a mask interrupt identifier sent by the interrupt receiving device.
  • the interrupt arbitration module performs arbitration on the interrupt signal to be sent from the interrupt sending device to obtain the target interrupt signal, including: the interrupt arbitration module reads the mask interrupt identifier from the mask register, and based on the The masked interrupt identifier, the masked interrupt signal corresponding to the masked interrupt identifier and the non-masked interrupt signal other than the masked interrupt signal are determined from the interrupt signals to be sent; the non-masked interrupt signal is arbitrated to obtain the Target interrupt signal.
  • the interrupt controller further includes: a suspension register; and the interrupt control method further includes: after the interrupt arbitration module determines the masked interrupt signal from the interrupt signal to be sent, Store the masked interrupt signal in the suspending register; after receiving the unmasking interrupt identifier issued by the interrupt receiving device, based on the unmasking interrupt identifier, from the suspending register, read and unmask the The interrupt signal corresponding to the masked interrupt identifier is used as the interrupt signal to be sent.
  • the interrupt interface module includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module corresponding to PCIe includes: a data packet integration module, a message signal interrupt table register. , and an interrupt mapping register file; the interrupt control method further comprises: the interrupt mapping register file stores the mapping relationship information between the interrupt signal and the data address pair identifier; the message signal interrupt table register stores the data address pair Identifies the corresponding data address pair; the data address pair includes: an instruction and a processing data register address indicated by the instruction; the data packet integration module, based on the received target interrupt signal, extracts the data from the interrupt mapping register file from the interrupt mapping register file.
  • FIG. 11 a flowchart of another interrupt control method provided by an embodiment of the present disclosure is applied to an interrupt controller, where the interrupt controller includes: an interrupt arbitration module, and a high-speed serial computer expansion bus standard PCIe corresponding The interrupt interface module; the interrupt interface module is connected with the interrupt arbitration module; the interrupt control method includes:
  • the interrupt arbitration module arbitrates the interrupt signal to be sent from the interrupt sending device, obtains the target interrupt signal, and sends the target interrupt signal to the corresponding target interrupt interface module;
  • the interrupt control method is applied to the interrupt controller, and the interrupt controller includes an interrupt interface module corresponding to the high-speed serial computer expansion bus standard PCIe; the interrupt interface module corresponding to the PCIe It includes: a data packet integration module, a message signal interrupt table register, and an interrupt mapping register file; the interrupt control method includes: the interrupt mapping register file stores the mapping relationship information between the interrupt signal and the data address pair identifier; the The message signal interrupt table register stores the data address pair corresponding to the data address pair identifier; the data address pair includes: an instruction and a processing data register address indicated by the instruction; the data packet integration module is based on the received target interrupt signal, determine the target data address pair identifier corresponding to the target interrupt signal from the interrupt mapping register file; use the target data address pair identifier to read the target from the message signal interrupt table register A data address pair; the target data address pair is integrated by PCIe, an interrupt data packet is generated, and the interrupt data packet is sent to the interrupt receiving device corresponding to the target interrupt interface module.
  • the interrupt controller includes an
  • An embodiment of the present disclosure further provides a chip, including the interrupt controller according to any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a computer device, including an instruction memory and the interrupt controller described in any of the foregoing embodiments, or the chip described in the embodiment of the present disclosure.
  • Embodiments of the present disclosure further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the steps of the interrupt control method described in the foregoing method embodiments are executed.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • Embodiments of the present disclosure further provide a computer program product, where the computer program product carries program codes, and the instructions included in the program codes can be used to execute the steps of the interrupt control method described in the foregoing method embodiments.
  • the computer program product carries program codes
  • the instructions included in the program codes can be used to execute the steps of the interrupt control method described in the foregoing method embodiments.
  • the foregoing method please refer to the foregoing method. The embodiments are not repeated here.
  • the above-mentioned computer program product can be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. Wait.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-executable non-volatile computer-readable storage medium.
  • the computer software products are stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本公开提供了一种中断控制器、中断控制方法、芯片、计算机设备以及存储介质，其中，该中断控制器包括：与多个中断发送设备连接的中断仲裁模块、分别与对应的中断接收设备连接的多个中断接口模块；多个中断接口模块分别与中断仲裁模块连接且能够采用不同的通信协议与对应的中断接收设备进行数据传输；其中，中断仲裁模块，用于对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；中断接口模块，在作为目标中断接口模块时，用于响应于接收到中断仲裁模块发送的目标中断信号，基于目标中断信号向对应的中断接收设备发送中断指令。本公开可以降低中断发送设备发送中断信号过程的复杂度。

Description

中断控制器、中断控制方法、芯片、计算机设备以及介质
相关公开的交叉引用
本公开要求于2021年4月29日提交的、申请号为202110473987.9的中国专利公开的优先权，该中国专利公开的全部内容以引用的方式并入本文中。
技术领域
本公开涉及计算机技术领域，具体而言，涉及一种中断控制器、中断控制方法、芯片、计算机设备以及存储介质。
背景技术
在不同应用场景中，数据传输时使用的通信协议不同。以要传输的数据包括中断信号为例，当中断发送设备向多个中断接收设备发送中断信号时，若不同的中断接收设备与中断发送设备进行通信所使用的通信协议不同，在发送中断信号时，需要中断发送设备不断的更换与不同中断接收设备进行通信的通信接口。很明显，这种方式发送中断信号过程较为复杂。
发明内容
本公开实施例至少提供一种中断控制器、中断控制方法、芯片、计算机设备以及存储介质。
第一方面，本公开实施例提供了一种中断控制器，包括：与多个中断连接设备连接的中断仲裁模块、以及分别与对应的中断接收设备连接的多个中断接口模块；多个所述中断接口模块分别与所述中断仲裁模块连接、且能够采用不同的通信协议与对应的中断接收设备进行数据传输；其中，所述中断仲裁模块，用于对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；多个所述中断接口模块，用于在作为所述目标中断接口模块时，响应于接收到所述中断仲裁模块发送的目标中断信号，基于所述目标中断信号向与所述目标中断接口模块连接的中断接收设备发送中断指令。
这样，在中断发送设备需要向中断接收设备发送中断信号时，仅需要将中断信号发送至中断控制器即可，不需要中断发送设备进行接口的切换，降低中断发送设备发送中断信号过程的复杂度。同时，可以解决单一接口模块通信灵活度不足的问题，使得应用场景多变。
一种可选的实施方式中，所述中断仲裁模块，用于：将当前接收到的中断发送设备发送的中断信号作为所述待发送中断信号，和/或，将历史中断信号中除历史目标中断信号外的其他中断信号，作为所述待发送中断信号；其中，所述历史中断信号为所述中断仲裁模块在历史数据处理周期接收到的所述中断发送设备发送的中断信号，所述历史目标中断信号为在历史数据处理周期中确定的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块在对待发送中断信号进行仲裁时，用于基于下述至少一种优先级，从所述待发送中断信号中，确定目标中断信号：所述待发送中断信号对应的第一优先级、多个所述中断接口模块分别对应的第二优先级、与所述待发送中断信号对应的中断发送设备的第三优先级。
一种可选的实施方式中，所述中断仲裁模块，在基于所述待发送中断信号对应的第一优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：从所述待发送中断信号中确定第一优先级最高的至少一个待发送中断信号，作为所述目标中断信号；或者，基于对所述多个中断接口模块的调度顺序，从所述多个中断接口模块中，确定一个或多个所述目标中断接口模块，从每个所述目标中断接口模块对应的待发送中断信号中，按所述第一优先级确定所述目标中断信号。
这样，可以保证将中断发送设备发送的所有中断信号中优先级最高的中断信号先行发送，使得中断接收设备可以先接收到较为重要的中断信号并进行处理。这样，可以在例如多任务处理的场景下，提高具备先后顺序的任务处理的安全性。或者，还可以保证多个中断接口模块对应的中断接收设备均可以接收到目标中断信号并进行数据处理，提高算力的利用率。
一种可选的实施方式中，所述中断仲裁模块，在基于多个所述中断接口模块分别对应的第二优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：基于所述多个中断接口模块分别对应的第二优先级，从所述多个中断接口模块中，确定一个或多个所述目标中断接口模块；从所述待发送中断信号中，确定与每个所述目标中断接口模块对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块，在从所述待发送中断信号中，确定与所述目标中断接口模块对应的目标中断信号时，用于：从所述待发送中断信号中，确定与所述目标中断接口模块对应的第一备选中断信号；基于所述第一备选中断信号的接收顺序、或者所述第一 备选中断信号分别对应的第一优先级，从所述第一备选中断信号中，确定所述目标中断信号。
这样，可以优先向多个中断接口模块中更重要的一个中断接口模块发送对应的目标中断信号，以使更重要的一个中断接口模块优先处理对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块，在基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号对应的中断发送设备中，确定一个或多个目标中断发送设备；从所述待发送中断信号中，确定与每个所述目标中断发送设备对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块，在从所述待发送中断信号中，确定与所述目标中断发送设备对应的目标中断信号时，用于：从所述待发送中断信号中，确定与所述目标中断发送设备对应的第二备选中断信号；基于下述至少一种，从所述第二备选中断信号中，确定所述目标中断信号：所述第二备选中断信号对应的第一优先级、所述中断接口模块分别对应的第二优先级、所述第二备选中断信号的接收顺序。
这样，可以优先向多个中断发送设备中更重要的一个中断发送设备发送对应的目标中断信号，以使更重要的一个中断发送设备优先发送对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块在对待发送中断信号进行仲裁时，用于：基于所述待发送中断信号，从多个所述中断接口模块中，确定至少两个目标中断接口模块；针对所述至少两个目标中断接口模块中的每个中断接口模块，从与该中断接口模块对应的待发送中断信号中，确定与该中断接口模块对应的目标中断信号。
这样，中断控制器还可以同时向多个中断接口模块发送对应的目标中断信号，以提高效率，并且提升了多个中断接口模块的利用率，提高了多个中断接收设备处理中断信号的算力利用率。
一种可选的实施方式中，所述中断控制器还包括：屏蔽寄存器；所述屏蔽寄存器，用于接收所述中断接收设备下发的待屏蔽中断标识；所述中断仲裁模块，在对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号时，用于：从所述屏蔽寄存器中读取所述屏蔽中断标识，并基于所述屏蔽中断标识，从所述待发送中断信号中确定与所述屏蔽中断标识对应的被屏蔽中断信号以及除所述被屏蔽中断信号以外的非屏蔽中断信号；对所述非屏蔽中断信号进行仲裁，得到所述目标中断信号。
一种可选的实施方式中，所述中断控制器，还包括悬挂寄存器；所述中断仲裁模块，还用于在从所述待发送中断信号中确定非屏蔽中断信号后，将被屏蔽中断信号存储至所述悬挂寄存器；在接收到所述中断接收设备下发的解除屏蔽中断标识后，基于所述解除屏蔽中断标识，从所述悬挂寄存器中，读取与所述解除屏蔽中断标识对应的中断信号，作为所述待发送中断信号。
一种可选的实施方式中，所述中断接口模块包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断映射寄存器堆，用于存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器，用于存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块，在基于所述目标中断信号向所述对应的中断接收设备发送中断指令时，用于基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
第二方面，本公开实施例还提供了一种中断控制器，包括：中断仲裁模块、以及高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述中断接口模块与所述中断仲裁模块连接；所述中断仲裁模块，用于对待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；所述中断接口模块，用于响应于接收到所述中断仲裁模块发送的目标中断信号，基于所述目标中断信号向与所述目标中断接口模块连接的中断接收设备发送中断指令。
一种可选的实施方式中，所述中断控制器包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断映射寄存器堆，用于存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器，用于存储所述数据地址对标识对应的数据地址对；所述数据 地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块，用于基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
第三方面，本公开实施例还提供一种中断控制方法，应用于中断控制器，所述中断控制器包括：与多个中断发送设备连接的中断仲裁模块、以及分别与对应的中断接收设备连接的多个中断接口模块；多个所述中断接口模块分别与所述中断仲裁模块连接，且能够采用不同的通信协议与所述对应的中断接收设备进行数据传输；所述中断控制方法包括：所述中断仲裁模块对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；所述中断接口模块，在作为所述目标中断接口模块时，响应于接收到所述中断仲裁模块发送的目标中断信号，基于所述目标中断信号向对应的中断接收设备发送中断指令。
一种可选的实施方式中，所述中断控制方法还包括：所述中断仲裁模块将当前接收到的中断发送设备发送的中断信号确定为所述待发送中断信号，和/或，将历史中断信号中除历史目标中断信号外的其他中断信号，作为所述待发送中断信号；其中，历史中断信号为所述中断仲裁模块在历史数据处理周期接收到的所述中断发送设备发送的中断信号，所述历史目标中断信号为在历史数据处理周期中确定的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块对待发送中断信号进行仲裁，包括基于下述至少一种优先级，从所述待发送中断信号中，确定目标中断信号：所述待发送中断信号对应的第一优先级、多个所述中断接口模块分别对应的第二优先级、与所述待发送中断信号对应的中断发送设备的第三优先级。
一种可选的实施方式中，所述中断仲裁模块基于所述待发送中断信号对应的第一优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中确定第一优先级最高的至少一个待发送中断信号，作为所述目标中断信号；或者，基于对所述多个中断接口模块的调度顺序，从所述多个中断接口模块中，确定一个或多个目标中断接口模块，从每个所述目标中断接口模块对应的待发送中断信号中，按所述第一优先级确定所述目标中断信号。
一种可选的实施方式中，所述中断仲裁模块基于多个所述中断接口模块分别对应的第二优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块基于所述多个中断接口模块分别对应的第二优先级，从所述多个中断接口模块中，确定一个或多个目标中断接口模块；从所述待发送中断信号中，确定与每个所述目标中断接口模块对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断接口模块对应的目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断接口模块对应的第一备选中断信号；基于所述第一备选中断信号的接收顺序、或者所述第一备选中断信号分别对应的第一优先级，从所述第一备选中断信号中，确定所述目标中断信号。
一种可选的实施方式中，所述中断仲裁模块基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号对应的中断发送设备中，确定一个或多个目标中断发送设备；从所述待发送中断信号中，确定与每个所述目标中断发送设备对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断发送设备对应的目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断发送设备对应的第二备选中断信号；基于下述至少一种，从所述第二备选中断信号中，确定所述目标中断信号：所述第二备选中断信号对应的第一优先级、所述中断接口模块分别对应的第二优先级、所述第二备选中断信号的接收顺序。
一种可选的实施方式中，所述中断仲裁模块对待发送中断信号进行仲裁，包括：所述中断仲裁模块基于所述待发送中断信号，从多个所述中断接口模块中，确定至少两个目标中断接口模块；针对所述至少两个目标中断接口模块中的每个中断接口模块，从与该中断接口模块对应 的待发送中断信号中，确定与该中断接口模块对应的目标中断信号。
一种可选的实施方式中，所述中断控制器还包括屏蔽寄存器。所述中断控制方法还包括：所述屏蔽寄存器接收所述中断接收设备下发的待屏蔽中断标识。相应地，所述中断仲裁模块对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，包括：所述中断仲裁模块从所述屏蔽寄存器中读取所述屏蔽中断标识，并基于所述屏蔽中断标识，从所述待发送中断信号中确定与屏蔽中断标识对应的被屏蔽中断信号以及除被屏蔽中断信号以外的非屏蔽中断信号；对所述非屏蔽中断信号进行仲裁，得到所述目标中断信号。
一种可选的实施方式中，所述中断控制器，还包括悬挂寄存器；所述中断控制方法还包括：所述中断仲裁模块在从所述待发送中断信号中确定被屏蔽中断信号后，将被屏蔽中断信号存储至所述悬挂寄存器；在接收到所述中断接收设备下发的解除屏蔽中断标识后，基于所述解除屏蔽中断标识，从所述悬挂寄存器中，读取与所述解除屏蔽中断标识对应的中断信号，作为所述待发送中断信号。
一种可选的实施方式中，所述中断接口模块包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断控制方法还包括：所述中断映射寄存器堆存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
第四方面，本公开实施例还提供一种中断控制方法，应用于中断控制器，所述中断控制器包括：中断仲裁模块、以及高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块与所述中断仲裁模块连接；所述中断控制方法包括：所述中断仲裁模块对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；所述中断接口模块在作为目标中断接口模块时，响应于接收到所述中断仲裁模块发送的目标中断信号，基于所述目标中断信号向与所述目标中断接口模块连接的中断接收设备发送中断指令。
一种可选的实施方式中，所述中断控制方法应用于所述中断控制器，所述中断控制器包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断控制方法包括：所述中断映射寄存器堆存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
第五方面，本公开可选实现方式还提供一种芯片，包括如第一方面任一项所述的中断控制器，或者如第二方面任一项所述的中断控制器。
第六方面，本公开可选实现方式还提供一种计算机设备，包括指令存储器和如第一方面或第二方面任一项所述的中断控制器，或如第五方面所述的芯片。
第七方面，本公开可选实现方式还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被运行时执行上述第三方面或第四方面中任一种可能的实施方式中的步骤。
关于上述中断控制方法、芯片、计算机设备、及计算机可读存储介质的效果描述参见上述中断控制器的说明，这里不再赘述。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单 地介绍。这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种中断控制器的示意图；
图2示出了本公开实施例所提供的一种中断控制器处理中断信号的示意图；
图3示出了本公开实施例提供的另一种中断控制器处理中断信号的示意图；
图4示出了本公开实施例提供的另一种中断控制器处理中断信号的示意图；
图5示出了本公开实施例提供的另一种中断控制器处理中断信号的示意图；
图6示出了本公开示例提供的另外一种中断控制器的示意图；
图7示出了本公开实施例提供的一种应用于PCIe的中断控制器的示意图；
图8示出了本公开示例提供的一种在中断控制器中，PCIe通信协议下的中断接口模块的示意图；
图9示出了本公开实施例提供的一种多个中断发送设备与多个中断接收设备之间中断信号传输路径的示意图；
图10示出了本公开实施例提供的一种中断控制方法的流程图；
图11示出了本公开实施例所提供的另一种中断控制方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
经研究发现，不同设备间传输数据时，需要依赖于相对应的通信协议，在传输数据的两侧设备所使用的通信协议不同时，两个设备之间将无法进行数据的传输。以中断发送设备向中断接收设备发送中断信号为例，中断发送设备通常可以使用总线传输的方式向中断接收设备发送中断信号，若不同中断接收设备与中断发送设备在进行通信时使用的通信协议不同，那么中断发送设备在向不同中断接收设备发送中断信号时，需要频繁的依据要发送的中断接收设备所使用的通信协议切换接口，造成中断信号发送的过程较为复杂。
同时，中断发送设备判断与对应中断接收设备之间的通信协议，确定通信接口，并向通信接口发送中断信号的过程，需要占用中断发送设备的计算资源。本公开实施例中，为了便于描述，将基于中断信号向中断接收设备发送中断指令的过程，简称为向中断接收设备发送中断信号。
基于上述研究，本公开提供了一种中断控制器，通过在该中断控制器中设置多个中断接口模块，并且不同的中断接口模块可以设置为采用不同的通信协议，使得中断发送设备在需要向采用不同通信协议的中断接收设备发送中断信号时，仅需要将中断信号发送至中断控制器即可，不需要中断发送设备进行接口的切换，降低中断发送设备发送中断信号过程的复杂度。
另外，由于是由中断控制器中的中断仲裁模块来确定中断信号要发往的具体中断接口模块，并利用确定出的中断接口模块将中断信号发送给对应的中断接收设备，因此不需要占用中断发送设备的计算资源。
以上均是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及下文中本公开针对上述问题所提出的解决方案，都应该是发明人在本公开过程中对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本公开实施例提供的中断控制器，可以仅与一个中断发送设备连接，这样，该中断发送设备可以使用一个专用的中断控制器向中断接收设备发送中断信号；在将一个中断发送设备与一个中断控制器进行连接时，可以将两者通过接口连接，也可以将两者通过电路连接。也可以在中断控制器上设置多个输入端口，通过多个输入端口与不同的中断发送设备连接，不同的中断发送设备可以分别将中断信号通过同一中断控制器，发送给相同或者不同的中断接收设备。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种中断控制器进行详细介绍，参见图1所示，为本公开实施例提供的中断控制器的示意图，所述中断控制器包括中断仲裁模块110、以及与中断仲裁模块110分别连接的多个中断接口模块120。
其中，中断仲裁模块110，用于对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；
中断接口模块120，用于在作为目标中断接口模块时，响应于接收到所述中断仲裁模块110发送的目标中断信号，基于所述目标中断信号向与所述目标中断接口模块连接的中断接收设备发送中断指令。
其中，多个中断接口模块120例如可以包括分别采用多个不同的通信协议的中断接口模块120，通信协议例如可以包括下述至少两种：高速串行计算机扩展总线标准(Peripheral Component Interconnect express，PCIe)协议、串行外设接口(Serial Peripheral Interface，SPI)协议、I2C总线(Inter－Integrated Circuit，I2C)协议、通用串行总线(Universal Serial Bus，USB)协议、以及以太网(Ethernet)协议。多个中断接口模块120例如包括：PCIe接口、SPI接口、I2C接口、USB接口、以太网接口中的至少两种。为了便于描述，将采用某一通信协议的中断接口模块120称为该通信协议对应的中断接口模块120。
此处，多个对应任一通信协议的中断信号可以通过该通信协议对应的中断接口模块进行传输。因此任一通信协议对应一个中断接口模块即可，而无需为一个通信协议设置对应的多个中断接口模块120。示例性的，在图1中，示出了PCIe通信协议对应的中断接口模块120-0、SPI通信协议对应的中断接口模块120-1、以及I2C通信协议对应的中断接口模块120-2。在另一种可行的实现方式中，如果存在大量对应同一种通信协议的中断信号，可以为此种通信协议设置至少两个中断接口模块120，以避免可能出现的中断信号传输拥塞。与一个通信协议对应的中断接口模块120的数量可以由本领域技术人员根据实际情况进行设置，本公开实施例不做具体限定。
具体地，待发送中断信号例如可以包括中断仲裁模块110当前接收到的、中断发送设备发送的中断信号。中断发送设备在向中断仲裁模块110发送中断信号时，可以根据实际情况，按照自身的数据处理周期或者数据处理时序，有序的逐一向中断控制器中的中断仲裁模块110发送中断信号，或者在一个数据处理周期或数据处理时序的一个时间片中向中断仲裁模块110发送多个中断信号。
中断仲裁模块110在确定待发送中断信号时，例如可以采用下述方式：将当前接收到的、中断发送设备发送的中断信号确定为待发送中断信号，和/或将历史中断信号中除历史目标中断信号外的中断信号，作为待发送中断信号。
在具体实施中，在第一个仲裁周期，也即首次接收到由中断发送设备发送的中断信号的仲裁周期，由于该中断信号是新接收的，因此可以将由中断仲裁模块110新接收到的中断信号均作为待发送中断信号，中断发送设备发送的中断信号例如可以包括中断信号a、中断信号b、……、中断信号i、以及中断信号j。
另外，中断发送设备发送的中断信号例如可以包括对应N种不同通信协议的中断信号(以下也可简称为N种中断信号)，每种中断信号又可以包括M(N、M均为正整数)个中断信号，不同种类的中断信号的数量可以相同，也可以不同。
在除第一个仲裁周期外的其他仲裁周期，也即非首次接收到由中断发送设备发送的中断信号的仲裁周期，由于可能存在中断发送设备在历史数据处理周期发送给中断控制器的中断信号，并且这些中断信号并未在历史数据处理周期中发送给对应的中断接收设备，因此，在确定待发送中断信号时，还要将中断发送设备在历史数据处理周期中发送的历史中断信号中，除历史目标中断信号外的其他中断信号也确定为待发送中断信号，其中历史目标中断信号为在历史数据处理周期中确定并完成发送的目标中断信号。
另外，作为待发送中断信号的历史中断信号，例如可以包括：在历史数据处理周期中，被屏蔽的，但在当前数据处理周期中被取消屏蔽的中断信号。具体的，可以参见下文的详细描述，在此不再赘述。还可以包括：在当前数据处理周期被中断发送设备发送给中断仲裁模块110，但是在之前的仲裁周期由于未被确定为目标中断信号而未被发送给中断接收设备的中断信号。本公开实施例中，中断控制器可以包括状态寄存器，状态寄存器用于保存中断信号的状态信息。中断控制器可以根据需要查询或清除状态寄存器中保存的信息。
中断仲裁模块110在对待发送中断信号进行仲裁时，例如可以基于下述至少一种优先级， 从待发送中断信号中，确定目标中断信号：待发送中断信号对应的第一优先级、多个中断接口模块120分别对应的第二优先级、与待发送中断信号对应的中断发送设备的第三优先级。
在具体实施中，中断仲裁模块110在从待发送中断信号中确定目标中断信号时，例如可以采用下述方式(A)、(B)、以及(C)中至少一种：
(A)：中断仲裁模块110基于待发送中断信号对应的第一优先级，从待发送中断信号中，确定目标中断信号。
具体地，在中断仲裁模块110利用第一优先级确定目标中断信号时，可以采用下述方式(A1)或者(A2)：
(A1)：基于待发送中断信号对应的第一优先级，从待发送中断信号中确定第一优先级最高的至少一个待发送中断信号，作为目标中断信号。
其中，第一优先级可以预先确定，例如为中断信号a确定对应第一优先级0、为中断信号b确定对应第一优先级1、……、以及为中断信号j确定对应第一优先级9，并确定优先级由低到高的顺序为第一优先级0、第一优先级1、第一优先级2、……、第一优先级9，也即第一优先级0的优先级最低，第一优先级9的优先级最高。此时，对于第一优先级不同的中断信号，中断仲裁模块110可以依据其对应的第一优先级，确定向中断接口模块120发送的目标中断信号。
在一种可能的实施方式中，中断仲裁模块110可以接收到多个第一优先级不同的中断信号，例如同时接收到中断信号a～中断信号c。此时，由于中断信号c的第一优先级更高，因此中断仲裁模块110先将中断信号c作为目标中断信号，并将中断信号c对应的中断接口模块120作为目标中断接口模块，例如为中断接口模块120-0，然后将中断信号c发送至中断接口模块120-0。
参见图2所示，为本公开实施例提供的一种中断控制器处理中断信号的示意图，中断仲裁模块110在接收到中断发送设备200-2发送的中断信号a、中断发送设备200-1发送的中断信号b、以及中断发送设备200-0发送的中断信号c后，将中断信号c作为目标中断信号发送给中断信号c对应的中断接口模块120-0中。此处，可以保证将中断发送设备发送的所有中断信号中优先级最高的中断信号先行发送，使得中断接收设备可以先接收到较为重要的中断信号并进行处理。这样，可以在例如多任务处理的场景下，通过为需要优先处理的任务设置较高等级的优先级，并为其他需要处理的任务设置等级较低的优先级。这样，能够保证优先处理较为重要的任务。
在另一种可能的实施方式中，中断仲裁模块110还可能接收到多个第一优先级相同的中断信号，此时，由于中断信号的接收有在时间上的先后顺序，因此在存在多个第一优先级相同的中断信号时，可以按照接收到中断信号的时间顺序确定目标中断信号，例如，确定接收较早的中断信号为目标中断信号。
(A2)：基于对多个中断接口模块120的调度顺序，从多个中断接口模块120中，确定一个或多个目标中断接口模块120，从目标中断接口模块120对应的待发送中断信号中，确定第一优先级最高的中断信号作为目标中断信号。
示例性的，参见图3所示，为本公开实施例提供的另一种中断控制器处理中断信号的示意图。其中，多个中断接口模块120可以包括中断接口模块120-0、中断接口模块120-1、以及中断接口模块120-2。向每个中断接口模块120发送的中断信号分别包括：向中断接口模块120-0发送中断信号h、中断信号i、以及中断信号j；向中断接口模块120-1发送中断信号e、中断信号f、以及中断信号g；向中断接口模块120-2发送中断信号a、中断信号b、中断信号c、以及中断信号d。
多个中断接口模块120的调度顺序，例如可以根据多个中断接口模块120分别对应的各个中断接收设备的重要性程度确定。示例性的，在中断接口模块120-0、中断接口模块120-1、以及中断接口模块120-2分别对应的中断接收设备300-0、中断接收设备300-1、中断接收设备300-2中，中断接收设备300-2承担较为重要的数据处理任务，而中断接收设备300-0承担最简单的数据处理任务时，可以确定三个中断接口模块120的调度顺序为中断接口模块120-2→中断接口模块120-1→中断接口模块120-0。在利用多个中断接口模块120的调度顺序确定目标中断接口模块时，由于中断接口模块120-2的调度顺序为最先，因此先将中断接口模块120-2作为目标中断接口模块。并且，还可以确定中断接口模块120-2对应的待发送中断信号，也即中断信号a、中断信号b、中断信号c、以及中断信号d，并将其中第一优先级最高的中断信号，也即中断信号d，确定为目标中断信号。
然后，即可以将中断信号d作为目标中断信号，并利用中断接口模块120-2发送至中断接 收设备300-2中。
此处，参见图3所示，中断接收设备300-2接收到中断信号d，也即图3中①表示的发送过程。
在一种可能的实施方式中，在利用中断接口模块120-2完成对中断接口模块120-2对应的目标中断信号的发送后，中断仲裁模块110还可以继续依据中断接口模块120的调度顺序进行轮询，也即将中断接口模块120-1确定为目标中断接口模块，并确定中断接口模块120-1对应的多个中断信号中的目标中断信号。
同样的，对于中断接口模块120-1对应的多个待发送中断信号，也即中断信号e、中断信号f、以及中断信号g，可以确定其中第一优先级最高的中断信号g作为目标中断信号，并利用中断接口模块120-1将其发送至中断接收设备300-1中；接着，对于中断接口模块120-0对应的多个待发送中断信号，也即中断信号h、中断信号i、中断信号j，可以确定其中第一优先级最高的中断信号j作为目标中断信号，并利用中断接口模块120-0将其发送至中断接收设备300-0中。
参见图3所示，其中①表示的发送过程对应中断接收设备300-2最先接收到中断信号d，②表示的发送过程对应中断接收设备300-1接着接收到中断信号g，③表示的发送过程对应中断接收设备300-0最后接收到中断信号j。
在另一种可能的实施方式中，在中断接口模块120-2发送与其对应的目标中断信号后，还可能存在新的中断信号向中断接口模块120-1和/或中断接口模块120-0发送，则在分别确定向中断接口模块120-1和中断接口模块120-0发送的目标中断信号时，可以根据接收到的所有待发送中断信号确定目标中断信号。
利用这种方式，可以根据多个中断接口模块120的调度顺序，确定多个中断接口模块120的重要程度，并以轮询的方式向多个中断接口模块120依次发送对应的最高优先级的中断信号，使多个中断接口模块120中较为重要的中断接口模块120可以先接收到对应的目标中断信号，然后其他中断接口模块120可以同样依照重要性程度接收到对应的目标中断信号；另外，还可以保证多个中断接口模块120对应的中断接收设备300均可以接收到目标中断信号并进行数据处理，提高多个中断接口模块120的利用率，并提高多个中断接收设备300处理中断信号的算力利用率。
(B)：中断仲裁模块110基于多个中断接口模块120分别对应的第二优先级，从待发送中断信号中，确定目标中断信号。
在具体实施中，当中断仲裁模块110利用第二优先级确定目标中断信号时，可以基于多个中断接口模块120分别对应的第二优先级，从多个中断接口模块120中，确定一个或多个目标中断接口模块120；从待发送中断信号中，确定与每个目标中断接口模块120对应的目标中断信号。
其中，第二优先级可以预先确定，例如为中断接口模块120-0确定对应第二优先级0、为中断接口模块120-1确定对应第二优先级1、为中断接口模块120-2确定对应第二优先级2，也即优先级最高的中断接口模块为中断接口模块120-2，其次为中断接口模块120-1，优先级最低的中断接口模块为中断接口模块120-0。
以图3所示的向多个中断接口模块120发送中断信号的对应关系为例，在多个中断接口模块120包括中断接口模块120-0～中断接口模块120-2时，可以确定优先级最高的为第二优先级2，对应的中断接口模块为中断接口模块120-2，并将其确定为目标中断接口模块。
然后，再从多个待发送中断信号中，确定与目标中断接口模块对应的目标中断信号。
具体地，可以根据下述方式确定目标中断接口模块对应的目标中断信号：从待发送中断信号中，确定与目标中断接口模块对应的第一备选中断信号；基于第一备选中断信号的接收顺序、或者第一备选中断信号分别对应的第一优先级，从第一备选中断信号中，确定目标中断信号。
仍以图3所示的向多个中断接口模块120发送中断信号的对应关系为例，待发送中断信号包括中断信号a～中断信号j，确定的与目标中断接口模块120-2对应的第一备选中断信号，例如可以包括中断发送设备200-2发送的多个中断信号：中断信号a、中断信号b、中断信号c、以及中断信号d。本公开实施例中，第一备选中断信号可以是待发送中断信号中需目标中断接口模块传输的所有中断信号，或部分中断信号。其中，部分中断信号例如为需传输至与目标中断接口模块连接的特定中断接收设备的中断信号。
在从第一备选中断信号中确定目标中断信号时，例如可以采用下述方式(B1)或(B2)中的任一种：
(B1)：依据第一备选中断信号的接收顺序，从第一备选中断信号中确定目标中断信号。示例性的，第一备选中断信号的接收顺序可以为中断信号a→中断信号b→中断信号c→中断信号d。此时，可以将先接收到的中断信号a作为目标中断信号。这样，可以保证先将多个第一备选中断信号中较先被中断仲裁模块110接收的中断信号发送到中断接收设备进行处理，防止滞留。
参见图4所示，为本公开实施例提供的另一种中断控制器处理中断信号的示意图。在图4中，中断发送设备200-2依次向中断仲裁模块110发送中断信号a～中断信号d，中断仲裁模块110依据第一备选中断信号的接收顺序，确定目标中断信号为中断信号a，并将中断信号a发送至与中断信号a对应的中断接收设备300-2中。
(B2)：依据第一备选中断信号分别对应的第一优先级，从第一备选中断信号中确定目标中断信号。
此处，与上述(A1)相似，第一备选中断信号对应的第一优先级包括：中断信号a对应第一优先级0、中断信号b对应第一优先级1、中断信号c对应第一优先级2、中断信号d对应第一优先级3。在这种情况下，可以确定优先级最高的第一优先级，也即优先级3，并将其对应的中断信号d作为目标中断信号。
(C)：中断仲裁模块110基于待发送中断信号对应的中断发送设备的第三优先级，从待发送中断信号中，确定目标中断信号。
在具体实施中，当中断仲裁模块110利用第三优先级确定目标中断信号时，可以基于待发送中断信号对应的中断发送设备的第三优先级，从待发送中断信号对应的中断发送设备中，确定一个或多个目标中断发送设备；从待发送中断信号中，确定与每个目标中断发送设备对应的目标中断信号。
第三优先级可以预先确定，例如包括为中断发送设备200-0确定对应第三优先级0、为中断发送设备200-1确定对应第三优先级1、为中断发送设备200-2确定对应第三优先级2。则在中断发送设备200-0～中断发送设备200-2中，最高的优先级为第三优先级2，对应的中断发送设备为中断发送设备200-2。此时，即可以确定中断发送设备200-2为目标中断发送设备。
然后，即可以根据目标中断发送设备确定对应的目标中断信号。
具体地，可以采用下述方式确定目标中断信号：从待发送中断信号中，确定与目标中断发送设备对应的第二备选中断信号；基于下述至少一种，从第二备选中断信号中，确定目标中断信号：第二备选中断信号对应的第一优先级、中断接口模块120分别对应的第二优先级、第二备选中断信号的接收顺序。
以图4所示的示意图为例，中断仲裁模块110例如可以接收中断发送设备200-2发送的中断信号a～中断信号d。在从待发送中断信号中确定第二备选中断信号时，可以将目标中断发送设备，也即中断发送设备200-2，对应的中断信号a～中断信号d作为第二备选中断信号。在从第二备选中断信号中确定目标中断信号时，例如可以采用下述方式(C1)、(C2)、(C3)中的至少一种：
(C1)：依据第二备选中断信号对应的第一优先级，从第二备选中断信号中确定目标中断信号。此处，利用第一优先级从第二备选中断信号中，即从中断信号a～中断信号d中确定目标中断信号的方式，与上述(A1)以及(A2)的方式相似，在此不再赘述。
(C2)：依据中断接口模块120分别对应的第二优先级，从第二备选中断信号中确定目标中断信号。此处，利用第二优先级从第二备选中断信号中，即从中断信号a～中断信号d中确定目标中断信号的方式，与上述(B)中确定目标中断信号的方式相似，这里同样不再赘述。
(C3)、依据第二备选中断信号的接收顺序，从第二备选中断信号中确定目标中断信号。此处，利用接收顺序从第二备选中断信号中，即从中断信号a～中断信号d中确定目标中断信号的方式，与上述确定(B1)中确定目标中断信号的方式相似，这里同样不再赘述。
这样，可以根据中断发送设备的优先级，确定需要优先发送中断信号的中断发送设备200或者选取出较为重要的中断发送设备200，并将其对应的中断信号作为第二备选中断信号，以使中断仲裁模块110可以优先将较为重要的目标中断信号先发送至对应的中断接口模块120。
在另一种可选的实施方式中，还可以存在中断仲裁模块110确定同时向多个中断接口模块120发送对应的目标中断信号的情况。
具体地，中断仲裁模块110可以根据下述方式进行仲裁：基于待发送中断信号，从多个中断接口模块120中，确定至少两个目标中断接口模块120；针对至少两个目标中断接口模块120 中的每个中断接口模块120，从与该中断接口模块120对应的待发送中断信号中，确定与该中断接口模块120对应的目标中断信号。
参见图5所示，为本公开实施例提供的另一种中断控制器处理中断信号的示意图。在图5中，在中断接口模块120-0对应第一优先级0、中断接口模块120-1对应第一优先级1、中断接口模块120-2对应第一优先级2时，虽然优先级最高的中断接口模块为中断接口模块120-2，但是中断发送设备200-2并未发送中断信号，即中断接口模块120-2无对应的中断信号，因此不向中断接口模块120-2发送中断信号。
另外，对于中断接口模块120-0以及中断接口模块120-1，因为均存在有对应的中断信号，因此将这两个中断接口模块120均作为目标中断接口模块。
示例性的，在向中断接口模块120-0发送中断信号时，例如可以依照上述(A1)相似的方式确定向其发送的目标中断信号，也即中断信号d；同时，还可以确定向中断接口模块120-1发送的目标中断信号，也即中断信号g。在另一种可能的实施方式中，中断仲裁模块110可以基于待发送中断信号对应的第一优先级、多个中断接口模块120分别对应的第二优先级、待发送中断信号对应的中断发送设备200的第三优先级中的至少一种，确定至少两个目标中断接口模块。例如，在基于待发送中断信号对应的第一优先级确定至少两个目标中断接口模块时，中断仲裁模块110可以在待发送中断信号中确定第一优先级最高和次高的中断信号，然后将用于传输这两个中断信号的中断接口模块120作为目标中断接口模块。中断仲裁模块110确定至少两个目标中断接口模块的具体处理过程，与上述方式(A)、(B)、以及(C)的方案类似，在此不再赘述。
在另一种可能的实施方式中，中断接收设备还可以向中断控制器下发屏蔽中断标识，例如在图像数据处理的过程中，在某一待处理图像数据过大时，可能在预设的处理时间中无法完成对此待处理图像数据的处理，因此中断接收设备可以向中断控制器下发屏蔽中断标识，被屏蔽的中断对应的任务例如包括发送新的待处理图像数据。这样，中断接收设备可以先不接收新的待处理图像数据，而是将正在处理的图像数据处理结束后，再向中断控制器发送解除屏蔽中断标识，以保证重新接收新的待处理图像数据，从而保证中断接收设备不会有堆积的待处理图像数据，防止从对应的寄存器中溢出导致的数据丢失，并且减少数据混杂导致的错误。
在具体实施中，参见图6所示，本公开示例还提供另外一种中断控制器，包括屏蔽寄存器130，在中断接收设备300下发屏蔽中断标识时，可以由屏蔽寄存器130接收此屏蔽中断标识。屏蔽寄存器130接收屏蔽中断标识后，中断仲裁模块110可以从屏蔽寄存器130中读取屏蔽中断标识，并基于屏蔽中断标识，对待发送中断信号进行仲裁，得到目标中断信号。
以中断控制器接收中断发送设备200-0向中断接收设备300-0发送中断信号a～中断信号e为例进行说明。中断接收设备300-0向中断控制器下发屏蔽中断标识，可以对应一个中断信号，例如中断信号a；或者对应多个中断信号，例如中断信号d和中断信号e。
在中断接收设备300-0向中断控制器下发屏蔽中断标识后，由中断控制器中的屏蔽寄存器130接收此屏蔽中断标识，然后，中断仲裁模块110从屏蔽寄存器130中读取屏蔽中断标识，从待发送中断信号中确定与屏蔽中断表示对应的被屏蔽中断信号以及除被屏蔽中断信号以外的非屏蔽中断信号。
示例性的，在屏蔽中断标识对应的中断信号包括中断信号a时，中断仲裁模块110从待发送中断信号包括的中断信号a～中断信号e中确定非屏蔽中断信号，包括中断信号b～中断信号e，再对非屏蔽中断信号进行仲裁得到目标中断信号。
在屏蔽中断标识对应的中断信号包括中断信号e和中断信号f时，由于待发送中断信号中仅包括中断信号a～中断信号e，而不包括中断信号f，因此中断仲裁模块110确定的非屏蔽中断信号包括中断信号a～中断信号d，然后再对非屏蔽中断信号进行仲裁得到目标中断信号。
此处，中断仲裁模块110对所述非屏蔽中断信号进行仲裁，得到所述目标中断信号的方式，与上述(A)、(B)、以及(C)中中断仲裁模块110确定目标中断信号的方式相似，在此不再赘述。
另外，在中断控制器中，还可以包括悬挂寄存器140，用于存储被屏蔽中断信号。具言之，在中断仲裁模块110从待发送中断信号中确定被屏蔽中断信号后，可以将被屏蔽中断信号存储至悬挂寄存器140。此时，悬挂寄存器140中保留被屏蔽中断信号，直至屏蔽寄存器130接收到中断接收设备下发的解除屏蔽中断标识，中断仲裁模块110从屏蔽寄存器130处获取解除中断屏蔽标识并基于此解除屏蔽中断标识，从悬挂寄存器140中，得到与解除屏蔽中断标识对应 的中断信号，作为待发送中断信号。不同的通信协议可以对应于不同的悬挂寄存器140，例如可以为某一通信协议设置专用的寄存器，例如在通信协议包括PCIe时，可以设置挂起寄位数组(Pending Bit Array，PBA)作为PCIe对应的悬挂寄存器。
本公开实施例中还提供了一种应用于高速串行计算机扩展总线标准PCIe的中断控制器。
参见图7所示，为本公开实施例提供的一种应用于PCIe的中断控制器，包括：中断仲裁模块710、以及高速串行计算机扩展总线标准PCIe对应的中断接口模块720；中断接口模块720与中断仲裁模块710连接；其中，
中断仲裁模块710，用于对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；
PCIe对应的中断接口模块720，用于在作为目标中断接口模块时，响应于接收到中断仲裁模块710发送的目标中断信号，基于目标中断信号向与目标中断接口模块连接的中断接收设备发送中断指令。
具体地，PCIe对应的中断接口模块720还可以包括数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆。
其中，中断映射寄存器堆，用于存储中断信号和数据地址对标识之间的映射关系信息；
报文信号中断表寄存器，用于存储数据地址对标识对应的数据地址对；数据地址对中包括：指令、以及指令指示的处理数据寄存器地址；
数据包整合模块，在基于目标中断信号向与目标中断接口模块连接的中断接收设备发送中断指令时，用于基于接收到的目标中断信号，从中断映射寄存器堆中确定与目标中断信号对应的目标数据地址对标识；利用目标数据地址对标识，从报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对目标数据地址对进行整合，生成中断数据包，并向中断接口模块对应的中断接收设备发送中断数据包。
参见图8所示，为本公开实施例提供的一种在中断控制器中，PCIe通信协议下的中断接口模块720的示意图。在图8中，PCIe通信协议下的中断接口模块720包括数据包整合模块810、报文信号中断表寄存器(Message Signaled Interrupt-X Table RAM，MSI-X Table RAM)820、以及中断映射寄存器堆830。
中断接收设备可以向中断映射寄存器堆830下发中断信号和数据地址对(pair)标识之间的映射关系信息，例如可以包括中断信号a对应pair0、中断信号b对应pair1、以及中断信号c对应pair2。另外，还可以向报文信号中断表寄存器820下发数据地址对标识对应的数据地址对，例如包括pair0对应的数据地址对：0X00-ABC、pair1对应的数据地址对：0X01-DEF、pair2对应的数据地址对：0X02-XYZ。其中，数据地址对中包括指令、以及指令指示的待处理数据的寄存器地址，例如ABC、DEF、XYZ可以对应不同的指令，0X00、0X01、以及0X02例如可以对应指令指示的待处理数据的寄存器地址。
在中断接口模块720接收到目标中断信号后，数据包整合模块810基于接收到的目标中断信号，例如中断信号a，从中断映射寄存器堆830中确定与目标中断信号对应的目标数据地址对标识，例如为pair0；利用目标数据地址对标识pair0，从报文信号中断表寄存器820中，读取目标数据地址对0X00-ABC；利用PCIe对目标数据地址对进行整合，例如添加报头信息，然后生成中断数据包，并向中断接口模块720对应的中断接收设备发送中断数据包。
本公开另一实施例中，还提供一种多个中断发送设备向多个中断接收设备发送中断信号的示例。参见图9所示，为本公开实施例提供的一种多个中断发送设备与多个中断接收设备之间中断信号传输路径的示意图。在图9中，包括三个中断接收设备，分别为中断接收设备300-0、中断接收设备300-1、以及中断接收设备300-2；还包括三个中断发送设备，分别为中断发送设备200-0、中断发送设备200-1、中断发送设备200-2。在每个中断发送设备中，均包含有对应的一个中断控制器，包括中断控制器100-0～中断控制器100-2，每个中断发送设备与其内部的中断控制器一体设置。由于每个中断控制器中包含有与中断接收设备300-0～中断接收设备300-2使用的通信协议对应的中断接口模块，因此任一中断发送设备200可以将一个中断信号发送至中断接收设备300-0～中断接收设备300-2中的任一个。另外，在完成对一个中断信号的发送后，再对下一个中断信号进行发送时，中断发送设备200可以选择与前一个中断信号相同的中断接收设备300，或者与前一个中断信号不同的中断接收设备300。具体通过中断控制器向不同中断接收设备300发送中断信号的过程参见上述任一通过中断控制器发送目标中断信号的实施例，在此不再赘述。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于同一发明构思，本公开实施例中还提供了与中断控制器对应的中断控制方法，由于本公开实施例中的中断控制方法解决问题的原理与本公开实施例上述中断控制器相似，因此中断控制方法的实施可以参见中断控制器的实施，重复之处不再赘述。
参照图10所示，为本公开实施例提供的一种中断控制方法的流程图，应用于中断控制器，所述中断控制器包括：与多个中断发送设备连接的中断仲裁模块、以及分别与对应的中断接收设备连接的多个中断接口模块；多个中断接口模块分别与中断仲裁模块连接，且能够采用不同的通信协议与对应的中断接收设备进行数据传输；中断控制方法包括：
S1001：中断仲裁模块对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；
S1002：中断接口模块，在作为目标中断接口模块时，响应于接收到中断仲裁模块发送的目标中断信号，基于目标中断信号向对应的中断接收设备发送中断指令。
一种可选的实施方式中，所述中断控制方法还包括：所述中断仲裁模块将当前接收到的中断发送设备发送的中断信号确定作为所述待发送中断信号，和/或，将历史中断信号中除历史目标中断信号外的中断信号，作为所述待发送中断信号；其中，历史中断信号为所述中断仲裁模块在历史数据处理周期接收到的所述中断发送设备发送的中断信号，所述历史目标中断信号为在历史数据处理周期中确定的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块对待发送中断信号进行仲裁，包括基于下述至少一种优先级，从所述待发送中断信号中，确定目标中断信号：所述待发送中断信号对应的第一优先级、多个所述中断接口模块分别对应的第二优先级、与所述待发送中断信号对应的中断发送设备的第三优先级。
一种可选的实施方式中，所述中断仲裁模块基于所述待发送中断信号对应的第一优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中确定第一优先级最高的至少一个待发送中断信号，作为所述目标中断信号；或者，基于对所述多个中断接口模块的调度顺序，从所述多个中断接口模块中，确定一个或多个目标中断接口模块，从每个所述目标中断接口模块对应的待发送中断信号中，按所述第一优先级确定所述目标中断信号。
一种可选的实施方式中，所述中断仲裁模块基于多个所述中断接口模块分别对应的第二优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块基于所述多个中断接口模块分别对应的第二优先级，从所述多个中断接口模块中，确定一个或多个目标中断接口模块；从所述待发送中断信号中，确定与每个所述目标中断接口模块对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断接口模块对应的目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断接口模块对应的第一备选中断信号；基于所述第一备选中断信号的接收顺序、或者所述第一备选中断信号分别对应的第一优先级，从所述第一备选中断信号中，确定所述目标中断信号。
一种可选的实施方式中，所述中断仲裁模块基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号中，确定所述目标中断信号，包括：所述中断仲裁模块基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号对应的中断发送设备中，确定一个或多个目标中断发送设备；从所述待发送中断信号中，确定与每个所述目标中断发送设备对应的目标中断信号。
一种可选的实施方式中，所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断发送设备对应的目标中断信号，包括：所述中断仲裁模块从所述待发送中断信号中，确定与所述目标中断发送设备对应的第二备选中断信号；基于所述第二备选中断信号对应的第一优先级、所述中断接口模块分别对应的第二优先级、所述第二备选中断信号的接收顺序中至少一种，从所述第二备选中断信号中，确定所述目标中断信号。
一种可选的实施方式中，所述中断仲裁模块对待发送中断信号进行仲裁，包括：所述中断仲裁模块基于所述待发送中断信号，从多个所述中断接口模块中，确定至少两个目标中断接口 模块；针对所述至少两个目标中断接口模块中的每个中断接口模块，从与该中断接口模块对应的待发送中断信号中，确定与该中断接口模块对应的目标中断信号。
一种可选的实施方式中，所述中断控制器还包括：屏蔽寄存器；所述中断控制方法还包括：所述屏蔽寄存器接收所述中断接收设备下发的屏蔽中断标识。相应地，所述中断仲裁模块对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，包括：所述中断仲裁模块从所述屏蔽寄存器中读取所述屏蔽中断标识，并基于所述屏蔽中断标识，从所述待发送中断信号中确定与屏蔽中断标识对应的被屏蔽中断信号以及除被屏蔽中断信号以外的非屏蔽中断信号；对所述非屏蔽中断信号进行仲裁，得到所述目标中断信号。
一种可选的实施方式中，所述中断控制器，还包括：悬挂寄存器；所述中断控制方法还包括：所述中断仲裁模块在从所述待发送中断信号中确定被屏蔽中断信号后，将被屏蔽中断信号存储至所述悬挂寄存器；在接收到所述中断接收设备下发的解除屏蔽中断标识后，基于所述解除屏蔽中断标识，从所述悬挂寄存器中，读取与所述解除屏蔽中断标识对应的中断信号，作为所述待发送中断信号。
一种可选的实施方式中，所述中断接口模块包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断控制方法还包括：所述中断映射寄存器堆存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
参见图11所示，为本公开实施例提供的另一种中断控制方法的流程图，应用于中断控制器，所述中断控制器包括：中断仲裁模块、以及高速串行计算机扩展总线标准PCIe对应的中断接口模块；中断接口模块与中断仲裁模块连接；中断控制方法包括：
S1101：中断仲裁模块对来自中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送目标中断信号；
S1102：中断接口模块在作为目标中断接口模块时，响应于接收到中断仲裁模块发送的目标中断信号，基于目标中断信号向与目标中断接口模块连接的中断接收设备发送中断指令。
一种可选的实施方式中，所述中断控制方法应用于所述中断控制器，所述中断控制器包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；所述中断控制方法包括：所述中断映射寄存器堆存储中断信号和数据地址对标识之间的映射关系信息；所述报文信号中断表寄存器存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；所述数据包整合模块基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
本公开实施例还提供了一种芯片，包括如本公开任一实施例所述的中断控制器。
本公开实施例还提供了一种计算机设备，包括指令存储器和上述任一实施例所述的中断控制器，或如本公开实施例所述的芯片。
本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的中断控制方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的中断控制方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (16)

  1. 一种中断控制器，其特征在于，包括：
    中断仲裁模块，与多个中断发送设备连接，用于对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送所述目标中断信号；
    多个中断接口模块，分别与所述中断仲裁模块连接，且分别与对应的中断接收设备连接，用于在作为所述目标中断接口模块时，响应于接收到所述中断仲裁模块发送的所述目标中断信号，基于所述目标中断信号向所述对应的中断接收设备发送中断指令，
    其中，所述多个中断接口模块能够采用不同的通信协议与所述对应的中断接收设备进行数据传输。
  2. 根据权利要求1所述的中断控制器，其特征在于，所述待发送中断信号包括：
    所述中断仲裁模块当前接收到的所述中断发送设备发送的中断信号，和/或
    历史中断信号中除历史目标中断信号外的其他中断信号，其中，所述历史中断信号为所述中断仲裁模块在历史数据处理周期接收到的所述中断发送设备发送的中断信号，所述历史目标中断信号为在所述历史数据处理周期中确定的目标中断信号。
  3. 根据权利要求1或2所述的中断控制器，其特征在于，所述中断仲裁模块在对所述待发送中断信号进行仲裁时，基于下述至少一种优先级，从所述待发送中断信号中，确定所述目标中断信号：
    所述待发送中断信号对应的第一优先级、
    多个所述中断接口模块分别对应的第二优先级、
    与所述待发送中断信号对应的中断发送设备的第三优先级。
  4. 根据权利要求3所述的中断控制器，其特征在于，所述中断仲裁模块，在基于所述待发送中断信号对应的第一优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：
    从所述待发送中断信号中确定第一优先级最高的至少一个待发送中断信号，作为所述目标中断信号。
  5. 根据权利要求3所述的中断控制器，其特征在于，所述中断仲裁模块，在基于所述待发送中断信号对应的第一优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：
    基于对所述多个中断接口模块的调度顺序，从所述多个中断接口模块中，确定一个或多个目标中断接口模块；
    针对每个所述目标中断接口模块，从所述目标中断接口模块对应的待发送中断信号中，按所述第一优先级确定所述目标中断信号。
  6. 根据权利要求3所述的中断控制器，其特征在于，所述中断仲裁模块，在基于多个所述中断接口模块分别对应的第二优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：
    基于多个所述中断接口模块分别对应的第二优先级，从多个所述中断接口模块中，确定一个或多个目标中断接口模块；
    针对每个所述目标中断接口模块，从所述待发送中断信号中，确定与所述目标中断接口模块对应的目标中断信号。
  7. 根据权利要求6所述的中断控制器，其特征在于，所述中断仲裁模块，在从所述待发送中断信号中，确定与所述目标中断接口模块对应的目标中断信号时，用于：
    从所述待发送中断信号中，确定与所述目标中断接口模块对应的第一备选中断信号；
    基于所述第一备选中断信号的接收顺序、或者所述第一备选中断信号分别对应的第一优先级，从所述第一备选中断信号中，确定所述目标中断信号。
  8. 根据权利要求3所述的中断控制器，其特征在于，所述中断仲裁模块，在基于 所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号中，确定所述目标中断信号时，用于：
    基于所述待发送中断信号对应的中断发送设备的第三优先级，从所述待发送中断信号对应的中断发送设备中，确定一个或多个目标中断发送设备；
    针对每个所述目标中断发送设备，从所述待发送中断信号中，确定与所述目标中断发送设备对应的目标中断信号。
  9. 根据权利要求8所述的中断控制器，其特征在于，所述中断仲裁模块，在从所述待发送中断信号中，确定与所述目标中断发送设备对应的目标中断信号时，用于：
    从所述待发送中断信号中，确定与所述目标中断发送设备对应的第二备选中断信号；
    基于所述第二备选中断信号对应的第一优先级、所述中断接口模块分别对应的第二优先级、所述第二备选中断信号的接收顺序中至少一种，从所述第二备选中断信号中，确定所述目标中断信号。
  10. 根据权利要求1至9任一项所述的中断控制器，其特征在于，
    所述中断控制器还包括屏蔽寄存器，用于接收所述中断接收设备下发的屏蔽中断标识；
    所述中断仲裁模块，在对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号时，用于：
    从所述屏蔽寄存器中读取所述屏蔽中断标识，并
    基于所述屏蔽中断标识，从所述待发送中断信号中确定与所述屏蔽中断标识对应的被屏蔽中断信号以及除所述被屏蔽中断信号以外的非屏蔽中断信号；
    对所述非屏蔽中断信号进行仲裁，得到所述目标中断信号。
  11. 根据权利要求10所述的中断控制器，其特征在于，
    所述中断控制器还包括悬挂寄存器，用于存储所述被屏蔽中断信号；
    所述中断仲裁模块，还用于：在接收到所述中断接收设备下发的解除屏蔽中断标识后，基于所述解除屏蔽中断标识，从所述悬挂寄存器中，读取与所述解除屏蔽中断标识对应的中断信号，作为所述待发送中断信号。
  12. 根据权利要求1至11任一项所述的中断控制器，其特征在于，所述中断接口模块包括高速串行计算机扩展总线标准PCIe对应的中断接口模块；
    所述PCIe对应的中断接口模块包括：数据包整合模块、报文信号中断表寄存器、以及中断映射寄存器堆；
    所述中断映射寄存器堆，用于存储中断信号和数据地址对标识之间的映射关系信息；
    所述报文信号中断表寄存器，用于存储所述数据地址对标识对应的数据地址对；所述数据地址对中包括：指令、以及所述指令指示的处理数据寄存器地址；
    所述数据包整合模块，在基于所述目标中断信号向所述对应的中断接收设备发送中断指令时，用于基于接收到的目标中断信号，从所述中断映射寄存器堆中确定与所述目标中断信号对应的目标数据地址对标识；利用所述目标数据地址对标识，从所述报文信号中断表寄存器中，读取目标数据地址对；利用PCIe对所述目标数据地址对进行整合，生成中断数据包，并向所述目标中断接口模块对应的中断接收设备发送所述中断数据包。
  13. 一种中断控制方法，其特征在于，应用于中断控制器，所述中断控制器包括与多个中断发送设备连接的中断仲裁模块、以及分别与对应的中断接收设备连接的多个中断接口模块；多个所述中断接口模块分别与所述中断仲裁模块连接，且能够采用不同的通信协议与所述对应的中断接收设备进行数据传输；所述中断控制方法包括：
    所述中断仲裁模块对来自所述中断发送设备的待发送中断信号进行仲裁，得到目标中断信号，并向对应的目标中断接口模块发送所述目标中断信号；
    所述中断接口模块，在作为所述目标中断接口模块时，响应于接收到所述中断仲裁模块发送的所述目标中断信号，基于所述目标中断信号向与所述对应的中断接收设备发 送中断指令。
  14. 一种芯片，其特征在于，包括：如权利要求1至12任一项所述的中断控制器。
  15. 一种计算机设备，其特征在于，包括：指令存储器和如权利要求1至12中任一项所述的中断控制器，或者包括如权利要求14所述的芯片。
  16. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时执行如权利要求13所述的中断控制方法的步骤。
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