WO2020143237A1 - 一种dma控制器和异构加速系统 - Google Patents

一种dma控制器和异构加速系统 Download PDF

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WO2020143237A1
WO2020143237A1 PCT/CN2019/103683 CN2019103683W WO2020143237A1 WO 2020143237 A1 WO2020143237 A1 WO 2020143237A1 CN 2019103683 W CN2019103683 W CN 2019103683W WO 2020143237 A1 WO2020143237 A1 WO 2020143237A1
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dma
data
descriptor
processing device
module
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PCT/CN2019/103683
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English (en)
French (fr)
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王峰
张静东
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郑州云海信息技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • the invention relates to the technical field of data processing, in particular to a DMA controller and a heterogeneous acceleration system.
  • the FPGA is connected to the server host through the PCIE interface.
  • the server host sends the data to be accelerated to the FPGA through the PCIE interface.
  • the relevant data is returned through the PCIE interface.
  • the data transmission volume is very large.
  • the DMA mechanism is introduced in the PCIE interface to solve the problem of large data volume transmission with the server host.
  • the DMA (Direct Memory Access, direct memory access) mechanism is mainly: receiving related instructions from the server host, and then perform data transfer, after the data transfer is complete, send an interrupt to the server host.
  • the DMA function in the PEIE interface is mainly divided into two, one is the DMA controller, which is responsible for receiving and parsing the instructions from the server host, and the other is the DMA mover, which is responsible for the server host according to the instructions. The corresponding data is moved between the memory and the on-chip memory of the FPGA.
  • connection methods of accelerator cards are becoming more and more diversified. For example, they can be connected to the server host through the PCIE interface, or they can be interconnected through optical ports or other interfaces.
  • the existing DMA controller and the PCIE module cannot be used together, which makes the control method single, and can only receive commands from the server host through PCIE, and cannot receive other home logic masters (such as FPGA). Commands of other server hosts or other terminals capable of issuing instructions other than the server host for accelerated data processing. This limits the flexibility and reusability of DMA.
  • the purpose of the present invention is to provide a DMA controller and a heterogeneous acceleration system to improve the flexibility of DMA and further improve the flexibility of the heterogeneous acceleration processing mode.
  • the present invention provides the following technical solutions:
  • a DMA controller including: a feedback module, a descriptor control module and a data interface module;
  • the data interface module includes a first sub-module and a second sub-module, the first sub-module is used to establish a communication connection with the first data processing device, and the second sub-module is used to establish with the DMA mover Communication connection
  • the descriptor control module is configured to receive the data movement request sent by the first data processing device, and parse the data movement request to obtain a descriptor; send the descriptor to the DMA mover, so that The DMA mover performs data movement between the second data processing device and the acceleration device based on the descriptor;
  • the feedback module is configured to receive the moving completion notification information fed back by the DMA mover, and notify the first data processing device that the data moving has been completed.
  • the feedback module is specifically configured to notify the first data processing device that the data transfer has been completed by sending an interrupt signal to the first data processing device.
  • a multi-task processing module the multi-task processing module includes:
  • a description table processing unit configured to receive the descriptor table sent by the DMA mover or send the descriptors in the descriptor table one by one and transfer them to the cache unit;
  • the buffer unit is configured to receive the descriptor and send the descriptor to the DMA mover according to the receiving order.
  • the cache unit is specifically configured to send a notification that the data migration is completed to the first data processing device when the migration completion notification information matches the last descriptor to be executed in the descriptor table news.
  • the second sub-module includes a sending unit for sending data and a receiving unit for receiving data.
  • the communication protocol type of the first sub-module is at least one of PEIC, Avalon-MM and Avalon-ST.
  • a heterogeneous acceleration system including:
  • the first data processing device, the acceleration device, the DMA mover, the second data processing device, and the DMA controller as described above;
  • the first data processing device and the DMA controller establish a communication connection through the first sub-module
  • the DMA controller and the DMA mover establish a communication connection through the second sub-module
  • the second data processing device and the acceleration device implement data transfer through the DMA transfer device.
  • the second data processing device and the acceleration device execute data descriptors executed by the DMA controller through the DMA mover.
  • the DMA mover After completing the data movement based on the descriptor sent by the DMA controller, the DMA mover returns the ID of the descriptor to the DMA controller, and the DMA controller receives the ID , Sending an interrupt signal to the first data processing device.
  • the acceleration device is any one of GPGPU, Xeon Phi and FPGA.
  • the DMA controller includes: a feedback module, a descriptor control module, and a data interface module; wherein, the data interface module includes a first submodule and a second submodule.
  • the first submodule is used to A data processing device establishes a communication connection
  • the second submodule is used to establish a communication connection with the DMA mover
  • a descriptor control module is used to receive the data transfer request sent by the first data processing device, and parse the data transfer request to obtain the descriptor ;
  • the feedback module is used to receive the move completion notification information fed back by the DMA mover, and Notify the first data processing device that the data transfer has been completed.
  • a first sub-module for establishing a communication connection with the first data processing device is provided specifically, and a second sub-module for establishing a communication connection with the DMA mover is provided specifically.
  • the descriptor control module can receive the data moving request sent by the first data processing device, and parse the data moving request to obtain the descriptor; and send the descriptor to the DMA mover. After receiving the descriptor, the DMA mover can move the data between the second data processing device and the acceleration device based on the descriptor, and after completing the data transfer, send the transfer completion notification information to the DMA controller.
  • the feedback module in the DMA controller receives the moving completion notification information fed back by the DMA mover, and can notify the first data processing device that the data moving has been completed. That is to say, the DMA controller can receive the data migration request sent by the first data processing device other than the second data processing device, and finally realize the data migration between the second data processing device and the acceleration device based on the data migration request. In this way, based on the DMA controller, the first data processing device can cause the acceleration device to accelerate the relevant calculations in the second data processing device, which increases the flexibility of the DMA.
  • the embodiments of the present invention also provide a heterogeneous acceleration system corresponding to the above DMA device, which has the above technical effects, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a DMA controller according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a processing flow of a DMA controller for a data movement request in an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a heterogeneous acceleration system in an embodiment of the present invention.
  • FIG. 4 is a heterogeneous acceleration system in an embodiment of the present invention.
  • first and second of the first submodule and the second submodule are only used to distinguish different interface modules, and do not mean that the interface modules have the meanings of sub-order, order, or degree of importance.
  • the first sub-module refers to an interface module in the DMA device that can establish a communication connection with the first data processing device
  • the second sub-module refers to an interface module in the DMA device that can establish a communication connection with the DMA mover.
  • the first and second of the first processing device and the second processing device are only used to distinguish the two processing devices involved are not the same processing device.
  • the first processing device is a device that sends a data migration request
  • the second processing device is a device to be accelerated during data acceleration processing, such as a common FPGA-based acceleration card to accelerate CPU data processing, where The accelerated target device is the CPU.
  • FIG. 1 is a schematic structural diagram of a DMA controller according to an embodiment of the present invention.
  • the device includes:
  • the first sub-module in the DMA mover can be a module capable of communicating with different first data processing devices, such as a PEIC module, Avalon-MM module, and Avalon-ST At least one of the modules. That is, the communication protocol in the first sub-module may be at least one of PCIE, Avalon-MM, and Avalon-ST.
  • the second sub-module may be a module that can achieve a communication connection with the DMA mover, for example, the second sub-module may establish communication with the MDA mover that uses the PEIE interface for communication.
  • the second submodule may specifically include a sending unit for sending data and a receiving unit for receiving data. For example, the TX_ST (transmit) port and the RX_ST (receive) port implement data transmission and data reception accordingly.
  • the register set can be set in the descriptor control module, so that the first data processing device can access the DMA controller.
  • the following describes the DMA controller in detail by taking the overall process of the DMA controller processing the data movement request as an example.
  • FIG. 2 is a schematic diagram of a processing flow of a DMA controller for a data movement request in an embodiment of the present invention.
  • the data request processing process includes:
  • S101 Receive a data migration request sent by a first data processing device, and analyze the data migration request to obtain a descriptor for data migration.
  • the first data processing device may specifically be a user logic master, such as common devices with user logic (smartphone, CPU, and intelligent image/video/voice acquisition device, etc.).
  • the first data processing device may establish a communication connection with the DMA controller through the first sub-module.
  • the DMA controller may parse the data transfer request and parse to obtain the data transfer descriptor.
  • the descriptor may have a uniquely identified ID.
  • information such as the source location, destination location, and data length of the data to be moved can be recorded, which is commonly used for data migration.
  • the descriptor can be sent to the DMA mover.
  • the DMA mover may be located inside the PCIE. After the DMA mover obtains the descriptor, it will move data between the second data processing device and the acceleration device connected thereto.
  • acceleration devices may include but are not limited to GPGPU, Xeon, Phi, and FPGA.
  • GPGPU is the most common acceleration card, and is connected to the second data processing device through PCI-e (same as PCIE); GPU was first used for graphics processing cards, namely The graphics card has now evolved into an acceleration card; Xeon Phi is a co-processor produced by Intel, and is connected to the second data processing device through PCI-e; FPGA acceleration card is also a plug-and-play accelerator card due to its significant hardware processing speed.
  • the data object to be moved and the direction of data movement can be known from the descriptor.
  • the data movement process between the second data processing device and the acceleration device based on the descriptor please refer to the common data movement The process will not be repeated here.
  • the transfer completion notification information can be sent to the DMA controller.
  • the DMA controller receives the moving completion notification information fed back by the DMA moving device.
  • the method of receiving the notification may be specifically a method of detecting the RX_ST receiving port to learn that the DMA mover has completed the data transfer information.
  • a notification message that the data transfer is late can be sent to the first data processing device.
  • the DMA controller can use the feedback module for notification.
  • the feedback module is specifically used to notify the first data processing device that the data transfer has been completed by sending an interrupt signal to the first data processing device.
  • the DMA controller provided in the embodiment of the present invention can receive the data transfer request sent by the first data processing device in addition to the data transfer request sent by the first data processing device.
  • the device connected to the first sub-module can be switched.
  • the second data processing device can be connected to the first sub-module to realize the current common use of the second data processing device as the control terminal. Realize accelerated processing of own data.
  • the DMA controller includes: a feedback module, a descriptor control module, and a data interface module; wherein, the data interface module includes a first submodule and a second submodule.
  • the first submodule is used to A data processing device establishes a communication connection
  • the second submodule is used to establish a communication connection with the DMA mover
  • a descriptor control module is used to receive the data transfer request sent by the first data processing device, and parse the data transfer request to obtain the descriptor ;
  • the feedback module is used to receive the move completion notification information fed back by the DMA mover, and Notify the first data processing device that the data transfer has been completed.
  • a first sub-module for establishing a communication connection with the first data processing device is provided specifically, and a second sub-module for establishing a communication connection with the DMA mover is provided specifically.
  • the descriptor control module can receive the data moving request sent by the first data processing device, and parse the data moving request to obtain the descriptor; and send the descriptor to the DMA mover.
  • the DMA mover can perform data transfer between the second data processing device and the acceleration device based on the descriptor, and after completing the data transfer, send the transfer completion notification information to the DMA controller.
  • the feedback module in the DMA controller receives the moving completion notification information fed back by the DMA mover, and can notify the first data processing device that the data moving has been completed. That is to say, the DMA controller can receive the data migration request sent by the first data processing device other than the second data processing device, and finally realize the data migration between the second data processing device and the acceleration device based on the data migration request. In this way, based on the DMA controller, the first data processing device can cause the acceleration device to accelerate the relevant calculations in the second data processing device, which increases the flexibility of the DMA.
  • the embodiments of the present invention also provide corresponding improvements.
  • the same steps as in the above-mentioned embodiments or the corresponding steps can be referred to each other, and the corresponding beneficial effects can also be cross-referenced, which will not be repeated in the preferred/improved embodiments herein.
  • a multi-task processing module can also be added to the DMC controller provided in the embodiment of the present invention, so that the DMC controller can process a batch of instructions (descriptor table) at a time. That is, the following multi-task processing module is set in the DMC controller.
  • the multitasking module includes:
  • Description table processing unit used to receive the DMA mover or the descriptor table sent, and read the descriptors in the descriptor table one by one to the cache unit;
  • the buffer unit is used to receive the descriptor and send the descriptor to the DMA mover according to the receiving order.
  • data movement can be performed on the descriptor table, that is, the execution of batches of instructions is realized without the need for the data migration controller to input instructions or data movement requests multiple times, to simplify the data processing flow.
  • the cache unit is specifically used to send a notification message that the data migration is completed to the first data processing device when the migration completion notification information matches the last descriptor to be executed in the descriptor table.
  • an embodiment of the present invention also provides a heterogeneous acceleration system.
  • the heterogeneous acceleration system described below and the DMA controller described above can be cross-referenced.
  • FIG. 3 is a schematic structural diagram of a heterogeneous acceleration system according to an embodiment of the present invention.
  • the system includes:
  • the first data processing device and the DMA controller establish a communication connection through the first sub-module 301
  • the DMA controller and the DMA mover establish a communication connection through the second sub-module 302
  • the second data processing device and the acceleration device Realize data movement.
  • the acceleration device is any one of GPGPU, XeonPhi and FPGA.
  • the second data processing device and the acceleration device execute the descriptor sent by the DMA controller through the DMA mover to realize data transfer.
  • the DMA mover returns the ID of the descriptor to the DMA controller after completing the data movement based on the descriptor sent by the DMA controller. After receiving the ID, the DMA controller sends an interrupt signal to the first data processing device.
  • an acceleration device Using the accelerated heterogeneous system provided by the embodiments of the present invention, an acceleration device, a DMA mover, a first data processing device, a second data processing device, and the DMA controller as described above; wherein, the first data processing device and the DMA control The device establishes a communication connection through the first submodule, the DMA controller and the DMA mover establish a communication connection through the second submodule, and the second data processing device and the acceleration device implement data transfer through the DMA mover.
  • the first data processing device may send a data transfer request to the DMA controller.
  • the DMA controller analyzes the data transfer request to obtain a descriptor, and then sends the descriptor to the DMA mover.
  • the DMA mover can perform data transfer between the second data processing device and the acceleration device based on the descriptor, and after completing the data transfer, send the transfer completion notification information to the DMA controller.
  • the feedback module in the DMA controller receives the moving completion notification information fed back by the DMA mover, and can notify the first data processing device that the data moving has been completed.
  • the first data processing device other than the second data processing device can finally realize the data migration between the second data processing device and the acceleration device through the data migration request sent, and then achieve the data Processing acceleration.
  • the first data processing device can cause the acceleration device to accelerate the relevant calculations in the second data processing device, which increases the flexibility of the DMA.
  • FIG. 4 is a heterogeneous acceleration system according to an embodiment of the present invention, in which DCM (Describe Control Master, description control master module) is the same as the feedback module above, DMS (Describe Control Service, describes control master module) The same as the descriptor control module above, DTS (describe table service, description table service module), the same as the description table processing unit above, FIFO (First in First), the specific implementation of the queue in this article, and the cache unit above .
  • DCM Describe Control Master, description control master module
  • DMS Describe Control Service, describes control master module
  • DTS subscribe table service, description table service module
  • FIFO First in First
  • the DMA controller is independent of the PCIE module, and has multiple independent Avalon-MM and Avalon-ST interfaces (to achieve the role of the first submodule above), the corresponding functions of each interface are clear, you can choose to connect the module in PCIE It is used to receive instructions from the second data processing device, and can also be connected to other user logic to receive instructions from user logic, which solves the problem of a single master source.
  • a FIFO for storing the descriptor table is set inside the DMA controller, so that a single instruction (single descriptor) or a batch of instructions (descriptor table) can be executed, so that the efficiency and flexibility of the DMA controller are greatly enhanced.
  • the second data processing device or user logic accesses the registers through the DCS module.
  • the DCS module generates corresponding descriptors based on the information in the registers and sends them to the DMA mover through the TX_ST port.
  • the DMA mover executes instructions to perform related data move.
  • the size of the descriptor can correspond to the size of the FIFO, for example, the descriptor table corresponding to the size of the common FIFO contains up to 128 descriptors, which can be less than 128)
  • the data corresponding to a certain descriptor of the DMA mover will move the descriptor table into the FIFO inside the DMA controller through the DTS module, and then the FIFO will send each descriptor in the descriptor table to the DMA mover through the TX_ST port Execution, after the DMA mover finishes the data movement, it will return the ID of the descriptor just executed.
  • the ID is the identifier of each descriptor in the descriptor table.
  • the ID is sent to the DCM module through the RX_ST port.
  • the DCM module judges whether this is the last descriptor in the descriptor table. If it is the last one, it means that the entire descriptor table has been executed. DCM will send the second data processing device or user logic The sending is interrupted to inform that the data transfer has been completed.
  • the DMA controller is no longer bound to the PCIE module, and can receive the data migration request of the first data processing device that is different from the second data processing device. By switching the device with the first submodule of the DMA controller, it can also receive a data migration request from the second data processing device, or receive data migration from other first data processing devices with user logic other than the second data processing device request. In addition, a single descriptor can be executed or the entire descriptor table can be executed in batches.
  • the independent DMA controller can also be used as an independent IP core, which facilitates the development of accelerator cards and shortens the development cycle.

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Abstract

一种DMA控制器和一种异构加速系统，DMA控制器包括：反馈模块（100）、描述符控制模块（200）和数据接口模块（300）；其中，数据接口模块（300）包括第一子模块（301）和第二子模块（302），第一子模块（301），用于与第一数据处理设备建立通信连接，第二子模块（302）用于与DMA搬移器（402）建立通信连接；描述符控制模块（200），用于接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器（402），以使DMA搬移器（402）基于描述符在第二数据处理设备和加速设备（401）之间进行数据搬移；反馈模块（100），用于接收DMA搬移器（402）反馈的搬移完成通知信息，并通知第一数据处理设备数据搬移已完成。该DMA控制器可增大DMA的灵活性。

Description

一种DMA控制器和异构加速系统
本申请要求于2019年01月08日提交至中国专利局、申请号为201910016298.8、发明名称为“一种DMA控制器和异构加速系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及数据处理技术领域，特别是涉及一种DMA控制器和一种异构加速系统。
背景技术
随着异构加速日益广泛的应用，基于诸如FPGA的加速设备也发展迅速。FPGA通过PCIE接口与服务器主机连接，服务器主机通过PCIE接口将需要加速的数据发送给FPGA，FPGA处理完成后通过PCIE接口返回相关的数据。在PCIE接口两侧的服务器主机与FPGA的数据传输中，数据传输量很大，为了提升传输速率，于是在PCIE接口引入DMA机制，解决了与服务器主机之间的大数据量的传输问题。
该DMA(Direct Memory Access，直接内存存取)机制主要：接收来自服务器主机的相关指令，然后执行数据搬移，数据搬移完成后向服务器主机发送中断。也就是说，PEIE接口中的DMA功能主要分为两个，一个是DMA控制器，用于负责接收和解析来自服务器主机端的指令，另一个是DMA搬移器，用于负责根据指令在服务器主机的内存和FPGA的片上存储器之间搬移对应的数据。
目前，加速卡的连接方式越来越多样化，如可通过PCIE接口与服务器主机连接，也可以通过光口或其他接口实现加速卡之间的互联。但是，现有的DMA控制器与PCIE模块合在一起，不能单独使用，这样使得控制方式单一，只能通过PCIE接收来自服务器主机端的指令，而不能接收来自其他户用逻辑master(如通过FPGA进行数据加速处理的服务器主机之外的其他服务器主机或其他能够发出指令的终端)的指令。如此，便限制了DMA的灵活性和可复用性。
综上所述，如何有效地通过DMA的灵活性和可复用性等问题，是目前本领域技术人员急需解决的技术问题。
发明内容
本发明的目的是提供一种DMA控制器和一种异构加速系统，以提升DMA的灵活性，进一步提高异构加速处理模式的灵活性。
为解决上述技术问题，本发明提供如下技术方案：
一种DMA控制器，包括：反馈模块、描述符控制模块和数据接口模块；
其中，所述数据接口模块包括第一子模块和第二子模块，所述第一子模块，用于与第一数据处理设备建立通信连接，所述第二子模块用于与DMA搬移器建立通信连接；
所述描述符控制模块，用于接收所述第一数据处理设备发送的数据搬移请求，并解析所述数据搬移请求，获得描述符；将所述描述符发送给所述DMA搬移器，以使所述DMA搬移器基于所述描述符在第二数据处理设备和加速设备之间进行数据搬移；
所述反馈模块，用于接收所述DMA搬移器反馈的搬移完成通知信息，并通知所述第一数据处理设备数据搬移已完成。
优选地，所述反馈模块，具体用于以向所述第一数据处理设备发送中断信号的方式，通知所述第一数据处理设备数据搬移已完成。
优选地，还包括：多任务处理模块，所述多任务处理模块包括：
描述表处理单元，用于接收所述DMA搬移器或发送的描述符表，并将所述描述符表内的描述符逐个读取后传递给所述缓存单元；
缓存单元，用于接收所述描述符，并按照接收顺序将所述描述符发送给所述DMA搬移器。
优选地，所述缓存单元，具体用于在所述搬移完成通知信息与所述描述符表中最后一个待执行的描述符匹配时，向所述第一数据处理设备发送数据搬移已完成的通知消息。
优选地，所述第二子模块包括用于发送数据的发送单元和用于接收数据的接收单元。
优选地，所述第一子模块的通信协议类型为PEIC、Avalon-MM和Avalon-ST中至少一种。
一种异构加速系统，包括：
第一数据处理设备、加速设备、DMA搬移器、第二数据处理设备和如上述的DMA控制器；
其中，所述第一数据处理设备与所述DMA控制器通过所述第一子模块建立通信连接，所述DMA控制器与所述DMA搬移器通过所述第二子模块建立通信连接，所述第二数据处理设备与所述加速设备通过所述DMA搬移器实现数据搬移。
优选地，所述第二数据处理设备与所述加速设备通过所述DMA搬移器执行所述DMA控制器发送的描述符实现数据搬移。
优选地，所述DMA搬移器在基于所述DMA控制器发送的描述符完成数据搬移之后，将所述描述符的ID返还给所述DMA控制器，所述DMA控制器接收到所述ID后，向所述第一数据处理设备发送中断信号。
优选地，所述加速设备为GPGPU、Xeon Phi和FPGA中的任意一种。
本发明实施例所提供的DMA控制器，包括：反馈模块、描述符控制模块和数据接口模块；其中，数据接口模块包括第一子模块和第二子模块，第一子模块，用于与第一数据处理设备建立通信连接，第二子模块用于与DMA搬移器建立通信连接；描述符控制模块，用于接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器，以使DMA搬移器基于描述符在第二数据处理设备和加速设备之间进行数据搬移；反馈模块，用于接收DMA搬移器反馈的搬移完成通知信息，并通知第一数据处理设备数据搬移已完成。
在该DMA控制器中，专门设置有用于与第一数据处理设备建立通信连接的第一子模块，以及专门设置有用于与DMA搬移器建立通信连接的第二子模块。且描述符控制模块，可接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器。DMA搬移器接收到该描述符之后，便可基于描述符在第二数据处理设备和加速设备之间进行数据搬移，并在完成数据搬移之后，向DMA控制器发送搬移完成通知信息。在DMA控制器中的反馈模块接收DMA搬移器反馈的搬移完成通知信息，便可通知第一数据处理设备数据搬移已完成。也就是说，该DMA控制器可接收第二数据处理设备以外的第一数据处理设备发送的 数据迁移请求，且基于该数据迁移请求最终实现第二数据处理设备与加速设备之间的数据迁移。如此，基于DMA控制器，第一数据处理设备便可令加速设备对第二数据处理设备中的相关计算进行加速处理，增大了DMA的灵活性。
相应地，本发明实施例还提供了与上述DMA设备相对应的异构加速系统，具有上述技术效果，在此不再赘述。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中一种DMA控制器的结构示意图；
图2为本发明实施例中DMA控制器对数据搬移请求的处理流程示意图；
图3为本发明实施例中一种异构加速系统的结构示意图；
图4为本发明实施例中一种异构加速系统。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一：
需要说明的是，第一子模块和第二子模块中的第一和第二仅用于区别不同的接口模块，并非指接口模块之间具有次第、先后顺序或轻重程度等含义。具体的，第一子模块即指DMA设备中能够与第一数据处理设备建立通信连接的接口模块，第二子模块即指DMA设备中能够与DMA搬移器建立通信连接的接口模块。
相应的，第一处理设备和第二处理设备中的第一和第二仅用于区别两个涉及到的处理设备不为同一个处理设备。具体的，即第一处理设备为发送数据迁移请求的设备，而第二处理设备为数据加速处理过程中的被加速对象设备，如常见的基于FPGA的加速卡对CPU的数据处理进行加速，其中被加速对象设备即为CPU。
请参考图1，图1为本发明实施例中一种DMA控制器的结构示意图，该设备包括：
反馈模块100、描述符控制模块200和数据接口模块300；其中，数据接口模块包括第一子模块301和第二子模块302，第一子模块，用于与第一数据处理设备建立通信连接，第二子模块用于与DMA搬移器建立通信连接；描述符控制模块，用于接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器，以使DMA搬移器基于描述符在第二数据处理设备和加速设备之间进行数据搬移；反馈模块，用于接收DMA搬移器反馈的搬移完成通知信息，并通知第一数据处理设备数据搬移已完成。
由于第一数据处理设备的类型可多样化，因而DMA搬移器中的第一子模块可为能够与不同的第一数据处理设备实现通信的模块，如PEIC模块、Avalon-MM模块和Avalon-ST模块中至少一种。即第一子模块内的通信协议可为PCIE、Avalon-MM和Avalon-ST中的至少一种。相应地，第二子模块为能够与DMA搬移器实现通信连接的模块即可，如，第二子模块为能够与使用PEIE接口进行通信的MDA搬移器建立通信的即可。具体的，第二子模块具体可以包括用于发送数据的发送单元和用于接收数据的接收单元。例如，在TX_ST(发送)端口和RX_ST(接收)端口相应实现数据发送和数据接收。
其中，描述符控制模块内可设置寄存器组，以便第一数据处理设备访问DMA控制器。
为了便于描述，下面以DMA控制器对数据搬移请求进行处理的整体过程为例，对DMA控制器进行详细说明。
请参考图2，图2为本发明实施例中DMA控制器对数据搬移请求的处理流程示意图。该数据请求处理过程，包括：
S101、接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得进行数据搬移的描述符。
其中，第一数据处理设备可具体为用户逻辑master，如具有用户逻辑的常见设备(智能手机、CPU和智能图像/视频/语音采集设备等)。第一数据处理设备可通过第一子模块与DMA控制器建立通信连接。
DMA控制器接收到第一数据处理设备发送的数据搬移请求之后，可对数据搬移请求进行解析，解析得到数据搬移的描述符。其中，该描述符可具有唯一标识的ID，另外，在该描述符中，可记录待搬移的数据的源位置、目的位置和数据长度等常见用于进行数据搬移的信息。
S102、将描述符发送给DMA搬移器，以便搬移器利用描述符在第二数据处理设备和加速设备之间进行数据搬移。
得到描述符之后，可将描述符发送给DMA搬移器。该DMA搬移器可位于PCIE内部，DMA搬移器得到描述符之后，便将与之相连接第二数据处理设备和加速设备之间进行数据搬移。其中，加速设备可包括但不限于GPGPU、Xeon Phi和FPGA，GPGPU为最常见的加速卡，通过PCI-e(同PCIE)与第二数据处理设备相连；GPU最早为用于图形处理卡，即显卡，目前演变为加速卡；Xeon Phi为intel生产的协处理器，通过PCI-e与第二数据处理设备相连；FPGA加速卡以其硬件处理速度显著，同样为即插即用的加速卡。
具体的，被搬移的数据对象、以及数据搬移的方向均可从描述符中得知，关于如何基于描述符，实现第二数据处理设备与加速设备之间的数据搬移过程可参见常见的数据搬移过程，在此不再赘述。
在DMA搬移完成数据搬移之后，可向DMA控制器发送搬移完成通知信息。
S103、接收DMA搬移器反馈的搬移完成通知信息。
DMA控制器接收到DMA搬移器反馈的搬移完成通知信息。具体的，接收该通知的方式可具体为通过检测RX_ST接收端口的方式，得知DMA搬移器完成数据搬移信息。
S104、向第一数据处理设备发送数据搬移完成的通知消息。
在接收到搬移完成通知信息之后，便可向第一数据处理设备发送数据搬移晚点的通知消息。具体的，DMA控制器可利用反馈模块进行通知。具 体的，反馈模块，具体用于以向第一数据处理设备发送中断信号的方式，通知第一数据处理设备数据搬移已完成。
在实际用于中，在本发明实施例所提供的DMA控制器，除可接收第一数据处理设备发送的数据搬移请求，还接收第二数据处理设备发出的数据搬移请求。具体的，可通过切换与第一子模块相连接的设备即可，如将第二数据处理设备与第一子模块接通便可实现目前常见的，以第二数据处理设备自身作为控制端，实现自身数据加速处理。
本发明实施例所提供的DMA控制器，包括：反馈模块、描述符控制模块和数据接口模块；其中，数据接口模块包括第一子模块和第二子模块，第一子模块，用于与第一数据处理设备建立通信连接，第二子模块用于与DMA搬移器建立通信连接；描述符控制模块，用于接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器，以使DMA搬移器基于描述符在第二数据处理设备和加速设备之间进行数据搬移；反馈模块，用于接收DMA搬移器反馈的搬移完成通知信息，并通知第一数据处理设备数据搬移已完成。
在该DMA控制器中，专门设置有用于与第一数据处理设备建立通信连接的第一子模块，以及专门设置有用于与DMA搬移器建立通信连接的第二子模块。且描述符控制模块，可接收第一数据处理设备发送的数据搬移请求，并解析数据搬移请求，获得描述符；将描述符发送给DMA搬移器。DMA搬移器接收到该描述符之后，便可基于描述符在第二数据处理设备和加速设备之间进行数据搬移，并在完成数据搬移之后，向DMA控制器发送搬移完成通知信息。在DMA控制器中的反馈模块接收DMA搬移器反馈的搬移完成通知信息，便可通知第一数据处理设备数据搬移已完成。也就是说，该DMA控制器可接收第二数据处理设备以外的第一数据处理设备发送的数据迁移请求，且基于该数据迁移请求最终实现第二数据处理设备与加速设备之间的数据迁移。如此，基于DMA控制器，第一数据处理设备便可令加速设备对第二数据处理设备中的相关计算进行加速处理，增大了DMA的灵活性。
需要说明的是，基于上述实施例，本发明实施例还提供了相应的改进方案。在优选/改进实施例中涉及与上述实施例中相同步骤或相应步骤之间 可相互参考，相应的有益效果也可相互参照，在本文的优选/改进实施例中不再一一赘述。
优选地，为了提高DMC控制器的处理速度，还可在本发明实施例中所提供的DMC控制器中增加多任务处理模块，使得DMC控制器可一次性处理批量的指令(描述符表)。即在DMC控制器中设置如下的多任务处理模块。该多任务处理模块包括：
描述表处理单元，用于接收DMA搬移器或发送的描述符表，并将描述符表内的描述符逐个读取后传递给缓存单元；
缓存单元，用于接收描述符，并按照接收顺序将描述符发送给DMA搬移器。
如此，便可针对描述符表进行数据搬移，即实现执行批量的指令，而无需数据迁移控制器多次输入指令或数据搬移请求，以简化数据处理流程。相应地，在执行批量指令时，需在完成所有的指令之后，再向第一数据处理设备发送数据搬移已完成的通知信息。具体的，即缓存单元，具体用于在搬移完成通知信息与描述符表中最后一个待执行的描述符匹配时，向第一数据处理设备发送数据搬移已完成的通知消息。
实施例二：
相应于上面的方法实施例，本发明实施例还提供了一种异构加速系统，下文描述的异构加速系统与上文描述的DMA控制器可相互对应参照。
请参考图3，图3为本发明实施例中一种异构加速系统的结构示意图，该系统，包括：
加速设备401、DMA搬移器402、第一数据处理设备403、第二数据处理设备400和如上述的DMA控制器404；
其中，第一数据处理设备与DMA控制器通过第一子模块301建立通信连接，DMA控制器与DMA搬移器通过第二子模块302建立通信连接，第二数据处理设备与加速设备通过DMA搬移器实现数据搬移。
其中，加速设备为GPGPU、Xeon Phi和FPGA中的任意一种。
其中，第二数据处理设备与加速设备通过DMA搬移器执行DMA控制器发送的描述符实现数据搬移。
其中，DMA搬移器在基于DMA控制器发送的描述符完成数据搬移之 后，将描述符的ID返还给DMA控制器，DMA控制器接收到ID后，向第一数据处理设备发送中断信号。
应用本发明实施例所提供的加速异构系统，加速设备、DMA搬移器、第一数据处理设备、第二数据处理设备、和如上述的DMA控制器；其中，第一数据处理设备与DMA控制器通过第一子模块建立通信连接，DMA控制器与DMA搬移器通过第二子模块建立通信连接，第二数据处理设备与加速设备通过DMA搬移器实现数据搬移。
第一数据处理设备可向DMA控制器发送数据搬移请求，DMA控制器接收到数据搬移请求之后，对数据搬移请求进行解析，得到描述符，然后，将描述符发送给DMA搬移器。DMA搬移器接收到该描述符之后，便可基于描述符在第二数据处理设备和加速设备之间进行数据搬移，并在完成数据搬移之后，向DMA控制器发送搬移完成通知信息。在DMA控制器中的反馈模块接收DMA搬移器反馈的搬移完成通知信息，便可通知第一数据处理设备数据搬移已完成。也就是说，在本系统中，除第二数据处理设备以外的第一数据处理设备，可通过发送的数据迁移请求，最终实现第二数据处理设备与加速设备之间的数据迁移，进而达到数据处理的加速。如此，基于DMA控制器，第一数据处理设备便可令加速设备对第二数据处理设备中的相关计算进行加速处理，增大了DMA的灵活性。
实施例三：
为了便于本领域技术人员更好地理解本发明实施例所提供的技术方案，下面以具体的应用场景为例，对本发明实施例所提供的技术方案进行详细说明。
请参考图4，图4为本发明实施例中一种异构加速系统，其中，DCM(Describe Control master，描述控制master模块)同上文中的反馈模块，DMS(Describe Control Service，描述控制master模块)同上文中的描述符控制模块，DTS(describe table Service，描述表服务模块)，同上文中的描述表处理单元，FIFO(First in First out，在本文中为队列的具体实现)，同上文中的缓存单元。
该DMA控制器独立于PCIE模块，且拥有多个独立的Avalon-MM和Avalon-ST接口(实现上文中的第一子模块的作用)，各个接口对应的功能 清晰，可以选择连接在PCIE的模块上，用于接收来自第二数据处理设备端的指令，也可以选择连接在其他用户逻辑上，用于接收来自用户逻辑的指令，这样就解决了master源单一的问题。
同时在DMA控制器内部设置存储描述符表的FIFO，这样可以执行单一指令(单一描述符)，也可以执行批量的指令(描述符表)，这样DMA控制器的效率和灵活性都大大增强。
DCS模块内部有一组寄存器，第二数据处理设备或者用户逻辑通过DCS模块访问寄存器，DCS模块根据寄存器的信息生成对应描述符，通过TX_ST端口发给DMA搬移器，DMA搬移器执行指令进行相关数据的搬移。如果要搬移的数据是一个描述符表(描述符的大小可与FIFO的大小向对应，例如，常见的FIFO的大小所对应的描述符表最多包含128个描述符，可以少于128个)内的某个描述符对应的数据，DMA搬移器会通过DTS模块将描述符表搬进DMA控制器内部的FIFO，然后FIFO会将描述符表中的每一个描述符通过TX_ST端口发给DMA搬移器执行，DMA搬移器执行完数据搬移后，会返回刚才执行完的描述符的ID，ID是每个描述符在描述符表中的标识。ID通过RX_ST端口发给DCM模块，DCM模块判断这是否是描述符表中的最后一个描述符，如果是最后一个，表示整个描述符表已经执行完，DCM会向第二数据处理设备或者用户逻辑发送中断，以告知本次的数据搬移已经执行完。
DMA控制器不再与PCIE模块绑定，可接收区别于第二数据处理设备的第一数据处理设备的数据迁移请求。通过切换与DMA控制器的第一子模块的设备，还可以接收来自第二数据处理设备的数据迁移请求，或接收非第二数据处理设备的其他具有用户逻辑的第一数据处理设备的数据迁移请求。另外，可以可执行单一描述符，也可以批量执行整个描述符表内描述符。
相比较与PCIE模块功能合并的DMA控制器，独立的DMA控制器的灵活性和可移植性以及可扩展性都大大增强。另外，独立的DMA控制器还可以作为独立的IP核，为加速卡的开发提供便利，缩短开发周期。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来 实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。

Claims (10)

  1. 一种DMA控制器，其特征在于，包括：反馈模块、描述符控制模块和数据接口模块；
    其中，所述数据接口模块包括第一子模块和第二子模块，所述第一子模块，用于与第一数据处理设备建立通信连接，所述第二子模块用于与DMA搬移器建立通信连接；
    所述描述符控制模块，用于接收所述第一数据处理设备发送的数据搬移请求，并解析所述数据搬移请求，获得描述符；将所述描述符发送给所述DMA搬移器，以使所述DMA搬移器基于所述描述符在第二数据处理设备和加速设备之间进行数据搬移；
    所述反馈模块，用于接收所述DMA搬移器反馈的搬移完成通知信息，并通知所述第一数据处理设备数据搬移已完成。
  2. 根据权利要求1所述的DMC控制器，其特征在于，所述反馈模块，具体用于以向所述第一数据处理设备发送中断信号的方式，通知所述第一数据处理设备数据搬移已完成。
  3. 根据权利要求1所述的DMC控制器，其特征在于，还包括：多任务处理模块，所述多任务处理模块包括：
    描述表处理单元，用于接收所述DMA搬移器或发送的描述符表，并将所述描述符表内的描述符逐个读取后传递给所述缓存单元；
    缓存单元，用于接收所述描述符，并按照接收顺序将所述描述符发送给所述DMA搬移器。
  4. 根据权利要求3所述的DMA控制器，其特征在于，所述缓存单元，具体用于在所述搬移完成通知信息与所述描述符表中最后一个待执行的描述符匹配时，向所述第一数据处理设备发送数据搬移已完成的通知消息。
  5. 根据权利要求1所述的DMA控制器，其特征在于，所述第二子模块包括用于发送数据的发送单元和用于接收数据的接收单元。
  6. 根据权利要求1至5任一项所述的DMA控制器，其特征在于，所述第一子模块的通信协议类型为PEIC、Avalon-MM和Avalon-ST中至少一种。
  7. 一种异构加速系统，其特征在于，包括：
    第一数据处理设备、加速设备、DMA搬移器、第二数据处理设备和如权利要求1至6任一项所述的DMA控制器；
    其中，所述第一数据处理设备与所述DMA控制器通过所述第一子模块建立通信连接，所述DMA控制器与所述DMA搬移器通过所述第二子模块建立通信连接，所述第二数据处理设备与所述加速设备通过所述DMA搬移器实现数据搬移。
  8. 根据权利要求7所述的异构加速系统，其特征在于，所述第二数据处理设备与所述加速设备通过所述DMA搬移器执行所述DMA控制器发送的描述符实现数据搬移。
  9. 根据权利要求8所述的异构加速系统，其特征在于，所述DMA搬移器在基于所述DMA控制器发送的描述符完成数据搬移之后，将所述描述符的ID返还给所述DMA控制器，所述DMA控制器接收到所述ID后，向所述第一数据处理设备发送中断信号。
  10. 根据权利要求7所述的异构加速系统，其特征在于，所述加速设备为GPGPU、Xeon Phi和FPGA中的任意一种。
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