WO2022222178A1 - 驱动方法、驱动电路及显示装置 - Google Patents

驱动方法、驱动电路及显示装置 Download PDF

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Publication number
WO2022222178A1
WO2022222178A1 PCT/CN2021/091430 CN2021091430W WO2022222178A1 WO 2022222178 A1 WO2022222178 A1 WO 2022222178A1 CN 2021091430 W CN2021091430 W CN 2021091430W WO 2022222178 A1 WO2022222178 A1 WO 2022222178A1
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WIPO (PCT)
Prior art keywords
driving
data
bit data
output
sub
Prior art date
Application number
PCT/CN2021/091430
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English (en)
French (fr)
Inventor
刘金风
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/413,979 priority Critical patent/US11682356B2/en
Publication of WO2022222178A1 publication Critical patent/WO2022222178A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application relates to the field of display, and in particular, to a driving method, a driving circuit and a display device.
  • A Active Matrix
  • Mini-LED Mini Light Emitting Diode
  • the AM Mini-LED backlight driving method means that the charging time of each area of the backlight is short, and the charging time decreases with the increase of the number of gray levels of the backlight. A certain rise and fall time is required.
  • the charging time of the Mini-LED backlight has a minimum limit, so the number of gray levels is limited by the charging time.
  • the existing backlight control technology it is difficult for the existing backlight control technology to meet the requirements for the gray-scale depth of the high-end backlight.
  • Embodiments of the present application provide a driving method, a driving circuit and a display device, which can increase the number of grayscales of a light-emitting unit, improve the brightness depth of the light-emitting unit, and meet the requirements for grayscale depth of high-level light emission.
  • An embodiment of the present application provides a driving method, and the driving method includes the following steps:
  • the drive data includes N bits of data
  • each group of the sub-bit data includes N/M bits of data, where M is a positive divisor of N and M is not 1 or N;
  • a corresponding driving voltage and a corresponding driving time are used to drive the corresponding light-emitting unit to emit light.
  • the step of dividing the data of the N bits into M groups of sub-bit data sequentially includes:
  • the divided groups of the sub-bit data are sequentially recorded as the first-level sub-bit data, the second-level sub-bit data... and the M-th level sub-bit data.
  • the larger the number of stages of the sub-bit data the shorter the driving time corresponding to the sub-bit data.
  • the first-level sub-bit data, the second-level sub-bit data . . . and the M-th level sub-bit data correspond to
  • the driving times are respectively P1, P2... and PM, and the P1, the P2... and the PM satisfy:
  • the sum of the driving times corresponding to the M groups of the sub-bit data is the time of M frames.
  • a group of the sub-bit data corresponds to one of the driving voltages.
  • the data of the sub-bit data is selected from one of 2N/M kinds of different data
  • the driving voltage corresponding to the sub-bit data is selected from 2N/M kinds of data.
  • the larger the binary value formed by the data of N/M sub-bits in the sub-bit data the higher the potential of the driving voltage corresponding to the sub-bit data. high.
  • the embodiments of the present application further provide a driving circuit for implementing each step in the driving method provided by the embodiments of the present application.
  • the driving circuit includes a voltage output module and a light-emitting module, and an output end of the voltage output module is connected to The driving voltage input end of the light-emitting module is connected to output a corresponding driving voltage to the light-emitting module according to driving data, the driving data includes data of N bits, and the voltage output module includes:
  • N/M 2 (N/M) output branches
  • the output end of any one of the output branches is connected to the driving voltage input end of the light-emitting module, and different output branches are used to input different input to the light-emitting module.
  • Drive voltage where M is a positive divisor of N and M is not 1 or N.
  • the voltage output module includes at least one raw voltage input terminal, and the output branch is electrically connected to the raw voltage input terminal.
  • the original voltage input terminal is only one
  • the output branch includes a first output branch, a second output branch... and a second ( N/M) output branch
  • the first output branch is directly connected to the original voltage input terminal
  • the second output branch is connected to the original voltage input terminal through a first resistor, Vietnamese .
  • the 2nd (N/M) output branch is connected with the (2(N/M)-1)th resistor, « The raw voltage input is connected and grounded.
  • the number of raw voltage input terminals is 2 (N/M), including a first raw voltage input terminal, a second raw voltage input terminal... and a first raw voltage input terminal.
  • 2(N/M) original voltage input terminals the output branch includes a first output branch, a second output branch... and a second (N/M) output branch, the first output branch The output branch is directly connected to the first original voltage input terminal, the second output branch is directly connected to the second original voltage input terminal, ..., the second (N/M) The output branch is directly connected to the second (N/M) original voltage input terminal.
  • each of the output branches includes a switch control unit for controlling the conduction of the output branches.
  • the switch control unit is a DIP switch.
  • the switch control unit includes N/M switch transistors connected in series, one end of the switch control unit is electrically connected to the output end of the voltage output module, and the switch controls The other end of the unit is electrically connected to the original voltage input end.
  • the gate of one switching transistor on each output branch is connected to the same gate control. Voltage.
  • the light-emitting module includes a charging unit, a driving unit, an energy storage unit, and a light-emitting unit,
  • the charging unit is electrically connected to the driving unit and the energy storage unit, and is used for writing a data signal into the energy storage unit according to a scan signal;
  • the driving unit is electrically connected to the energy storage unit, the charging unit and the light-emitting unit, and is used for driving the light-emitting unit to work under the control of the energy storage unit;
  • the energy storage unit is used for storing the data signal, and controlling the working state of the driving unit according to the data signal.
  • an embodiment of the present application further provides a display device, including a driving circuit, the driving circuit includes a voltage output module and a light-emitting module, an output end of the voltage output module and a driving voltage input end of the light-emitting module connected to output a corresponding driving voltage to the light-emitting module according to driving data, where the driving data includes N bits of data, and the voltage output module includes:
  • N/M 2 (N/M) output branches
  • the output end of any one of the output branches is connected to the driving voltage input end of the light-emitting module, and different output branches are used to input different input to the light-emitting module.
  • Drive voltage where M is a positive divisor of N and M is not 1 or N.
  • the voltage output module includes at least one raw voltage input terminal, and the output branch is electrically connected to the raw voltage input terminal.
  • each of the output branches includes a switch control unit for controlling the conduction of the output branches.
  • Embodiments of the present application provide a driving method, a driving circuit, and a display device.
  • the driving method includes the following steps: acquiring driving data, where the driving data includes data of N bits; and dividing the data of the N bits into M groups in sequence.
  • Sub-bit data each group of sub-bit data includes data of N/M bits, wherein M is a positive divisor of N and M is not 1 or N; and according to each group of sub-bit data , using the corresponding driving voltage and corresponding driving time to drive the corresponding light-emitting unit to emit light.
  • the original N-bit data is divided into M groups of sub-bit data, and according to each sub-bit data, the corresponding driving voltage and driving time are used to drive the light-emitting unit, and the original gray-scale display is converted into
  • the divided M gray-scale display increases the number of gray-scales of the light-emitting unit, improves the brightness depth of the light-emitting unit, and meets the requirements of high-level light-emitting for gray-scale depth.
  • FIG. 1 is a flowchart of a driving method provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a driving method provided by an embodiment of the present application.
  • FIG. 3 is a first circuit diagram of a drive circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the effect of the driving method provided by the embodiment of the present application.
  • Embodiments of the present application provide a driving method, a driving circuit, and a display device, so as to increase the number of grayscales of a light-emitting unit, improve the brightness depth of the light-emitting unit, and meet the grayscale depth requirements of high-level light emission.
  • FIG. 1 shows a flowchart of a driving method provided by an embodiment of the present application.
  • the driving method provided by the embodiment of the present application includes:
  • Step S1 Acquire driving data, where the driving data includes N bits of data.
  • the driving data is obtained from a timing controller (Time Controller, Tcon) or a field programmable gate array (Field Programmable Gate Array, FPGA), and the driving data is binary data obtained by algorithm processing based on the data information of the screen to be displayed.
  • the bit data of the driving data is 8 bits
  • the light-emitting unit can emit 256 kinds of light with different brightness, that is, the brightness corresponding to 0-255 gray scale; when the bit data of the driving data is 12 bits, the light-emitting unit can emit light with different brightness.
  • the N-bit data includes the data of the 0th bit to the data of the N-1th bit, and the data of each bit is any one of 0 or 1, wherein the 0th bit is the smallest but the highest bit, The N-1th bit is the largest but least significant bit.
  • Step S2 divide the data of N bits into M groups of sub-bit data in turn, and each group of sub-bit data includes N/M bits of data, wherein M is a positive divisor of N and M is not 1 or N.
  • the data of every N/M bits in the N-bit data is divided into a group of sub-bit data, and the divided groups of sub-bit data are divided into They are sequentially recorded as the first-level sub-bit data, the second-level sub-bit data, ..., the M-th level sub-bit data.
  • the data of the 0-(N/M-1) bit is divided into the first group of sub-bit data, which is recorded as the first-level sub-bit data; the N/M-(2N/M-1) bit
  • the bit data is divided into a second group of sub-bit data, which is denoted as the second-level sub-bit data, and sequentially to the M-th level of sub-bit data.
  • the first-level sub-bit data has the highest level
  • the M-th level sub-bit data has the lowest level.
  • Step S3 according to each group of sub-bit data, use the corresponding driving voltage and the corresponding driving time to drive the corresponding light-emitting unit to emit light.
  • the sub-bit data of each group corresponds to the driving voltage of a specific potential, because each group of sub-bit data includes N/M bits of data, and the data of each bit is selected from For any one of 0 and 1, correspondingly, the sub-bit data has 2N/M possibilities. Therefore, the driving voltage corresponding to the sub-bit data has 2N/M different potentials.
  • the driving voltages corresponding to the two sub-bit data are the same; if the two sub-bit data are different, that is If one of the numbers or arrangement sequences of 0s and 1s in the two sub-bit data is the same, the corresponding driving voltages of the two bit data are different.
  • the original bit data is divided into M groups of sub-bit data, and 2N/M driving voltages of different potentials are used to drive the light-emitting unit, and the gray-scale number of the light-emitting unit is changed from the original one.
  • a single fixed type is divided into the current 2N/M type, which improves the number of gray levels of the light-emitting unit and improves the brightness depth of the light-emitting unit.
  • the larger the binary value formed by the data of N/M bits in the sub-bit data the higher the potential of the driving voltage corresponding to the sub-bit data.
  • the binary value formed by the sub-bit data (11) is 11, and the binary value formed by the sub-bit data (10) is 10, then the potential of the driving voltage corresponding to the sub-bit data (11) is greater than that of the sub-bit data (10 ) corresponding to the potential of the driving voltage.
  • the larger the binary value formed by the bit data the larger the number of gray levels corresponding to the bit data.
  • the 8-bit data (00000000) corresponds to the 0th grayscale
  • the 8-bit data (01111111) corresponds to the 127th grayscale.
  • grayscale 8-bit data (11111111) corresponds to the 255th grayscale.
  • the greater the number of gray levels the greater the corresponding luminous brightness. That is, for the sub-bit data of the same series, the larger the binary value formed by the sub-bit data, the higher the corresponding driving voltage and the brighter the corresponding light-emitting brightness.
  • the magnitude of the binary value formed by the sub-bit data is combined with the potential of the driving voltage, and then the driving voltage and the luminous brightness are combined.
  • the higher potential setting highlights the difference in the weight of different sub-bit data in the brightness, thereby improving the contrast of different gray scales, and further improving the brightness depth of the light-emitting unit.
  • the sub-bit data of each group corresponds to one driving time
  • the sum of the driving times corresponding to M groups of sub-bit data is the time of M frames, that is, a complete N-bit data adopts the time of M frames as a time. unit to drive.
  • the time of M frames as a time unit to drive N-bit data
  • the number of gray levels is no longer limited by the charging time, and the gray level of the light-emitting unit is improved. number, which improves the brightness depth of the light-emitting unit.
  • the driving time corresponding to the sub-bit data of the same level is the same, and the driving time corresponding to the sub-bit data of different levels is different, and the higher the level of the sub-bit data, the longer the driving time corresponding to the sub-bit data.
  • 8-bit data (00000000) corresponds to the 0th grayscale
  • 8-bit data (00000001) corresponds to the 1st grayscale
  • 8-bit data (01111111) corresponds to the 127th grayscale
  • the data (11111111) corresponds to the 255th grayscale.
  • the present application provides a driving circuit for implementing steps S1-S3 in the driving method provided by the embodiment of the present application.
  • FIG. 3 and FIG. 4 respectively show two circuit diagrams of the driving circuit provided by the embodiments of the present application.
  • the driving circuit provided by the embodiment of the present application includes: a voltage output module 30 and a light-emitting module 40.
  • the output end of the voltage output module 30 is connected to the driving voltage input end of the light-emitting module 40, and is used for sending the data to the light-emitting module according to the driving data.
  • the driving data includes N bits of data
  • the voltage output module 30 includes: 2 (N/M) output branches, the output end of any output branch and the driving voltage input of the light-emitting module 40 The terminals are connected, and different output branches are used to output different driving voltages to the light-emitting module 40 , wherein M is a positive divisor of N and M is not 1 or N.
  • the driving circuit by adding a voltage output module with 2 (N/M) output branches, it is used to output 2 (N/M) different driving voltages to the light emitting module, and 2N/M different driving voltages are used.
  • the driving voltage of the potential drives the light-emitting unit, the driving voltage of the light-emitting unit is changed from the original one to the current 2N/M type, and the corresponding gray level is correspondingly increased to 2N/M level, which improves the gray level of the light-emitting unit. number, which improves the brightness depth of the light-emitting unit.
  • the voltage output module 30 includes at least one raw voltage input terminal, and each output branch is electrically connected to the raw voltage input terminal.
  • the output branch includes a first output branch, a second output branch... and a second (N/M) Output branch
  • the first output branch is directly connected to the original voltage input terminal
  • the second output branch is connected to the original voltage input terminal through the first resistor, ..., the second (N/M) output branch It is connected to the original voltage input terminal and grounded through the series circuit of the 2nd (N/M)-1 resistor, . . . , the second resistor and the first resistor.
  • the output branch includes the first output branch, the second output branch, ... and the second (N/M) output branch, the first output branch It is directly connected to the first original voltage input terminal, the second output branch is directly connected to the second original voltage input terminal, ..., the second (N/M) output branch is connected to the second (N/M) The raw voltage input is connected directly.
  • each output branch includes a switch control unit for controlling the conduction of the output branch.
  • the switch control unit is a DIP switch.
  • the switch control unit includes N/M series-connected switch transistors, one end of the switch control unit is electrically connected to the output end of the voltage output module, the other end is electrically connected to the original voltage input end, and any one of the output branches is electrically connected to the output end of the voltage output module.
  • the gate of one switching transistor is electrically connected to the gate of one switching transistor on the other (M/2-1) output branches and is connected to a gate control voltage, and is not connected to the gate of other switching transistors.
  • the light-emitting module 40 includes a charging unit, a driving unit, an energy storage unit, and a light-emitting unit, and the charging unit is electrically connected to the driving unit and the energy storage unit, and is used for writing a data signal into the energy storage unit according to a scan signal;
  • the driving unit is electrically connected with the energy storage unit, the charging unit and the light-emitting unit, and is used for driving the light-emitting unit to work under the control of the energy storage unit;
  • the energy storage unit is used for storing data signals and controlling the working state of the driving unit according to the data signals. Specifically, as shown in FIG. 3 and FIG.
  • the driving unit is the first thin film transistor T1
  • the charging unit is the second thin film transistor T2
  • the energy storage unit is the capacitor C1
  • the light emitting unit includes a subminiature light emitting diode LED.
  • the gate of the second thin film transistor T2 is connected to the scan signal Vscan
  • the first end of the second thin film transistor T2 is connected to the data signal Vdata
  • the second end of the second thin film transistor T2 is connected to the gate of the first thin film transistor T1 and the capacitor C1
  • the first end of the first thin film transistor T1 is connected to the output end of the light emitting unit LED
  • the second end of the first thin film transistor T1 is connected to the second end of the capacitor C1 and connected to the ground signal VSS
  • the light emitting unit The input terminal of the LED is connected to the output terminal of the voltage output module 30 .
  • FIG. 2 shows a schematic diagram of a driving method provided by an embodiment of the present application.
  • B[0] is the highest bit data
  • B[7] is the lowest bit data.
  • B[0-1] 00
  • B[2-3] 01
  • B[4-5] 10
  • B[6-7] 11
  • the group of sub-bit data B[4-5] is denoted as the third-level sub-bit data
  • the fourth group of sub-bit data B[6-7] is denoted as the fourth-level sub-bit data.
  • the number of stages of the first-level sub-bit data B[0-1] is the highest
  • the second-level sub-bit data B[2-3] has the second highest level
  • the third-level sub-bit data B[ 4-5] has the next lowest level
  • the 4th level sub-bit data B[6-7] has the lowest level.
  • the divided 2-bit data has four different options of 00, 01, 10, and 11, and each type of 2-bit data corresponds to a specific driving voltage.
  • the corresponding driving voltage is V1
  • the corresponding driving voltage is V2
  • the corresponding driving voltage is V3
  • the corresponding driving voltage is V4. That is, the driving voltage of sub-bit data B[0-1] is V1, the driving voltage of sub-bit data B[2-3] is V2, the driving voltage of sub-bit data B[4-5] is V3, and the driving voltage of sub-bit data B[4-5] is V3.
  • the driving voltage of the bit data B[6-7] is V4.
  • the potential of the driving voltage V4 is greater than the potential of the driving voltage V3, the potential of the driving voltage V3 is greater than the potential of the driving voltage V2, the potential of the driving voltage V2 is greater than the potential of the driving voltage V1, and the potential of the driving voltage V1 is preferably the ground potential.
  • the divided groups of sub-bit data are driven in an independent driving manner, and the driving time corresponding to the sub-bit data of different levels is different.
  • the driving of the first-level sub-bit data B[0-1] The time is P1
  • the driving time of the second-level sub-bit data B[2-3] is P2
  • the driving time of the third-level sub-bit data B[4-5] is P3
  • the voltage output module 30 includes an original voltage input terminal, which is connected to the original input voltage V4, and a ground terminal, which is connected to the ground power V1, and a first resistor R1 is passed between the original voltage input terminal and the ground terminal.
  • the second resistor R2 and the third resistor R3 are connected in series.
  • the first output branch includes series-connected switching transistors T9 and T10, and is directly connected to the original voltage input end and the input end of the driving module 40;
  • the second output branch includes series-connected switching transistors T7 and T8, which are connected to the original voltage through a first resistor R1
  • the voltage input terminal is directly connected to the input terminal of the driving module 40;
  • the third output branch includes switching transistors T5 and T6 connected in series, connected to the original voltage input terminal through the first resistor R1 and the second resistor R2 and directly connected to the input terminal of the driving module 40
  • the fourth output branch includes switch transistors T3 and T4 connected in series, connected to the original voltage input terminal and grounded through the first resistor R1, the second resistor R2 and the third resistor R3, and also directly connected to the input terminal of the driving module 40.
  • the gate of the switching transistor T3 is connected to the gate of the switching transistor T5 and connected to the first gate control voltage G1(0), the first gate control voltage G1(0) corresponds to the first bit data 0 of the 2-bit data ;
  • the gate of the switching transistor T7 is connected to the gate of the switching transistor T9 and is connected to the second gate control voltage G1(1), the second gate control voltage G1(1) corresponds to the first bit data of the 2-bit data 1;
  • the gate of the switching transistor T4 is connected to the gate of the switching transistor T8 and is connected to the third gate control voltage G2(0), the third gate control voltage G2(0) corresponds to the second bit of the 2-bit data Data 0;
  • the gate of the switching transistor T6 is connected to the gate of the switching transistor T10 and connected to the fourth gate control voltage G2(1), which corresponds to the second gate of the 2-bit data Bit data 1.
  • the voltage output module 30 includes four original voltage input terminals, respectively connected to the first original input voltage V1, the second original input voltage V2, the third original input voltage V3 and the fourth original input voltage V4, wherein The first original input voltage V1 is the ground voltage.
  • One end of the first output branch is directly connected to the fourth original voltage V4, and the other end is directly connected to the input end of the drive module 40; one end of the second output branch is directly connected to the third original voltage V3, and the other end is directly connected to the drive module 40 One end of the third output branch is directly connected to the second original voltage V2, and the other end is directly connected to the input end of the drive module 40; one end of the fourth output branch is directly connected to the first original voltage V1, and the other end is directly connected to the first original voltage V1. Connect to the input terminal of the driving module 40 .
  • the switching transistor T3 and the switching transistor T4 are turned on,
  • the voltage output module 30 inputs the driving voltage V1 to the driving module through the fourth output branch, and drives the light-emitting unit LED to emit light within the driving time P1;
  • the switching transistor T7 and the switching transistor T8 are turned on, the voltage output module 30 inputs the driving voltage V3 to the driving module through the second output branch, and drives the light-emitting unit LED to emit light within the driving time P3; for the fourth-level sub-bit
  • FIG. 5 shows a schematic diagram of the effect of the driving method provided by the embodiment of the present application.
  • the driving voltage V1 drives the LED of the display unit in the first frame time P1, and displays the grayscale corresponding to the first level 2 bits B[0-1], in the second frame time P2
  • the driving voltage V1 drives the LED of the display unit to display the gray scale corresponding to the second level 2-bit B[2-3]
  • the driving voltage V1 drives the LED of the display unit during the third frame time P3 to display the third level of 2-bit B[4-5] ] corresponding grayscale
  • the driving voltage V1 drives the display unit LED in the fourth frame time P4 to display the grayscale corresponding to the fourth level 2 bits B[6-7].
  • the 4-frame grayscale display effects are superimposed on each other, which is equivalent to a display effect corresponding to 0 grayscale.
  • the driving voltage V1 drives the display unit LED in the first frame time P1
  • the driving voltage V4 drives the display unit LED in the second frame time P2
  • the voltage V4 drives the display unit LED
  • the driving voltage V4 drives the display unit LED in the fourth frame time P4.
  • the gradation display effects are superimposed on each other, and the final equivalent is the display
  • the voltage V4 drives the display unit LED
  • the driving voltage V4 drives the display unit LED in the third frame time P3
  • the driving voltage V4 drives the display unit LED in the fourth frame time P4. level display effect.
  • the original gray-scale display is converted into The divided four gray-scale display improves the gray-scale number of the light-emitting unit and improves the brightness depth of the light-emitting unit.
  • the embodiments of the present application also provide a display device, the display device includes any of the driving circuits provided in the embodiments of the present application, and has the technical features and technical effects of any of the driving circuits provided in the embodiments of the present application.
  • the display device includes any of the driving circuits provided in the embodiments of the present application, and has the technical features and technical effects of any of the driving circuits provided in the embodiments of the present application.
  • the driving method includes the following steps: acquiring driving data, where the driving data includes N bits of data; It is equally divided into M groups of sub-bit data, and the sub-bit data of each group includes N/M bits of data, where M is a positive divisor of N and M is not 1 or N; according to each group For the sub-bit data, a corresponding driving voltage and a corresponding driving time are used to drive the corresponding light-emitting unit to emit light.
  • the light-emitting unit is driven by the corresponding driving voltage and driving time, and the original gray-scale display is converted into a division
  • the latter M gray-scale display increases the number of gray-scales of the light-emitting unit, improves the brightness depth of the light-emitting unit, and meets the requirements of high-level light-emitting for gray-scale depth.

Abstract

本申请公开了一种驱动方法、驱动电路及显示装置，该驱动方法包括：获取驱动数据，驱动数据包括N个比特位的数据；将N个比特位的数据依次等分为M组均包括N/M个比特位的数据的子比特位数据，其中，M为N的正约数且M不为1或N；以及根据每一组子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。

Description

驱动方法、驱动电路及显示装置 技术领域
本申请涉及显示领域，具体涉及一种驱动方法、驱动电路及显示装置。
 背景技术
主动矩阵式（Active Matrix，AM）的迷你发光二极管（Mini Light Emitting Diode，Mini-LED）背光驱动方法由于局部可控、LED驱动芯片数量较少、以及成本低等优势成为液晶显示面板（Liquid Crystal Display，LCD）的背光趋势。
然而，采用AM Mini-LED背光驱动方法意味着背光每一区的充电时间短，并且充电时间随着背光灰阶级数的增大而缩小，又由于背光面板存在一定的压降，对面板充电时需要一定的上升和下降时间，为满足充电需求，Mini-LED背光的充电时长有最小限定，因此灰阶级数受限于充电时间。随着市场对背光灰阶亮度的要求越来越高，现有的背光控制技术很难满足高阶背光对灰阶深度的要求。
 技术问题
本申请实施例提供一种驱动方法、驱动电路及显示装置，可以增加发光单元的灰阶数量，提高发光单元的亮度深度，满足高阶发光对灰阶深度的要求。
 技术解决方案
本申请实施例提供一种驱动方法，所述驱动方法包括以下步骤：
获取驱动数据，所述驱动数据包括N个比特位的数据；
将所述N个比特位的数据依次等分为M组子比特位数据，每一组的所述子比特位数据均包括N/M个比特位的数据，其中，M为N的正约数且M不为1或N；以及
根据每一组所述子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。
可选的，在本申请的一些实施例中，所述步骤将所述N个比特位的数据依次等分为M组子比特位数据的步骤，包括：
按照比特位由高到低的顺序，将所述N个比特位的数据中每N/M个比特位的数据划分为一组所述子比特位数据；以及
将划分后的各组所述子比特位数据依次记为第1级子比特位数据、第2级子比特位数据......和第M级子比特位数据。
可选的，在本申请的一些实施例中，所述子比特位数据的级数越大，所述子比特位数据对应的驱动时间越短。
可选的，在本申请的一些实施例中，所述第1级子比特位数据、所述第2级子比特位数据......和所述第M级子比特位数据对应的驱动时间分别为P1、P2......和PM，所述P1、所述P2......和所述PM满足：
P1：P2：......：PM =2（M-1）：2（M-2）：...：20。
可选的，在本申请的一些实施例中，M组所述子比特位数据对应的驱动时间之和为M帧的时间。
可选的，在本申请的一些实施例中，一组所述子比特位数据对应于一个所述驱动电压。
可选的，在本申请的一些实施例中，所述子比特位数据的数据选自2N/M种不同数据中的一种，所述子比特位数据对应的驱动电压选自2N/M种不同电位的驱动电压中的一种。
可选的，在本申请的一些实施例中，所述子比特位数据中N/M个子比特位的数据构成的二进制数值越大，所述子比特位数据对应的所述驱动电压的电位越高。
相应的，本申请实施例还提供一种驱动电路，用于实施本申请实施例提供驱动方法中的各个步骤，所述驱动电路包括电压输出模块和发光模块，所述电压输出模块的输出端与所述发光模块的驱动电压输入端连接，用于根据驱动数据向所述发光模块输出对应的驱动电压，所述驱动数据包括N个比特位的数据，所述电压输出模块包括：
2(N/M)条输出支路，任意一条所述输出支路的输出端与所述发光模块的驱动电压输入端连接，不同的所述输出支路用于对所述发光模块输入不同的驱动电压，所述M为N的正约数且M不为1或N。
可选的，在本申请的一些实施例中，所述电压输出模块包括至少一个原始电压输入端，所述输出支路与所述原始电压输入端电连接。
可选的，在本申请的一些实施例中，所述原始电压输入端仅为一个，所述输出支路包括第一输出支路、第二输出支路......和第2(N/M)输出支路，所述第一输出支路与所述原始电压输入端直接连接，所述第二输出支路通过第一电阻与所述原始电压输入端连接，......，所述第2(N/M)输出支路通过第（2(N/M)-1）电阻、......、所述第二电阻和所述第一电阻的串联电路与所述原始电压输入端连接且接地。
可选的，在本申请的一些实施例中，所述原始电压输入端为2(N/M)个，包括第一原始电压输入端、第二原始电压输入端......和第2(N/M)原始电压输入端，所述输出支路包括第一输出支路、第二输出支路......和第2(N/M)输出支路，所述第一输出支路与所述第一原始电压输入端直接连接，所述第二输出支路与所述第二原始电压输入端直接连接，......，所述第2(N/M)输出支路与所述第2(N/M)原始电压输入端直接连接。
可选的，在本申请的一些实施例中，每一所述输出支路均包括开关控制单元，用于控制所述输出支路的导通。
可选的，在本申请的一些实施例中，所述开关控制单元为拨码开关。
可选的，在本申请的一些实施例中，所述开关控制单元包括N/M个串联的开关晶体管，所述开关控制单元的一端电连接所述电压输出模块的输出端，所述开关控制单元的另一端电连接所述原始电压输入端。
可选的，在本申请的一些实施例中，在任意的M/2条所述输出支路中，每一条所述输出支路上的一个所述开关晶体管的栅极接入同一个栅极控制电压。
可选的，在本申请的一些实施例中，所述发光模块包括充电单元、驱动单元、储能单元以及发光单元，
所述充电单元与所述驱动单元以及所述储能单元电连接，用于根据扫描信号将数据信号写入所述储能单元；
所述驱动单元与所述储能单元、所述充电单元以及所述发光单元电连接，用于在所述储能单元的控制下驱动所述发光单元工作；以及
所述储能单元用于存储所述数据信号，并根据所述数据信号控制所述驱动单元的工作状态。
相应的，本申请实施例还提供一种显示装置，包括一种驱动电路，所述驱动电路包括电压输出模块和发光模块，所述电压输出模块的输出端与所述发光模块的驱动电压输入端连接，用于根据驱动数据向所述发光模块输出对应的驱动电压，所述驱动数据包括N个比特位的数据，所述电压输出模块包括：
2(N/M)条输出支路，任意一条所述输出支路的输出端与所述发光模块的驱动电压输入端连接，不同的所述输出支路用于对所述发光模块输入不同的驱动电压，所述M为N的正约数且M不为1或N。
可选的，在本申请的一些实施例中，所述电压输出模块包括至少一个原始电压输入端，所述输出支路与所述原始电压输入端电连接。
可选的，在本申请的一些实施例中，每一所述输出支路均包括开关控制单元，用于控制所述输出支路的导通。
 有益效果
本申请实施例提供一种驱动方法、驱动电路及显示装置，该驱动方法包括以下步骤：获取驱动数据，驱动数据包括N个比特位的数据；将N个比特位的数据依次等分为M组子比特位数据，每一组的子比特位数据均包括N/M个比特位的数据，其中，M为N的正约数且M不为1或N；以及根据每一组子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。本申请通过将原始N比特位数据划分为M组子比特位数据，根据每一子比特位数据，采用对应的驱动电压和驱动时间对发光单元进行驱动，由原始的一种灰阶显示转换为划分后的M种灰阶显示，提高了发光单元的灰阶数量，提高发光单元的亮度深度，满足高阶发光对灰阶深度的要求。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是本申请实施例提供的驱动方法的种流程图；
图2是本申请实施例提供的驱动方法的示意图；
图3是本申请实施例提供的驱动电路的第一种电路图；
图4是本申请实施例提供的驱动电路的第二种电路图；
图5是本申请实施例提供的驱动方法的效果示意图。
 本发明的实施方式
本申请实施例提供一种驱动方法、驱动电路及显示装置，以增加发光单元的灰阶数量，提高发光单元的亮度深度，满足高阶发光对灰阶深度的要求。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
在一种实施例中，请参照图1，图1示出了本申请实施例提供的驱动方法的流程图。如图所示，本申请实施例提供的驱动方法包括：
步骤S1、获取驱动数据，驱动数据包括N个比特位的数据。
具体的，从时序控制器（Time Controller，Tcon）或现场可编辑阵列（Field Programmable Gate Array，FPGA）获取驱动数据，驱动数据是基于待显示画面的数据信息通过算法处理得到的二进制数据。驱动数据的比特位数决定了发光单元的最大灰阶级数，发光单元的灰阶级数G与驱动数据的比特位数N满足G=2N。当驱动数据的比特位数据为8比特位时，发光单元可以发出256种不同亮度的光，即0-255灰阶对应的亮度；当驱动数据的比特位数据为12比特位时，发光单元可以发出4096种不同亮度的光，即0-4095灰阶对应的亮度。N比特位数据包括第0比特位的数据至第N-1比特位的数据，每一个比特位的数据均为0或1中的任意一个，其中，第0比特位为最小但最高比特位，第N-1比特位是最大但最低比特位。
步骤S2、将N个比特位的数据依次等分为M组子比特位数据，每一组的子比特位数据均包括N/M个比特位的数据，其中，M为N的正约数且M不为1或N。
具体的，按照比特位由高到低的顺序，将N个比特位的数据中每N/M个比特位的数据划分为一组子比特位数据，并将划分后的各组子比特位数据依次记为第1级子比特位数据、第2级子比特位数据、......、第M级子比特位数据。如将第0-（N/M-1）比特位的数据划分为第一组子比特位数据，记为第1级子比特位数据；将第N/M-（2N/M-1）比特位的数据划分为第二组子比特位数据，记为第2级子比特位数据，依次往后至第M级子比特位数据。其中，第1级子比特位数据的级数最高，第M级子比特位数据的级数最低。
步骤S3、根据每一组子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。
其中，每一组的子比特位数据对应于一个具体电位的驱动电压，由于每一组子比特位数据中包括N/M个比特位的数据，而其中的每一个比特位的数据又选自0和1中的任意一个，相对应的，子比特位数据有2N/M种可能，因此，子比特位数据对应的驱动电压有2N/M种不同的电位。若两个子比特位数据相同，即两个子比特位数据中0和1的数量和排列顺序均相同，则所述两个比特位数据对应的驱动电压相同；若两个子比特位数据不相同，即两个子比特位数据中0和1的数量或排列顺序存在一者相同，则两个比特位数据对应的驱动电压不同。本实施例提供的驱动方法，通过将原始的比特位数据划分为M组子比特位数据，且采用2N/M种不同电位的驱动电压对发光单元进行驱动，发光单元的灰阶级数从原始的单一固定一种，划分为现在的2N/M种，提高了发光单元的灰阶级数，提高了发光单元的亮度深度。
进一步，在本申请实施例中，子比特位数据中N/M个比特位的数据构成的二进制数值越大，所述子比特位数据对应的驱动电压的电位越高。例如子比特位数据（11）构成的二进制数值为11，子比特位数据（10）构成的二进制数值为10，则子比特位数据（11）对应的驱动电压的电位大于子比特位数据（10）对应的驱动电压的电位。由于比特位数据构成的二进制数值越大，该比特位数据对应的灰阶级数越大，例如8比特位数据（00000000）对应于第0级灰阶，8比特位数据（01111111）对应于第127级灰阶，8比特位数据（11111111）对应于第255级灰阶。而灰阶级数越大，对应的发光亮度越大。即对于相同级数的子比特位数据，子比特位数据构成的二进制数值越大，对应的驱动电压越大，则对应的发光亮度越亮。本实施例将子比特位数据构成的二进制数值的大小与驱动电压的电位结合起来，进而将驱动电压与发光亮度结合起来，通过将构成的二进制数值较大的子比特位数据对应的驱动电压的电位设置的较高，凸显了不同子比特位数据在亮度中的权重差异，从而提高了不同灰阶的对比度，进一步提高了发光单元的亮度深度。
其中，每一组的子比特位数据对应于一个驱动时间，M组子比特位数据对应的驱动时间之和为M帧的时间，即一个完整的N比特位数据采用M帧的时间作为一个时间单元进行驱动。本实施例通过采用M帧的时间作为一个时间单元对N比特位数据进行驱动，保证了发光单元具有充足的充电时间，使灰阶级数不再受充电时间的限制，提高了发光单元的灰阶级数，提高了发光单元的亮度深度。
进一步，同一级的子比特位数据对应的驱动时间相同，不同级的子比特位数据对应的驱动时间不同，且子比特位数据的级数越高，子比特位数据对应的驱动时间越长。记第1级子比特位数据、第2级子比特位数据......和第M级子比特位数据对应的驱动时间分别为P1、P2......和PM，P1、P2......和PM满足：P1：P2：......：PM=2（M-1）：2（M-2）：...：20。由于比特位数据的比特位越高，其对灰阶级数的影响越大。例如8比特位数据（00000000）对应于第0级灰阶，8比特位数据（00000001）对应于第1级灰阶；而8比特位数据（01111111）对应于第127级灰阶，8比特位数据（11111111）对应于第255级灰阶。本实施例通过将级数较高的子比特位数据对应的驱动时间设置的较长，进一步凸显了不同子比特位数据在亮度中的权重差异，从而提高了不同灰阶的对比度，进一步提高了发光单元的亮度深度。
在一种实施例中，本申请提供一种驱动电路，用于实施本申请实施例提供的驱动方法中的步骤S1-S3。请参照图3和图4，图3和图4分别示出了本申请实施例提供的驱动电路的两种电路图。如图所示，本申请实施例提供的驱动电路包括：电压输出模块30和发光模块40，电压输出模块30的输出端与发光模块40的驱动电压输入端连接，用于根据驱动数据向发光模块40输出对应的驱动电压，驱动数据包括N个比特位的数据，电压输出模块30包括：2(N/M)条输出支路，任意一条输出支路的输出端与发光模块40的驱动电压输入端连接，不同的输出支路用于对发光模块40输出不同的驱动电压，其中，M为N的正约数且M不为1或N。
本实施例提供的驱动电路，通过增设具有2(N/M)条输出支路的电压输出模块，用于向发光模块输出2(N/M)种不同的驱动电压，采用2N/M种不同电位的驱动电压对发光单元进行驱动，发光单元的驱动电压由原始的一种变为现在的2N/M种，对应的灰阶级数相应的提高为2N/M级，提高了发光单元的灰阶级数，提高了发光单元的亮度深度。
在一种实施例中，电压输出模块30包括至少一个原始电压输入端，且各条输出支路与该原始电压输入端电连接。在一种实施例中，如图3所示，原始电压输入端仅为一个，输出支路包括第一输出支路、第二输出支路......和第2(N/M)输出支路，第一输出支路与原始电压输入端直接连接，第二输出支路通过第一电阻与原始电压输入端连接，......，第2(N/M)输出支路通过第2(N/M)-1电阻、......、第二电阻和第一电阻的串联电路与原始电压输入端连接且接地。在另一种实施例中，如图4所示，始电压输入端为2(N/M)个，包括第一原始电压输入端、第二原始电压输入端、......和第2(N/M)原始电压输入端，输出支路包括第一输出支路、第二输出支路、......和第2(N/M)输出支路，第一输出支路与第一原始电压输入端直接连接，第二输出支路与第二原始电压输入端直接连接，......，第2(N/M)输出支路与第2(N/M)原始电压输入端直接连接。
在一种实施例中，每一输出支路均包括开关控制单元，用于控制输出支路的导通。在一种实施方案中，开关控制单元为拨码开关。在另一种实施例中，开关控制单元包括N/M个串联的开关晶体管，开关控制单元的一端电连接电压输出模块的输出端，另一端电连接原始电压输入端，且任意一条输出支路上的一个开关晶体管的栅极与另外（M/2-1）条输出支路上的一个开关晶体管的栅极电连接且接入一个栅极控制电压，且不与其他开关晶体管的栅极连接。
在一种实施例中，发光模块40包括充电单元、驱动单元、储能单元以及发光单元，充电单元与驱动单元以及储能单元电连接，用于根据扫描信号将数据信号写入储能单元；驱动单元与储能单元、充电单元以及发光单元电连接，用于在储能单元的控制下驱动发光单元工作；储能单元用于存储数据信号，并根据数据信号控制驱动单元的工作状态。具体的，如图3和图4所示，驱动单元为第一薄膜晶体管T1，充电单元为第二薄膜晶体管T2，储能单元为电容器C1，发光单元包括次迷你发光二极管LED。第二薄膜晶体管T2的栅极接入扫描信号Vscan，第二薄膜晶体管T2的第一端接入数据信号Vdata，第二薄膜晶体管T2的第二端与第一薄膜晶体管T1的栅极、电容器C1的第一端连接，第一薄膜晶体管T1的第一端与发光单元LED的输出端连接，第一薄膜晶体管T1的第二端与电容器C1的第二端连接且接入地信号VSS，发光单元LED的输入端与电压输出模块30的输出端连接。
下面将结合具体的实施例对本申请实施例提供的驱动方法及驱动电路进行详细的阐述，以8比特位数据的背光为例。
请参照图2，图2示出了本申请实施例提供的驱动方法的示意图。本实施例中，前端时序控制器Tcon或FPGA提供的8比特驱动数据为B=00011011，其中，第0比特位的数据B[0]=0，第1比特位的数据B[1]=0，第2比特位的数据B[2]=0，第3比特位的数据B[3]=1，第4比特位的数据B[4]=1，第5比特位的数据B[5]=0，第6比特位的数据B[6]=1，第7比特位的数据B[7]=1。其中，B[0]为最高比特位数据，B[7]为最低比特位数据。
按照比特位由高到低的顺序，将原始的8比特位数据中每2个比特位的数据划分为一组子比特位数据，即将原始的8比特位数据划分为四组2比特位数据，如B[0-1]=00，B[2-3]=01，B[4-5]=10，B[6-7]=11。并将第一组子比特位数据B[0-1]记为第1级子比特位数据，第二组子比特位数据B[2-3]记为第2级子比特位数据，第三组子比特位数据B[4-5]记为第3级子比特位数据，第四组子比特位数据B[6-7]记为第4级子比特位数据。其中，第1级子比特位数据B[0-1]的级数为最高，第2级子比特位数据B[2-3]的级数为次高，第3级子比特位数据B[4-5]的级数为次低，第4级子比特位数据B[6-7]的级数最低。
划分后的2比特位数据有00、01、10、11四种不同的选择，每一种2比特位数据对应于一个特定的驱动电压。如当2比特位数据为00时，对应的驱动电压为V1；当2比特位数据为01时，对应的驱动电压为V2；当2比特位数据为10时，对应的驱动电压为V3；当2比特位数据为11时，对应的驱动电压为V4。即子比特位数据B[0-1]的驱动电压为V1，子比特位数据B[2-3]的驱动电压为V2，子比特位数据B[4-5]的驱动电压为V3，子比特位数据B[6-7]的驱动电压为V4。其中驱动电压V4的电位大于驱动电压V3的电位，驱动电压V3的电位大于驱动电压V2的电位，驱动电压V2的电位大于驱动电压V1的电位，驱动电压V1的电位优选为接地电位。
划分后的各组子比特位数据采用独立驱动的方式进行驱动，不同级的子比特位数据对应的驱动时间不同，如图所示，第1级子比特位数据B[0-1]的驱动时间为P1，第2级子比特位数据B[2-3]的驱动时间为P2，第3级子比特位数据B[4-5]的驱动时间为P3，第4级子比特位数据B[6-7]的驱动时间为P4，P1、P2、P3和P4满足P1：P2：P3：P4=23：22：21：20，且P1+P2+P3+P4=一个时间单元（4帧时间）。
如图3所示，电压输出模块30包括一个原始电压输入端，接入原始输入电压V4，还包括一个接地端，接入地电V1，原始电压输入端和接地端之间通过第一电阻R1、第二电阻R2和第三电阻R3串联在一起。第一输出支路包括串联的开关晶体管T9和T10，且直接连接原始电压输入端和驱动模块40的输入端；第二输出支路包括串联的开关晶体管T7和T8，通过第一电阻R1连接原始电压输入端且直接连接驱动模块40的输入端；第三输出支路包括串联的开关晶体管T5和T6，通过第一电阻R1、第二电阻R2连接原始电压输入端且直接连接驱动模块40的输入端；第四输出支路包括串联的开关晶体管T3和T4，通过第一电阻R1、第二电阻R2和第三电阻R3连接原始电压输入端且接地，同时还直接连接驱动模块40的输入端。开关晶体管T3的栅极和开关晶体管T5的栅极连接且接入第一栅极控制电压G1（0），第一栅极控制电压G1（0）对应于2比特位数据的第一位数据0；开关晶体管T7的栅极和开关晶体管T9的栅极连接且接入第二栅极控制电压G1（1），第二栅极控制电压G1（1）对应于2比特位数据的第一位数据1；开关晶体管T4的栅极和开关晶体管T8的栅极连接且接入第三栅极控制电压G2（0），第三栅极控制电压G2（0）对应于2比特位数据的第二位数据0；开关晶体管T6的栅极和开关晶体管T10的栅极连接且接入第四栅极控制电压G2（1），第四栅极控制电压G2（1）对应于2比特位数据的第二位数据1。
如图4所示，电压输出模块30包括四个原始电压输入端，分别接入第一原始输入电压V1、第二原始输入电压V2、第三原始输入电压V3和第四原始输入电压V4，其中第一原始输入电压V1为接地电压。第一输出支路的一端直接接入第四原始电压V4，另一端直接连接驱动模块40的输入端；第二输出支路的一端直接接入第三原始电压V3，另一端直接连接驱动模块40的输入端；第三输出支路的一端直接接入第二原始电压V2，另一端直接连接驱动模块40的输入端；第四输出支路的一端直接接入第一原始电压V1，另一端直接连接驱动模块40的输入端。
在采用如图2所示的驱动电压和驱动时间对发光单元LED进行驱动的过程中，对于第一级子比特位数据B[0-1]=00，开关晶体管T3和开关晶体管T4导通，电压输出模块30通过第四输出支路向驱动模块输入驱动电压V1，在驱动时间P1内驱动发光单元LED发光；对于第二级子比特位数据B[2-3]=01，开关晶体管T5和开关晶体管T6导通，电压输出模块30通过第三输出支路向驱动模块输入驱动电压V2，在驱动时间P2内驱动发光单元LED发光；对于第三级子比特位数据B[4-5]=10，开关晶体管T7和开关晶体管T8导通，电压输出模块30通过第二输出支路向驱动模块输入驱动电压V3，在驱动时间P3内驱动发光单元LED发光；对于第四级子比特位数据B[6-7]=11，开关晶体管T9和开关晶体管T10导通，电压输出模块30通过第一输出支路向驱动模块输入驱动电压V4，在驱动时间P4内驱动发光单元LED发光。
记驱动时间P1为新的第1帧时间，驱动时间P2为新的第2帧时间，驱动时间P3为新的第3帧时间，驱动时间P4为新的第4帧时间。请参照图5，图5示出了本申请实施例提供的驱动方法的效果示意图。如图所示，0灰阶对应的8比特位数据B(0)=00000000，对应的2比特位数据B[0-1]=00，B[2-3]=00，B[4-5]=00，B[6-7]=00，第1帧时间P1内驱动电压V1驱动显示单元LED，显示第一级2比特B[0-1]对应的灰阶，第2帧时间P2内驱动电压V1驱动显示单元LED，显示第二级2比特B[2-3]对应的灰阶，第3帧时间P3内驱动电压V1驱动显示单元LED，显示第三级2比特B[4-5]对应的灰阶，第4帧时间P4内驱动电压V1驱动显示单元LED，显示第四级2比特B[6-7]对应的灰阶。由于人眼的滞后效应和显示装置的高刷新平路，4帧灰阶显示效果相互叠加，等效为0灰阶对应的显示效果。同样的，对于8比特位数据B(63)=00111111，第1帧时间P1内驱动电压V1驱动显示单元LED，第2帧时间P2内驱动电压V4驱动显示单元LED，第3帧时间P3内驱动电压V4驱动显示单元LED，第4帧时间P4内驱动电压V4驱动显示单元LED，4帧灰阶显示效果相互叠加，最后等效为63灰阶的显示效果；对于8比特位数据B(127)=01111111，第1帧时间P1内驱动电压V2驱动显示单元LED，第2帧时间P2内驱动电压V4驱动显示单元LED，第3帧时间P3内驱动电压V4驱动显示单元LED，第4帧时间P4内驱动电压V4驱动显示单元LED，4帧灰阶显示效果相互叠加，最后等效为127灰阶的显示效果；对于8比特位数据B(189)=10111101，第1帧时间P1内驱动电压V3驱动显示单元LED，第2帧时间P2内驱动电压V4驱动显示单元LED，第3帧时间P3内驱动电压V4驱动显示单元LED，第4帧时间P4内驱动电压V2驱动显示单元LED，4帧灰阶显示效果相互叠加，最后等效为189灰阶的显示效果；对于8比特位数据B(255)=11111111，第1帧时间P1内驱动电压V1驱动显示单元LED，第2帧时间P2内驱动电压V4驱动显示单元LED，第3帧时间P3内驱动电压V4驱动显示单元LED，第4帧时间P4内驱动电压V4驱动显示单元LED，4帧灰阶显示效果相互叠加，最后等效为255灰阶的显示效果。这样，通过将原始8比特位数据划分为四组子比特位数据，根据每一子比特位数据，采用对应的驱动电压和驱动时间对发光单元进行驱动，由原始的一种灰阶显示转换为划分后的四种灰阶显示，提高了发光单元的灰阶级数，提高了发光单元的亮度深度。
相应的，本申请实施例还提供一种显示装置，该显示装置包括本申请实施例提供的任意一种驱动电路，具备本申请实施例提供的任意一种驱动电路的技术特征和技术效果，具体实施方式及工作原理请参照上述具体实施例，在此不再赘述。
综上所述，本申请实施例提供一种驱动方法、驱动电路及显示装置，该驱动方法包括以下步骤：获取驱动数据，驱动数据包括N个比特位的数据；将N个比特位的数据依次等分为M组子比特位数据，每一组的子比特位数据均包括N/M个比特位的数据，其中，M为N的正约数且M不为1或N；根据每一组子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。通过将原始N比特位数据划分为M组子比特位数据，根据每一阻子比特位数据，采用对应的驱动电压和驱动时间对发光单元进行驱动，由原始的一种灰阶显示转换为划分后的M种灰阶显示，提高了发光单元的灰阶数量，提高发光单元的亮度深度，满足高阶发光对灰阶深度的要求。
以上对本申请实施例所提供的驱动方法、驱动电路及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动方法，所述驱动方法包括以下步骤：
    获取驱动数据，所述驱动数据包括N个比特位的数据；
    将所述N个比特位的数据依次等分为M组子比特位数据，每一组的所述子比特位数据均包括N/M个比特位的数据，其中，M为N的正约数且M不为1或N；以及
    根据每一组所述子比特位数据，采用对应的驱动电压和对应的驱动时间，驱动对应的发光单元发光。
  2. 如权利要求1所述的驱动方法，其中，所述步骤将所述N个比特位的数据依次等分为M组子比特位数据包括：
    按照比特位由高到低的顺序，将所述N个比特位的数据中每N/M个比特位的数据划分为一组所述子比特位数据；以及
    将划分后的各组所述子比特位数据依次记为第1级子比特位数据、第2级子比特位数据......和第M级子比特位数据。
  3. 如权利要求2所述的驱动方法，其中，所述子比特位数据的级数越大，所述子比特位数据对应的驱动时间越短。
  4. 如权利要求3所述的驱动方法，其中，所述第1级子比特位数据、所述第2级子比特位数据......和所述第M级子比特位数据对应的驱动时间分别为P1、P2......和PM，所述P1、所述P2......和所述PM满足：
    P1：P2：......：PM=2（M-1）：2（M-2）：...：20。
  5. 如权利要求4所述的驱动方法，其中，M组所述子比特位数据对应的驱动时间之和为M帧的时间。
  6. 如权利要求1所述的驱动方法，其中，一组所述子比特位数据对应于一个所述驱动电压。
  7. 如权利要求6所述的驱动方法，其中，所述子比特位数据的数据选自2N/M种不同数据中的一种，所述子比特位数据对应的驱动电压选自2N/M种不同电位的驱动电压中的一种。
  8. 如权利要求7所述的驱动方法，其中，所述子比特位数据中N/M个子比特位的数据构成的二进制数值越大，所述子比特位数据对应的所述驱动电压的电位越高。
  9. 一种驱动电路，用于实施如权利要求1所述的驱动方法中的各个步骤，所述驱动电路包括电压输出模块和发光模块，所述电压输出模块的输出端与所述发光模块的驱动电压输入端连接，用于根据驱动数据向所述发光模块输出对应的驱动电压，所述驱动数据包括N个比特位的数据，所述电压输出模块包括：
    2(N/M)条输出支路，任意一条所述输出支路的输出端与所述发光模块的驱动电压输入端连接，不同的所述输出支路用于对所述发光模块输入不同的驱动电压，所述M为N的正约数且M不为1或N。
  10. 如权利要求9所述的驱动电路，其中，所述电压输出模块包括至少一个原始电压输入端，所述输出支路与所述原始电压输入端电连接。
  11. 如权利要求10所述的驱动电路，其中，所述原始电压输入端仅为一个，所述输出支路包括第一输出支路、第二输出支路......和第2(N/M)输出支路，所述第一输出支路与所述原始电压输入端直接连接，所述第二输出支路通过第一电阻与所述原始电压输入端连接，......，所述第2(N/M)输出支路通过第（2(N/M)-1）电阻、......、所述第二电阻和所述第一电阻的串联电路与所述原始电压输入端连接且接地。
  12. 如权利要求10所述的驱动电路，其中，所述原始电压输入端为2(N/M)个，包括第一原始电压输入端、第二原始电压输入端......和第2(N/M)原始电压输入端，所述输出支路包括第一输出支路、第二输出支路......和第2(N/M)输出支路，所述第一输出支路与所述第一原始电压输入端直接连接，所述第二输出支路与所述第二原始电压输入端直接连接，......，所述第2(N/M)输出支路与所述第2(N/M)原始电压输入端直接连接。
  13. 如权利要求9所述的驱动电路，其中，每一所述输出支路均包括开关控制单元，用于控制所述输出支路的导通。
  14. 如权利要求13所述的驱动电路，其中，所述开关控制单元为拨码开关。
  15. 如权利要求13所述的驱动电路，其中，所述开关控制单元包括N/M个串联的开关晶体管，所述开关控制单元的一端电连接所述电压输出模块的输出端，所述开关控制单元的另一端电连接所述原始电压输入端。
  16. 如权利要求15所述的驱动电路，其中，在任意的M/2条所述输出支路中，每一条所述输出支路上的一个所述开关晶体管的栅极接入同一个栅极控制电压。
  17. 如权利要求9所述的驱动电路，其中，所述发光模块包括充电单元、驱动单元、储能单元以及发光单元，
    所述充电单元与所述驱动单元以及所述储能单元电连接，用于根据扫描信号将数据信号写入所述储能单元；
    所述驱动单元与所述储能单元、所述充电单元以及所述发光单元电连接，用于在所述储能单元的控制下驱动所述发光单元工作；以及
    所述储能单元用于存储所述数据信号，并根据所述数据信号控制所述驱动单元的工作状态。
  18. 一种显示装置，其包括一种驱动电路，所述驱动电路包括电压输出模块和发光模块，所述电压输出模块的输出端与所述发光模块的驱动电压输入端连接，用于根据驱动数据向所述发光模块输出对应的驱动电压，所述驱动数据包括N个比特位的数据，所述电压输出模块包括：
    2(N/M)条输出支路，任意一条所述输出支路的输出端与所述发光模块的驱动电压输入端连接，不同的所述输出支路用于对所述发光模块输入不同的驱动电压，所述M为N的正约数且M不为1或N。
  19. 如权利要求18所述的显示装置，其中，所述电压输出模块包括至少一个原始电压输入端，所述输出支路与所述原始电压输入端电连接。
  20. 如权利要求18所述的显示装置，其中，每一所述输出支路均包括开关控制单元，用于控制所述输出支路的导通。
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