WO2022222046A1 - 半导体器件、电子设备及形成半导体器件的方法 - Google Patents

半导体器件、电子设备及形成半导体器件的方法 Download PDF

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WO2022222046A1
WO2022222046A1 PCT/CN2021/088523 CN2021088523W WO2022222046A1 WO 2022222046 A1 WO2022222046 A1 WO 2022222046A1 CN 2021088523 W CN2021088523 W CN 2021088523W WO 2022222046 A1 WO2022222046 A1 WO 2022222046A1
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semiconductor device
layer
substrate
nucleation layer
forming
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PCT/CN2021/088523
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English (en)
French (fr)
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段焕涛
倪茹雪
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华为技术有限公司
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Priority to PCT/CN2021/088523 priority Critical patent/WO2022222046A1/zh
Priority to CN202180097201.6A priority patent/CN117178369A/zh
Publication of WO2022222046A1 publication Critical patent/WO2022222046A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device, an electronic device including the semiconductor device, and a method for forming the semiconductor device.
  • Gallium Nitride (GaN)-based High Electron Mobility Transistor have the characteristics of high breakdown voltage and high electron mobility. It is more and more widely used in high-power radio frequency devices, high-voltage switching devices and other fields. For example, it has a wide range of applications in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment and other systems.
  • the present application provides a semiconductor device, an electronic device and a method for forming a semiconductor device, and the main purpose is to provide a semiconductor device with better performance.
  • the present application provides a semiconductor device, which can be applied in a radio frequency device, or in a charging device, or in other devices.
  • the semiconductor device includes: a substrate and a formation layer disposed on the substrate, the substrate is a substrate containing silicon, for example, the formation layer here may be made of
  • the IIIA group nitride is formed, and the formation layer includes a nucleation layer, a channel layer and a barrier layer.
  • the nucleation layer is arranged on the substrate, the channel layer is arranged on the nucleation layer, and the barrier layer is arranged on the channel layer.
  • the nucleation layer contains a P-type impurity that can be combined with hydrogen, and the P-type impurity contains elements in the II group, such as magnesium, calcium, etc.;
  • a substance includes a substance obtained by combining an element in group IIIA with hydrogen, for example, the first substance may be a substance obtained by combining Al and hydrogen.
  • the nucleation layer includes a group IIIA nitride
  • the group IIIA species in the nucleation layer is easily diffused into the substrate, such as aluminum (Al), which in turn easily
  • a P-type parasitic channel is formed as an acceptor impurity in a substrate containing a silicon material.
  • the nucleation layer contains P-type impurities, such as magnesium (Mg).
  • P-type impurities such as magnesium (Mg).
  • Mg magnesium
  • the complex that is, the hydrogen species is stabilized in the nucleation layer by the complex formed, and subsequently, during the formation of the rest of the semiconductor device or during the annealing process, the complex formed by the P-type impurity with the hydrogen Due to the high temperature, the chemical bond between the P-type impurity and hydrogen will be broken.
  • the hydrogen species in the free state will diffuse into the substrate, as a donor impurity combined with the acceptor impurity diffused into the substrate to passivate It reduces the acceptor impurities in the substrate, thereby inhibiting the formation of a P-type parasitic channel, or even if a P-type parasitic channel is formed, the conductivity of the formed P-type parasitic channel is very low. performance has little impact.
  • the P-type impurity includes an element in Group IIA.
  • the elements in group IIA are selected as P-type impurities because the elements in group IIA are easily combined with hydrogen species to form complexes, for example, beryllium (Be), magnesium (Mg), calcium (Ca), strontium ( One or a combination of at least two of Sr) and barium (Ba).
  • Be beryllium
  • Mg magnesium
  • Ca calcium
  • strontium One or a combination of at least two of Sr
  • barium barium
  • one or a combination of at least two of zinc (Zn), carbon (C), mercury (Hg), and cadmium (Cd) may be selected.
  • the P-type impurities include magnesium.
  • Mg has a smaller ionization energy than other P-type impurities among P-type impurities, it is easy to be doped, and it is also easy to combine with hydrogen species to form a complex.
  • the ionization energy of the magnesium entering the nucleation layer is higher than that of the IIIA substances in the nucleation layer, so the holes generated by the ionization of Mg are much lower than the actual Mg doping concentration.
  • Mg acts as an acceptor impurity, Due to the presence of dislocations, vacancies and impurities in the nucleation layer, the N-type will be present. In this way, the holes and electrons generated by the ionization of magnesium are compensated, and no conductive channels are introduced into the nucleation layer.
  • the concentration of the P-type impurity may be selected to be less than or equal to 1 ⁇ 10 22 cm ⁇ 3 .
  • a high concentration of P-type impurity doping is required, for example, a high concentration of Mg doping is required.
  • Mg doping due to the limitation of solid solubility, the solubility of Mg in IIIA nitride materials (eg, GaN) is limited, and high doping amounts cannot be achieved.
  • the doping concentration reaches a certain level and the Mg impurity concentration is increased, Mg will combine with the reactive gas nitrogen to form Mg 3 N 2 without entering the GaN lattice, thereby affecting the crystal quality of the GaN material.
  • Mg atoms when the Mg doping concentration is large, Mg atoms will be in the interstitial position between the lattices (the Mg in the interstitial position between the lattices is called Mgi) instead of the substitutional Ga atoms (the Mg substitution of Ga is called as Mgi).
  • MgGa substitution atoms Mgi will form a complex (Mgi-V N ) with a large number of N vacancies (V N ) in the GaN material, which exhibits the characteristics of donors, resulting in the self-compensating effect of Mg atoms .
  • the concentration of P-type impurities is required and cannot be too small. Otherwise, the formation of P-type parasitic channels cannot be suppressed, nor too large, because it will affect the quality of the IIIA nitride nucleation layer and even deteriorate the performance of semiconductor devices.
  • the concentration of the P-type impurity is: less than or equal to 1 ⁇ 10 21 cm ⁇ 3 .
  • the concentration of magnesium can be selected as: 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • the nucleation layer contains a second substance, and the second substance includes a substance obtained by combining an element in group II with hydrogen.
  • the reason for the existence of the second substance is that during the annealing process, the chemical bonds existing in the second substance in the nucleation layer are not completely broken, so that a part of the second substance remains in the nucleation layer.
  • the above-mentioned first substance is located in a region of the substrate close to the nucleation layer.
  • the nucleation layer includes an aluminum nitride AlN material.
  • a P-type impurity capable of combining with hydrogen is doped in the group IIIA nitride nucleation layer including the aluminum nitride AlN material.
  • the lattice arrangement in the group IIIA nitride nucleation layer containing aluminum nitride (AlN) material is not very neat.
  • the purpose of setting the group IIIA nitride nucleation layer is to make the lattice arrangement of the channel layer grown on it more uniform. Neat, the performance of the channel layer is better.
  • the P-type impurities are doped into the IIIA nitride nucleation layer with an irregular lattice, so that the damage to the crystal lattice arrangement in the IIIA nitride nucleation layer is not very serious, and further It has little effect on the performance of the IIIA nitride nucleation layer.
  • the P-type impurities in the IIIA nitride nucleation layer combine with hydrogen to form a complex, and then the chemical bond is destroyed at high temperature, The free hydrogen species will quickly diffuse into the substrate, shortening the diffusion path of the hydrogen species.
  • the channel layer includes a gallium nitride GaN material.
  • the group IIIA nitride nucleation layer including the aluminum nitride AlN material can ensure that the lattice arrangement in the group IIIA nitride channel layer including the gallium nitride GaN material is more orderly, and the channel layer of the group IIIA nitride can be improved.
  • the barrier layer includes an aluminum gallium nitride (AlGaN) material.
  • the group IIIA nitride barrier layer is arranged on the group IIIA nitride channel layer, and the group IIIA nitride barrier layer is used to cooperate with the group IIIA nitride channel layer, so that the group IIIA nitride channel layer is connected to the group IIIA nitride channel layer.
  • the contact region of the IIIA nitride barrier layer generates 2DEG through polarization, thereby conducting current.
  • the semiconductor device further includes: a transition layer, the transition layer is disposed between the nucleation layer and the channel layer, and the transition layer here may also include group IIIA nitrides.
  • the above-mentioned transition layer is a compositionally graded transition layer structure.
  • the present application also provides a method for forming a semiconductor device, the method for forming a semiconductor device comprising:
  • the group IIIA nitride is doped with a P-type impurity, the P-type impurity contains an element in the group II, and in the case where the reaction gas includes hydrogen, a nucleation layer is formed on the substrate containing silicon, so that the nucleation layer Doped with P-type impurities;
  • the structure including the substrate and the nucleation layer is annealed to produce a semiconductor device, and the substrate includes a first substance, and the first substance includes a substance obtained by combining a group IIIA element with hydrogen.
  • the nucleation layer is doped with P-type impurities
  • the carrier gas of the organic metal reaction source for forming the nucleation layer is hydrogen.
  • the P-type impurity can be combined with hydrogen to form a complex, that is, to stabilize the hydrogen in the formed complex; and then perform an annealing process.
  • a nitrogen atmosphere is generally used. Annealing treatment is carried out, as a result, the chemical bond between the P-type impurity and hydrogen will be broken in the complex containing hydrogen species, and the hydrogen species in the free state will diffuse into the substrate as a donor impurity and diffuse into the substrate.
  • the acceptor impurities in the substrate are combined to passivate the acceptor impurities in the substrate, so basically no P-type parasitic channel is formed in the semiconductor device formed by this method, even if a P-type parasitic channel is formed, the formed The conductivity of the P-type parasitic channel is also very low.
  • the P-type impurity is doped in the nucleation layer. Fast entry into the substrate along a short path to suppress the formation of P-type parasitic channels.
  • the ion implantation method requires the IIIA nitride to form a layer. After at least part of the formation, it is taken out from the reaction chamber, and then the ion implantation process is performed.
  • the doping process is performed in the reaction chamber, and the nucleation layer is formed by using In this way, the phenomenon of contamination of the semiconductor device will not be caused by taking out the unmanufactured semiconductor device, and the method provided by the present application does not need to add other additional processes compared with the existing process, and does not require complex Preparation Process.
  • the P-type impurities include elements in Group IIA.
  • the P-type impurities include elements in Group IIA.
  • Be beryllium
  • Mg magnesium
  • Ca calcium
  • strontium Sr
  • Ba barium
  • the concentration of the doped P-type impurities is: less than or equal to 1 ⁇ 10 22 cm ⁇ 3 .
  • the method when the nucleation layer is formed on the surface of the substrate, the method includes: doping a magnesium species (for example, magnesium dimethylocene) for forming the nucleation layer, so that the nucleation layer is doped with magnesium P-type impurity magnesium capable of combining with hydrogen is doped.
  • a magnesium species for example, magnesium dimethylocene
  • Mg has a smaller ionization energy than other P-type impurities among P-type impurities, it is easy to be doped, and it is also easy to combine with hydrogen species to form a complex.
  • the concentration of magnesium is 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • the annealing treatment is performed in an atmosphere including nitrogen.
  • the method further includes: forming a channel layer on the nucleation layer; forming a barrier layer on the I-channel layer .
  • a semiconductor device including a nucleation layer, a channel layer and a barrier layer is formed.
  • the present application also provides an electronic device, comprising a circuit board and a semiconductor device in any implementation manner of the first aspect or a semiconductor device obtained in any implementation manner of the second aspect, the circuit board and the semiconductor device electrical connection.
  • the electronic device provided by the embodiment of the present application includes the semiconductor device prepared by the embodiment of the first aspect or the embodiment of the second aspect. Therefore, the electronic device provided by the embodiment of the present application and the semiconductor device of the above technical solution can solve the same technical problems, and achieve the same expected effect.
  • Fig. 1 is a partial structural schematic diagram of a base station
  • Fig. 2 is the exploded schematic diagram of the partial structure of the mobile phone
  • FIG. 3 is a schematic diagram of a part of the structure of some electronic devices such as a base station or a mobile phone;
  • FIG. 4 is a schematic structural diagram of a semiconductor device
  • FIG. 5 is a schematic structural diagram of another semiconductor device
  • FIG. 6 shows a schematic diagram of forming a P-type parasitic channel in the structure shown in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • FIG. 9 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of suppressing the formation of a P-type parasitic channel according to an embodiment of the application.
  • FIG. 11 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • 11-middle frame 110-frame; 111-carrying board; 12-rear shell; 13-display screen; 01-circuit board; 021-semiconductor device; 022-electrical connection structure; 023-package substrate; 03-another electrical connection structure;
  • An embodiment of the present application provides an electronic device, which may include a communication device (eg, a base station, a mobile phone), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF Induction and microwave heating equipment, etc.
  • a communication device eg, a base station, a mobile phone
  • a wireless charging device e.g., a wireless charging device
  • a medical device e.g., a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF Induction and microwave heating equipment, etc.
  • RF radio frequency
  • the above electronic devices basically include semiconductor devices, such as power amplifiers (PAs).
  • PAs power amplifiers
  • the main function of PAs is to amplify radio frequency signals.
  • Figure 1 shows a simple schematic diagram of the structure of a base station.
  • the base station includes a control unit, and the control unit in the base station includes a wireless transceiver, an antenna and related signal processing circuits, etc., wherein the control unit mainly includes four components: a cell controller, a voice channel controller, and a signaling channel. Controller and multi-port interface for expansion.
  • the control unit of a base station usually controls several base transceiver stations. Through the remote commands of the transceiver station and the mobile station, the control unit of the base station is responsible for all mobile communication interface management, mainly the allocation, release and management of wireless channels.
  • the base station also includes a transmission unit, which is connected to the core network, and the control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and the business is processed.
  • the base station also includes a baseband unit and a radio frequency (RF) unit.
  • the baseband unit mainly performs functions such as baseband modulation and demodulation, radio resource allocation, call processing, power control, and soft handover.
  • the RF unit mainly completes the conversion between the air radio frequency channel and the baseband digital channel, and then amplifies the signal through a power amplifier (PA), and then sends it to the antenna through the radio frequency feeder for transmission.
  • PA power amplifier
  • Terminal equipment such as mobile phones ( mobile phone), tablet computer (pad), etc., receive the radio waves emitted by the antenna through the wireless channel, and then demodulate their own signals.
  • the base station further includes a power supply unit, which can be used to supply power to structures such as a transmission unit, a baseband unit, and a control unit.
  • a power supply unit which can be used to supply power to structures such as a transmission unit, a baseband unit, and a control unit.
  • FIG. 2 shows a structural diagram of another electronic device.
  • the electronic device is a mobile phone as an example.
  • the mobile phone may include a middle frame 11 , a rear case 12 and a display screen 13 .
  • the middle frame 11 includes a carrier board 111 for carrying the display screen 13, and a frame 110 surrounding the carrier board 111.
  • the carrier board 111 carries the RF unit and the PA device. After the PA device amplifies the signal output by the RF unit, It is fed to the antenna in the mobile phone (for example, the antenna may be arranged along the edge of the frame 110) to transmit and receive signals.
  • a laterally-diffused metal-oxide semiconductor (LDMOS)-formed device may be used as the PA, or a gallium arsenide (GaAs)-formed device may be used as the PA.
  • LDMOS laterally-diffused metal-oxide semiconductor
  • GaAs gallium arsenide
  • the requirements for the above-mentioned PA functions to amplify radio frequency signals are also increasing.
  • the communication frequency band of 5G migrates to the high frequency band, for example, to 3GHz to 5GHz.
  • gallium arsenide (GaAs) devices The prominent disadvantage of gallium arsenide (GaAs) devices is low power (for example, the power is usually lower than 50W), and the prominent disadvantage of LDMOS devices is the limitation of operating frequency (operating frequency is generally below 3GHz). Therefore, gallium arsenide (GaAs) devices and LDMOS can no longer meet the needs of 5G communication networks.
  • gallium nitride (GaN) RF power devices not only reflect the high-frequency performance of gallium arsenide devices, but also combine the power processing capabilities of LDMOS devices. , which can better meet the requirements of high communication frequency band and high power of 5G. Therefore, the application range of gallium nitride (GaN) devices is getting wider and wider.
  • the semiconductor device 021 of the above apparatus is carried on a package substrate 023, and the semiconductor device 021 is disposed on the package substrate 023 through an electrical connection structure (eg, a metal layer) 022, so that the semiconductor device 021 can be connected to the package substrate 023.
  • an electrical connection structure eg, a metal layer
  • Other electronic devices on the substrate 023 perform signal interconnection.
  • the package substrate 023 is then disposed on the circuit board 01 through another electrical connection structure 03, such as on a printed circuit board (PCB), where the other electrical connection structure 03 may be a ball grid array , BGA) or other electrical connection structures.
  • PCB printed circuit board
  • the semiconductor device 021 shown in FIG. 3 may include the structure shown in FIG. 4 .
  • FIG. 4 is a cross-sectional structural diagram of a semiconductor device 021, and the semiconductor device 021 includes: a substrate, a GaN layer grown on the substrate, and An aluminum gallium nitride (AlGaN) layer, and source, gate, and drain electrodes disposed over the AlGaN layer.
  • AlGaN aluminum gallium nitride
  • a phenomenon is that at high temperature, silicon (Si) in the substrate easily reacts with gallium (Ga) (which can be called as reflow etching) to form a silicon-gallium eutectic alloy, which in turn makes the GaN layer and AlGaN There are pits on the surface of the layer, or holes in the GaN layer and in the AlGaN layer; another phenomenon is that there is a large lattice mismatch and thermal mismatch between Si and GaN in the substrate, which will Tensile stress is generated in the GaN layer, and a large number of lattice threading dislocations are formed. If these lattice threading dislocations continue to extend toward the surface of the AlGaN layer, cracks will appear on the surface of the AlGaN layer.
  • Ga gallium
  • FIG. 5 is a cross-sectional structure diagram of another semiconductor device 021, in conjunction with FIG. 5, before growing the GaN layer structure on the substrate, aluminum nitride (AlN ) layer, on the one hand, the AlN layer acts as a barrier layer to prevent reflow etching, avoiding the formation of holes and pits, and on the other hand, it can alleviate the lattice mismatch and thermal mismatch between the substrate and GaN.
  • AlN aluminum nitride
  • Al aluminum in the AlN layer tends to diffuse into the silicon substrate, and exists in the substrate as an acceptor impurity (also called a P-type impurity). within a certain range under the bottom surface to form a P-type parasitic channel (as shown by the dashed box in Figure 3).
  • parasitic channels may significantly increase the parasitic loss of the semiconductor device, so when mitigating the effects of parasitic channels in the semiconductor device, or suppressing or When such parasitic channel formation is prevented, parasitic losses in the resulting semiconductor device can be significantly reduced, which can lead to improved performance of the semiconductor device, eg, the semiconductor device has higher output power, power gain, efficiency and other advantages. Also, lower turn-on shifts, turn-on degradations, etc. may be exhibited in some power switching devices.
  • the embodiments of the present application provide a semiconductor device, which can suppress the formation of a P-type parasitic channel, thereby improving the performance of the semiconductor device.
  • FIG. 7 is a cross-sectional view of a semiconductor device 021, the semiconductor device 021 comprising: a substrate 1, a group IIIA nitride formation layer 2 disposed on the surface 101 of the substrate 1, and a group IIIA nitride formed layer 2 A source (Source) 3, a gate (Gate) 4 and a drain (Drain) on the surface of the layer 2 away from the substrate 1 are formed
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the surface 101 of the substrate 1 may be a silicon surface.
  • surface 101 may correspond to the surface of a silicon wafer.
  • surface 101 may correspond to a silicon surface of a composite substrate (eg, including a silicon layer and one or more underlying layers disposed below the silicon layer).
  • surface 101 may correspond to the surface of a silicon portion of a silicon-on-insulator substrate.
  • surface 101 may correspond to the surface of a silicon-on-sapphire substrate.
  • the surface 101 may correspond to the silicon surface of the oxygen implanted isolation substrate.
  • the substrate 1 may be a high-resistance substrate containing silicon, for example, the high-resistance substrate containing silicon may be a substrate structure with a resistivity greater than or equal to 1000 ⁇ cm, or a substrate with a resistivity greater than or equal to 2000 ⁇ cm
  • the bottom structure alternatively, can be a substrate structure greater than or equal to 5000 ⁇ cm.
  • High resistivity substrates containing silicon as described above are particularly useful in devices operating at high frequencies, such as RF devices, for example, high resistivity can reduce substrate losses and optimize semiconductor device performance.
  • the group IIIA nitride formation layer 2 shown in FIG. 7 can be understood in this way.
  • the group IIIA nitride formation layer 2 is made of any IIIA nitride material, and can also be understood to be made of any IIIA element nitride compound.
  • Group IIIA nitride materials may include boron nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), thallium nitride (TIN), and aluminum gallium nitride (AlGaN) ), or a combination of at least two of them, or any alloys that may include Group IIIA and Group VA elements, such as Indium Gallium Nitride (InGaN), Aluminum Indium Gallium Nitride (AlInGaN), Gallium Arsenide Nitride Phosphorus (GaAsPbN), aluminum indium gallium arsenide phosphorus (AlInGaAsPbN), etc.
  • BN boron nitride
  • AlN aluminum nitride
  • GaN gallium nitride
  • InN indium nitride
  • TIN thallium nitride
  • AlGaN
  • the structure that can be realized by the group IIIA nitride formation layer 2 will be described below.
  • a structure of the group IIIA nitride formation layer 2 is given.
  • Layer 2 is not limited to the structure shown in FIG. 7 , and at least one other structure may be added on the basis of the structure shown in FIG. 7 , or some structures may be removed based on the structure shown in FIG. 7 .
  • the group IIIA nitride formation layer 2 includes a nucleation layer 21 , and the nucleation layer 21 can be formed on the surface 101 of the substrate 1 , that is, can directly cover the surface 101 of the substrate 1 .
  • nucleation layer 21 The purpose of providing nucleation layer 21 is that, in some cases, group IIIA nitride materials (eg, gallium nitride or other group IIIA nitrides) may be difficult to heteroepitaxially grow directly on substrate 1 by using A nucleation layer 21 is formed on the nucleation layer 21, and the remaining IIIA nitride material (eg, gallium nitride) is grown on the nucleation layer 21, so that, in some examples, the nucleation layer 21 can be used to alleviate growth in the nucleation layer.
  • group IIIA nitride materials eg, gallium nitride or other group IIIA nitrides
  • the remaining IIIA nitride material eg, gallium nitride
  • the difference between the crystal lattice of the IIIA nitride material on the substrate 1 and the crystal lattice of the substrate 1 under the nucleation layer 21 can also be understood in this way, the crystal lattice of the substrate 1 and the gallium nitride can be alleviated by the nucleation layer 21 Mismatch or thermal mismatch to make the lattice growth of gallium nitride or other group IIIA nitrides more orderly.
  • the nucleation layer 21 may contain an aluminum nitride (AlN) material.
  • Aluminum Nitride (AlN) material can be understood in this way, Aluminum Nitride (AlN) material refers to Aluminum Nitride (AlN) and any alloy thereof, such as Aluminum Gallium Nitride (AlGaN), Aluminum Indium Nitride
  • AlInN Aluminum Indium Gallium Nitride
  • AlInGaN Aluminum Indium Gallium Nitride Arsenic Phosphide
  • AlInGaAsPbN Aluminum Indium Gallium Nitride Arsenic Phosphide
  • AlN aluminum nitride
  • the above-mentioned nucleation layer 21 may include a one-layer structure or at least two-layer structure.
  • these multilayer structures may be made of the same material, or may be made of different materials.
  • different semiconductor growth conditions may be used to form these multilayer structures. Differences in these semiconductor growth conditions may include differences in growth temperature, growth pressure, or reactant flow rates, among others.
  • the IIIA nitride formation layer 2 further includes a transition layer 22 , and the transition layer 22 can be formed on the side of the nucleation layer 21 away from the substrate 1 , that is, formed on the nucleation layer 21 .
  • the transition layer 22 is formed of a compositionally graded Group IIIA nitride material, for example, the transition layer 22 may include AlxGa(1-x)N, where x may be along the growth direction ( That is, as shown in FIG. 7 along the P direction away from the substrate 1 ) gradually decreases, for example, x may decrease from a value of 1 to a value of 0.
  • compositionally graded transition layer 22 may be graded according to the following exemplary regularity.
  • x in the composition of AlxGa(1-x)N is continuously graded from a value of 1 at the lower surface 102 surface of the transition layer 22 to a value of 0 at the upper surface 103 of the transition layer 22 .
  • x in the composition of AlxGa(1-x)N is discontinuously graded from a value of 1 at the surface of the lower surface 102 of the transition layer 22 to a value of 0 at the upper surface 103 of the transition layer 22 .
  • discontinuous grading is performed with AlN, Al0.6Ga0.4N and Al0.4Ga0.6N , and Al0.2Ga0.8N .
  • x in the composition of AlxGa(1-x)N changes parabolically from a value of 1 at the surface of the lower surface 102 of the transition layer 22 to a value of 0 at the surface of the upper surface 103 of the transition layer 22;
  • Other continuous or non-continuous gradient form changes.
  • gallium nitride alloys such as AlxInyGa(1-x-y)N, InyGa(1-y)N, and the like may be selected to form.
  • the elements of the alloy eg, the concentration of at least one of Ga, Al, In, vary along the thickness of the transition layer.
  • the transition layer has an AlxInyGa(1-y)N composition
  • at least one of x and y can be varied.
  • y can be varied.
  • the IIIA nitride formation layer 2 further includes a channel layer 23 , and the channel layer 23 may be formed on the side of the transition layer 22 away from the nucleation layer 21 , that is, formed on the transition layer 22 .
  • the channel layer 23 may contain a gallium nitride (GaN) material.
  • GaN gallium nitride
  • the transition layer 22 of the GaN material is generally doped (for example, doped with elements such as carbon or iron) , the purpose of suppressing leakage is achieved by doping, but the channel layer 23 of GaN material is used to carry current, and a GaN epitaxial layer with high quality and low impurities is required.
  • the IIIA nitride formation layer 2 further includes an insertion layer 24 .
  • the insertion layer 24 may be formed on the side of the channel layer 23 away from the transition layer 22 , that is, formed on the channel layer 23 .
  • the insertion layer 24 may contain an AlN material, and the polarization effect of the AlGaN, AlN, and GaN structures can generate a higher concentration of two-dimensional electron gas, and the infiltration of the two-dimensional electron gas into the barrier layer is reduced, which can be reduced by the insertion layer 24.
  • the random scattering of the alloy increases the mobility, which is beneficial to improve the output characteristics of the device.
  • the IIIA nitride formation layer 2 further includes a barrier layer 25 .
  • the barrier layer 25 may be formed on the side of the insertion layer 24 away from the channel layer 23 , that is, formed on the insertion layer 24 .
  • the barrier layer 25 may include AlGaN material, or may include at least one of AlInN or AlInGaN in combination with AlGaN, wherein the aluminum content in the barrier layer 25 is different from that in the transition layer 22 and the channel layer 23 .
  • the barrier layer 25 is used to match the channel layer 23 to generate a two-dimensional electron gas (2DEG) between the channel layer 23 and the barrier layer 25 through polarization, thereby conducting current.
  • 2DEG two-dimensional electron gas
  • the IIIA nitride formation layer 2 further includes a cap layer 26 , and the cap layer 26 may be formed on the side of the barrier layer 25 away from the insertion layer 24 , that is, formed on the barrier layer 25 .
  • the capping layer 26 comprises a GaN material, where the capping layer comprises GaN, the resulting surface morphology can be smoother with fewer surface defects than a surface formed in the absence of the capping layer.
  • the use of GaN material to terminate the growth of the epitaxial layer also facilitates subsequent chemical treatment of the surface of the epitaxial layer.
  • the substance includes a substance obtained by combining an element in group IIIA with hydrogen, as shown in the circle structure in substrate 1 in FIG. 8 , due to the presence of this substance, a P-type parasitic channel will not be formed.
  • the nucleation layer 21 contains a P-type impurity containing a group II element, as indicated by a black circle in FIG. 8 , and the P-type impurity containing a group II element can combine with hydrogen.
  • FIG. 9 is a process flow diagram of the method for forming the semiconductor device shown in FIG. 8
  • FIG. 10 is a cross-sectional view after each step of the process flow for manufacturing the semiconductor device is completed.
  • Step S1 includes: doping P-type impurities in the IIIA nitride,
  • the P-type impurity contains an element in the group II, and in the case where the reactive gas includes hydrogen gas, the nucleation layer 21 of the group IIIA nitride is formed on the substrate 1 containing silicon, so that the nucleation layer of the group IIIA nitride is formed 21 is doped with P-type impurities.
  • Step S1 will be explained in detail below with reference to FIG. 10 .
  • the P-type impurity of Mg is taken as an example, and when the nucleation layer 21 of group IIIA nitride is formed on the substrate 1 containing silicon, at least one of group II is doped into the In the group IIIA nitride material used for forming the nucleation layer 21 of the group IIIA nitride, and the reaction gas used for growing the nucleation layer 21 of the group IIIA nitride includes hydrogen, so that during the growth process, at least Two phenomena, one phenomenon is shown in (a) of FIG. 10, the IIIA species in the group IIIA nitride diffuses into the substrate 1 containing silicon, such as (a) of FIG. 10, is Take the diffusion of Al towards the substrate 1 as an example.
  • Al acts as an acceptor impurity to form a P-type parasitic channel in the region of the substrate 1 close to the nucleation layer 21 of the group IIIA nitride, as shown in FIG. 10(a).
  • the region shown with black dots represents the P-type parasitic channel; another phenomenon is shown in (a) of Fig. 10, the P-type impurity Mg combines with H to form a complex, which can It is represented by Mg-H.
  • Fig. 10 only takes the P-type impurity of Mg as an example to illustrate, in addition to Mg, at least one of the II group can also be used, for example, beryllium (Be), magnesium (Mg), calcium in the IIA group can be used (Ca), strontium (Sr), barium (Ba) one or a combination of at least two; for another example, zinc (Zn), carbon (C), mercury (Hg), cadmium (Cd) in the IIB group can be used ) or a combination of at least two of them; for another example, beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), carbon (C) can be used ), a combination of at least two of mercury (Hg), cadmium (Cd).
  • Be beryllium
  • Mg magnesium
  • calcium in the IIA group can be used
  • strontium (Sr) barium
  • Ba zinc (Zn) in the IIB group
  • the material forming the nucleation layer 21 is doped with Mg impurities, for example, magnesium bismuthcene (C 10 H 10 Mg) and the like may be doped.
  • Mg impurities for example, magnesium bismuthcene (C 10 H 10 Mg) and the like may be doped.
  • step S2 in FIG. 9 and (b) in FIG. 10 is the structure diagram after step S2 is completed.
  • the structure of the nucleation layer 21 is annealed to obtain a semiconductor device, and the region of the substrate 1 close to the nucleation layer 21 of the group IIIA nitride contains a first substance, and the first substance includes a substance in the group IIIA and Substances obtained by hydrogen bonding.
  • Step S2 will be explained in detail below with reference to FIG. 10 .
  • a P-type parasitic channel is formed in a region of the substrate 1 close to the nucleation layer 21 of the group IIIA nitride, and in the formation of the group IIIA nitride
  • the region of the core layer 21 close to the substrate 1 contains at least one substance in the II group formed by combining with hydrogen, for example, a complex formed by combining magnesium and hydrogen.
  • step S2 On the basis of the completion of step S1, when step S2 is performed again, as shown in (b) of FIG. 10 , during the annealing process, the complex formed by the P-type impurity and hydrogen occurs between the P-type impurity and the hydrogen.
  • the chemical bond is broken, for example, the chemical bond between Mg and H in the Mg-H complex shown in Fig. 10(b) is broken, and then H becomes a free state.
  • an acceptor impurity for example, Al
  • a P-type impurity containing at least one of Group II is formed in the nucleation layer 21. Since the lattice arrangement in the nucleation layer 21 is not very neat, the purpose of providing the nucleation layer is to allow the grooves grown thereon. The lattice arrangement of the channel layer is more orderly, and the performance of the channel layer is better. In the embodiment of the present application, the nucleation layer 21 whose lattice is not very neat is doped with a P-type impurity containing at least one of group II, so that the lattice arrangement in the nucleation layer 21 is not very damaged. Indeed, and thus have little effect on the performance of the nucleation layer 21 .
  • the free hydrogen species in the substrate 1 will quickly diffuse into the substrate 1 , shorten the diffusion path of hydrogen species, it can also be understood that in unit time, more hydrogen species will diffuse into the substrate to passivate the acceptor impurities in the substrate and suppress the formation of P-type parasitic channels .
  • the nucleation layer 21 is doped with a P-type impurity containing at least one of group II.
  • the transition layer 22 above the nucleation layer 21 is n-type or high-resistance type, the diffusion coefficient of hydrogen species in the substrate 1 containing silicon is much higher than that in n-type or high-resistance nitride, so the hydrogen species will diffuse into the substrate 1 containing silicon to passivate chemical acceptor impurities.
  • a P-type impurity comprising at least one of Group II is doped into the Group IIIA nitride, and the P-type impurity is combined with the reactive gas hydrogen to form a complex
  • annealing is performed. During the annealing process, the chemical bonds in the complex are destroyed, the hydrogen species is released in a free state, and the free hydrogen species will diffuse into the substrate 1 , to passivate the acceptor impurities that can form the P-type parasitic channel, thereby suppressing the formation of the P-type parasitic channel.
  • the hydrogen species can be implanted into the substrate 1 containing silicon by ion implantation, which can be implemented by, when at least part of the substrate 1 is completed. After the group IIIA nitride layer 2 is formed, it is taken out of the reaction chamber and hydrogen species is injected, which is likely to cause pollution and affect the performance of the semiconductor device.
  • the method for forming a semiconductor device provided by the embodiments of the present application, it is not necessary to take out the nucleation layer 21 from the reaction chamber before forming the nucleation layer 21, but the formation of the nucleation layer 21 is always completed in the reaction chamber.
  • the present application utilizes the reaction gas hydrogen in the reaction chamber to suppress the formation of the P-type parasitic channel, and does not require an additional process for providing hydrogen substances.
  • the ions When the hydrogen species is implanted by the ion implantation method, the ions are accelerated into an ion beam having a predetermined energy and then guided to the surface of the semiconductor substrate.
  • the high-energy ions in the ion beam are doped into the semiconductor material and embedded into the crystal lattice of the semiconductor material, that is to say, ion implantation will introduce a greater ability, which may damage the lattice compared to the solution of the present application. Arrange.
  • Mg can be selected as a P-type impurity to be doped in the nucleation layer 21, because Mg in the P-type impurity has a smaller ionization energy than other P-type impurities, is easy to dope, and is also very It is easy to combine with hydrogen species to form complexes.
  • the ionization energy of the magnesium entering the nucleation layer 21 is higher than that of the IIIA substances in the nucleation layer 21, such as Al, so the holes generated by the ionization of Mg are much lower than the actual Mg doping concentration.
  • Mg acts as an acceptor impurity, and the nucleation layer 21 will present an N-type due to the existence of dislocations, vacancies and impurities. In this case, the holes and electrons generated by the ionization of magnesium are compensated and will not be introduced into the nucleation layer 21.
  • Conductive channel is provided.
  • the concentration of the P-type impurity may be selected to be less than or equal to 1 ⁇ 10 22 cm ⁇ 3 .
  • Mg as a doping impurity
  • a high-concentration P-type impurity doping is required, for example, a high-concentration Mg doping is required.
  • Mg in IIIA nitride materials eg, GaN
  • high doping amounts cannot be achieved.
  • Mg atoms when the Mg doping concentration is large, Mg atoms will be in the interstitial position between the lattices (the Mg in the interstitial position between the lattices is called Mgi) instead of the substitutional Ga atoms (the Mg substitution of Ga is called as Mgi).
  • MgGa substitution atoms Mgi will form a complex (Mgi-VN) with a large number of N vacancies (V N ) in GaN materials, which exhibits the characteristics of donors, leading to the self-compensation effect of Mg atoms.
  • the concentration of P-type impurities is required and cannot be too small. Otherwise, the formation of P-type parasitic channels cannot be suppressed, and it cannot be too large, because it will affect the quality of the IIIA nitride formation layer and even deteriorate the semiconductor. device performance.
  • the concentration of magnesium when Mg is selected as the doping impurity, can be selected as: 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 ; or, the concentration of magnesium can be selected as: 5 ⁇ 10 18 cm -3 to 1 ⁇ 10 21 cm -3 .
  • a method for preparing a semiconductor device is given below, and the method includes a method for forming a specific layer structure of the group IIIA nitride formation layer 2 .
  • FIG. 11 is a process flow diagram of a method for forming the semiconductor device
  • FIG. 12 is a cross-sectional view after each step of the process flow for manufacturing the semiconductor device is completed.
  • Step S01 in FIG. 11, and (a) in FIG. 12, (a) in FIG. 12 is a structural diagram after step S01 in FIG. 11 is executed.
  • step S01 of FIG. 11 and (a) of FIG. 12 the growth of the Mg-doped nucleation layer 2 is performed on the substrate 1 containing silicon.
  • the reaction gas includes ammonia gas and hydrogen gas
  • the reactants include trimethylaluminium (trimethylaluminium) and magnesium bismuth
  • the reaction temperature is about 1100°C
  • the final molding The thickness of the nucleation layer 21 is about 50 nm to 500 nm, such as 300 nm.
  • Mg doping may be doped in the entire growth process of the nucleation layer 21 , for example, Mg2C is doped, or Mg doping may be doped during the preceding growth process of the nucleation layer 21 .
  • MgO can be doped, and no MgO is needed during the formation of the latter 200 nm nucleene layer.
  • the Mg doping when Mg doping is doped, can be selected to be 5 ⁇ 10 19 cm ⁇ 3 . Also, 5 ⁇ 10 19 cm ⁇ 3 here is just an exemplary optional concentration value.
  • the substrate 1 Before growing the nucleation layer 21 on the substrate 1, the substrate 1 can also be deoxidized.
  • the substrate 1 can be placed in a growth chamber, and hydrofluoric acid is used for high-temperature surface cleaning to remove the substrate. 1 oxide layer on the surface.
  • the atmosphere may include hydrogen, the temperature is 1100° C., and the time is about 5 minutes.
  • reaction temperature and reaction time are only an exemplary illustration, and the substrate 1 can be chemically cleaned at other suitable reaction temperatures and reaction times.
  • Al will gradually diffuse into the substrate 1.
  • the Al is basically located in the region of the substrate 1 close to the nucleation layer 21, and Al as an acceptor impurity forms a P-type parasitic channel in the substrate 1 .
  • the Mg doping in the nucleation layer 21 is combined with the hydrogen gas in the reaction gas and exists in the nucleation layer 21 in the form of a complex.
  • step S02 in FIG. 11 is performed, and (b) in FIG. 12 is a structural diagram after step S02 in FIG. 11 is performed.
  • step S02 of FIG. 11 and (b) of FIG. 12 the growth of the transition layer 22 is performed.
  • the reaction gas includes ammonia gas and hydrogen gas, and the reactant includes trimethyl aluminum and trimethyl gallium; the reaction temperature is about 1100°C.
  • the thickness of the finally formed transition layer 22 is about 100 nm to 5000 nm, for example, it can be 1000 nm.
  • the transition layer 22 formed here is a multi-layer AlxGa(1-x)N structure, and the formed multi-layer AlxGa(1-x)N structure can be referred to as the first layer of AlxGa(1-x)N along the direction away from the substrate 1 respectively.
  • -x)N structure second-layer AlxGa(1-x)N structure, third-layer AlxGa(1-x)N structure, etc.
  • the thickness of each layer can be selected as: the thickness of the first layer of AlxGa(1-x)N structure is 330nm, the thickness of the second layer of AlxGa(1-x)N The thickness of the structure is 330 nm, and the thickness of the third-layer AlxGa(1-x)N structure is 340 nm.
  • these composition data and thickness data are only illustrative.
  • step S03 in FIG. 11 is executed
  • step S03 in FIG. 11 is executed
  • step Sc) in FIG. 12 is a structural diagram after step S03 in FIG. 11 is executed.
  • step S03 of FIG. 11 and (c) of FIG. 12 the growth of the channel layer 23 is performed.
  • the reactant gas includes ammonia gas and hydrogen gas, and the reactant includes trimethyl gallium (trimethyl gallium); the reaction temperature is about 1050°C.
  • the thickness of the formed channel layer 23 is substantially 100 nm to 500 nm.
  • step S04 in FIG. 11 is executed, and (d) in FIG. 12 is a structural diagram after step S04 in FIG. 13 is executed.
  • step S04 of FIG. 11 and (d) of FIG. 12 the growth of the insertion layer 24 is performed.
  • the reaction gas includes ammonia gas and hydrogen gas, and the reactant includes trimethylaluminum.
  • the reaction temperature is about 1050°C.
  • the thickness of the formed channel layer 23 is substantially 0.2 nm to 2 nm, for example, it may be 0.7 nm.
  • step S05 in FIG. 11 is executed
  • step S05 in FIG. 11 is executed
  • step S05 in FIG. 11 is executed
  • step S05 in FIG. 12 is a structural diagram after step S05 in FIG. 11 is executed.
  • the growth of the barrier layer 25 is performed in step S05 of FIG. 11 and (e) of FIG. 12 .
  • the reactive gases include ammonia gas and hydrogen gas, and the reactants include trimethyl aluminum and trimethyl gallium.
  • the reaction temperature is about 1050°C.
  • the thickness of the formed barrier layer 25 is substantially 10 nm to 60 nm, for example, may be 30 nm.
  • the barrier layer 25 formed here has an AlxGa(1-x)N structure, where x can be about 0.2.
  • step S06 in FIG. 11 is executed
  • step Sf in FIG. 12 is a structural diagram after step S06 in FIG. 11 is executed.
  • the growth of the cap layer 26 is performed in step S06 of FIG. 11 and (f) of FIG. 12 .
  • the reactant gas includes ammonia gas, hydrogen gas, and the reactant includes trimethylgallium.
  • the reaction temperature is about 1050°C.
  • the thickness of the formed cap layer 26 is substantially 0.1 nm to 10 nm, for example, it may be 1 nm.
  • the Mg impurities in the nucleation layer 21 and the hydrogen gas are continuously combined with chemical bonds, As well as the breaking of chemical bonds, however, the number of bonds will be relatively greater than the number of cracks.
  • step S07 in FIG. 11 is executed.
  • step S07 in FIG. 11 annealing treatment is performed.
  • the structure of substrate 1 and epitaxial layer 2 containing silicon can be taken out from the growth chamber, A tube furnace is used for annealing treatment, the annealing atmosphere includes nitrogen, the temperature is 600°C to 900°C, such as about 800°C, and the annealing time is 1min to 180min, such as about 45min.
  • the annealing treatment can also be carried out in an annealing furnace, the atmosphere is a gas that does not contain hydrogen, for example, it can include nitrogen, air, argon or a mixed gas thereof, the reaction temperature is 600 °C to 1000 °C, and the reaction time is 1min to 180min .
  • the annealing process since the annealing process is performed in an atmosphere that does not contain hydrogen, the chemical bond in the complex formed by the Mg impurities in the nucleation layer 21 and the hydrogen is destroyed, and the hydrogen species will be in the form of a free state. In this case, free hydrogen will diffuse into the substrate 1, and the donor impurities will combine with the acceptor impurities in the substrate 1, thereby destroying the previously formed P-type parasitic channel.
  • step S08 in FIG. 11 and (g) in FIG. 12 are performed.
  • a source electrode, a gate electrode and a drain electrode are formed to form a semiconductor device.
  • the structure shown in FIG. 13 is a structural diagram of the semiconductor device obtained by the above method.
  • the substance Including a substance obtained by combining an element in group IIIA with hydrogen as shown in the circle structure in the substrate 1 in FIG.
  • there may also be substances obtained by combining the elements of group II with hydrogen in the nucleation layer 21 such as the complex of magnesium and hydrogen. This is because the above-mentioned In the annealing process of , it is possible that the group II substances in the nucleation layer 21 combined with hydrogen are not completely broken, and a part remains, and then the structure shown in FIG. 13 will appear.

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Abstract

本申请实施例提供一种半导体器件、电子设备和形成半导体器件的方法，涉及半导体技术领域，该半导体器件的形成方法与现有工艺兼容程度较高。该半导体器件包括衬底和设置在衬底上的成核层，该衬底是包含硅的衬底。其中，成核层包含有能够与氢结合的P型杂质，且该P型杂质包含II族中的元素，比如，可以包括镁、钙等；还有，衬底中包含有第一物质，该第一物质包括IIIA族中的元素与氢结合得到的物质，例如，第一物质可以是Al与氢相结合得到的物质。由于在衬底中具有第一物质，进而会扼制P型寄生沟道的形成。

Description

半导体器件、电子设备及形成半导体器件的方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件、包含该半导体器件的电子设备及形成该半导体器件的方法。
背景技术
基于化合物半导体材料制得的半导体器件，比如，氮化镓(Gallium Nitride，GaN)基高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)，由于具有高击穿电压、高电子迁移率的特性，越来越多地被高功率射频器件、耐高压开关器件等领域广泛采用，比如，在雷达、无线通信、导航、卫星通讯、电子对抗设备等系统中有着广泛的应用。
但是，目前的基于化合物半导体材料的半导体器件性能还不是很理想，比如，输出功率、开关速度、功率增益和效率等，还需要进一步的优化。
发明内容
本申请提供一种半导体器件、电子设备及形成半导体器件的方法，主要目的是提供一种性能更优的半导体器件。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种半导体器件，该半导体器件可以被应用在射频器件中，或者被应用在充电器件中，或者被应用在其他器件中。该半导体器件包括：衬底和设置在衬底上的形成层，该衬底是包含硅的衬底，比如，这里的形成层可以是由
IIIA族氮化物形成，形成层包括成核层、沟道层和势垒层，成核层设置在衬底上，沟道层设置在成核层上，势垒层设置在沟道层上。其中，成核层包含有能够与氢结合的P型杂质，该P型杂质包含II族中的元素，比如，可以包括镁、钙等；还有，衬底中包含有第一物质，该第一物质包括IIIA族中的元素与氢结合得到的物质，例如，第一物质可以是Al与氢相结合得到的物质。
在包含有成核层的半导体器件中，比如，该成核层包括IIIA族氮化物，这样的话，成核层中的IIIA族物质容易朝衬底中扩散，比如，铝(Al)，进而容易在包含有硅材料的衬底中作为受主杂质形成P型寄生沟道。
而本申请实施例提供的半导体器件中，在成核层中包含有P型杂质，比如，包含镁(Mg)，该P型杂质在该半导体器件形成过程中，可以与反应气体氢气结合，形成络合物，也就是通过形成的络合物将氢物质稳定在该成核层中，随后，在半导体器件的其余部分的形成过程中或者退火工艺中，P型杂质与氢形成的络合物会因为高温而使P型杂质与氢之间的化学键打破，这样的话，呈游离态的氢物质就会扩散至衬底中，作为施主杂质与扩散至衬底中的受主杂质相结合，以钝化衬底中的受主杂质，进 而，会抑制P型寄生沟道的形成，或者即使形成了P型寄生沟道，形成的P型寄生沟道的电导率也是很低的，对该半导体器件的性能影响不大。
在第一方面可能的实现方式中，P型杂质包含IIA族中的元素。
选择IIA族中的元素作为P型杂质，是因为IIA族中的元素容易与氢物质结合，形成络合物，比如，可以选择铍(Be)、镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)中的一种或者至少两种的组合。
另外，P型杂质也可以选择锌(Zn)、碳(C)、汞(Hg)、镉(Cd)中的一种或者至少两种的组合。
在第一方面可能的实现方式中，P型杂质包括镁。
因为在P型杂质中Mg相比其他P型杂质的电离能小，容易掺杂，并且也很容易与氢物质结合形成络合物。
除此之外，就是进入成核层的镁相比成核层中的IIIA族物质的电离能高，所以Mg电离产生的空穴比实际Mg掺杂的浓度低很多，Mg作为受主杂质，成核层中由于位错、空位和杂质的存在会呈现出N型，这样的话，镁电离产生的空穴与电子相补偿，进而不会在成核层中引入导电通道。
在第一方面可能的实现方式中，P型杂质的浓度可以选择为：小于或者等于1×10 22cm -3。
为了实现高空穴浓度的P型材料，就需要高浓度的P型杂质掺杂，比如，需要高浓度的Mg掺杂。而受固溶度的限制，Mg在IIIA族氮化物材料(比如，GaN)中的溶解度是有限的，无法达到高掺入量。当掺杂浓度达到一定程度后，再增加Mg杂质浓度，Mg会与反应气体氮气结合形成Mg 3N 2而不会进入GaN晶格,进而影响GaN材料的晶体质量。并且当Mg掺杂浓度很大时，Mg原子会处于晶格之间的间隙位置(把处于晶格之间的间隙位置的Mg称为Mgi)而不是替位Ga原子(把Mg取代Ga称为MgGa替位原子)，Mgi会和GaN材料中大量的N空位(vacancy，V N)组成络合物(Mgi-V N)，该络合物表现出施主的特性，导致Mg原子的自补偿效应。
所以，对于P型杂质的浓度是有要求的，不能太小，否则，无法抑制P型寄生沟道的形成，也不能太大，因为会影响IIIA族氮化物成核层的质量，甚至恶化该半导体器件的性能。
在第一方面可能的实现方式中，进一步的，P型杂质的浓度为：小于或者等于1×10 21cm -3。
在第一方面可能的实现方式中，当P型杂质选择镁(Mg)时，镁的浓度可以选择为：1×10 18cm -3至1×10 21cm -3。
在第一方面可能的实现方式中，成核层中包含有第二物质，第二物质包括II族中的元素与氢结合得到的物质。
存在第二物质的原因是：在进行退火工艺时，存在于成核层的第二物质内的化学键没有被完全打破，进而会剩余一部分存在在成核层中。
在第一方面可能的实现方式中，上述的第一物质位于衬底的靠近成核层的区域中。
在第一方面可能的实现方式中，成核层包括氮化铝AlN材料。
也就是说，将能够与氢结合的P型杂质掺杂在包含氮化铝AlN材料的IIIA族氮化物成核层中。在包含氮化铝AlN材料的IIIA族氮化物成核层中晶格排布不是很整齐，设置IIIA族氮化物成核层的目的是让生长在其上的沟道层的晶格排布更加整齐，沟道层的性能更好。在本申请实施例中，将P型杂质掺杂在晶格不是很整齐的IIIA族氮化物成核层中，对该IIIA族氮化物成核层中的晶格排布破坏不是很严重，进而对IIIA族氮化物成核层的性能影响很小，除此之外，位于IIIA族氮化物成核层中的P型杂质与氢结合形成络合物后，再在高温下化学键被破坏后，游离的氢物质会很快的扩散至衬底中，缩短氢物质的扩散路径，也可以这样理解，在单位时间内，会有更多的氢物质扩散至衬底中，衬底中的更多的受主杂质被氢物质钝化的，抑制P型寄生沟道的形成。还有，氮化铝成核层中的铝物质会作为受主杂质扩散至衬底中，铝与游离的氢物质很容易结合，形成稳定的络合物。
在第一方面可能的实现方式中，沟道层包括氮化镓GaN材料。
可以这样理解，包含氮化铝AlN材料的IIIA族氮化物成核层可以保障包括氮化镓GaN材料的IIIA族氮化物沟道层中的晶格排布更加整齐，提高该IIIA族氮化物沟道层中二维电子气(two-dimensional electron gas，2DEG)的密度和迁移率。
在第一方面可能的实现方式中，势垒层包括氮化铝镓AlGaN材料。
比如，将IIIA族氮化物势垒层设置在IIIA族氮化物沟道层的上面，IIIA族氮化物势垒层用于配合IIIA族氮化物沟道层，以在IIIA族氮化物沟道层与IIIA族氮化物势垒层相接区域通过极化作用产生2DEG，从而导通电流。
在第一方面可能的实现方式中，该半导体器件还包括：过渡层，过渡层设置在成核层和沟道层之间，这里的过渡层也可以包括IIIA族氮化物。
在第一方面可能的实现方式中，上述的过渡层是一种组分渐变(compositionally graded)的过渡层结构。
第二方面，本申请还提供了一种形成半导体器件的方法，该半导体器件的形成方法包括：
在IIIA族氮化物中掺杂P型杂质，P型杂质包含II族中的元素，并在反应气体包括氢气的情况下，在包含有硅的衬底上形成成核层，以使成核层中掺杂有P型杂质；
对包含有衬底和成核层的结构进行退火处理，以制得半导体器件，且衬底中包含有第一物质，第一物质包括IIIA族中的元素与氢结合得到的物质。
本申请提供的半导体器件的形成方法中，由于在成核层中掺杂了P型杂质，并且形成该成核层的有机金属反应源载气为氢气。这样的话，该P型杂质能够与氢气相结合，形成络合物，也就是把氢气稳定在形成的络合物中；然后再进行退火工艺，在退火的过程中，一般采用氮气的氛围气体中进行退火处理，如此一来，包含有氢物质的络合物会出现P型杂质与氢之间的化学键破裂，呈游离态的氢物质就会扩散至衬底中，作为施主杂质与扩散至衬底中的受主杂质相结合，以钝化衬底中的受主杂质，所以采用该种方法形成的半导体器件中基本不会形成P型寄生沟道，即使形成有P型寄生沟道，形成的P型寄生沟道的电导率也是很低的。
还有，通过在形成成核层的材料中掺杂P型杂质，以将P型杂质掺杂在成核层 中，当P型杂质与氢结合得到的络合物发生化学键破裂后，氢可以沿着较短的路径快速的进入衬底中，以抑制P型寄生沟道的形成。
另外，由于P型杂质进入成核层的方式是通过将P型杂质掺杂在IIIA族氮化物材料而进入，而不是通过离子注入等方式，离子注入法是需要将IIIA族氮化物形成层的至少部分形成后，再将其从反应室中取出，再进行离子注入工艺，但是，本申请提供的形成半导体器件的方法中，是在反应室中进行掺杂工艺，并利用了形成成核层的氢气，这样不会因为要将未制成的半导体器件取出，而对半导体器件造成污染的现象，且本申请提供的方法相比现有的工艺无需再增加其他额外的工艺，不需在复杂制备工艺。
在第二方面可能的实现方式中，在IIIA族氮化物中掺杂P型杂质时，P型杂质包含IIA族中的元素。比如，可以选择铍(Be)、镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)中的一种或者至少两种的组合。
在第二方面可能的实现方式中，在IIIA族氮化物中掺杂P型杂质时，掺杂的P型杂质的浓度为：小于或者等于1×10 22cm -3。
采用该浓度的P型杂质既可以抑制P型寄生沟道的形成，也不会影响IIIA族氮化物成核层的质量。
在第二方面可能的实现方式中，在衬底的表面上形成成核层时，包括：在用于形成成核层中掺杂镁物质(比如，二茂镁)，以在成核层中掺杂能够与氢结合的P型杂质镁。
因为在P型杂质中Mg相比其他P型杂质的电离能小，容易掺杂，并且也很容易与氢物质结合形成络合物。
在第二方面可能的实现方式中，在用于形成成核层的材料中掺杂镁物质时，镁的浓度为：1×10 18cm -3至1×10 21cm -3。
在第二方面可能的实现方式中，在对包含有衬底和成核层的结构进行退火处理时，在包括氮气的气氛中进行退火处理。
可以这样理解，在气氛为氮气，而没有氢气的环境中进行退火处理时，P型杂质与氢结合得到的络合物的化学键会不断的破裂，以使氢物质呈游离态。
在第二方面可能的实现方式中，在衬底上形成成核层之后，在进行退火处理之前，方法还包括：在成核层上形成沟道层；在I沟道层上形成势垒层。
这样就形成了包含成核层、沟道层和势垒层的半导体器件。
第三方面，本申请还提供了一种电子设备，包括电路板和上述第一方面任一实现方式中的半导体器件或者上述第二方面任一实现方式制得的半导体器件，电路板与半导体器件电连接。
本申请实施例提供的电子设备包括第一方面实施例或者第二方面实施例制得的半导体器件，因此本申请实施例提供的电子设备与上述技术方案的半导体器件能够解决相同的技术问题，并达到相同的预期效果。
附图说明
图1为基站的部分结构示意图；
图2为手机的部分结构的爆炸示意图；
图3为基站或者手机等一些电子设备中的部分结构示意图；
图4为一种半导体器件的结构示意图；
图5为另一种半导体器件的结构示意图；
图6示出了图5所示结构中形成P型寄生沟道的原理图；
图7为本申请实施例的一种半导体器件的结构示意图；
图8为本申请实施例的一种半导体器件的结构示意图；
图9为本申请实施例的半导体器件的形成方法的流程框图；
图10为本申请实施例的一种抑制P型寄生沟道形成的原理图；
图11为本申请实施例的半导体器件的形成方法的流程框图；
图12为本申请实施例制得半导体器件的方法中各步骤完成后相对应的结构示意图；
图13为本申请实施例的一种半导体器件的结构示意图。
附图标记：
11-中框；110-边框；111-承载板；12-后壳；13-显示屏；01-电路板；021-半导体器件；022-电连接结构；023-封装基板；03-另一电连接结构；
1-衬底；2-IIIA族氮化物形成层；3-源极；4-栅极；5-漏极；21-成核层；22-过渡层；23-沟道层；24-插入层；25-势垒层；26-帽层。
具体实施方式
本申请实施例提供一种电子设备，该电子设备可以包括通信设备(比如，基站、手机)、无线充电设备、医疗设备、雷达、导航设备、射频(radio frequency，RF)等离子体照明设备、RF感应和微波加热设备等。本申请实施例对上述电子设备的具体形式不做特殊限制。
上述电子设备中，基本都包括半导体器件，比如，包括功率放大器(power amplifier，PA)，PA的主要作用是放大射频信号，以基站为例，图1给出了一种基站的简单的结构示意图，该基站包括控制单元，基站中的控制单元包括无线收发信机、天线和有关的信号处理电路等，其中，该控制单元主要包括四个部件：小区控制器、话音信道控制器、信令信道控制器和用于扩充的多路端接口。一个基站的控制单元通常控制几个基站收发台，通过收发台和移动台的远端命令，基站的控制单元负责所有的移动通信接口管理，主要是无线信道的分配、释放和管理等。
继续结合图1，该基站还包括传输单元，此传输单元与核心网连接，核心网侧的控制信令、语音呼叫或数据业务信息通过传输单元发送到基站的控制单元中，通过控制单元对这些业务进行处理。
再结合图1，该基站还包括基带单元和射频(radio frequency，RF)单元，基带单元主要是完成基带的调制与解调、无线资源的分配、呼叫处理、功率控制与软切换等功能。RF单元主要是完成空中射频信道和基带数字信道之间的转换，再经过功率放大器(power amplifier，PA)对信号的放大处理，然后通过射频馈线送到天线上进行发射，终端设备，比如手机(mobile phone)、平板电脑(pad)等，通过无线信道接收 天线所发射的无线电波，然后解调出属于自己的信号。
继续结合图1，该基站还包括供电单元，此供电单元可以用于对传输单元、基带单元、控制单元等结构进行供电。
图2给出了另一种电子设备的结构图，该电子设备以手机为例，该手机可以包括中框11、后壳12以及显示屏13。该中框11包括用于承载显示屏13的承载板111，以及绕承载板111一周的边框110，承载板111上承载有RF单元和PA器件，PA器件对RF单元输出的信号进行放大后，馈送至手机中的天线上(比如，天线可以沿边框110的边缘设置)，以收发信号。
在一些实施方式中，可采用横向扩散金属氧化物半导体(laterally-diffused metal-oxide semiconductor，LDMOS)形成的器件作为PA，或者采用砷化镓(GaAs)形成的器件作为PA。
随着第四代移动通信技术(4rd generation of wireless communications technologies，4G)向第五代移动通信技术(5rd generation of wireless communications technologies，5G)的发展，对上述的PA的放大射频信号功能要求也越来越高，比如，相比于4G网络通信，5G的通信频段往高频波段迁移，例如，向3GHz至5GHz迁移。
砷化镓(GaAs)器件突出的劣势为功率较低(例如，功率通常低于50W)，LDMOS器件突出的缺点是工作频率(工作频率一般在3GHz以下)存在局限。所以，砷化镓(GaAs)器件和LDMOS已经无法满足5G通信网络需求，但是，氮化镓(GaN)射频功率器件在体现砷化镓器件高频性能的同时，结合了LDMOS器件的功率处理能力，更能满足5G的高通信频段、高功率等要求，所以，氮化镓(GaN)器件的应用范围越来越广。
如图3所示，上述设备的半导体器件021被承载在封装基板023上，并且半导体器件021通过电连接结构(比如，金属层)022设置在封装基板023上，以使半导体器件021可以与封装基板023上的其他电子器件进行信号互连。封装基板023再通过另一电连接结构03设置在电路板01上，比如设置在印制电路板(printed circuit board，PCB)上，这里的另一电连接结构03可以是球阵列(ball grid array，BGA)或者其他电连接结构。
在图3所示的半导体器件021可以包括如图4所示的结构，图4为一种半导体器件021的断面结构图，该半导体器件021包括：衬底，生长在衬底上的GaN层和氮化铝镓(AlGaN)层，以及设置在AlGaN层上方的源极、栅极和漏极。
在图4所示结构的生长过程中，会出现以下现象。比如，一种现象是：在高温下，衬底中的硅(Si)容易与镓(Ga)反应(可以被称为回熔刻蚀)形成硅-镓共熔合金，进而使GaN层和AlGaN层的表面出现凹坑，或者是在GaN层内和AlGaN层内出现孔洞；另一种现象是：衬底中的Si与GaN之间存在很大的晶格失配和热失配，从而会在GaN层中产生张应力，形成大量晶格穿透位错，这些晶格穿透位错如果继续朝AlGaN层的表面延伸的话，就会使AlGaN层的表面出现裂纹。
为了杜绝出现上述两种现象，如图5所示，图5为另一种半导体器件021的断面结构图，结合图5，通常在衬底上生长GaN层结构之前，先生长氮化铝(AlN)层， AlN层一方面作为阻挡层起到防止回熔刻蚀的作用，避免形成孔洞凹坑现象，另一方面可以缓解衬底与GaN之间的晶格失配与热失配。
然而，如图6所示，在插有AlN层的半导体器件021中，AlN层中的铝(Al)易向硅衬底中扩散，作为受主杂质(也可以叫P型杂质)存在于衬底表面下一定范围内，以形成P型寄生沟道(如图3中的虚线框所示)。
在上述的半导体器件中，减轻寄生沟道的影响是所期望的，因为寄生沟道可能显著地提高该半导体器件的寄生损耗，所以，当减轻半导体器件中寄生沟道的影响，或者，抑制或防止这种寄生沟道的形成时，所得到的半导体器件中的寄生损耗可以被显著降低，这可以导致该半导体器件的性能的改善，比如，该半导体器件具有更高的输出功率、功率增益、效率以及其它优点。还有，在一些功率开关器件可以表现出更低的导通移位、导通退化等。
本申请实施例给出了一种半导体器件，该半导体器件可以抑制P型寄生沟道的形成，进而能够提高该半导体器件的性能。
下面结合附图对本申请的半导体器件进行详细说明。
结合图7，图7是一种半导体器件021的剖面图，该半导体器件021包括：衬底1、设置在衬底1表面101上的IIIA族氮化物形成层2，以及设置在IIIA族氮化物形成层2的远离衬底1的表面上的源极(Source)3、栅极(Gate)4和漏极(Drain)
5。
在可选择的实施方式中，可以采用金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)或分子束外延(molecular beam epitaxy，MBE)作为生长技术，在衬底1上生长IIIA族氮化物形成层2。
上述的衬底1可以包含硅，可以这样对包含硅的衬底1解释，如图7，衬底1的表面101可以是硅表面。例如，在一些实施例中，表面101可以对应于硅晶片的表面。在另外一些实施例中，表面101可以对应于复合衬底(例如，包括硅层和一个或更多个设置在硅层下方的下层)的硅表面。在另外一些实施例中，表面101可以对应于绝缘体上硅衬底的硅部分的表面。还在另外一些实施例中，表面101可以对应于蓝宝石上硅衬底的表面。再在另外一些实施例中，表面101可以对应于注氧隔离衬底的硅表面。
另外，衬底1可以是包含硅的高电阻衬底，比如，包含硅的高电阻衬底可以是电阻率大于或者等于1000Ω·cm的衬底结构，或者可以是大于或等于2000Ω·cm的衬底结构，再或者可以是大于或等于5000Ω·cm的衬底结构。
将上述所述的包含硅的高电阻衬底应用在高频下工作的器件(例如RF器件)中是特别有用的，例如，高电阻率可以降低衬底损耗，优化半导体器件性能。
可以这样理解图7所示的IIIA族氮化物形成层2，IIIA族氮化物形成层2是由任何IIIA族氮化物材料制得，也可以理解为由任何IIIA族元素氮化物化合物制得。比如，IIIA族氮化物材料可以包括氮化硼(BN)、氮化铝(AlN)、氮化镓(GaN)、氮化铟(InN)、氮化铊(TIN)和氮化铝镓(AlGaN)中的一种或者至少两种的组合，或者可以包括IIIA族元素和VA族元素形成的任何合金，比如，氮化铟镓(InGaN)、氮化铝铟镓(AlInGaN)、氮化镓砷磷(GaAsPbN)、氮化铝铟镓砷磷(AlInGaAsPbN)等。
下述对IIIA族氮化物形成层2可实现的结构进行说明，比如，如图7所示，给出了一种IIIA族氮化物形成层2的结构，当然，本申请的IIIA族氮化物形成层2不局限于图7所示结构，可以在图7所示结构基础上增加至少一种其他结构，或者在图7所示结构基础上去掉一些结构。
以图7为例来说明，IIIA族氮化物形成层2包括成核层21，该成核层21可以形成在衬底1的表面101上，即可以直接覆盖在衬底1的表面101上。
设置成核层21的目的是：在一些情况下，IIIA族氮化物材料(例如，氮化镓或者其它IIIA族氮化物)可能难以直接在衬底1上进行异质外延生长，通过在衬底1上形成成核层21，再在成核层21上生长其余IIIA族氮化物材料(例如，氮化镓)，这样的话，在一些示例中，可利用成核层21缓解生长在成核层21之上的IIIA族氮化物材料的热膨胀系数与位于成核层21之下的衬底1的热膨胀系数的差异；在另外一些示例中，可利用成核层21缓解生长在成核层21之上的IIIA族氮化物材料的晶格与位于成核层21之下的衬底1的晶格的差异，也可以这样理解，通过成核层21可以缓解衬底1与氮化镓的晶格失配或者热失配，以使氮化镓或者其他IIIA族氮化物的晶格生长的更加整齐。
成核层21可以包含氮化铝(AlN)材料。可以这样理解氮化铝(AlN)材料，氮化铝(AlN)材料是指氮化铝(AlN)及其任何合金，例如氮化铝镓(AlGaN)、氮化铝铟
(AlInN)、氮化铝铟镓(AlInGaN)、氮化铝铟镓砷磷化物(AlInGaAsPbN)等。在这些氮化铝(AlN)合金中，具有高浓度的铝并且可以包含少量镓和铟中的至少一种，或者不包括镓和铟，也就是合金浓度相对铝浓度是比较小的。
上述的成核层21可以包含一层结构或者至少两层结构。当成核层21包含至少两层结构时，这些多层结构可以由相同材料制得，或者由不同材料制得。另外，当成核层21包含至少两层结构时，可以使用不同的半导体生长条件来形成这些多层结构。这些半导体生长条件的不同可以包括生长温度、生长压力或者反应物流率不同等。
继续结合图7，该IIIA族氮化物形成层2还包括过渡层22，过渡层22可以形成在成核层21的远离衬底1的一侧，也就是形成在成核层21之上。
在一些可选择的实施方式中，过渡层22由组分渐变(compositionally graded)的IIIA族氮化物材料形成，例如，过渡层22可以包括AlxGa(1-x)N，其中x可以沿生长方向(也就是图7所示的沿远离衬底1的P方向)逐渐减小，比如，x可以由值1减小到值0。
组分渐变的过渡层22可以依照下述示例性的规律渐变。
比如，AlxGa(1-x)N的组分中的x，从过渡层22的下表面102表面处的值1连续地渐变成过渡层22上表面103处的值0。
再比如，AlxGa(1-x)N的组分中的x，从过渡层22的下表面102表面处的值1不连续地渐变成过渡层22上表面103处的值0。例如，从过渡层22的下表面102表面至过渡层22的上表面103，以AlN、Al 0.6Ga 0.4N和Al 0.4Ga 0.6N，以及Al 0.2Ga 0.8N进行不连续的渐变。
再例如，AlxGa(1-x)N的组分中的x，从过渡层22的下表面102表面处的值1呈抛物线渐变成过渡层22上表面103表面处的值0；或者，呈其他连续或者非连续的 渐变形式变化。
另外，在一些可选择的实施例中，可以选择如AlxInyGa(1-x-y)N、InyGa(1-y)N等的氮化镓合金形成。合金的元素，例如，Ga、Al、In中的至少一种的浓度沿过渡层的厚度是变化的。示例的，过渡层具有AlxInyGa(1-y)N组分时，x和y中的至少一个是可以变化的。再示例的，过渡层InyGa(1-y)N组分的某些实施例中，y是可以变化的。
继续结合图7，该IIIA族氮化物形成层2还包括沟道层23，沟道层23可以形成在过渡层22的远离成核层21的一侧，也就是形成在过渡层22之上。
沟道层23可以包含氮化镓(GaN)材料。如图7，当过渡层22的上表面103处为GaN材料，且沟道层23也为GaN材料时，GaN材料的过渡层22中一般会掺杂(比如，掺杂碳或者铁等元素)，通过掺杂来实现抑制漏电的目的，但是，GaN材料的沟道层23用来走电流，需要高质量低杂质的GaN外延层。
继续结合图7，该IIIA族氮化物形成层2还包括插入层24，插入层24可以形成在沟道层23的远离过渡层22的一侧，也就是形成在沟道层23之上。
插入层24可以包含AlN材料，通过AlGaN、AlN、GaN结构的极化效应可产生更高的二维电子气浓度，并且二维电子气向势垒层的渗入量降低，通过插入层24能够减少合金无序散射从而提高迁移率，有利于改善器件的输出特性。
继续结合图7，该IIIA族氮化物形成层2还包括势垒层25，势垒层25可以形成在插入层24的远离沟道层23的一侧，也就是形成在插入层24之上。
势垒层25可以包含AlGaN材料，也可以包括AlInN或AlInGaN中的至少一种与AlGaN组合制成，其中，势垒层25中的铝含量与过渡层22和沟道层23中的铝含量不同。
势垒层25用于配合沟道层23，以在沟道层23与势垒层25之间通过极化作用产生二维电子气(two-dimensional electron gas，2DEG)，从而导通电流。
继续结合图7，该IIIA族氮化物形成层2还包括帽层26，帽层26可以形成在势垒层25的远离插入层24的一侧，也就是形成在势垒层25之上。
在一些可选择的实施例中，帽层26包含GaN材料，在覆层包含GaN的情况下，相对于不存在覆层时形成的表面，所得到的表面形态可以更平滑，表面缺陷更少。另外，采用GaN材料终止外延层的生长，也助于后续对外延层的表面进行化学处理。
在上述半导体器件021中，如图8所示，图8示出了成核层21和衬底1中的微观结构，在衬底1的靠近成核层21的区域中包含有至少一种物质，该物质包括IIIA族中的元素与氢结合得到的物质，如图8中的衬底1中的圆圈结构所示，由于该物质的存在，就不会形成P型寄生沟道，另外，在成核层21中包含有II族元素的P型杂质，如图8中的黑色圆圈所示，该包含有II族元素的P型杂质能够与氢结合。
下面通过描述图8所示结构的形成方法，来解释P型寄生沟道是如何被抑制的。
图9为图8所示半导体器件的形成方法的工艺流程图，图10为制造该半导体器件工艺流程的每一步骤完成后的剖面图。
参照图9的步骤S1和图10中的(a)的结构图，图10中的(a)为完成步骤S1 后的结构图，步骤S1包括：在IIIA族氮化物中掺杂P型杂质，P型杂质包含II族中的元素，并在反应气体包括氢气的情况下，在包含有硅的衬底1上形成IIIA族氮化物的成核层21，以使IIIA族氮化物的成核层21中掺杂有P型杂质。
下面结合图10对步骤S1详细解释。
在图10中，是以Mg所为P型杂质为例来说明，当在包含硅的衬底1上形成IIIA族氮化物的成核层21时，将II族中的至少一种掺杂在用于形成IIIA族氮化物的成核层21的IIIA族氮化物材料中，并且用于生长IIIA族氮化物的成核层21的反应气体包括氢气，这样的话，在生长过程中，会出现至少两种现象，一种现象是如图10中的(a)所示的，IIIA族氮化物中的IIIA族物质扩散至包含硅的衬底1中，比如图10中的(a)，是以Al朝衬底1扩散为例，这样的话，Al作为受主杂质，在衬底1的靠近IIIA族氮化物的成核层21的区域形成了P型寄生沟道，图10中(a)所示的具有黑色圆点的区域代表P型寄生沟道；另一种现象是如图10中的(a)所示的，P型杂质Mg与H结合，形络合物，该络合物可以用Mg-H表示。
图10仅是以Mg所为P型杂质为例来说明，除过Mg，还可以采II族中的至少一种，比如，可以采用IIA族中的铍(Be)、镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)中的一种或者至少两种的组合；再比如，可以采用IIB族中锌(Zn)、碳(C)、汞(Hg)、镉(Cd)中的一种或者至少两种的组合；再比如，可以采用铍(Be)、镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)、锌(Zn)、碳(C)、汞(Hg)、镉(Cd)中的至少两种的组合。
在一些可选择的实施方式中，在形成成核层21的材料中掺杂Mg杂质，例如，可以掺杂二茂镁(C 10H 10Mg)等。
参照图9的步骤S2和图10中的(b)的结构图，图10中的(b)为完成步骤S2后的结构图，步骤S2包括：对包含有衬底1和IIIA族氮化物的成核层21的结构进行退火处理，以制得半导体器件，且衬底1的靠近IIIA族氮化物的成核层21的区域中包含有第一物质，第一物质包括IIIA族中的物质与氢结合得到的物质。
下面结合图10对步骤S2详细解释。
在完成图10的(a)所示的步骤S1之后，在衬底1的靠近IIIA族氮化物的成核层21的区域中形成有P型寄生沟道，并且，在IIIA族氮化物的成核层21的靠近衬底1的区域中包含有II族中的至少一种与氢结合形成的物质，比如，镁与氢结合形成的络合物。
在完成步骤S1的基础上，再进行步骤S2时，如图10的(b)所示的，在进行退火工艺中，P型杂质与氢形成的络合物发生P型杂质与氢之间的化学键被打破，比如，如图10的(b)所示的Mg-H络合物中的Mg与H之间的化学键被破坏，进而，H成为游离态，这样的话，呈游离态的氢物质就会扩散至衬底1中，作为施主杂质与扩散至衬底中的受主杂质(比如，Al)相结合，以钝化衬底中的受主杂质，进而，会破坏了P型寄生沟道，或者即使形成了P型寄生沟道，形成的P型寄生沟道的电导率也是很低的，对该半导体器件的性能影响也不很大。
将包含II族中的至少一种的P型杂质形成在成核层21中，因为在成核层21中晶格排布不是很整齐，设置成核层的目的是让生长在其上的沟道层的晶格排布更加整 齐，沟道层的性能更好。在本申请实施例中，将包含II族中的至少一种的P型杂质掺杂在晶格不是很整齐的成核层21中，对该成核层21中的晶格排布破坏不是很严重，进而对成核层21的性能影响很小。除此之外，位于成核层21中的掺杂的P型杂质与氢结合形成络合物后，再在高温下化学键被破坏后，游离的氢物质会很快的扩散至衬底1中，缩短氢物质的扩散路径，也可以这样理解，在单位时间内，会有更多的氢物质扩散至衬底中，以钝化衬底中的受主杂质，抑制P型寄生沟道的形成。
除此之外，将包含有II族中的至少一种的P型杂质掺杂在成核层21，如图7所示，由于成核层21之上的过渡层22为n型或高阻型，氢物质在包含有硅的衬底1中的扩散系数远高于在n型或高阻氮化物中的扩散系数，所以，氢物质会朝包含有硅的衬底1中扩散，以钝化受主杂质。
基于上述描述，在该半导体器件的形成过程中，将包含II族中的至少一种的P型杂质掺杂在IIIA族氮化物中，并且所述的P型杂质与反应气体氢气结合形成络合物，以将氢稳定在络合物中，然后再进行退火处理，在退火过程中，络合物内的化学键被破坏，氢物质被释放呈游离态，游离的氢物质会扩散至衬底1中，以钝化可以形成P型寄生沟道的受主杂质，进而抑制P型寄生沟道的形成。
还有，在一些可选择的实施方式中，可以通过离子注入法将氢物质注入至包含有硅的衬底1中，该离子注入法的可实现方式为，当完成衬底1上的至少部分IIIA族氮化物形成层2后，将其从反应腔中取出，进行氢物质的注入，这样容易引起污染，影响半导体器件的性能。
相反，本申请实施例提供的半导体器件的形成方法中，不需要在将成核层21形成之前，将其从反应腔中取出，而是一直在反应腔中完成成核层21的形成，另外，本申请是利用了反应腔中的反应气体氢气，来抑制P型寄生沟道的形成，也不需要额外的提供氢物质的工艺。
若采用离子注入法注入氢物质时，离子被加速成具有规定的能量的离子束后被引向半导体衬底的表面。离子束中的高能离子掺入半导体材料并且被镶嵌到半导体材料的晶格之中，也就是说，离子注入会引入较大的能力，相比本申请的方案，有可能会对破坏晶格的排布。
在一些可选择的实施方式中，可以选择Mg作为P型杂质掺杂在成核层21中，因为在P型杂质中Mg相比其他P型杂质的电离能小，容易掺杂，并且也很容易与氢物质结合形成络合物。
除此之外，就是进入成核层21的镁相比成核层21中的IIIA族物质，比如Al，的电离能高，所以Mg电离产生的空穴比实际Mg掺杂的浓度低很多，Mg作为受主杂质，成核层21中由于位错、空位和杂质的存在会呈现出N型，这样的话，镁电离产生的空穴与电子相补偿，进而不会在成核层21中引入导电通道。
在IIIA族氮化物形成层中掺杂包含II族中的至少一种的P型杂质时，P型杂质的浓度可以选择为：小于或者等于1×10 22cm -3。
以Mg作为掺入杂质为例，为了实现高空穴浓度的P型材料，就需要高浓度的P型杂质掺杂，比如，需要高浓度的Mg掺杂。而受固溶度的限制，Mg在IIIA族氮化物材料(比如，GaN)中的溶解度是有限的，无法达到高掺入量。当掺杂浓度达到一 定程度后，再增加Mg杂质浓度，Mg会与反应气体氮气结合形成Mg 3N 2而不会进入GaN晶格,进而影响GaN材料的晶体质量。并且当Mg掺杂浓度很大时，Mg原子会处于晶格之间的间隙位置(把处于晶格之间的间隙位置的Mg称为Mgi)而不是替位Ga原子(把Mg取代Ga称为MgGa替位原子)，Mgi会和GaN材料中大量的N空位(vacancy，V N)组成络合物(Mgi-VN)，该络合物表现出施主的特性，导致Mg原子的自补偿效应。
所以，对于P型杂质的浓度是有要求的，不能太小，否则，无法抑制P型寄生沟道的形成，也不能太大，因为会影响IIIA族氮化物形成层的质量，甚至恶化该半导体器件的性能。
在可选择的实施方式中，当选用Mg作为掺入杂质时，镁的浓度可以选择为：1×10 18cm -3至1×10 21cm -3；或者，镁的浓度可以选择为：5×10 18cm -3至1×10 21cm -3。
下面给出了一种半导体器件的制备方法，该方法包括了IIIA族氮化物形成层2的具体的层结构的形成方法。
图11为该半导体器件的形成方法的工艺流程图，图12为制造该半导体器件工艺流程的每一步骤完成后的剖面图。
如图11中的步骤S01，和图12中的(a)，图12中的(a)是执行图11中的步骤S01后的结构图。
如图11的步骤S01和图12的(a)，在包含有硅的衬底1上进行Mg掺杂的成核层2的生长。
这里的包含有硅的衬底1的结构在上述已经解释过了，在此不再赘述。
在进行Mg掺杂的成核层21生长时，示例的，反应气体包括氨气、氢气，以及反应物包括三甲基铝(trimethyl aluminium)、二茂镁；反应温度为1100℃左右，最终成型的成核层21的厚度约为50nm至500nm，比如可以为300nm。
在可选择的实施例中，可以在成核层21的整个生长过程中都掺杂Mg掺杂，比如，掺杂二茂镁，也可以在成核层21的前段生长过程中掺杂Mg掺杂，后段生长无需再掺杂，比如，可以在厚度为100nm的成核层21之前，掺杂二茂镁，后200nm的成核层形成的过程中不需要再掺杂二茂镁。
在一些可选择的实施例中，在掺杂Mg掺杂时，Mg掺杂可以选取5×10 19cm -3。同样的，这里的5×10 19cm -3仅是一种示例性的可选的浓度值。
在衬底1上生长成核层21之前，也可以对衬底1进行去氧化处理，比如，可以将衬底1放在生长腔体中，采用氢氟酸进行高温表面清洗，以去除衬底1表面上的氧化层。在进行去氧化处理时，气氛可以包括氢气，温度在1100℃，时间为5min左右。
对于上述的反应温度、反应时间仅是一种示例性说明，可以在其他适宜的反应温度和反应时间下对衬底1进行化学清洗。
在进行成核层21的生长过程中，Al会逐渐扩散至衬底1中，基于衬底1是高阻硅衬底时，Al基本处于衬底1的靠近成核层21的区域内，且Al作为受主杂质，在衬底1中形成了P型寄生沟道。
还有，掺杂在成核层21中的Mg掺杂会与反应气体中的氢气相结合，以络合物 的形态存在于成核层21中。
完成图11中的步骤S01之后，执行图11中的步骤S02，和图12中的(b)，图12中的(b)是执行图11中的步骤S02后的结构图。
如图11的步骤S02和图12的(b)，进行过渡层22的生长。
在生长过渡层22时，示例的，反应气体包括氨气、氢气，以及反应物包括三甲基铝(trimethyl aluminium)、三甲基镓(trimethyl gallium)；反应温度为1100℃左右。最终成型的过渡层22的厚度约为100nm至5000nm，比如可以为1000nm。
这里形成的过渡层22为多层AlxGa(1-x)N结构，可以沿着远离衬底1的方向，将形成的多层AlxGa(1-x)N结构分别称为第一层AlxGa(1-x)N结构、第二层AlxGa(1-x)N结构、第三层AlxGa(1-x)N结构等，比如，具有三层结构时，在第一层AlxGa(1-x)N结构中，x为0.8，在第二层AlxGa(1-x)N结构中，x为0.5，在第三层AlxGa(1-x)N结构中，x为0.2。在这三层AlxGa(1-x)N结构中，对于每一层的厚度可以选择为：第一层AlxGa(1-x)N结构的厚度为330nm，第二层AlxGa(1-x)N结构的厚度为330nm，第三层AlxGa(1-x)N结构的厚度为340nm，当然，这些组分数据、厚度数据都是一种示例性说明而已。
完成图11中的步骤S02之后，执行图11中的步骤S03，和图12中的(c)，图12中的(c)是执行图11中的步骤S03后的结构图。
如图11的步骤S03和图12的(c)，进行沟道层23的生长。
在生长沟道层23时，示例的，反应气体包括氨气、氢气，以及反应物包括三甲基镓(trimethyl gallium)；反应温度为1050℃左右。形成的沟道层23的厚度基本为100nm至500nm。
完成图11中的步骤S03之后，执行图11中的步骤S04，和图12中的(d)，图12中的(d)是执行图13中的步骤S04后的结构图。
如图11的步骤S04和图12的(d)，进行插入层24的生长。
在生长插入层24时，示例的，反应气体包括氨气、氢气，以及反应物包括三甲基铝；反应温度为1050℃左右。形成的沟道层23的厚度基本为0.2nm至2nm，比如可以为0.7nm。
完成图11中的步骤S04之后，执行图11中的步骤S05，和图12中的(e)，图12中的(e)是执行图11中的步骤S05后的结构图。
如图11的步骤S05和图12的(e)，进行势垒层25的生长。
在进行势垒层25生长时，反应气体包括氨气、氢气，以及反应物包括三甲基铝、三甲基镓。反应温度为1050℃左右。形成的势垒层25的厚度基本为10nm至60nm，比如，可以为30nm。
这里形成的势垒层25为AlxGa(1-x)N结构，其中，x可以为0.2左右。
完成图11中的步骤S05之后，执行图11中的步骤S06，和图12中的(f)，图12中的(f)是执行图11中的步骤S06后的结构图。
如图11的步骤S06和图12的(f)，进行帽层26的生长。
在进行帽层26生长时，反应气体包括氨气、氢气，以及反应物包括三甲基镓。反应温度为1050℃左右。形成的帽层26的厚度基本为0.1nm至10nm，比如可以 为1nm。
在进行上述的过渡层22、沟道层23、插入层24、势垒层25或者帽层26的任一层结构生长时，成核层21中的Mg杂质与氢气不断的进行化学键的结合，以及化学键的破裂，但是，结合的数量相对会大于破解的数量。
完成图11中的步骤S06之后，执行图11中的步骤S07。
如图11的步骤S07，进行退火处理。
将上述的过渡层22、沟道层23、插入层24、势垒层25以及帽层26生长完成之后，可以将包含有硅的衬底1和外延层2的结构从生长腔室中取出，采用管式炉进行退火处理，退火的气氛包括氮气，温度为600℃至900℃，比如800℃左右，退火时间为1min至180min，比如45min左右。当然，也可以退火炉中进行退火处理，气氛为不包含有氢的气体，比如，可以包括氮气、空气、氩气或其混合气体，反应温度为600℃至1000℃，反应时间为1min至180min。
在进行退火工艺中，由于该退火工艺是在不包含氢的氛围中进行，处于成核层21中的Mg杂质与氢形成的络合物中的化学键被破坏，氢物质就会以游离态的形式存在，这样的话，游离的氢就会扩散至衬底1中，所为施主杂质，与衬底1中的受主杂质相结合，进而破坏了先前形成的P型寄生沟道。
完成图11中的步骤S07之后，执行图11中的步骤S08和图12中的(g)。
如图11的步骤S08和图12中的(g)，形成源极、栅极和漏极，以形成半导体器件。
图13所示结构为采用上述方法制得的半导体器的结构图，在最终成型的半导体器件021中，不仅在衬底1的靠近成核层21的区域中包含有至少一种物质，该物质包括IIIA族中的元素与氢结合得到的物质，如图13中的衬底1中的圆圈结构所示，另外，在成核层21中包含有II族中的至少一种的P型杂质，如图13中的黑色圆圈所示，当然，还有可能在成核层21中存在II族中的元素与氢结合得到的物质，比如镁与氢结合的络合为，这是因为在进行上述的退火工艺中，有可能存在于成核层21中的II族物质与氢结合的物质没有被完全的打破，还会剩余一部分，进而，就会出现图13所示的结构。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种半导体器件，其特征在于，包括：
    衬底，包含硅；
    成核层，设置在所述衬底上；
    沟道层，设置在所述成核层上；
    势垒层，设置在所述沟道层上；
    其中，所述成核层包含有P型杂质，且所述P型杂质包含II族中的元素；
    所述衬底中包含有第一物质，所述第一物质包括IIIA族中的元素与氢结合得到的物质。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述P型杂质包含IIA族中的元素。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述P型杂质的浓度为：小于或者等于1×10 22cm -3。
  4. 根据权利要求1-3中任一项所述的半导体器件，其特征在于，所述P型杂质包括镁。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述镁的浓度为：1×10 18cm -3至1×10 21cm -3。
  6. 根据权利要求1-5中任一项所述的半导体器件，其特征在于，所述成核层中包含有第二物质，所述第二物质包括所述II族中的元素与氢结合得到的物质。
  7. 根据权利要求1-6中任一项所述的半导体器件，其特征在于，所述第一物质位于所述衬底的靠近所述成核层的区域中。
  8. 根据权利要求1-7中任一项所述的半导体器件，其特征在于，所述成核层包括氮化铝AlN材料。
  9. 根据权利要求1-8中任一项所述的半导体器件，其特征在于，所述沟道层包括氮化镓GaN材料。
  10. 根据权利要求1-9中任一项所述的半导体器件，其特征在于，所述势垒层包括氮化铝镓AlGaN材料。
  11. 根据权利要求1-10中任一项所述的半导体器件，其特征在于，所述半导体器件还包括：
    过渡层，位于所述成核层和所述沟道层之间。
  12. 一种形成半导体器件的方法，其特征在于，包括：
    在IIIA族氮化物中掺杂P型杂质，所述P型杂质包含II族中的元素，并在反应气体包括氢气的情况下，在包含有硅的衬底上形成成核层，以使所述成核层中掺杂有所述P型杂质；
    对包含有所述衬底和所述成核层的结构进行退火处理，以制得半导体器件，且所述衬底中包含有第一物质，所述第一物质包括所述IIIA族中的元素与氢结合得到的物质。
  13. 根据权利要求12所述的形成半导体器件的方法，其特征在于，在所述IIIA族 氮化物中掺杂所述P型杂质时，所述P型杂质包含IIA族中的元素。
  14. 根据权利要求12或13所述的形成半导体器件的方法，其特征在于，在所述IIIA族氮化物中掺杂所述P型杂质时，掺杂的所述P型杂质的浓度为：小于或者等于1×10 22cm -3。
  15. 根据权利要求12-14中任一项所述的形成半导体器件的方法，其特征在于，在所述衬底上形成所述成核层时，包括：
    在用于形成所述成核层的材料中掺杂镁物质，以在所述成核层中具有能够与氢结合的P型杂质镁。
  16. 根据权利要求15所述的形成半导体器件的方法，其特征在于，在用于形成所述成核层的材料中掺杂所述镁物质时，所述镁的浓度为：1×10 18cm -3至1×10 21cm -3。
  17. 根据权利要求15或16所述的形成半导体器件的方法，其特征在于，所述镁杂质包含二茂镁。
  18. 根据权利要求12-17中任一项所述的形成半导体器件的方法，其特征在于，在对包含有所述衬底和所述成核层的结构进行所述退火处理时，包括：
    在包括氮气的气氛中进行所述退火处理。
  19. 根据权利要求12-18中任一项所述的形成半导体器件的方法，其特征在于，在所述衬底上形成所述成核层之后，在进行所述退火处理之前，所述方法还包括：
    在所述成核层上形成沟道层；
    在所述沟道层上形成势垒层。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～11中任一项所述的半导体器件，或者如权利要求12～19中任一项所述的形成半导体器件的方法制得的半导体器件；所述电路板与所述半导体器件电连接。
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