WO2022202548A1 - 配線体、実装基板、配線付き配線転写版、配線体用中間材、配線体の製造方法、及び、実装基板の製造方法 - Google Patents
配線体、実装基板、配線付き配線転写版、配線体用中間材、配線体の製造方法、及び、実装基板の製造方法 Download PDFInfo
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- WO2022202548A1 WO2022202548A1 PCT/JP2022/011947 JP2022011947W WO2022202548A1 WO 2022202548 A1 WO2022202548 A1 WO 2022202548A1 JP 2022011947 W JP2022011947 W JP 2022011947W WO 2022202548 A1 WO2022202548 A1 WO 2022202548A1
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- wiring
- layer
- film
- wiring body
- substrate
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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
Definitions
- the present disclosure relates to a wiring body, a mounting substrate, a wiring transfer plate with wiring, an intermediate material for wiring body, a method for manufacturing a wiring body, and a method for manufacturing a mounting substrate.
- a wiring body or the like that can be used as a redistribution layer (RDL).
- RDL redistribution layer
- a silicon interposer is composed of a silicon wafer.
- a fine multilayer wiring layer is formed by a semiconductor process on the surface of the silicon wafer on which the semiconductor device is mounted, and connection terminals and electric circuits connected to the semiconductor package substrate are formed on the back surface of the silicon wafer. , and the front and back circuits are electrically connected by TSV (Through Silicon Via) penetrating the silicon wafer.
- silicon interposers which require a wafer-level manufacturing process, have the problem of high manufacturing costs. Therefore, the application of silicon interposers is often limited to servers, high-end PCs, high-end graphics, and the like, which require performance rather than cost, which is an obstacle to their widespread use.
- silicon is a semiconductor
- forming a wiring layer directly on a silicon wafer has the problem of degrading electrical characteristics.
- the transmission distance from the semiconductor package substrate becomes longer by the amount of the silicon interposer than when the semiconductor device is directly mounted on the semiconductor package substrate. There is a problem that noise becomes easy to ride.
- thin fine wiring can be formed such that at least L/S is 2/2 ⁇ m to 5/5 ⁇ m and the wiring layer thickness per layer is 3 to 10 ⁇ m. requested.
- one layer of wiring on the outermost surface of the semiconductor element mounting surface of a semiconductor package substrate manufactured by a normal process is polished by CMP (Chemical Mechanical Polishing).
- CMP Chemical Mechanical Polishing
- SAP semi-additive process
- MSAP modified semi-additive process
- the line width of the wiring is reduced to 2 to 5 ⁇ m, it is necessary to reduce the thickness of the interlayer insulation layer from the viewpoint of impedance and manufacturing.
- the thickness of the interlayer insulating layer has been studied to use a liquid insulating resin instead of a film-like insulating resin as an insulating material for the interlayer insulating layer.
- the thickness of the inter-layer insulation layer after curing depends on the irregularities of the via electrodes and wiring, so it is difficult to make the thickness of the inter-layer insulation layer constant.
- one aspect of the wiring body according to the present disclosure is a wiring body arranged on a substrate having a conductor, the wiring body comprising a via hole formed in an insulating layer positioned on the substrate. a via electrode provided inside the substrate and connected to the conductor through the via hole; and wiring provided above the substrate through the insulating layer, wherein the via electrode is provided above the insulating layer.
- the lower layer located in the line and the lower layer of the wiring are made of the same material.
- one aspect of the mounting substrate according to the present disclosure includes the wiring body described above and a substrate on which the wiring body is arranged.
- one aspect of the wiring transfer plate with wires is a wiring transfer plate with wires, which is a wiring transfer plate on which transfer wirings for transferring to another member are formed, comprising: a base material; a release layer formed on a substrate; a transfer plate insulating layer covering the substrate so as to have an opening on the release layer; and a transfer plate insulating layer formed on the release layer in the opening. and an adhesion film formed to cover the plating film and the transfer plate insulating layer, wherein the plating film and the adhesion film are wirings for transfer to be transferred to another member.
- one aspect of the wiring transfer plate with wiring according to the present disclosure is an intermediate material for a wiring body, which is an intermediate material for a wiring body arranged on a substrate having a conductor, and An adhesion film formed on an insulating layer provided on the substrate, and wiring formed on the adhesion film.
- one aspect of the method for manufacturing a wiring body according to the present disclosure is a method for manufacturing a wiring body arranged on a substrate having a conductor, wherein an adhesion film is formed through an insulating layer positioned on the substrate. and a wiring body layer positioned on the adhesion film; and removing a portion of the adhesion film and the insulation layer to form a via hole in the insulation layer so as to expose the conductor.
- forming a seed film so as to cover the exposed conductor, the adhesion film, and the wiring body layer; selectively forming a resist on the seed film; forming a via electrode body layer on the exposed seed film; removing the seed film and removing the adhesion film existing under the exposed seed film.
- one aspect of the method for manufacturing a mounted board according to the present disclosure is a method for manufacturing a mounted board in which a wiring body is arranged on the board, the method including a step of arranging the wiring body on the board, The wiring body is manufactured by the wiring body manufacturing method described above.
- the wiring can be miniaturized and the pitch can be narrowed.
- FIG. 1 is a plan view showing an example of a wiring pattern of one wiring layer in a wiring body of a mounting substrate according to Embodiment 1.
- FIG. FIG. 2 is a cross-sectional view of the inter-via wiring portion of the mounting substrate taken along line II-II of FIG.
- FIG. 3 is a cross-sectional view of the interlayer connection portion of the mounting board taken along line III-III in FIG.
- FIG. 4 is a diagram for explaining a method of manufacturing a wiring transfer plate with wiring used when manufacturing the wiring body and the mounting substrate according to the first embodiment.
- FIG. 5 is a diagram for explaining a method of manufacturing a wiring transfer plate.
- FIG. 6A is a cross-sectional view showing a modification of the wiring transfer plate.
- FIG. 6B is a cross-sectional view of an inter-via wiring portion of the mounting board according to the modification.
- FIG. 6C is a cross-sectional view of an interlayer connection portion of a mounting substrate according to a modification.
- FIG. 7 is a diagram showing a configuration when the wiring transfer plate with wiring produced in FIG. 4 is cut along another cross section.
- FIG. 8 is a diagram (cross-sectional view of a portion corresponding to the inter-via wiring portion in FIG. 2) for explaining the wiring body manufacturing method and the mounting substrate manufacturing method according to the first embodiment.
- FIG. 9 is a diagram (a cross-sectional view of a portion corresponding to the interlayer connection portion in FIG. 3) for explaining the wiring body manufacturing method and the mounting substrate manufacturing method according to the first embodiment.
- FIG. 10 is a diagram for explaining a method of manufacturing a conventional mounting substrate having via electrodes and wiring.
- FIG. 11 is a cross-sectional view of a mounting substrate showing a first application example of the wiring body according to the first embodiment.
- FIG. 12 is a cross-sectional view of a mounting board showing a second application example of the wiring body according to the first embodiment.
- FIG. 13 is a cross-sectional view of a mounting substrate showing a third application example of the wiring body according to the first embodiment.
- 14 is a cross-sectional view of a mounting substrate according to Embodiment 2.
- FIG. 15A and 15B are diagrams for explaining the wiring body manufacturing method and the mounting board manufacturing method according to the second embodiment.
- FIG. 15A and 15B are diagrams for explaining the wiring body manufacturing method and the mounting board manufacturing method according to the second embodiment.
- FIG. 16 is a cross-sectional view of a mounting substrate according to Embodiment 3.
- FIG. 17A and 17B are diagrams for explaining a wiring body manufacturing method and a mounting substrate manufacturing method according to the third embodiment.
- 18 is a cross-sectional view of a mounting substrate according to Embodiment 4.
- FIG. 19 is a diagram for explaining another example of the wiring transfer plate manufacturing method.
- each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, scales and the like are not always the same in each drawing. Moreover, in each figure, the same code
- FIG. 1 is a plan view showing an example of a wiring pattern of one wiring layer in a wiring body 30 of a mounting substrate 1 according to Embodiment 1.
- FIG. FIG. 2 is a cross-sectional view of the inter-via wiring portion of the mounting substrate 1 along line II-II of FIG. 3 is a cross-sectional view of the interlayer connection portion of the mounting board 1 taken along line III--III in FIG.
- the mounting board 1 is, for example, a semiconductor package board, and has a plurality of wiring layers on which wiring is formed. Therefore, as shown in FIG. 1, the mounting substrate 1 includes, as the wiring bodies 30, via electrodes 31 for electrically connecting wiring between wiring layers, and wiring 32 which is wiring in one of the wiring layers. .
- the wiring 32 is connected to the via electrode 31 .
- the via electrode 31 is formed, for example, at the end of the portion where the wiring 32 extends, but it is not limited to this.
- the via electrode 31 may be formed in the middle of the wiring 32 .
- each wiring layer a plurality of via electrodes 31 and wirings 32 are formed.
- the mounting board 1 is a small ultra-high-density mounting board on which wirings 32 are mounted at high density.
- the mounting substrate 1 includes a substrate 10 and an insulating layer 20 and a wiring body 30 located on the substrate 10 .
- the wiring body 30 includes at least via electrodes 31 and wirings 32 as conductive members.
- the insulating layer 20 may be a part of the wiring body 30 .
- the substrate 10 has conductors 11 .
- the conductor 11 is, for example, a wiring or an electrode formed in a wiring layer different from the wiring 32 .
- the substrate 10 is a wiring board that is a board with wiring having wiring formed of copper foil or the like, and is, for example, a buildup board, a multilayer wiring board, a double-sided wiring board, or a single-sided wiring board. . Therefore, the substrate 10 is provided with a plurality of wirings or the like as the conductors 11 over a single layer or a plurality of layers. 2 and 3 schematically show only the conductors 11 formed on the outermost surface layer of the conductors 11 of the substrate 10. As shown in FIG.
- the mounting board 1 is an ultra-high-density mounting board
- the board 10 is a build-up board.
- the substrate 10 is not limited to a wiring substrate such as a build-up substrate, and may be an IC package substrate or an IC chip itself as long as it has wiring or electrodes as the conductor 11. good too.
- the insulating layer 20 is formed on the substrate 10 . Specifically, the insulating layer 20 covers the entire substrate 10 so as to cover the conductors 11 in the surface layer of the substrate 10 .
- the insulating layer 20 is arranged between the conductor 11 of the substrate 10 and the wiring 32 . Therefore, the insulating layer 20 is an interlayer insulating layer.
- the wiring layer in which the wiring that is the conductor 11 on the surface layer of the substrate 10 is formed is defined as the first wiring layer WL1, and the wiring 32 of the wiring body 30 is formed.
- the insulating layer 20 is an interlayer insulating layer between the first wiring layer WL1 and the second wiring layer WL2.
- a via hole 21 is formed in the insulating layer 20 .
- the via hole 21 is a through hole formed on the conductor 11 of the substrate 10 .
- a via electrode 31 is formed in the via hole 21 .
- the via hole 21 has a truncated cone shape with an inclined inner surface (tapered surface). Therefore, the opening shape (top view shape) of via hole 21 is circular, and the cross-sectional shape of via hole 21 is trapezoidal.
- the shape of the via hole 21 may be a truncated pyramid shape such as a quadrangular truncated pyramid shape, or may be a columnar shape or a prismatic shape.
- the insulating layer 20 is made of an insulating material.
- the insulating material forming the insulating layer 20 is, for example, an insulating resin.
- the insulating resin material for forming the insulating layer 20 may be a liquid insulating resin material having fluidity, which is composed of a photocurable resin such as an ultraviolet curable resin or a thermosetting resin.
- a prepreg made of a film-like insulating resin made of a thermosetting resin or a thermoplastic resin may also be used.
- An insulating resin sheet can be used as the film-like insulating resin. In this case, the insulating resin sheet preferably has adhesiveness.
- the insulating material forming the insulating layer 20 is not limited to an organic insulating material such as an insulating resin, and may be an inorganic insulating material such as a silicon oxide film or a silicon nitride film.
- the wiring body 30 is arranged on the substrate 10 having the conductor 11 .
- the via electrode 31 of the wiring body 30 is arranged on the conductor 11 of the substrate 10
- the wiring 32 of the wiring body 30 is arranged above the substrate 10 with the insulating layer 20 interposed therebetween.
- the wiring 32 is arranged on the insulating layer 20 . As shown in FIG. 2, the wiring 32 is arranged above the conductor 11 as the wiring of the substrate 10 with the insulating layer 20 interposed therebetween, but it is not limited to this.
- the wiring 32 is formed on the insulating layer 20 by a transfer method using a wiring transfer plate. It should be noted that the wiring 32 may not be entirely located on the main surface of the insulating layer 20 , and the lower portion of the wiring 32 may be located within the insulating layer 20 .
- the via electrode 31 is connected to the conductor 11 of the substrate 10 through the via hole 21 of the insulating layer 20 .
- the via electrode 31 is a plug that connects upper and lower wirings sandwiching the insulating layer 20 .
- the via electrodes 31 are composed of wirings (conductors 11) of the first wiring layer WL1 located directly below the insulating layer 20 and wirings (wirings 32) of the second wiring layer WL2 located directly above the insulating layer 20. is connected to
- At least a part of the via electrode 31 is provided inside the via hole 21 .
- the via electrode 31 is embedded in the via hole 21 without gaps.
- the via electrode 31 is formed not only inside the via hole 21 but also protruding from the main surface of the insulating layer 20 .
- the height of the via electrode 31 from the main surface of the insulating layer 20 is higher than the height of the wiring 32 from the main surface of the insulating layer 20 .
- the via electrode 31 is formed over the conductor 11 of the substrate 10 and over the insulating layer 20 .
- the via electrode 31 is formed so as to run over the main surface of the insulating layer 20 from inside the via hole 21 of the insulating layer 20 . Therefore, the planar view area of the portion of the via electrode 31 protruding from the insulating layer 20 is larger than the maximum diameter area of the portion of the via electrode 31 embedded in the via hole 21 .
- the shape of the portion of the via electrode 31 embedded in the via hole 21 is the same as the shape of the via hole 21 . Therefore, in the present embodiment, the portion of the via electrode 31 embedded in the via hole 21 has a truncated cone shape with an inclined side surface (tapered surface). The minimum diameter of the portion of the via electrode 31 embedded in the via hole 21 is larger than the width of the wiring 32 .
- the via electrode 31 has a seed layer 31a, a via electrode body layer 31b provided on the seed layer 31a, and an adhesion layer 31c.
- the via electrode 31 further includes an electroless plated layer 31d between the adhesion layer 31c and the seed layer 31a. Note that the electroless plated layer 31d may be omitted.
- the seed layer 31 a is formed on the conductor 11 of the substrate 10 within the via hole 21 . Specifically, seed layer 31 a is formed on the upper surface of conductor 11 so as to be in contact with conductor 11 . The seed layer 31 a is formed along the inner surface of the insulating layer 20 from above the conductor 11 within the via hole 21 .
- the seed layer 31a is formed up to the main surface of the insulating layer 20 . That is, it is formed over the conductor 11 of the substrate 10 and over the main surface of the insulating layer 20 .
- the film thickness of the seed layer 31a is constant. Therefore, the seed layer 31 a is formed so as to extend over the main surface of the insulating layer 20 from the conductor 11 in the via hole 21 .
- the seed layer 31a is a seed electrode made of a conductive material for forming the via electrode body layer 31b by plating. Therefore, the seed layer 31a is preferably made of a conductive material with low electrical resistance.
- the seed layer 31a is a metal film made of a metal material containing copper, which is a low-resistance material, for example. In this case, the seed layer 31a may not be made of copper only, but may contain copper and other metal such as nickel. Note that the seed layer 31a may be a single film composed of only one metal film, or may be a laminated film in which a plurality of metal films are stacked.
- the via electrode body layer 31b is a plated film laminated on the seed layer 31a.
- via electrode body layer 31b is an electrolytic plated film formed by an electrolytic plating method.
- the via electrode body layer 31b is an electrolytic Cu-plated film made of copper.
- the via electrode body layer 31b is positioned on the seed layer 31a and is formed so as to fill the inside of the via hole 21 .
- the via electrode body layer 31 b is formed up to the insulating layer 20 .
- the via electrode body layer 31b is formed over the conductor 11 and the insulating layer 20 on the seed layer 31a.
- the via electrode body layer 31b is formed so as to run over the main surface of the insulating layer 20 from inside the via hole 21 of the insulating layer 20 .
- the via electrode body layer 31b constitutes most of the via electrode 31. In the present embodiment, via electrode body layer 31b occupies 90% or more of via electrode 31 in the cross-sectional view of FIG.
- the adhesion layer 31 c is formed on the insulating layer 20 . Specifically, the adhesion layer 31 c is provided between the insulating layer 20 and the seed layer 31 a located on the insulating layer 20 . In the present embodiment, the adhesion layer 31 c is a lower layer positioned above the insulating layer 20 in the via electrode 31 . That is, in the portion of the via electrode 31 located above the insulating layer 20, the adhesion layer 31c, the electroless plated layer 31d, the seed layer 31a, and the via electrode body layer 31b are laminated in this order on the insulating layer 20.
- the adhesion layer 31 c is the bottom layer of the portion of the via electrode 31 located above the insulating layer 20 .
- the seed layer 31 a is the bottom layer of the via electrode 31 in the portion of the via electrode 31 inside the via hole 21 of the insulating layer 20 .
- the adhesion layer 31c (first adhesion layer) of the via electrode 31 is formed in the same layer as the adhesion layer 32a (second adhesion layer) of the wiring 32, which will be described later. That is, the adhesion layer 31c of the via electrode 31 and the adhesion layer 32a of the wiring 32 are made of the same material and formed in the same process.
- the electroless plated layer 31d is an electroless plated film formed by an electroless plating method. Specifically, the electroless plated layer 31d is an electroless Cu plated film made of copper. As described above, in the via electrode 31, the via electrode body layer 31b and the electroless plated layer 31d are both Cu plated films, and the electroless plated layer 31d is an electroless Cu plated film.
- the layer 31b is an electrolytic Cu plating film. Therefore, the via electrode body layer 31b and the electroless plated layer 31d contain copper with different crystal grain sizes.
- the average crystal grain size of copper forming the via-electrode body layer 31b which is an electrolytic Cu-plated film
- the average crystal grain size of copper forming the electroless-plated layer 31d is larger than the average crystal grain size of copper forming the electroless-plated layer 31d, which is an electroless-plated film.
- the average crystal grain size of copper forming the electroless plated layer 31d is smaller than the average crystal grain size of copper forming the via electrode body layer 31b, which is an electrolytic Cu plated film.
- the wiring 32 has an adhesion layer 32a provided as a lower layer of the wiring 32, and a wiring body layer 32b provided on the adhesion layer 32a.
- the adhesion layer 32 a is the bottom layer of the wiring 32 .
- the adhesion layer 32 a is provided on the main surface of the insulating layer 20 .
- the wiring 32 further has a conductive layer 32c provided on the wiring body layer 32b, and an electroless plated layer 32d provided between the adhesion layer 32a and the wiring body layer 32b. That is, the wiring 32 has a laminated structure in which the adhesion layer 32a, the electroless plated layer 32d, the wiring body layer 32b, and the conductive layer 32c are laminated in this order in the direction away from the insulating layer 20.
- FIG. The lower portion of the wiring body layer 32b and the adhesion layer 32a have the same line width.
- the adhesion layer 32a is provided to facilitate adhesion between the wiring 32 and the insulating layer 20.
- the adhesion layer 32 a has a function or structure for enhancing adhesion between the wiring 32 and the insulating layer 20 .
- the adhesion layer 32 a has a fine uneven structure as a structure for enhancing the adhesion between the wiring 32 and the insulating layer 20 .
- the adhesion layer 32a has a fine uneven structure as a whole layer, but it is not limited to this. 20 side. By providing the adhesion layer 32a having the fine uneven structure in this way, the adhesion layer 32a can be easily adhered to the insulating layer 20 by the anchor effect.
- Such a fine concavo-convex structure of the adhesion layer 32a is, for example, a needle-like concavo-convex shape with a height of 500 nm or less.
- the adhesion layer 32a is made of a metal film containing copper.
- the fine concavo-convex structure of the adhesion layer 32a is made of copper and/or copper oxide.
- a fine concave-convex structure can be formed by forming copper oxide having needle-like crystals on the copper surface and roughening the copper surface.
- the micro unevenness structure may be formed by slightly etching the copper surface by micro-roughening etching to roughen the surface.
- the adhesion layer 32a may be composed of a metal element other than copper.
- the adhesion layer 32a of the wiring 32 and the adhesion layer 31c of the via electrode 31 are formed in the same layer. That is, the adhesion layer 32a, which is the lower layer of the wiring 32, and the adhesion layer 31c, which is the lower layer of the via electrode 31 located on the insulating layer 20, are made of the same material and have the same fine uneven structure. Note that the adhesion layer 32a may be formed on the electroless plated layer 32d.
- the wiring body layer 32b is a plated film laminated under the conductive layer 32c.
- the wiring body layer 32b is an electroless plated film formed by an electroless plating method.
- the wiring body layer 32b is an electroless Cu plating film made of copper.
- the wiring body layer 32b of the wiring 32 and the via electrode body layer 31b of the via electrode 31 are both Cu-plated films, but the wiring body layer 32b is an electroless Cu-plated film, and the via electrode body layer 31b is an electroless Cu-plated film.
- 31b is an electrolytic Cu plating film. Therefore, the via electrode main layer 31b and the wiring main layer 32b contain copper with different crystal grain sizes. Specifically, the average crystal grain size of copper forming the via electrode main layer 31b, which is an electrolytic Cu-plated film, is larger than the average crystal grain size of copper forming the wiring main body layer 32b, which is an electroless plated film. In other words, the average crystal grain size of copper forming the wiring body layer 32b, which is an electroless plated film, is smaller than the average crystal grain size of copper forming the via electrode body layer 31b, which is an electrolytic Cu plated film.
- Both the wiring body layer 32b of the wiring 32 and the via electrode body layer 31b of the via electrode 31 are plated films, but the wiring 32 does not have a seed layer as a lower layer. That is, the via electrode 31 has the seed layer 31a as its lower layer, but the wiring 32 does not have the seed layer as its lower layer.
- the wiring body layer 32b of the wiring 32 constitutes most of the wiring 32. In this embodiment, the wiring body layer 32b occupies 90% or more of the wiring 32 in the cross-sectional view of FIG.
- the conductive layer 32c formed on the wiring body layer 32b functions as a part of the conductor of the wiring 32 and also functions as a protective layer that protects the wiring body layer 32b. That is, when the seed layer 31a of the via electrode 31 is formed by etching and patterning the seed film, the conductive layer 32c can prevent the wiring body layer 32b from being etched and reduced. That is, when etching the seed film, the wiring body layer 32b can be protected by the conductive layer 32c. Thus, the conductive layer 32c functions as a protective layer that protects the wiring body layer 32b during etching.
- the conductive layer 32c is an electroless plated film like the wiring body layer 32b.
- the conductive layer 32c is composed of a material or structure different from that of the wiring body layer 32b.
- the conductive layer 32c is made of a conductive material different from that of the wiring body layer 32b.
- the conductive layer 32c is made of a conductive material other than copper.
- the conductive layer 32c is made of a material containing any one of nickel (Ni), palladium (Pd), platinum (Pt), and silver (Ag). That is, the conductive layer 32c is an electroless plated film containing any of these materials.
- the electroless plated layer 32d is an electroless plated film formed by an electroless plating method, like the wiring body layer 32b. Specifically, the electroless plated layer 32d is an electroless Cu plated film made of copper. However, the electroless plated film of the wiring body layer 32b and the electroless plated film of the electroless plated layer 32d are formed in separate steps.
- the electroless plated film of the wiring body layer 32b is of a type that is selectively deposited on the electrodes, and the electroless plated film of the electroless plated layer 32d can be formed uniformly over the entire surface of the insulating layer. is of type.
- FIG. 4A and 4B are diagrams for explaining a method of manufacturing the wiring transfer plate 200 with wiring used when manufacturing the wiring body 30 and the mounting substrate 1 according to the first embodiment.
- 5A and 5B are diagrams for explaining a method of manufacturing the wiring transfer plate 100.
- FIG. FIG. 6A is a cross-sectional view showing a modification of the wiring transfer plate.
- FIG. 6B is a cross-sectional view of an inter-via wiring portion of the mounting board according to the modification.
- FIG. 6C is a cross-sectional view of an interlayer connection portion of a mounting substrate according to a modification.
- FIG. 7 is a diagram showing a configuration when the wiring transfer plate 200 with wiring produced in FIG. 4 is cut along another cross section.
- FIG. 8 and 9 are diagrams for explaining the method for manufacturing the wiring body 30 and the method for manufacturing the mounting board 1 according to the first embodiment.
- 8 shows a method of manufacturing a portion corresponding to the inter-via wiring portion of FIG. 2
- FIG. 9 shows a method of manufacturing a portion corresponding to the interlayer connection portion of FIG.
- the wiring body 30 and the mounting substrate 1 are produced using the wiring transfer plate 100.
- the wiring transfer plate 100 is a wiring pattern plate for forming wiring (transfer wiring) to be transferred to another member (transfer target member) in a predetermined pattern.
- the wiring transfer plate 100 in the present embodiment is a plating pattern plate for forming an electroless plating film as transfer wiring.
- the electroless plated film formed by the wiring transfer plate 100 becomes at least part of the wiring to be transferred to another member.
- a method of manufacturing the wiring body 30 and the mounting board 1 using the wiring transfer plate 100 will be described below.
- a wiring transfer plate 200 with wiring is prepared in advance.
- the wiring transfer plate 200 with wiring is obtained by forming transfer wiring on the wiring transfer plate 100 .
- the wiring transfer plate 200 with wiring is the wiring transfer plate 100 on which the transfer wiring is formed.
- transfer wirings 36 for transferring to members constituting the mounting substrate 1 are formed.
- a wiring transfer plate 100 is prepared.
- the wiring transfer plate 100 is prepared in advance as shown in FIG.
- a substrate with a plating base material is received, in which a plating base material layer 130 is formed on a base material 110 serving as a support substrate.
- a highly rigid substrate such as a glass substrate or a metal substrate is preferably used.
- a metal substrate made of SUS is used as base material 110 .
- the plating base material layer 130 is a catalyst base material layer for forming an electroless plating film.
- the plating base material constituting the plating base material layer 130 one or a plurality of materials selected from nickel (Ni), palladium (Pd), platinum (Pt), chromium (Cr), iron (Fe), etc. can be used.
- the plating base material layer 130 is a nickel film.
- an insulating layer 120 that will become a transfer plate insulating layer is formed on the plating base material layer 130 .
- the insulating layer 120 for example, a photoresist can be used.
- the insulating layer 120 which is a photoresist, is exposed and developed to form a plurality of openings 121 in the insulating layer 120, and the plating base material layer 130 is formed. expose the That is, the insulating layer 120 covers the base material 110 so as to have the opening 121 on the plating base material layer 130 .
- the plating base material layer 130 functions as a release layer. good too. Giving releasability to the plating base material layer 130 means weakening the catalytic reaction effect of the plating base material layer 130 .
- the plating base material layer 130 can be provided with releasability.
- the release treatment for the plating base material layer 130 is not limited to the oxidation treatment.
- the plating base material layer 130 is a continuous film in FIG. 5, it is not limited to this.
- the plating base material layer 130 may be patterned and separated to form the plating base material layer 130A for each opening 121.
- FIG. 5 is a continuous film in FIG. 5, it is not limited to this.
- the plating base material layer 130 may be patterned and separated to form the plating base material layer 130A for each opening 121.
- the wiring 32 that will be the wiring for transfer is formed on the wiring transfer plate 100 .
- an electroless plating film (electroless plating layer) is formed on the plating base material layer 130 by an electroless plating method.
- a metal is deposited and grown by a catalytic reaction caused by the catalyst of the plating base material layer 130 , thereby forming an electroless plating film on the plating base material layer 130 .
- a conductive layer 32c and a wiring body layer 32b made of different materials are laminated as electroless plating films.
- the plating base material layer 130 is a nickel film
- a conductive layer 32c made of an electrolytic Pd-plated film is formed, and a wiring body layer 32b made of an electroless Cu-plated film is laminated on the conductive layer 32c.
- the conductive layer 32c is preferably an electroless plated film.
- the conductive layer 32c can be formed thin and with a uniform film thickness.
- the conductive layer 32c may be an electroplated film instead of an electroless plated film.
- the electroless Ni film or the electroless silver-plated film is removed without corroding Cu when forming a wiring body in a later step. Therefore, the wiring body can be easily made of only Cu. If the electroless Ni film remains, there is a concern that the wiring resistance of the wiring body will increase because the electroless Ni film generally contains substances such as boron and phosphorus and thus has high resistance. In addition, the electroless Ni film has magnetism, and there is a concern that the high-frequency characteristics and the like may be degraded. In addition, since silver is a metal that easily causes ion migration, there is a concern that reliability characteristics may deteriorate.
- FIG. 6B shows a cross-sectional view of the inter-via wiring portion of the mounting board corresponding to line II-II in FIG.
- FIG. 6C shows a cross-sectional view of the interlayer connection portion of the mounting board corresponding to line III-III in FIG.
- the conductive layer 32c remains at the connecting portion between the via electrode 31A and the wiring 32A. Good connection characteristics can be obtained as the seed layer 31a that forms the electrolytic Ni film or the electroless silver plating film and the electroless Cu film.
- the conductive layer 32c is an electroless Pd film or an electroless Pt film
- the electroless Pd film or the electroless Pt film generally contains almost no impurities, the surface resistance of the wiring can be kept low.
- it does not have magnetism, it is also advantageous in terms of high-frequency characteristics.
- Pd or Pt forming the electroless Pd film or the electroless Pt film is a metal that is more stable than Cu, it can function as a barrier layer that suppresses ion migration.
- the conductive layer 32c is preferably an electroless plated film.
- the film thickness of the conductive layer 32c can be formed to be uniform.
- the conductive layer 32c may be an electroplated film instead of an electroless plated film.
- an electroless plated film 33 is formed by an electroless plating method.
- an electroless Cu plating film is formed as the electroless plating film 33 .
- the electroless plated film 33 is formed not only on the metal but also on the insulating material. be.
- the electroless plated film 33 on the wiring body layer 32b is thinner than the electroless plated film on the insulating layer 120 because the electroless plated film 33 is difficult to self-grow on copper.
- an adhesion film 34 is formed.
- Adhesion film 34 is formed to cover electroless plated film 33 .
- the adhesion film 34 is formed over the entire upper surface of the substrate 110 .
- the adhesion film 34 can be formed by forming a metal film such as a copper film made of copper over the entire upper surface of the substrate 110 and performing an adhesion treatment to impart adhesion to the metal film.
- the adhesion film 34 having a fine uneven structure can be formed by roughening the metal film as adhesion treatment.
- the conductive layer 32c, the wiring body layer 32b, the electroless plated film 33, and the adhesion film 34 constituting the transfer wiring 36 are formed on the wiring transfer plate 100.
- the attached wiring transfer plate 200 is completed.
- the wiring transfer plate 200 with wiring has a structure as shown in FIG.
- the wiring transfer plate 200 with wiring thus manufactured can transfer the transfer wiring 36 to another member. That is, the conductive layer 32c, the wiring body layer 32b, the electroless plated film 33, and the adhesion film 34 are the transfer wiring 36 to be transferred to another member.
- the wiring transfer plate 100 after transferring the transfer wirings 36 of the wiring transfer plate 200 with wires to another member returns to the state of (a) in FIG. 4 and can be used repeatedly. That is, the wiring transfer plate 100 can be reused. Specifically, as shown in (b) to (e) of FIG. It can be transferred to another member.
- the wiring body 30 and the mounting board 1 are manufactured by using the wiring transfer plate 200 with wiring. 8 showing the cross section of the inter-via wiring portion of the mounting board 1 and FIG. 9 showing the cross section of the interlayer connecting portion of the mounting board 1.
- FIG. 8 showing the cross section of the inter-via wiring portion of the mounting board 1
- FIG. 9 showing the cross section of the interlayer connecting portion of the mounting board 1.
- the transfer wiring 36 is arranged on the substrate 10 with the insulating layer 20 interposed therebetween.
- the transfer wiring 36 is formed by a transfer method using a wiring transfer plate 200 with wiring prepared in advance.
- a substrate 10 having conductors 11 is prepared.
- a build-up substrate is prepared in which wirings, electrodes, etc. are formed as conductors 11 on the uppermost layer.
- an insulating material is placed between the substrate 10 having the conductor 11 and the wiring transfer plate 200 with wiring, thereby separating the substrate 10 and the wiring.
- An insulating layer 20 is formed between the attached wiring transfer plate 200 and the wiring transfer plate 200 .
- an insulating material to be the insulating layer 20 is placed on the substrate 10 having the conductors 11, and the wiring transfer plate 200 with wires is placed on the insulating material. That is, the insulating material of the insulating layer 20 is inserted between the substrate 10 and the wiring transfer plate 200 with wiring. At this time, the wiring transfer plate 200 with wiring is arranged so that the transfer wiring 36 faces the insulating layer 20 side.
- the liquid insulating resin material is used as the insulating material for the insulating layer 20
- the liquid insulating resin material is applied onto the substrate 10 having the conductors 11, and the wiring transfer plate 200 with wiring is applied thereon. to cure the liquid insulating resin material.
- the liquid insulating resin material is a thermosetting resin
- it is cured by heating or drying
- the liquid insulating resin material is a photocurable resin
- it is cured by light irradiation.
- the insulating layer 20 can be formed between the substrate 10 and the wiring transfer plate 200 with wiring.
- the film-like insulating resin sheet is placed on the substrate 10 having the conductors 11, and the wiring transfer plate 200 with wires is placed thereon. and heat-compress. At this time, the wiring transfer plate 200 with wiring is pressed toward the substrate 10 . Thereby, the insulating layer 20 can be formed between the substrate 10 and the wiring transfer plate 200 with wiring.
- the wiring transfer plate 100 included in the wiring transfer plate 200 with wiring is separated from the insulating layer 20 . That is, the wiring transfer plate 100 and the insulating layer 20 are separated. As a result, the transfer wiring 36 of the wiring transfer plate 200 with wiring is separated from the plating base material layer 130 (release layer) and transferred to the substrate 10 side. Specifically, the transfer wiring 36 of the wiring transfer plate 200 with wiring is transferred to the insulating layer 20 , and the transfer wiring 36 is formed on the insulating layer 20 .
- the conductive layer 32c, the wiring body layer 32b, the electroless plated film 33, and the adhesion film 34 are transferred to the insulating layer 20. As shown in FIG.
- the transfer wiring 36 is easily separated from the plating base material layer 130, and the transfer wiring Since 36 has the adhesion film 34 , it is easily adhered to the insulating layer 20 . Thereby, the transfer wiring 36 can be easily transferred to the insulating layer 20 . That is, the laminate (laminated wiring) of the conductive layer 32 c and the wiring body layer 32 b , the electroless plated film 33 and the adhesion film 34 can be easily transferred to the insulating layer 20 .
- the insulating resin sheet when a film-shaped insulating resin sheet is used as the insulating material for the insulating layer 20, the insulating resin sheet preferably has adhesiveness. This makes it easier for the adhesion film 34 of the transfer wiring 36 to adhere to the insulating layer 20 , so that the transfer wiring 36 can be transferred to the insulating layer 20 more easily.
- the member in which the transfer wiring 36 is transferred to the substrate 10 having the conductors 11 is the wiring body intermediate member 300 that is an intermediate member of the wiring body 30 arranged on the substrate 10 . Therefore, the wiring body intermediate material 300 is formed on the insulating layer 20 and includes the adhesion film 34 having the fine uneven structure, the electroless plated film 33 formed on the adhesion film 34, the conductive layer 32c and the wiring. and a body layer 32b.
- the electroless plated film 33, the adhesion film 34 and the insulating layer 20 are partly removed so that the conductor 11 is exposed.
- a via hole 21 is formed in the insulating layer 20 .
- the electroless plated film 33 , the adhesion film 34 and part of the insulating layer 20 can be removed to form the via hole 21 .
- the conductors 11 of the substrate 10 are exposed.
- a seed film 35 is formed to cover the exposed conductor 11, the electroless plated film 33, and the wiring body layer 32b. Specifically, after removing the residue of the insulating layer 20 by desmearing and laser processing, the seed film 35 is formed over the entire upper surface of the substrate 10 by electroless plating or sputtering. Further, in the present embodiment, since the conductive layer 32c exists on the wiring body layer 32b, the seed film 35 is laminated on each of the conductor 11, the electroless plated film 33 and the conductive layer 32c.
- the seed film 35 is a seed electrode for forming the via electrode body layer 31b of the via electrode 31 by electroplating. Therefore, the wiring body layer 32b and the conductive layer 32c can be protected by the seed film 35 until the seed film 35 is removed in subsequent steps.
- the seed film 35 covers not only the upper portion of the conductive layer 32c but also the side portions of the wiring body layer 32b and the conductive layer 32c. Therefore, a small amount of the seed film 35 component (such as Pd) is present on the top and side portions of the wiring body layer 32b and the conductive layer 32c.
- the seed film 35 is a metal film made of a metal material containing copper.
- the seed film 35 may consist of only copper, or may contain copper and other metals such as nickel.
- a resist 40 is selectively formed on the seed film 35 so that the portion of the seed film 35 covering the conductor 11 is exposed. . Specifically, an opening 41 is formed in the resist 40 above the conductor 11 .
- the resist 40 covers the wiring body layer 32b.
- a dry film resist (DFR), for example, can be used as the resist 40 .
- the via electrode body layer 31b is formed on the exposed seed film 35. Then, as shown in FIG. Specifically, the via electrode body layer 31b is formed so as to fill the inside of the opening 41 of the resist 40 .
- an electrolytic plated film is formed on the seed film 35 in the opening 41 by an electrolytic plating method as the via electrode main body layer 31b.
- the via electrode body layer 31b is an electrolytic Cu plating film.
- part of the via electrode body layer 31b is formed on the end of the transfer wiring 36 in the interlayer connection. Specifically, part of the via electrode body layer 31 b is formed on the seed film 35 laminated on the transfer wiring 36 .
- the resist 40 is removed. Specifically, the resist 40, which is a dry film resist, is removed. As a result, the portion of the seed film 35 covered with the resist 40 is exposed.
- the exposed seed film 35 is removed, and the electroless plated film 33 and the adhesion film existing under the exposed seed film 35 are removed.
- 34 is removed. That is, the portion of the seed film 35 that covers the wiring body layer 32b is removed, and the portions of the electroless plated film 33 and the adhesion film 34 that are not covered with the wiring body layer 32b and the via electrode body layer 31b are removed.
- the exposed seed film 35 and the electroless plated film 33 and adhesion film 34 existing under the exposed seed film 35 are removed by etching using an etchant.
- the seed film 35 and the conductive layer 32c of the transfer wiring 36 are made of different conductive materials, the seed film 35 can be selectively etched without etching the conductive layer 32c.
- the seed film 35, the electroless plated film 33, and the adhesion film 34 remain under the via electrode body layer 31b.
- the remaining seed film 35 becomes the seed layer 31a
- the remaining electroless plating film 33 becomes the electroless plating layer 31d
- the remaining adhesion film 34 becomes the adhesion layer 31c.
- the via electrode 31 having the seed layer 31a, the electroless plated layer 31d, the via electrode body layer 31b, and the adhesion layer 31c is formed.
- the seed film 35, the electroless plating film 33 and the adhesion film 34 are etched so that the electroless plating film 33 and the adhesion film 34 remain under the wiring body layer 32b.
- the remaining electroless plating film 33 becomes the electroless plating layer 32d, and the remaining adhesion film 34 becomes the adhesion layer 32a. and wiring 32 is formed.
- the electroless plated film 33 laminated on the wiring body layer 32b is thinner than the electroless plated film laminated on the insulating layer 120, so the thickness of the electroless plated layer 32d in the wiring 32 is The thickness is thinner than the thickness of the electroless plated layer 31 d in the via electrode 31 .
- the thickness of the electroless plating layer 31 d in the via electrode 31 is thicker than the thickness of the electroless plating layer 32 d in the wiring 32 .
- the wiring bodies 30 having the via electrodes 31 and the wirings 32 are formed, and the mounting substrate 1 having the wiring bodies 30 can be manufactured. That is, the wiring body 30 can be manufactured on the substrate 10 having the conductor 11 , and the mounting substrate 1 with the wiring body 30 arranged on the substrate 10 can be manufactured.
- FIG. 10 is a diagram for explaining a manufacturing method of a conventional mounting substrate 1X having via electrodes 31X and wirings 32X, and shows a general modified semi-additive process (MSAP method).
- MSAP method general modified semi-additive process
- the base material 110X is separated from the metal film 33X, and the metal film 33X is transferred to the insulating layer 20. Then, as shown in FIG. 10(b), the base material 110X is separated from the metal film 33X, and the metal film 33X is transferred to the insulating layer 20. Then, as shown in FIG. 10(b), the base material 110X is separated from the metal film 33X, and the metal film 33X is transferred to the insulating layer 20. Then, as shown in FIG.
- the metal film 33X and the insulating layer 20 are partly removed with a laser to form a via hole 21 on the conductor 11, exposing the conductor 11. Then, as shown in FIG. 10(c), the metal film 33X and the insulating layer 20 are partly removed with a laser to form a via hole 21 on the conductor 11, exposing the conductor 11. Then, as shown in FIG. 10(c), the metal film 33X and the insulating layer 20 are partly removed with a laser to form a via hole 21 on the conductor 11, exposing the conductor 11. Then, as shown in FIG.
- a seed film 35X made of an electroless plated film is formed over the entire upper surface of the substrate 10 by an electroless plating method. Thereby, a seed film 35X is formed on the exposed conductor 11.
- a resist 40X having openings 41X and 42X is formed.
- the opening 41X is formed in a portion corresponding to the via electrode 31X, and the opening 42X is formed in a portion corresponding to the wiring 32X.
- a dry film resist can be used as the resist 40X.
- an electrolytic plated film is formed on the seed film 35X in the openings 41X and 42X by an electrolytic plating method.
- an electroplated film to be the via electrode body layer 31b is formed on the seed film 35X covering the conductor 11 in the opening 41X, and a wiring body layer 32b is formed on the seed film 35X in the opening 42X.
- An electrolytic plated film is formed. That is, the via electrode body layer 31b and the wiring body layer 32b are formed at the same time.
- the via electrode body layer 31b and the wiring body layer 32b are electrolytic Cu plating films made of copper, for example.
- the resist 40X is removed to expose the seed film 35X.
- the exposed seed film 35X and the metal film 33X under the seed film 35X are removed by etching.
- the seed film 35X and the metal film 33X under the via electrode body layer 31b are left, and the remaining seed film 35X becomes the seed layer 31a and the via electrode 31X. is formed.
- the seed film 35X and the metal film 33X under the wiring body layer 32b remain, and the wiring 32X composed of the metal film 33X, the seed film 35X and the wiring body layer 32b is formed.
- the line width of the wiring 32X is smaller than the diameter of the via electrode 31X, the seed film 35X and the metal film 33X are removed as shown in FIG.
- the lower layer of the wiring 32X is undercut due to overetching. That is, when the seed film 35X is etched, the line width of the lower layer of the wiring 32X is reduced. Specifically, the metal film 33X and the seed film 35X in the wiring 32X are undercut to reduce the wiring width. As a result, a wiring defect may occur in the wiring 32X. Therefore, it is difficult to miniaturize the wiring 32X by the conventional manufacturing method of the mounting board 1X. In this case, the film thickness of the seed film 35X may be reduced so that the lower portion of the wiring 32X is not undercut. It is not possible.
- the adhesion layer 31c which is the lower layer of the via electrode 31 above the insulating layer 20
- the adhesion layer 32a which is the lower layer of the wiring 32
- the seed layer 31a that is the lower layer in the via hole 21 of the via electrode 31 and the adhesion layer 32a that is the lower layer of the wiring 32 are made of different conductive materials or uneven shapes.
- the seed layer 31a of the via electrode 31 and the adhesion layer 32a of the wiring 32 both contain copper, but are made of different conductive materials.
- the seed layer 31a and the adhesion layer 32a are metal films containing copper as the same metal element, but at least one of the seed layer 31a and the adhesion layer 32a is a metal film containing a metal element other than copper or has a different structure.
- the seed layer 31a and the adhesion layer 32a are made of different conductive materials or uneven shapes.
- the lower layer of the wiring 32 is the adhesion layer 32a, and unlike the via electrode 31, the wiring 32 does not have a seed layer as a lower layer.
- the via electrode 31 has an adhesion layer 31 c on the insulating layer 20 , but does not have an adhesion layer in the lower layer inside the via hole 21 .
- the portion of the via electrode 31 located above the insulating layer 20 includes the adhesion layer 31c and the seed layer 31a having a fine uneven structure. including both. Thereby, the adhesion between the via electrode 31 and the insulating layer 20 can be improved.
- the adhesion layer 31c of the via electrode 31 or the adhesion layer 32a of the wiring 32 is formed on the electroless plating layer 31d or the electroless plating layer 32d.
- the film thickness of the electroless plated layer 31d of 1 and the film thickness of the electroless plated layer 32d of the wiring 32 are different.
- the electroless plated layer 31 d of the via electrode 31 is thicker than the electroless plated layer 32 d of the wiring 32 .
- the wiring body 30 and the mounting board 1 according to the present embodiment even if the via electrodes 31 are provided, the wiring 32 can be miniaturized and narrowed in pitch.
- the method of manufacturing the wiring body 30 and the method of manufacturing the mounting substrate 1 in the present embodiment include the adhesion film 34 having the fine uneven structure and the a step of arranging the wiring body layer 32b located, and then a step of forming a via hole 21 in the insulating layer 20 so as to expose the conductor 11 by removing a part of the adhesion film 34 and the insulating layer 20; Next, a step of forming a seed film 35 so as to cover the exposed conductors 11, the adhesion film 34, and the wiring body layer 32b; a step of selectively forming a resist 40 on the exposed seed film 35; then a step of forming a via electrode body layer 31b on the exposed seed film 35; and removing the adhesion film 34 existing under the exposed seed film 35 .
- the wiring body layer 32b can be protected by the seed film 35 and the via electrode body layer 31b can be formed.
- the wiring 32 thus formed can be miniaturized and the pitch can be narrowed.
- the fine and narrow-pitch wiring 32 and the via electrodes 31 can be formed in the same wiring layer.
- the wiring body layer 32b is formed by the transfer method.
- the wiring body layer 32b is formed using a wiring transfer plate 200 with wiring, which is the wiring transfer plate 100 on which the transfer wiring 36 is formed.
- the wiring transfer plate 200 with wiring includes a base material 110, a release layer (plated base material layer 130) formed on the base material 110, and the base material 110 so as to have an opening 121 on the release layer.
- Insulating layer 120 (transfer plate insulating layer) covering wiring body layer 32b which is an electroless plated film formed on release layer 131 in opening 121, wiring body layer 32b, and insulating layer 120 and an adhesion film 34 formed to cover and having a fine concavo-convex structure.
- the wiring body layer 32b, which is an electroless plated film, and the adhesion film 34 are transfer wirings 36 to be transferred to another member.
- the fine wiring body layer 32b can be accurately transferred. can be formed.
- the wiring is formed by the photolithography method, if the surface of the portion where the wiring is formed has unevenness, the focus is shifted and the fine wiring cannot be formed with high precision.
- the wiring body layer 32b by the transfer method using the wiring transfer plate 200 with wiring, even if the surface of the portion where the wiring body layer 32b is to be formed has unevenness and is not flat, It can absorb the unevenness. As a result, the fine wiring body layer 32b can be formed with high precision.
- the wiring body layer 32b can be formed with high alignment accuracy.
- the wiring body layer 32b and the adhesion film 34 are simultaneously transferred by a transfer method. That is, the wiring transfer plate 100 is used to transfer not only the wiring body layer 32b but also the adhesion film 34 together with the wiring body layer 32b.
- the via electrode 31 includes a seed layer 31a formed over the conductor 11 and the insulating layer 20, and a seed layer 31a formed over the conductor 11 and the insulating layer 20 over the seed layer 31a.
- the adhesion layer 31c of the via electrode 31 is provided between the insulating layer 20 and the seed layer 31a located on the insulating layer 20.
- the via electrode body layer 31b can be easily formed by electroplating.
- the wiring 32 further has a conductive layer 32c provided on the wiring body layer 32b, and the conductive layer 32c is made of a conductive material different from that of the wiring body layer 32b. ing.
- the wiring body layer 32b can be protected by the conductive layer 32c. That is, selective etching using the difference in etching rate between the seed film 35 and the wiring body layer 32b becomes possible. As a result, it is possible to suppress a change in the line width of the wiring 32 due to film reduction when the seed film 35 is etched.
- the conductive layer 32c is also transferred by the wiring transfer plate 100 in the present embodiment.
- the conductive layer 32c is simultaneously transferred in addition to the wiring body layer 32b and the adhesion film 34.
- the wiring body layer 32b, the conductive layer 32c, and the adhesion film 34 can be efficiently formed.
- the via electrode body layer 31b and the wiring body layer 32b contain copper with different crystal grain sizes.
- the via electrode body layer 31b and the wiring body layer 32b can be formed by different manufacturing methods depending on the properties required other than low resistance.
- the via electrode body layer 31b and the wiring body layer 32b can be formed by different plating methods.
- the via electrode body layer 31b of the via electrode 31 is an electrolytic plated film formed by an electrolytic plating method, and occupies 90% or more of the via electrode 31 in a cross-sectional view.
- the via electrode body layer 31b as a relatively low-stress electrolytic plated film, it is possible to suppress the occurrence of plating peeling and cracks in the via electrode 31 due to internal stress.
- the wiring body layer 32b of the wiring 32 is an electroless plated film formed by an electroless plating method, and occupies 90% or more of the wiring 32 in a cross-sectional view.
- the line width of the wiring 32 in the present embodiment is preferably 5 ⁇ m or less, more preferably 2 ⁇ m or less.
- the wiring 32 is preferably 5 ⁇ m or less, more preferably 2 ⁇ m or less.
- the wiring body 30 manufactured in this manner can be used as a wiring layer or a redistribution layer (RDL) in a semiconductor package substrate.
- RDL redistribution layer
- the wiring body 30 can be used as a rewiring layer in the mounting board 1A, which is a 2.1D semiconductor package substrate (organic interposer).
- the mounting substrate 1B which is a 2.3D semiconductor package substrate (organic interposer).
- the substrate 10 is a buildup substrate.
- the wiring body 30 can be used as a rewiring layer in the mounting substrate 1C, which is a 2.5D semiconductor package substrate (Si or Glass interposer).
- the wiring body 30 can also be used as a rewiring layer in a mounting board that is an FO-WLP (Fan Out-Wafer Level Package).
- FO-WLP Full Out-Wafer Level Package
- mounting substrates 1A, 1B, and 1C shown in FIGS. 11 to 13 can also be applied to the following second and third embodiments.
- the wiring body 30 can also be applied to the buildup layer (wiring layer) itself of a general buildup board instead of the rewiring layer.
- the wiring body 30 can be applied to the wiring layer of the board 10, which is a buildup board shown in FIGS. 11 to 13. FIG.
- the wiring distance from the electronic component formed in the core such as an inductor or capacitor to the semiconductor is shortened, so the electrical characteristics are improved, and an interposer or rewiring layer is not required. Therefore, an inexpensive semiconductor package can be obtained.
- FIG. 14 is a cross-sectional view of a mounting board 1D according to the second embodiment.
- the wiring 32 in the first embodiment has the conductive layer 32c formed on the wiring body layer 32b, as shown in FIG. 2, the conductive layer 32c is not formed on the wiring body layer 32b.
- the wiring 32D is composed only of the adhesion layer 32a, the electroless plated layer 32d, and the wiring body layer 32b.
- the seed layer 31a of the via electrode 31 and the wiring body layer 32b of the wiring 32 contain the same metal.
- seed layer 31aD of via electrode 31D and wiring body layer 32b of wiring 32D contain different kinds of metals.
- both the seed layer 31a and the wiring body layer 32b are metal films containing copper, but in the present embodiment, the wiring body layer 32b is composed only of copper.
- the seed layer 31aD is a metal film containing a metal other than copper. That is, in the present embodiment, the wiring body layer 32b of the wiring 32D is the same as that of the first embodiment, but the seed layer 31aD of the via electrode 31D is different from that of the first embodiment and is made of a metal other than copper. contains.
- the wiring body 30D and the mounting structure according to the present embodiment are the same.
- the substrate 1D is the same as the wiring body 30 and the mounting substrate 1 according to the first embodiment.
- the wiring body 30D and the mounting board 1D configured in this way are manufactured by the method shown in FIG. 15A and 15B are diagrams for explaining a method for manufacturing the wiring body 30D and a method for manufacturing the mounting board 1D according to the second embodiment.
- a wiring transfer plate 200D with wiring is used in which transfer wirings 36D are formed on the wiring transfer plate 100.
- the wiring 32D is formed by the transfer method using the wiring transfer plate 200D with the wiring prepared in advance.
- the transfer wiring 36D does not have the conductive layer 32c.
- the transfer wiring 36D is composed of the wiring body layer 32b, the electroless plated film 33, and the adhesion film .
- transfer wiring 36D is arranged on substrate 10 with insulating layer 20 interposed therebetween.
- a substrate 10 having conductors 11 is prepared in the same manner as in the step of FIG. 8(a).
- an insulating material is placed between the substrate 10 having the conductors 11 and the wiring transfer plate 200D with wiring, similarly to the step of FIG. 8(b).
- the insulating layer 20 is formed between the substrate 10 and the wiring transfer plate 200D.
- the wiring transfer plate 100 included in the wiring transfer plate 200D with wiring is separated from the insulating layer 20 in the same manner as in the step of FIG. 8(c).
- the transfer wiring 36D of the wiring transfer plate 200D with wiring is separated from the release layer 131 and transferred to the substrate 10 side.
- the transfer wiring 36 ⁇ /b>D of the wiring transfer plate 200 ⁇ /b>D with wiring is transferred to the insulating layer 20 and formed on the insulating layer 20 .
- the wiring body layer 32b, the electroless plated film 33, and the adhesion film 34 are transferred to the insulating layer 20.
- FIG. 15(c) the wiring transfer plate 100 included in the wiring transfer plate 200D with wiring is separated from the insulating layer 20 in the same manner as in the step of FIG. 8(c).
- a via hole 21 is formed in the insulating layer 20 so that the conductor 11 is exposed. That is, the via hole 21 is formed in the insulating layer 20 by laser to expose the conductor 11 of the substrate 10 .
- a seed film is formed so as to cover the exposed conductors 11, the electroless plated film 33, and the wiring body layer 32b in the same manner as in the step (e) of FIG. Form 35D.
- a seed film 35 ⁇ /b>D is formed over the entire upper surface of the substrate 10 .
- the seed film 35D contains a different kind of metal than the wiring body layer 32b.
- the wiring body layer 32b is composed only of copper, but the seed film 35D contains a metal other than copper.
- the seed film 35D is selectively deposited on the seed film 35D so that the portion of the seed film 35D covering the conductor 11 is exposed.
- a resist 40 is formed.
- the via electrode body layer 31b is formed on the exposed seed film 35D in the same manner as in the step of FIG. 8(g). Specifically, the via electrode body layer 31b is formed so as to fill the inside of the opening 41 of the resist 40 .
- the via electrode body layer 31b is an electroplated film laminated on the seed film 35D of the opening 41 by electroplating. Specifically, the via electrode body layer 31b is an electrolytic Cu plating film.
- the resist 40 is removed in the same manner as in the step (h) of FIG. As a result, the portion of the seed film 35D covered with the resist 40 is exposed.
- the exposed seed film 35D and the electroless plated film 33 existing under the exposed seed film 35D and the adhesion are formed.
- the film 34 is removed by etching using an etchant. That is, the portion of the seed film 35D that covers the wiring body layer 32b is removed, and the electroless plated film 33 and the adhesion film 34 that are not covered with the wiring body layer 32b and the via electrode body layer 31b are removed.
- the seed film 35D is selectively etched without etching the wiring body layer 32b. be able to.
- the via electrode 31D having the seed layer 31aD, the via electrode body layer 31b, the electroless plated layer 31d, and the adhesion layer 31c is formed.
- the wiring 32D having the adhesion layer 32a, the electroless plated layer 32d, and the wiring body layer 32b is formed.
- the wiring body 30D having the via electrode 31D and the wiring 32D is formed, and the mounting substrate 1D having the wiring body 30D can be manufactured. That is, the wiring body 30D can be manufactured on the substrate 10 having the conductor 11, and the mounting board 1D having the wiring body 30D arranged on the substrate 10 can be manufactured.
- the adhesion layer 31c which is a lower layer positioned on the insulating layer 20 in the via electrode 31D
- the adhesion layer 32a which is the lower layer in 32D
- the lower layer of the wiring 32D is the adhesion layer 32a, and the wiring 32D does not have a seed layer as a lower layer.
- the adhesion layer 31c exists on the insulating layer 20, but the adhesion layer does not exist in the lower layer in the via hole 21.
- the seed layer 31aD which is the lower layer of the via electrode 31D
- the seed film 35D it is possible to suppress undercutting of the lower layer of the wiring 32D due to the etching. It is possible to suppress the reduction in the line width of the lower layer of the wiring 32D.
- the wiring 32D can be miniaturized and narrowed in pitch.
- the wiring 32D does not have the conductive layer 32c, and the wiring body layer 32b is not protected by the conductive layer 32c when the seed film 35D is etched. Since the layer 32b is made of a different kind of metal, selective etching using the difference in etching rate between the seed film 35D and the wiring body layer 32b is possible. In other words, although the conductive layer 32c is not formed on the wiring body layer 32b, it is possible to prevent the wiring body layer 32b from being removed by the etchant when the seed layer 31aD is etched with the etchant. As a result, it is possible to suppress a change in the line width of the wiring 32D due to film reduction during etching of the seed film 35D.
- the wiring 32D does not have the conductive layer 32c in the present embodiment, the wiring 32D may have the conductive layer 32c.
- FIG. 16 is a cross-sectional view of a mounting board 1E according to the third embodiment.
- the via electrode 31 is composed of the seed layer 31a, the via electrode body layer 31b which is an electrolytic plated film laminated on the seed layer 31a, the electroless plated layer 31d, and the adhesion layer 31c. but it is not limited to this.
- the via electrode 31E does not have the seed layer 31a, and the via electrode body layer 31bE and the electroless electrode body layer 31bE do not have the seed layer 31a. It is composed only of the plating layer 31d and the adhesion layer 31c.
- the via electrode body layer 31bE is formed of a conductive paste such as silver paste instead of an electrolytic plated film.
- the wiring body 30E and the mounting board 1E according to the present embodiment are the same as the wiring body 30 and the mounting board 1 according to the first embodiment except for the configuration of the via electrodes 31E.
- the wiring body 30E and mounting substrate 1E configured in this manner are manufactured by the method shown in FIG. 17A and 17B are diagrams for explaining the method for manufacturing the wiring body 30E and the method for manufacturing the mounting substrate 1E according to the third embodiment.
- a wiring transfer plate 200 with wiring is used in which the transfer wiring 36 is formed on the wiring transfer plate 100 . That is, also in the present embodiment, the wiring 32 is formed by the transfer method using the wiring transfer plate 200 with wiring prepared in advance.
- transfer wiring 36 is arranged on substrate 10 with insulating layer 20 interposed therebetween.
- steps of (a) to (c) of FIG. 17 are the same as the steps of (a) to (c) of FIG.
- the adhesive film 34 and a part of the insulating layer 20 are removed by a laser to form a via hole 21 in the insulating layer 20. As shown in FIG. to expose the conductors 11 of the substrate 10 .
- a via electrode body layer 31bE is formed to cover the exposed conductor 11, and then the electroless plated film 33 and adhesion film 34 are removed by etching. .
- via electrodes 31E can be formed.
- the via electrode body layer 31bE can be formed by applying a conductive paste, for example.
- the wiring body 30E having the via electrode 31E and the wiring 32 is formed, and the mounting substrate 1E having the wiring body 30E can be produced. That is, the wiring body 30E can be manufactured on the substrate 10 having the conductor 11, and the mounting board 1E with the wiring body 30E arranged on the substrate 10 can be manufactured.
- the adhesion layer 31c which is a lower layer positioned on the insulating layer 20 in the via electrode 31E
- the adhesion layer 32a which is the lower layer of the wiring 32
- the lower layer of the via electrode 31E in the via hole 21 is a part of the via electrode body layer 31bE made of a conductive paste, and is an adhesion layer that is the lower layer of the wiring 32.
- 32a is made of a different conductive material.
- the via electrode 31E does not have a seed layer, it is not necessary to etch the seed layer when forming the via electrode 31E. Therefore, since the layer under the wiring 32 is not undercut when the seed layer is etched, the line width of the layer under the wiring 32 is not reduced.
- the wiring 32E can be miniaturized and narrowed in pitch.
- FIG. 18 is a cross-sectional view of a mounting board 1F according to the fourth embodiment.
- the wiring 32 includes an adhesion layer 32a having a fine uneven structure, an electroless plating layer 32d (seed layer) that is an electroless plating film of Cu, and a wiring main body that is an electroless plating film of Cu.
- an adhesion layer 32a having a fine uneven structure an electroless plating layer 32d (seed layer) that is an electroless plating film of Cu
- a wiring main body that is an electroless plating film of Cu.
- the present invention is not limited to this.
- the wiring 32F does not have the conductive layer 32c that is the protective layer, and the adhesion layer 32aF and the It is composed of an electroless plated layer 32d and a wiring body layer 32bF.
- the adhesion layer 32aF is not formed with a micro uneven structure by copper oxide treatment or the like, but is formed by forming an organic thin film by organic adhesion treatment.
- the adhesive layer 32aF is chemically bonded to the resin forming the insulating layer 20. It is possible to form an organic thin film composed of an organic component and an organic component chemically bonded to copper constituting the wiring body layer 32bF.
- the adhesion layer 32a is formed by copper oxide treatment, there is a possibility that the electroless plated layer 32d (seed layer) may be peeled off during the copper oxide treatment, or the wiring 32 may be peeled off during etching because copper oxide is vulnerable to acid.
- the adhesion layer 32aF by an organic adhesion process as in the present embodiment, such a problem can be suppressed.
- the wiring body layer 32bF is not an electroless plated film but an electroplated film.
- the wiring body layer 32bF is an electroplating film made of copper.
- the wiring body 30F and the mounting board 1F according to the present embodiment are the same as the wiring body 30 and the mounting board 1 according to the first embodiment except for the configuration of the wiring 32F. Moreover, the present embodiment can be applied not only to the first embodiment, but also to the second and third embodiments.
- the insulating layer 120 serving as the transfer plate insulating layer in the wiring transfer plate 100 was a resist, but the present invention is not limited to this.
- the insulating layer 120 may be an insulating resin material made of an inorganic material such as SiO2 .
- the wiring transfer plate 100B having the insulating layer 120B can be produced by the method shown in FIG.
- a base material with a plating base material is received, in which a base material layer 130 is formed on a base material 110 serving as a supporting substrate.
- an insulating layer 120B (transfer plate insulating layer) made of SiO 2 is formed on the plating base material layer 130 .
- a resist 140 is formed on the insulating layer 120B.
- the resist 140 is patterned by exposing and developing the resist 140 to form an opening 141 in the resist 140 and expose the insulating layer 120B.
- the electroless plated film may be an electroplated film, and the electroplated film may be an electrolytic plated film.
- the electroless plated film and the electroplated film may be plated films without distinction.
- a wiring body according to the present disclosure is useful as a wiring layer or the like in a mounting substrate such as a semiconductor package substrate.
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Abstract
Description
まず、実施の形態1に係る配線体30及び実装基板1の構成について、図1~図3を用いて説明する。図1は、実施の形態1に係る実装基板1の配線体30における1つの配線層の配線パターンの一例を示す平面図である。図2は、図1のII-II線における同実装基板1のビア間配線部の断面図である。また、図3は、図1のIII-III線における同実装基板1の層間接続部の断面図である。
次に、実施の形態2に係る配線体30D及び実装基板1Dについて、図14を用いて説明する。図14は、実施の形態2に係る実装基板1Dの断面図である。
次に、実施の形態3に係る配線体30E及び実装基板1Eについて、図16を用いて説明する。図16は、実施の形態3に係る実装基板1Eの断面図である。
次に、実施の形態4に係る配線体30F及び実装基板1Fについて、図18を用いて説明する。図18は、実施の形態4に係る実装基板1Fの断面図である。
以上、本開示に係る配線体及び実装基板等について、実施の形態に基づいて説明したが、本開示は、上記実施の形態1~4に限定されるものではない。
10 基板
11 導電体
20 絶縁層
21 ビアホール
30、30A、30D、30E、30F 配線体
31、31A、31D、31E ビア電極
31a、31aD シード層
31b、31bE ビア電極本体層
31c 密着層
31d 無電解めっき層
32、32A、32D、32E、32F 配線
32a、32aF 密着層
32b、32bF 配線本体層
32c 導電層
32d 無電解めっき層
33 無電解めっき膜
34 密着膜
35、35D シード膜
36、36D 転写用配線
40 レジスト
41、141 開口部
100、100A、100B 配線転写版
110 基材
120、120B 絶縁層
121 開口部
130、130A めっき母材層
131 離型層
140 レジスト
200、200D 配線付き配線転写版
300 配線体用中間材
Claims (11)
- 導電体を有する基板の上に配置される配線体であって、
前記基板の上に位置する絶縁層に形成されたビアホール内に設けられ、前記ビアホールを介して前記導電体に接続されたビア電極と、
前記絶縁層を介して前記基板の上方に設けられた配線と、を備え、
前記ビア電極における前記絶縁層の上に位置する下部層と前記配線における下部層とは、同じ材料によって構成されている、
配線体。 - 前記ビア電極は、前記導電体の上と前記絶縁層の上とにわたって形成されたシード層と、前記シード層の上において前記導電体の上と前記絶縁層の上とにわたって形成されたビア電極本体層とを有し、
前記ビア電極における前記絶縁層の上に位置する下部層と前記配線における下部層とは、密着層であり、
前記ビア電極の前記密着層は、前記絶縁層の上に位置する部分の前記シード層と、前記絶縁層との間に設けられている、
請求項1に記載の配線体。 - 前記配線は、前記配線における前記密着層の上に設けられた配線本体層を有し、
前記ビア電極本体層と前記配線本体層とは、結晶粒径が異なる銅を含む、
請求項2に記載の配線体。 - 前記配線は、さらに、前記配線本体層の上に設けられ、前記配線本体層とは異なる材料又は構造からなる導電層を有する、
請求項3に記載の配線体。 - 請求項1~4のいずれか1項に記載の配線体と、
前記配線体が配置される基板と、を備える、
実装基板。 - 他の部材に転写するための転写用配線が形成された配線転写版である配線付き配線転写版であって、
基材と、
前記基材の上に形成された離型層と、
前記離型層の上に開口部を有するように前記基材を覆う転写版絶縁層と、
前記開口部内において前記離型層の上に形成されためっき膜と、
前記めっき膜と前記転写版絶縁層とを覆うように形成された密着膜とを備え、
前記めっき膜と前記密着膜とは、他の部材に転写される転写用配線である、
配線付き配線転写版。 - 導電体を有する基板の上に配置される配線体の中間材である配線体用中間材であって、
前記導電体を覆うように前記基板の上に設けられた絶縁層の上に形成された密着膜と、
前記密着膜の上に形成された配線と、を備える、
配線体用中間材。 - 導電体を有する基板の上に配置される配線体の製造方法であって、
前記基板の上に位置する絶縁層を介して密着膜と前記密着膜の上に位置する配線本体層とを配置する工程と、
次いで、前記密着膜及び前記絶縁層の一部を除去することで前記導電体を露出するように前記絶縁層にビアホールを形成する工程と、
次いで、露出した前記導電体と前記密着膜と前記配線本体層とを覆うようにシード膜を形成する工程と、
次いで、前記導電体を覆う部分の前記シード膜が露出するように前記シード膜の上に選択的にレジストを形成する工程と、
次いで、露出させた前記シード膜の上にビア電極本体層を形成する工程と、
次いで、前記レジストを除去した後に、露出する前記シード膜を除去するとともに、この露出する前記シード膜の下に存在する前記密着膜を除去する工程とを含む、
配線体の製造方法。 - 前記配線本体層と前記密着膜とを配置する工程において、前記配線本体層は、転写法によって形成される、
請求項8に記載の配線体の製造方法。 - 前記配線本体層と前記密着膜とを配置する工程において、前記配線本体層と前記密着膜とは、転写法によって同時に転写される、
請求項8に記載の配線体の製造方法。 - 基板の上に配線体が配置された実装基板の製造方法であって、
前記基板の上に配線体を配置する工程を含み、
前記配線体は、請求項8~10のいずれか1項に記載の配線体の製造方法により製造される、
実装基板の製造方法。
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EP22775336.5A EP4319496A1 (en) | 2021-03-22 | 2022-03-16 | Wiring body, mounting substrate, wiring transfer plate with wiring, intermediate material for wiring body, manufacturing method for wiring body, and manufacturing method for mounting substrate |
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JPH02113591A (ja) * | 1988-10-22 | 1990-04-25 | Matsushita Electric Works Ltd | 印刷配線板の製造方法 |
JPH03502022A (ja) * | 1987-07-08 | 1991-05-09 | レオナード クルツ ゲーエムベーハー ウント コンパニー | 導体路を備えた製品の製造方法およびその方法を実行するためのエンボスフイルム |
JP2006093746A (ja) * | 2005-12-26 | 2006-04-06 | Fujitsu Ltd | 多層配線基板製造方法および多層配線基板 |
US20110155428A1 (en) * | 2009-12-30 | 2011-06-30 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
JP2013507763A (ja) * | 2009-10-08 | 2013-03-04 | エルジー イノテック カンパニー リミテッド | プリント回路基板及びその製造方法 |
JP2017073530A (ja) * | 2015-10-09 | 2017-04-13 | 富士通株式会社 | 密着性向上材料、配線構造、及びその製造方法、並びに半導体装置、及びその製造方法 |
JP2020107681A (ja) | 2018-12-26 | 2020-07-09 | 新光電気工業株式会社 | 配線基板、半導体装置、及び配線基板の製造方法 |
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- 2022-03-16 WO PCT/JP2022/011947 patent/WO2022202548A1/ja active Application Filing
- 2022-03-16 US US18/548,458 patent/US20240147617A1/en active Pending
Patent Citations (7)
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JPH03502022A (ja) * | 1987-07-08 | 1991-05-09 | レオナード クルツ ゲーエムベーハー ウント コンパニー | 導体路を備えた製品の製造方法およびその方法を実行するためのエンボスフイルム |
JPH02113591A (ja) * | 1988-10-22 | 1990-04-25 | Matsushita Electric Works Ltd | 印刷配線板の製造方法 |
JP2006093746A (ja) * | 2005-12-26 | 2006-04-06 | Fujitsu Ltd | 多層配線基板製造方法および多層配線基板 |
JP2013507763A (ja) * | 2009-10-08 | 2013-03-04 | エルジー イノテック カンパニー リミテッド | プリント回路基板及びその製造方法 |
US20110155428A1 (en) * | 2009-12-30 | 2011-06-30 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
JP2017073530A (ja) * | 2015-10-09 | 2017-04-13 | 富士通株式会社 | 密着性向上材料、配線構造、及びその製造方法、並びに半導体装置、及びその製造方法 |
JP2020107681A (ja) | 2018-12-26 | 2020-07-09 | 新光電気工業株式会社 | 配線基板、半導体装置、及び配線基板の製造方法 |
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