WO2022196079A1 - Capteur d'imagerie à semi-conducteurs et dispositif d'imagerie - Google Patents

Capteur d'imagerie à semi-conducteurs et dispositif d'imagerie Download PDF

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Publication number
WO2022196079A1
WO2022196079A1 PCT/JP2022/001634 JP2022001634W WO2022196079A1 WO 2022196079 A1 WO2022196079 A1 WO 2022196079A1 JP 2022001634 W JP2022001634 W JP 2022001634W WO 2022196079 A1 WO2022196079 A1 WO 2022196079A1
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Prior art keywords
output
node
voltage
amplifier
transistor
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PCT/JP2022/001634
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English (en)
Japanese (ja)
Inventor
大輔 中川
パリット カンチャナウィローグン
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022196079A1 publication Critical patent/WO2022196079A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to solid-state imaging devices and imaging devices.
  • single-slope ADCs Analog to Digital Converters
  • a current source is generally connected to the node on the ground side of the vertical signal line wired along the column, and the analog signal from this node is input to the ADC and converted to a digital signal.
  • an amplifier is inserted between a node between a vertical signal line and a current source and an ADC.
  • the voltage of the analog signal is amplified by inserting an amplifier.
  • this amplifier it is necessary to provide a power supply on the power supply side of the amplifier in addition to the current source on the ground side of the vertical signal line.
  • the addition of the current source on the power supply side may increase the power consumption compared to the case where the voltage is not amplified.
  • the present disclosure provides a solid-state imaging device that amplifies the voltage for each column with low power consumption and reduced settling time.
  • the solid-state imaging device includes: a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; Prepare.
  • the output of the output node may be output as an analog signal.
  • the output of the amplifier may be output as an analog signal.
  • the output of the amplifier may be connected to the source of the input transistor via a boost capacitor.
  • the cascode transistor may comprise two transistors connected in series, and the output of the amplifier may be connected to a node between the two transistors via a boost capacitor.
  • a power supply side current source connected to a power supply node of a predetermined power supply voltage, and a pair of cascode transistors connected between the power supply side current source and the reference side current source.
  • the output node may be a node between the pair of cascode transistors.
  • the output of the amplifier may be connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor.
  • the output of the amplifier may be connected to a node between the pair of cascode transistors and the power supply side current source via a boost side capacitor.
  • the solid-state imaging device includes: a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; an analog-to-digit
  • FIG. 1 is a block diagram showing a configuration example of an imaging device according to an embodiment
  • FIG. FIG. 4 is a diagram showing a configuration example of a laminated structure of an element according to one embodiment
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to one embodiment
  • FIG. 1 is a circuit diagram showing a configuration example of a pixel circuit according to one embodiment
  • FIG. 3 is a block diagram showing a configuration example of a constant current source section according to one embodiment
  • FIG. FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 1 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • FIG. 1 is a block diagram showing an example of the configuration of an imaging device 100 according to one embodiment.
  • the imaging device 100 is a device for capturing image data (including frame data in moving images), and includes an optical section 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120.
  • the imaging device 100 also includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 .
  • the imaging device 100 may be implemented in, as non-limiting examples, a digital camera such as a digital still camera, a terminal such as a smartphone having an imaging function, a personal computer, or an in-vehicle camera.
  • a digital camera such as a digital still camera
  • a terminal such as a smartphone having an imaging function
  • a personal computer or an in-vehicle camera.
  • the optical unit 110 controls the light from the subject and guides it to the solid-state imaging device 200.
  • the solid-state imaging device 200 acquires an analog signal based on the intensity of the received light through photoelectric conversion in synchronization with a vertical synchronization signal, converts it into a digital image signal by an ADC, and outputs it.
  • the vertical synchronization signal is an odor signal with a predetermined frequency that indicates the timing of imaging.
  • the solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
  • the DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200.
  • the DSP circuit 120 outputs the processed image data via the bus 150 to an appropriate location such as the frame memory 160, the storage unit 170, and the like.
  • the display unit 130 displays image data.
  • the display unit 130 may be a liquid crystal panel or an organic EL (Electro Luminescence) panel as non-limiting examples.
  • the operation unit 140 generates an operation signal based on the user's operation.
  • the operation unit 140 includes, as non-limiting examples, input interfaces such as a touch panel, keyboard, mouse, and microphone.
  • a bus 150 is a path shared by the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 for mutual data transmission/reception.
  • the frame memory 160 temporarily holds image data for processing, for example.
  • the storage unit 170 stores various data such as image data.
  • the power supply unit 180 supplies power to the solid-state imaging device 200, the DPS circuit 120, the display unit 130, and the like.
  • FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to one embodiment.
  • a solid-state imaging device 200 includes a pixel chip 201 and a circuit chip 202 .
  • the pixel chip 201 and the circuit chip 202 are configured as stacked chips. These chips are electrically connected through connections such as vias. Instead of vias, they may be connected by Cu--Cu junctions, microbumps, or the like, as non-limiting examples.
  • FIG. 3 is a block diagram showing a non-limiting configuration example of the solid-state imaging device 200 according to one embodiment.
  • the solid-state imaging device 200 includes a row selection section 210, a DAC (Digital to Analog Converter) 220, a timing control circuit 230, a pixel array section 240, a constant current source section 300, an analog-to-digital conversion section 260, and a horizontal transfer section.
  • a scanning unit 270 and an image processing unit 280 are provided.
  • the row selection unit 210 sequentially selects and drives rows, and outputs analog pixel signals to the analog-to-digital conversion unit 260 via the constant current source unit 300.
  • the DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the analog-to-digital converter 260.
  • DA Digital to Analog
  • a ramp signal such as a sawtooth wave, a square wave, etc. may be used as non-limiting examples.
  • the timing control circuit 230 controls the operation timings of the row selection section 210, the DAC 220, the constant current source section 300, the analog-to-digital conversion section 260, and the horizontal transfer scanning section 270 in synchronization with the vertical synchronization signal Vsync.
  • a plurality of pixel circuits 250 are arranged in a two-dimensional lattice.
  • a set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a row (line)
  • a set of pixel circuits 250 arranged in a direction perpendicular to the horizontal direction is referred to as a column (column).
  • the pixel circuit 250 generates an analog pixel signal by photoelectric conversion under the control of the row selection section 210. Each pixel circuit 250 outputs a pixel signal to the constant current source section 300 via a vertical signal line 259 .
  • the analog-to-digital converter 260 uses the reference signal output by the DAC 220 to convert the analog input signal into a digital signal for each column.
  • the analog-to-digital conversion section 260 supplies digital signals to the image processing section 280 under the control of the horizontal transfer scanning section 270 .
  • the horizontal transfer scanning unit 270 controls the analog-to-digital conversion unit 260 to sequentially output digital signals.
  • the image processing unit 280 executes predetermined image processing on image data in which digital signals are arranged.
  • the image processing unit 280 outputs the processed image data to the DSP circuit 120 .
  • the above-described circuits in the solid-state imaging device 200 are appropriately dispersed and arranged in the pixel chip 201 and the circuit chip 202 .
  • the pixel array section 240 may be arranged on the pixel chip 201 , and circuits other than the pixel array section 240 , such as the analog-to-digital conversion section 260 , may be arranged on the circuit chip 202 .
  • the circuits arranged in each of the pixel chip 201 and the circuit chip 202 are not limited to this combination.
  • the pixel array section 240, the constant current source section 300, and the comparator in the analog-to-digital conversion section 260 can be arranged on the pixel chip 201, and the other circuits can be arranged on the circuit chip 202.
  • FIG. 4 is a circuit diagram showing an example of the pixel circuit 250 according to one embodiment.
  • the pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256.
  • the photoelectric conversion element 251 photoelectrically converts incident light to generate charges.
  • the photoelectric conversion element 251 includes, as non-limiting examples, a photodiode and an organic photoelectric conversion film.
  • the transfer transistor 252 is a transistor that transfers charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with the transfer signal TRG from the row selection section 210 .
  • the reset transistor 253 initializes the charge held in the floating diffusion layer 254 according to the reset signal RST from the row selection section 210.
  • the floating diffusion layer 254 accumulates charges and generates a voltage according to the amount of charges.
  • the amplification transistor 255 is a transistor that increases or decreases the voltage of the floating diffusion layer 254.
  • the selection transistor 256 is a transistor that outputs an amplified voltage signal as the pixel signal SIG in accordance with the selection signal SEL from the row selection unit 210 . Assuming that the number of columns is N (N: integer), the pixel signals of the n-th (n: integer of [1, N]) column are transmitted to the constant current source section 300 via the vertical signal line 259-n.
  • circuit of the pixel circuit 250 may be configured as a circuit that is not limited to the one illustrated in the figure as long as it can appropriately generate a pixel signal by photoelectric conversion.
  • FIG. 5 is a block diagram showing a non-limiting example of the constant current source section 300 according to one embodiment.
  • a column amplifier 310 is arranged for each column in the constant current source section 300 . Assuming that the number of columns is N, N column amplifiers 310 are arranged.
  • a pixel signal of the corresponding column is input to the n-th column amplifier 310 via the vertical signal line 259-n.
  • the column amplifier 310 amplifies the voltage of the pixel signal and outputs it to the analog-to-digital converter 260 via the signal line 309-n.
  • the voltage of the pixel signal before amplification is referred to as input voltage Vin
  • the voltage after amplification is referred to as output voltage Vout.
  • the column amplifier 310 is initialized by the auto-zero signal AZ from the timing control circuit 230 .
  • FIG. 6 is a block diagram showing a non-limiting example of the analog-to-digital converter 260 according to one embodiment.
  • the analog-to-digital converter 260 includes an ADC 261 and a latch circuit 266 for each column. Assuming that the number of columns is N, N ADCs 261 and N latch circuits 266 are arranged.
  • ADC 261 is a circuit that converts analog pixel signals into digital signals. This ADC 261 comprises capacitors 262 , 263 , a comparator 264 and a counter 265 . ADC 261 further performs CDS (Correlated Double Sampling) processing.
  • CDS Correlated Double Sampling
  • the comparator 264 is a comparator that compares the reference signal output from the DAC 220 and the pixel signal of the corresponding column.
  • the comparator 264 has a pair of input terminals, one of which receives the reference signal via the capacitor 262 and the other receives the pixel signal via the capacitor 263 .
  • Comparator 264 supplies the comparison result to counter 265 .
  • the counter 265 under the control of the timing control circuit 230, counts the count value over the period until the comparison result is inverted.
  • Counter 265 outputs a signal indicating the count value to latch circuit 266 as a digital signal.
  • a latch circuit 266 is a circuit that holds a digital signal.
  • the latch circuit 266 outputs the digital signal to the image processing section 280 in synchronization with the synchronization signal output from the horizontal transfer scanning section 270 .
  • capacitors 262 and 263 can be connected in parallel to one of the input terminals of comparator 264 (inverting input terminal, etc.). This also allows the input amplitude of comparator 264 to be reduced compared to FIG.
  • FIG. 8 is a circuit diagram showing one configuration example of the column amplifier 310 according to one embodiment.
  • Column amplifier 310 includes current reuse column amplifier 320 and amplifier 350 .
  • the current reuse column amplifier 320 is hereinafter referred to as CRCA (Current Reuse Column Amplifier).
  • CRCA Current Reuse Column Amplifier
  • FC-CRCA Fulled Cascode-CRCA
  • This FC-CRCA comprises an input stage 321 and a folded stage 340 .
  • the input stage 321 includes an input transistor 322 , an input side auto-zero switch 324 , a feedback capacitor 325 , a reference side capacitor 326 and a reference side current source transistor 327 .
  • a VSL capacitor 400 connected to the vertical signal line 259-n represents wiring capacitance between the vertical signal line 259-n and a reference voltage (eg, ground voltage).
  • the input transistor 322 for example, pMOS (p-channel Metal-Oxide Semiconductor Field-Effect Transistor) is used.
  • the input transistor 322 has a source connected to the vertical signal line 259 - n and a drain connected to the drain of the reference side current source transistor 327 .
  • the pixel circuit 250 generates a pixel signal by photoelectric conversion, and inputs this voltage as an input voltage Vin to the source of the input transistor 322 via the vertical signal line 259-n.
  • the input-side auto-zero switch 324 is a transistor that opens and closes the path between the gate and drain of the input transistor 322 according to the auto-zero signal AZ.
  • a feedback capacitor 325 is connected between the gate of the input transistor 322 and the output side auto-zero switch 344 and intermediate switch 346 .
  • a reference-side capacitor 326 is arranged between the gate of the input transistor 322 and a reference node of a predetermined reference voltage (eg, ground voltage).
  • a reference-side current source transistor 327 has a source connected to a reference node of a predetermined reference voltage (eg, ground voltage).
  • a predetermined reference voltage nbias is applied to the gate of the reference-side current source transistor 327, and a predetermined bias current is supplied according to this bias voltage nbias.
  • the reference-side current source transistor 327 is an example of a reference-side current source.
  • the folded stage 340 includes a power supply side current source transistor 342, cascode transistors 343 and 345, an output side auto-zero switch 344, and an intermediate switch 346.
  • the power supply side current source transistor 342 and the cascode transistor 343 are, for example, pMOS, and are connected in series to the power supply node.
  • a bias voltage pbias is applied to the gate of the current source transistor 342 on the power supply side, and a bias voltage pcas is applied to the gate of the cascode transistor 343 .
  • the power-side current source transistor 342 is an example of a power-side current source.
  • the output side auto-zero switch 344 is provided between the input stage 321 and the output node 328 .
  • a cascode transistor 345 is provided between the cascode transistor 343 and the reference side current source transistor 327 .
  • the cascode transistor 343 and the cascode transistor 345 share a drain and are connected in series.
  • a predetermined bias voltage ncas is applied to the gate of the cascode transistor 345 .
  • a node between the cascode transistors 343 and 345 is used as the output node 328 of the CRCA.
  • the output side auto-zero switch 344 is arranged between the feedback capacitor 325 and a predetermined reference voltage.
  • This predetermined reference voltage may be, for example, a reference voltage VR different from the reference voltage to which the reference-side capacitor 326 and the reference-side current source transistor 327 are connected. The same applies to the following figures.
  • Intermediate switch 346 is placed between feedback capacitor 325 and output node 328 .
  • the intermediate switch 346 is a switch to which an inverted signal xAZ of AZ applied to the input-side auto-zero switch 324 and the output-side auto-zero switch 344 is applied and which opens and closes according to this xAZ.
  • the intermediate switch 346 opens and closes exclusively with the input-side auto-zero switch 324 and the output-side auto-zero switch 344 .
  • the electric charge accumulated in the capacitor is appropriately reset by the auto-zero signal, and the reset state is appropriately released at the timing of reading the pixel signal.
  • the input side autozero switch 324 opens and closes the path between the input transistor 322 and the output node 328
  • the feedback capacitor 325 opens and closes the path between the input transistor 322 and the output node 328.
  • FC-CRCA the current flowing through the folded stage 340 is added to the input stage 321. This current can be small compared to the input stage 321 current. Since the input conversion noise of the power-side current source transistor 342 also becomes smaller as the current is reduced, it is better to reduce the current.
  • FC-CRCA output node 328 The output from FC-CRCA output node 328 is connected to amplifier 350 .
  • the provision of the folded stage 340 makes it possible to expand the range of the output signal by adding transistors in the form of cascodes.
  • the amplifier 350 is an amplification circuit and is connected between the output node 328 and the analog-to-digital converter 260 .
  • Amplifier 350 amplifies and outputs the signal output from output node 328 without feeding it back to CF-CRCA.
  • the column amplifier 310 inputs this output signal to the analog-to-digital converter 260 via the signal line 309-n. That is, both the signal input to the amplifier 350 and the signal output from the amplifier 350 are analog signals.
  • This amplifier 350 may be composed of, for example, a source follower.
  • the amplifier 350 separates the output of the CF-CRCA from the output capacitance, thereby reducing the effective capacitance seen from the VSL. Therefore, it is possible to shorten the settling time of the timing of outputting the signal from the solid-state imaging device 200 to the analog-to-digital converter 260 from the reset timing by the auto-zero signal AZ.
  • FIG. 9 is a circuit diagram showing the column amplifier 310 according to one embodiment.
  • the column amplifier 310 further includes a boost-side capacitor 351 for feeding back the signal output from the amplifier 350 in addition to the configuration of the first embodiment described above.
  • the amplifier 350 is a positive phase amplifier. That is, amplifier 350 is configured as a circuit that achieves signal amplification without inverting the result. Thus, if amplifier 350 is a positive phase amplifier, the output of amplifier 350 may be fed back to input stage 321 .
  • the boost-side capacitor 351 is a capacitor for feeding back the signal output by the positive-phase amplifier 350 to the input stage 321 .
  • the boost-side capacitor 351 By providing the positive phase amplifier and the boost side capacitor 351, it is possible to reduce the effective capacitance seen from the VSL.
  • FIG. 10 is a circuit diagram using an n-channel source follower as a non-limiting example of the positive-phase amplifier 350.
  • the positive phase amplifier 350 includes a boost transistor 352 and a boost side current source transistor 354 .
  • the boost transistor 352 is an nMOS to the gate of which the signal output from the output node 328 is applied, the drain is connected to the power supply voltage VDDH, and the source is connected to the drain of the boost side current source transistor 354 .
  • the boost-side current source transistor 354 is an nMOS with a bias voltage nbias applied to its gate, its drain connected to the source of the boost transistor 352, and its drain connected to the reference voltage.
  • the reference voltage to which the drain is connected may be the same reference voltage as the reference voltage to which the reference side capacitor 326 and the reference side current source transistor 327 are connected. The same applies to FIGS. 11 and 12 below.
  • the amplifier 350 forms an n-channel source follower with these two transistors.
  • the boost-side capacitor 351 is connected to a connection node between the source of the boost transistor 352 and the drain of the boost-side current source transistor 354, that is, a node outputting a signal obtained by amplifying the signal applied to the gate of the boost transistor 352, and an input Connected between the source of transistor 322 .
  • Vvsl be the source potential of the input transistor 322
  • Vbst be the output voltage of the amplifier 350
  • Cbst be the capacitance of the boost capacitor 351
  • Ibst be the current flowing from the source of the input transistor 322 to the boost capacitor 351.
  • A be the closed loop gain of CRCA and amplifier 350 .
  • the upper limit of the output is determined by the Vds of the boost transistor and the Vgs of the p-channel source follower. can be expanded.
  • a p-channel source follower may be used as long as it is amplified within the limits.
  • (Modification) 11 and 12 show a modification of the second embodiment described above.
  • the output of amplifier 350 may be the output of column amplifier 310, as shown in FIG.
  • the output of the source follower may be the output of the column amplifier 310, as shown in FIG.
  • the load capacitance (output capacitance) of the output destination is separated from the CRCA.
  • the signal amplified by the positive-phase amplifier 350 including the source follower can also be used as the output of the column amplifier 310.
  • a p-channel source follower may be used as a non-limiting example.
  • the feedback destination of the amplifier 350 is the source of the input transistor 322, but it is not limited to this form. As in each of the above-described embodiments, other feedback destinations may be used as long as they have a negative capacitance when viewed from VSL.
  • FIG. 13 is a circuit diagram showing another example of an unlimited feedback destination.
  • the positive phase amplifier 350 may be connected to the source of the cascode transistor 345 via the boost side capacitor 355 .
  • the same effect can be achieved with a smaller feedback capacitance.
  • FIG. 14 is a circuit diagram showing another example of an unlimited feedback destination.
  • the positive-phase amplifier 350 may be connected to a node between the drain of the power-side current source transistor 342 and the source of the cascode transistor 345 via a boost-side capacitor 356 . In this case as well, it is possible to achieve the same effect with a smaller feedback capacitance than in the case of feedback to the source of the input transistor 322 .
  • FIG. 15 is a circuit diagram showing another example of an unlimited feedback destination.
  • a positive phase amplifier 350 may be connected between the reference side current source transistor 327 and the reference side current source transistor 327' via a boost side capacitor 357.
  • FIG. In the example of FIG. 15, the reference side current source transistor in input stage 321 is split into two.
  • the two transistors may be nMOS with the same performance.
  • Bias voltages nbias1 and nbias2 for driving the respective transistors are applied to the respective transistors. For example, even if the bias voltages applied to the gates of the two transistors are the same, the bias voltages nbias1 and nbias2 may be short-circuited if the two transistors are capable of saturation operation.
  • the positive phase amplifier 350 is used in the examples of FIGS. 13 to 15, it may of course be a source follower, particularly an n-channel source follower.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated as the functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 17 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
  • the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031.
  • FIG. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to suppress the power consumption of the column amplifier, so it is possible to reduce the power consumption of the entire vehicle system.
  • the cascode transistor comprises two transistors connected in series; the output of the amplifier is connected to a node between the two transistors through a boost capacitor;
  • the solid-state imaging device according to any one of (1) to (3).
  • (6) a power supply side current source connected to a power supply node of a predetermined power supply voltage; a pair of cascode transistors connected between the power-side current source and the reference-side current source; further comprising the output node is a node between the pair of cascode transistors;
  • the solid-state imaging device according to any one of (1) to (5).
  • the output of the amplifier is connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor;
  • the output of the amplifier is connected to a node between the pair of cascode transistors and the power-side current source via a boost-side capacitor.
  • (9) a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; an analog-to-digital converter that converts the voltage output from the

Abstract

Le problème décrit par la présente invention est de raccourcir un temps de stabilisation. La solution selon l'invention porte sur un capteur d'imagerie à semi-conducteurs qui est pourvu d'un circuit de pixel, d'un transistor d'entrée, d'une source de courant côté référence, d'un circuit de rétroaction, d'un transistor cascode et d'un amplificateur. Le circuit de pixel génère une tension d'entrée par conversion photoélectrique. Le transistor d'entrée a une source à laquelle la tension d'entrée est appliquée, et un drain à partir duquel une tension de sortie correspondant à la tension est délivrée entre la source et une grille. La source de courant côté référence est connectée à un nœud de référence ayant une tension de référence prédéfinie et fournit un courant prédéfini. Le circuit de rétroaction comprend un condensateur de rétroaction qui fournit une partie du courant prédéfini à la grille du transistor d'entrée et est connecté entre un nœud de sortie à partir duquel la tension de sortie est émise et la grille du transistor d'entrée, un condensateur côté référence connecté entre la grille du transistor d'entrée et le nœud de référence, et un commutateur à zéro automatique côté entrée connecté entre la grille du transistor d'entrée et le nœud de sortie. Le transistor cascode est connecté entre la source de courant côté référence et le drain du transistor d'entrée. Un commutateur intermédiaire est connecté entre le condensateur de rétroaction et le nœud de sortie. L'amplificateur comprend un amplificateur de phase normale qui amplifie un signal émis par le nœud de sortie.
PCT/JP2022/001634 2021-03-15 2022-01-18 Capteur d'imagerie à semi-conducteurs et dispositif d'imagerie WO2022196079A1 (fr)

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WO2023089958A1 (fr) * 2021-11-22 2023-05-25 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs

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Publication number Priority date Publication date Assignee Title
JP2011029726A (ja) * 2009-07-21 2011-02-10 Panasonic Corp 固体撮像装置およびそれを備えたカメラ
JP2015119340A (ja) * 2013-12-18 2015-06-25 キヤノン株式会社 光電変換装置の駆動方法
JP2017038315A (ja) * 2015-08-13 2017-02-16 キヤノン株式会社 撮像装置及び撮像システム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029726A (ja) * 2009-07-21 2011-02-10 Panasonic Corp 固体撮像装置およびそれを備えたカメラ
JP2015119340A (ja) * 2013-12-18 2015-06-25 キヤノン株式会社 光電変換装置の駆動方法
JP2017038315A (ja) * 2015-08-13 2017-02-16 キヤノン株式会社 撮像装置及び撮像システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023089958A1 (fr) * 2021-11-22 2023-05-25 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs

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