WO2022196079A1 - Solid-state imaging sensor and imaging device - Google Patents

Solid-state imaging sensor and imaging device Download PDF

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Publication number
WO2022196079A1
WO2022196079A1 PCT/JP2022/001634 JP2022001634W WO2022196079A1 WO 2022196079 A1 WO2022196079 A1 WO 2022196079A1 JP 2022001634 W JP2022001634 W JP 2022001634W WO 2022196079 A1 WO2022196079 A1 WO 2022196079A1
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Prior art keywords
output
node
voltage
amplifier
transistor
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PCT/JP2022/001634
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French (fr)
Japanese (ja)
Inventor
大輔 中川
パリット カンチャナウィローグン
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022196079A1 publication Critical patent/WO2022196079A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to solid-state imaging devices and imaging devices.
  • single-slope ADCs Analog to Digital Converters
  • a current source is generally connected to the node on the ground side of the vertical signal line wired along the column, and the analog signal from this node is input to the ADC and converted to a digital signal.
  • an amplifier is inserted between a node between a vertical signal line and a current source and an ADC.
  • the voltage of the analog signal is amplified by inserting an amplifier.
  • this amplifier it is necessary to provide a power supply on the power supply side of the amplifier in addition to the current source on the ground side of the vertical signal line.
  • the addition of the current source on the power supply side may increase the power consumption compared to the case where the voltage is not amplified.
  • the present disclosure provides a solid-state imaging device that amplifies the voltage for each column with low power consumption and reduced settling time.
  • the solid-state imaging device includes: a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; Prepare.
  • the output of the output node may be output as an analog signal.
  • the output of the amplifier may be output as an analog signal.
  • the output of the amplifier may be connected to the source of the input transistor via a boost capacitor.
  • the cascode transistor may comprise two transistors connected in series, and the output of the amplifier may be connected to a node between the two transistors via a boost capacitor.
  • a power supply side current source connected to a power supply node of a predetermined power supply voltage, and a pair of cascode transistors connected between the power supply side current source and the reference side current source.
  • the output node may be a node between the pair of cascode transistors.
  • the output of the amplifier may be connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor.
  • the output of the amplifier may be connected to a node between the pair of cascode transistors and the power supply side current source via a boost side capacitor.
  • the solid-state imaging device includes: a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; an analog-to-digit
  • FIG. 1 is a block diagram showing a configuration example of an imaging device according to an embodiment
  • FIG. FIG. 4 is a diagram showing a configuration example of a laminated structure of an element according to one embodiment
  • 1 is a block diagram showing a configuration example of a solid-state imaging device according to one embodiment
  • FIG. 1 is a circuit diagram showing a configuration example of a pixel circuit according to one embodiment
  • FIG. 3 is a block diagram showing a configuration example of a constant current source section according to one embodiment
  • FIG. FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 1 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment
  • FIG. 2 is a block diagram showing a configuration
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment;
  • FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • FIG. 1 is a block diagram showing an example of the configuration of an imaging device 100 according to one embodiment.
  • the imaging device 100 is a device for capturing image data (including frame data in moving images), and includes an optical section 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120.
  • the imaging device 100 also includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 .
  • the imaging device 100 may be implemented in, as non-limiting examples, a digital camera such as a digital still camera, a terminal such as a smartphone having an imaging function, a personal computer, or an in-vehicle camera.
  • a digital camera such as a digital still camera
  • a terminal such as a smartphone having an imaging function
  • a personal computer or an in-vehicle camera.
  • the optical unit 110 controls the light from the subject and guides it to the solid-state imaging device 200.
  • the solid-state imaging device 200 acquires an analog signal based on the intensity of the received light through photoelectric conversion in synchronization with a vertical synchronization signal, converts it into a digital image signal by an ADC, and outputs it.
  • the vertical synchronization signal is an odor signal with a predetermined frequency that indicates the timing of imaging.
  • the solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
  • the DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200.
  • the DSP circuit 120 outputs the processed image data via the bus 150 to an appropriate location such as the frame memory 160, the storage unit 170, and the like.
  • the display unit 130 displays image data.
  • the display unit 130 may be a liquid crystal panel or an organic EL (Electro Luminescence) panel as non-limiting examples.
  • the operation unit 140 generates an operation signal based on the user's operation.
  • the operation unit 140 includes, as non-limiting examples, input interfaces such as a touch panel, keyboard, mouse, and microphone.
  • a bus 150 is a path shared by the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 for mutual data transmission/reception.
  • the frame memory 160 temporarily holds image data for processing, for example.
  • the storage unit 170 stores various data such as image data.
  • the power supply unit 180 supplies power to the solid-state imaging device 200, the DPS circuit 120, the display unit 130, and the like.
  • FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to one embodiment.
  • a solid-state imaging device 200 includes a pixel chip 201 and a circuit chip 202 .
  • the pixel chip 201 and the circuit chip 202 are configured as stacked chips. These chips are electrically connected through connections such as vias. Instead of vias, they may be connected by Cu--Cu junctions, microbumps, or the like, as non-limiting examples.
  • FIG. 3 is a block diagram showing a non-limiting configuration example of the solid-state imaging device 200 according to one embodiment.
  • the solid-state imaging device 200 includes a row selection section 210, a DAC (Digital to Analog Converter) 220, a timing control circuit 230, a pixel array section 240, a constant current source section 300, an analog-to-digital conversion section 260, and a horizontal transfer section.
  • a scanning unit 270 and an image processing unit 280 are provided.
  • the row selection unit 210 sequentially selects and drives rows, and outputs analog pixel signals to the analog-to-digital conversion unit 260 via the constant current source unit 300.
  • the DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the analog-to-digital converter 260.
  • DA Digital to Analog
  • a ramp signal such as a sawtooth wave, a square wave, etc. may be used as non-limiting examples.
  • the timing control circuit 230 controls the operation timings of the row selection section 210, the DAC 220, the constant current source section 300, the analog-to-digital conversion section 260, and the horizontal transfer scanning section 270 in synchronization with the vertical synchronization signal Vsync.
  • a plurality of pixel circuits 250 are arranged in a two-dimensional lattice.
  • a set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a row (line)
  • a set of pixel circuits 250 arranged in a direction perpendicular to the horizontal direction is referred to as a column (column).
  • the pixel circuit 250 generates an analog pixel signal by photoelectric conversion under the control of the row selection section 210. Each pixel circuit 250 outputs a pixel signal to the constant current source section 300 via a vertical signal line 259 .
  • the analog-to-digital converter 260 uses the reference signal output by the DAC 220 to convert the analog input signal into a digital signal for each column.
  • the analog-to-digital conversion section 260 supplies digital signals to the image processing section 280 under the control of the horizontal transfer scanning section 270 .
  • the horizontal transfer scanning unit 270 controls the analog-to-digital conversion unit 260 to sequentially output digital signals.
  • the image processing unit 280 executes predetermined image processing on image data in which digital signals are arranged.
  • the image processing unit 280 outputs the processed image data to the DSP circuit 120 .
  • the above-described circuits in the solid-state imaging device 200 are appropriately dispersed and arranged in the pixel chip 201 and the circuit chip 202 .
  • the pixel array section 240 may be arranged on the pixel chip 201 , and circuits other than the pixel array section 240 , such as the analog-to-digital conversion section 260 , may be arranged on the circuit chip 202 .
  • the circuits arranged in each of the pixel chip 201 and the circuit chip 202 are not limited to this combination.
  • the pixel array section 240, the constant current source section 300, and the comparator in the analog-to-digital conversion section 260 can be arranged on the pixel chip 201, and the other circuits can be arranged on the circuit chip 202.
  • FIG. 4 is a circuit diagram showing an example of the pixel circuit 250 according to one embodiment.
  • the pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256.
  • the photoelectric conversion element 251 photoelectrically converts incident light to generate charges.
  • the photoelectric conversion element 251 includes, as non-limiting examples, a photodiode and an organic photoelectric conversion film.
  • the transfer transistor 252 is a transistor that transfers charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with the transfer signal TRG from the row selection section 210 .
  • the reset transistor 253 initializes the charge held in the floating diffusion layer 254 according to the reset signal RST from the row selection section 210.
  • the floating diffusion layer 254 accumulates charges and generates a voltage according to the amount of charges.
  • the amplification transistor 255 is a transistor that increases or decreases the voltage of the floating diffusion layer 254.
  • the selection transistor 256 is a transistor that outputs an amplified voltage signal as the pixel signal SIG in accordance with the selection signal SEL from the row selection unit 210 . Assuming that the number of columns is N (N: integer), the pixel signals of the n-th (n: integer of [1, N]) column are transmitted to the constant current source section 300 via the vertical signal line 259-n.
  • circuit of the pixel circuit 250 may be configured as a circuit that is not limited to the one illustrated in the figure as long as it can appropriately generate a pixel signal by photoelectric conversion.
  • FIG. 5 is a block diagram showing a non-limiting example of the constant current source section 300 according to one embodiment.
  • a column amplifier 310 is arranged for each column in the constant current source section 300 . Assuming that the number of columns is N, N column amplifiers 310 are arranged.
  • a pixel signal of the corresponding column is input to the n-th column amplifier 310 via the vertical signal line 259-n.
  • the column amplifier 310 amplifies the voltage of the pixel signal and outputs it to the analog-to-digital converter 260 via the signal line 309-n.
  • the voltage of the pixel signal before amplification is referred to as input voltage Vin
  • the voltage after amplification is referred to as output voltage Vout.
  • the column amplifier 310 is initialized by the auto-zero signal AZ from the timing control circuit 230 .
  • FIG. 6 is a block diagram showing a non-limiting example of the analog-to-digital converter 260 according to one embodiment.
  • the analog-to-digital converter 260 includes an ADC 261 and a latch circuit 266 for each column. Assuming that the number of columns is N, N ADCs 261 and N latch circuits 266 are arranged.
  • ADC 261 is a circuit that converts analog pixel signals into digital signals. This ADC 261 comprises capacitors 262 , 263 , a comparator 264 and a counter 265 . ADC 261 further performs CDS (Correlated Double Sampling) processing.
  • CDS Correlated Double Sampling
  • the comparator 264 is a comparator that compares the reference signal output from the DAC 220 and the pixel signal of the corresponding column.
  • the comparator 264 has a pair of input terminals, one of which receives the reference signal via the capacitor 262 and the other receives the pixel signal via the capacitor 263 .
  • Comparator 264 supplies the comparison result to counter 265 .
  • the counter 265 under the control of the timing control circuit 230, counts the count value over the period until the comparison result is inverted.
  • Counter 265 outputs a signal indicating the count value to latch circuit 266 as a digital signal.
  • a latch circuit 266 is a circuit that holds a digital signal.
  • the latch circuit 266 outputs the digital signal to the image processing section 280 in synchronization with the synchronization signal output from the horizontal transfer scanning section 270 .
  • capacitors 262 and 263 can be connected in parallel to one of the input terminals of comparator 264 (inverting input terminal, etc.). This also allows the input amplitude of comparator 264 to be reduced compared to FIG.
  • FIG. 8 is a circuit diagram showing one configuration example of the column amplifier 310 according to one embodiment.
  • Column amplifier 310 includes current reuse column amplifier 320 and amplifier 350 .
  • the current reuse column amplifier 320 is hereinafter referred to as CRCA (Current Reuse Column Amplifier).
  • CRCA Current Reuse Column Amplifier
  • FC-CRCA Fulled Cascode-CRCA
  • This FC-CRCA comprises an input stage 321 and a folded stage 340 .
  • the input stage 321 includes an input transistor 322 , an input side auto-zero switch 324 , a feedback capacitor 325 , a reference side capacitor 326 and a reference side current source transistor 327 .
  • a VSL capacitor 400 connected to the vertical signal line 259-n represents wiring capacitance between the vertical signal line 259-n and a reference voltage (eg, ground voltage).
  • the input transistor 322 for example, pMOS (p-channel Metal-Oxide Semiconductor Field-Effect Transistor) is used.
  • the input transistor 322 has a source connected to the vertical signal line 259 - n and a drain connected to the drain of the reference side current source transistor 327 .
  • the pixel circuit 250 generates a pixel signal by photoelectric conversion, and inputs this voltage as an input voltage Vin to the source of the input transistor 322 via the vertical signal line 259-n.
  • the input-side auto-zero switch 324 is a transistor that opens and closes the path between the gate and drain of the input transistor 322 according to the auto-zero signal AZ.
  • a feedback capacitor 325 is connected between the gate of the input transistor 322 and the output side auto-zero switch 344 and intermediate switch 346 .
  • a reference-side capacitor 326 is arranged between the gate of the input transistor 322 and a reference node of a predetermined reference voltage (eg, ground voltage).
  • a reference-side current source transistor 327 has a source connected to a reference node of a predetermined reference voltage (eg, ground voltage).
  • a predetermined reference voltage nbias is applied to the gate of the reference-side current source transistor 327, and a predetermined bias current is supplied according to this bias voltage nbias.
  • the reference-side current source transistor 327 is an example of a reference-side current source.
  • the folded stage 340 includes a power supply side current source transistor 342, cascode transistors 343 and 345, an output side auto-zero switch 344, and an intermediate switch 346.
  • the power supply side current source transistor 342 and the cascode transistor 343 are, for example, pMOS, and are connected in series to the power supply node.
  • a bias voltage pbias is applied to the gate of the current source transistor 342 on the power supply side, and a bias voltage pcas is applied to the gate of the cascode transistor 343 .
  • the power-side current source transistor 342 is an example of a power-side current source.
  • the output side auto-zero switch 344 is provided between the input stage 321 and the output node 328 .
  • a cascode transistor 345 is provided between the cascode transistor 343 and the reference side current source transistor 327 .
  • the cascode transistor 343 and the cascode transistor 345 share a drain and are connected in series.
  • a predetermined bias voltage ncas is applied to the gate of the cascode transistor 345 .
  • a node between the cascode transistors 343 and 345 is used as the output node 328 of the CRCA.
  • the output side auto-zero switch 344 is arranged between the feedback capacitor 325 and a predetermined reference voltage.
  • This predetermined reference voltage may be, for example, a reference voltage VR different from the reference voltage to which the reference-side capacitor 326 and the reference-side current source transistor 327 are connected. The same applies to the following figures.
  • Intermediate switch 346 is placed between feedback capacitor 325 and output node 328 .
  • the intermediate switch 346 is a switch to which an inverted signal xAZ of AZ applied to the input-side auto-zero switch 324 and the output-side auto-zero switch 344 is applied and which opens and closes according to this xAZ.
  • the intermediate switch 346 opens and closes exclusively with the input-side auto-zero switch 324 and the output-side auto-zero switch 344 .
  • the electric charge accumulated in the capacitor is appropriately reset by the auto-zero signal, and the reset state is appropriately released at the timing of reading the pixel signal.
  • the input side autozero switch 324 opens and closes the path between the input transistor 322 and the output node 328
  • the feedback capacitor 325 opens and closes the path between the input transistor 322 and the output node 328.
  • FC-CRCA the current flowing through the folded stage 340 is added to the input stage 321. This current can be small compared to the input stage 321 current. Since the input conversion noise of the power-side current source transistor 342 also becomes smaller as the current is reduced, it is better to reduce the current.
  • FC-CRCA output node 328 The output from FC-CRCA output node 328 is connected to amplifier 350 .
  • the provision of the folded stage 340 makes it possible to expand the range of the output signal by adding transistors in the form of cascodes.
  • the amplifier 350 is an amplification circuit and is connected between the output node 328 and the analog-to-digital converter 260 .
  • Amplifier 350 amplifies and outputs the signal output from output node 328 without feeding it back to CF-CRCA.
  • the column amplifier 310 inputs this output signal to the analog-to-digital converter 260 via the signal line 309-n. That is, both the signal input to the amplifier 350 and the signal output from the amplifier 350 are analog signals.
  • This amplifier 350 may be composed of, for example, a source follower.
  • the amplifier 350 separates the output of the CF-CRCA from the output capacitance, thereby reducing the effective capacitance seen from the VSL. Therefore, it is possible to shorten the settling time of the timing of outputting the signal from the solid-state imaging device 200 to the analog-to-digital converter 260 from the reset timing by the auto-zero signal AZ.
  • FIG. 9 is a circuit diagram showing the column amplifier 310 according to one embodiment.
  • the column amplifier 310 further includes a boost-side capacitor 351 for feeding back the signal output from the amplifier 350 in addition to the configuration of the first embodiment described above.
  • the amplifier 350 is a positive phase amplifier. That is, amplifier 350 is configured as a circuit that achieves signal amplification without inverting the result. Thus, if amplifier 350 is a positive phase amplifier, the output of amplifier 350 may be fed back to input stage 321 .
  • the boost-side capacitor 351 is a capacitor for feeding back the signal output by the positive-phase amplifier 350 to the input stage 321 .
  • the boost-side capacitor 351 By providing the positive phase amplifier and the boost side capacitor 351, it is possible to reduce the effective capacitance seen from the VSL.
  • FIG. 10 is a circuit diagram using an n-channel source follower as a non-limiting example of the positive-phase amplifier 350.
  • the positive phase amplifier 350 includes a boost transistor 352 and a boost side current source transistor 354 .
  • the boost transistor 352 is an nMOS to the gate of which the signal output from the output node 328 is applied, the drain is connected to the power supply voltage VDDH, and the source is connected to the drain of the boost side current source transistor 354 .
  • the boost-side current source transistor 354 is an nMOS with a bias voltage nbias applied to its gate, its drain connected to the source of the boost transistor 352, and its drain connected to the reference voltage.
  • the reference voltage to which the drain is connected may be the same reference voltage as the reference voltage to which the reference side capacitor 326 and the reference side current source transistor 327 are connected. The same applies to FIGS. 11 and 12 below.
  • the amplifier 350 forms an n-channel source follower with these two transistors.
  • the boost-side capacitor 351 is connected to a connection node between the source of the boost transistor 352 and the drain of the boost-side current source transistor 354, that is, a node outputting a signal obtained by amplifying the signal applied to the gate of the boost transistor 352, and an input Connected between the source of transistor 322 .
  • Vvsl be the source potential of the input transistor 322
  • Vbst be the output voltage of the amplifier 350
  • Cbst be the capacitance of the boost capacitor 351
  • Ibst be the current flowing from the source of the input transistor 322 to the boost capacitor 351.
  • A be the closed loop gain of CRCA and amplifier 350 .
  • the upper limit of the output is determined by the Vds of the boost transistor and the Vgs of the p-channel source follower. can be expanded.
  • a p-channel source follower may be used as long as it is amplified within the limits.
  • (Modification) 11 and 12 show a modification of the second embodiment described above.
  • the output of amplifier 350 may be the output of column amplifier 310, as shown in FIG.
  • the output of the source follower may be the output of the column amplifier 310, as shown in FIG.
  • the load capacitance (output capacitance) of the output destination is separated from the CRCA.
  • the signal amplified by the positive-phase amplifier 350 including the source follower can also be used as the output of the column amplifier 310.
  • a p-channel source follower may be used as a non-limiting example.
  • the feedback destination of the amplifier 350 is the source of the input transistor 322, but it is not limited to this form. As in each of the above-described embodiments, other feedback destinations may be used as long as they have a negative capacitance when viewed from VSL.
  • FIG. 13 is a circuit diagram showing another example of an unlimited feedback destination.
  • the positive phase amplifier 350 may be connected to the source of the cascode transistor 345 via the boost side capacitor 355 .
  • the same effect can be achieved with a smaller feedback capacitance.
  • FIG. 14 is a circuit diagram showing another example of an unlimited feedback destination.
  • the positive-phase amplifier 350 may be connected to a node between the drain of the power-side current source transistor 342 and the source of the cascode transistor 345 via a boost-side capacitor 356 . In this case as well, it is possible to achieve the same effect with a smaller feedback capacitance than in the case of feedback to the source of the input transistor 322 .
  • FIG. 15 is a circuit diagram showing another example of an unlimited feedback destination.
  • a positive phase amplifier 350 may be connected between the reference side current source transistor 327 and the reference side current source transistor 327' via a boost side capacitor 357.
  • FIG. In the example of FIG. 15, the reference side current source transistor in input stage 321 is split into two.
  • the two transistors may be nMOS with the same performance.
  • Bias voltages nbias1 and nbias2 for driving the respective transistors are applied to the respective transistors. For example, even if the bias voltages applied to the gates of the two transistors are the same, the bias voltages nbias1 and nbias2 may be short-circuited if the two transistors are capable of saturation operation.
  • the positive phase amplifier 350 is used in the examples of FIGS. 13 to 15, it may of course be a source follower, particularly an n-channel source follower.
  • the technology according to the present disclosure (this technology) can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated as the functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 17 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
  • the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031.
  • FIG. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to suppress the power consumption of the column amplifier, so it is possible to reduce the power consumption of the entire vehicle system.
  • the cascode transistor comprises two transistors connected in series; the output of the amplifier is connected to a node between the two transistors through a boost capacitor;
  • the solid-state imaging device according to any one of (1) to (3).
  • (6) a power supply side current source connected to a power supply node of a predetermined power supply voltage; a pair of cascode transistors connected between the power-side current source and the reference-side current source; further comprising the output node is a node between the pair of cascode transistors;
  • the solid-state imaging device according to any one of (1) to (5).
  • the output of the amplifier is connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor;
  • the output of the amplifier is connected to a node between the pair of cascode transistors and the power-side current source via a boost-side capacitor.
  • (9) a pixel circuit that generates an input voltage by photoelectric conversion; an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate; a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current; A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor, a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor; a reference-side capacitor connected between the gate of the input transistor and a reference node; an input side auto-zero switch connected between the gate of the input transistor and the output node; a feedback circuit having a cascode transistor connected between the reference-side current source and the drain of the input transistor; an intermediate switch connected between the feedback capacitor and the output node; an amplifier having a positive-phase amplifier that amplifies a signal output from the output node; an analog-to-digital converter that converts the voltage output from the

Abstract

[Problem] To shorten a settling time. [Solution] Provided is a solid-state imaging sensor being provided with a pixel circuit, an input transistor, a reference-side current source, a feedback circuit, a cascode transistor, and an amplifier. The pixel circuit generates an input voltage through photoelectric conversion. The input transistor has a source to which the input voltage is applied, and a drain from which an output voltage corresponding to the voltage is output between the source and a gate. The reference-side current source is connected to a reference node having a predetermined reference voltage and supplies a predetermined current. The feedback circuit includes a feedback capacitor that feeds a part of the predetermined current back to the gate of the input transistor and is connected between an output node from which the output voltage is output and the gate of the input transistor, a reference-side capacitor connected between the gate of the input transistor and the reference node, and an input-side auto zero switch connected between the gate of the input transistor and the output node. The cascode transistor is connected between the reference-side current source and the drain of the input transistor. An intermediate switch is connected between the feedback capacitor and the output node. The amplifier has a normal-phase amplifier that amplifies a signal output from the output node.

Description

固体撮像素子及び撮像装置Solid-state imaging device and imaging device
　本開示は、固体撮像素子及び撮像装置に関する。 The present disclosure relates to solid-state imaging devices and imaging devices.
　固体撮像素子等の画素においては、アナログ信号をデジタル信号に変換するために、シングルスロープ型等のADC(Analog to Digital Converter)が用いられる。ADCをカラムごとに配置する場合、一般に、カラムに沿って配線された垂直信号線の接地側のノードに電流源が接続され、このノードからのアナログ信号がADCに入力され、デジタル信号へと変換される。例えば、電圧を増幅する目的において、垂直信号線及び電流源の間のノードとADCとの間にアンプを挿入した固体撮像素子が研究されている。 In pixels such as solid-state imaging devices, single-slope ADCs (Analog to Digital Converters) are used to convert analog signals into digital signals. When an ADC is arranged for each column, a current source is generally connected to the node on the ground side of the vertical signal line wired along the column, and the analog signal from this node is input to the ADC and converted to a digital signal. be done. For example, for the purpose of amplifying the voltage, research is being conducted on a solid-state imaging device in which an amplifier is inserted between a node between a vertical signal line and a current source and an ADC.
　このような形態では、アンプを挿入することにより、アナログ信号の電圧を増幅している。このアンプを駆動するためには、垂直信号線の接地側の電流源に加えて、アンプの電源側にも電源を備える必要がある。この電源側の電流源の追加により電圧を増幅しない場合と比較して消費電力が増大してしまうおそれがある。 In such a form, the voltage of the analog signal is amplified by inserting an amplifier. In order to drive this amplifier, it is necessary to provide a power supply on the power supply side of the amplifier in addition to the current source on the ground side of the vertical signal line. The addition of the current source on the power supply side may increase the power consumption compared to the case where the voltage is not amplified.
特開2016-5054号公報JP 2016-5054 A
　そこで、本開示では、消費電力が小さく、かつ、セトリング時間を短縮するカラムごとに電圧を増幅する固体撮像素子を提供する。 Therefore, the present disclosure provides a solid-state imaging device that amplifies the voltage for each column with low power consumption and reduced settling time.
　一実施形態によれば、固体撮像素子は、
　光電変換により入力電圧を生成する、画素回路と、
　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
　を有する帰還回路と、
　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
　を備える。 According to one embodiment, the solid-state imaging device includes:
a pixel circuit that generates an input voltage by photoelectric conversion;
an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
a reference-side capacitor connected between the gate of the input transistor and a reference node;
an input side auto-zero switch connected between the gate of the input transistor and the output node;
a feedback circuit having
a cascode transistor connected between the reference-side current source and the drain of the input transistor;
an intermediate switch connected between the feedback capacitor and the output node;
an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
Prepare.
　前記出力ノードの出力をアナログ信号として出力してもよい。 The output of the output node may be output as an analog signal.
　前記アンプの出力をアナログ信号として出力してもよい。 The output of the amplifier may be output as an analog signal.
　前記アンプの出力は、ブースト側キャパシタを介して前記入力トランジスタのソースに接続されてもよい。 The output of the amplifier may be connected to the source of the input transistor via a boost capacitor.
　前記カスコードトランジスタは、直列に接続された2つのトランジスタを備えてもよく、前記アンプの出力は、ブースト側キャパシタを介して前記2つのトランジスタの間のノードに接続されてもよい。 The cascode transistor may comprise two transistors connected in series, and the output of the amplifier may be connected to a node between the two transistors via a boost capacitor.
　所定電源電圧の電源ノードに接続される、電源側電流源と、前記電源側電流源と、前記基準側電流源と、の間に接続される、一対のカスコードトランジスタと、をさらに備えてもよく、前記出力ノードは、前記一対のカスコードトランジスタの間のノードであってもよい。 A power supply side current source connected to a power supply node of a predetermined power supply voltage, and a pair of cascode transistors connected between the power supply side current source and the reference side current source. , the output node may be a node between the pair of cascode transistors.
　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記基準側電流源との間のノードに接続されてもよい。 The output of the amplifier may be connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor.
　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記電源側電流源との間のノードに接続されてもよい。 The output of the amplifier may be connected to a node between the pair of cascode transistors and the power supply side current source via a boost side capacitor.
　一実施形態によれば、固体撮像装置は、
　光電変換により入力電圧を生成する、画素回路と、
　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
　を有する帰還回路と、
　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
　前記出力ノードから出力される電圧、又は、前記アンプから出力される電圧を、デジタル信号に変換するアナログデジタル変換器と、
　を備える。 According to one embodiment, the solid-state imaging device includes:
a pixel circuit that generates an input voltage by photoelectric conversion;
an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
a reference-side capacitor connected between the gate of the input transistor and a reference node;
an input side auto-zero switch connected between the gate of the input transistor and the output node;
a feedback circuit having
a cascode transistor connected between the reference-side current source and the drain of the input transistor;
an intermediate switch connected between the feedback capacitor and the output node;
an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
an analog-to-digital converter that converts the voltage output from the output node or the voltage output from the amplifier into a digital signal;
Prepare.
一実施形態に係る撮像装置の構成例を示すブロック図。1 is a block diagram showing a configuration example of an imaging device according to an embodiment; FIG. 一実施形態に係る素子の積層構造の構成例を示す図。FIG. 4 is a diagram showing a configuration example of a laminated structure of an element according to one embodiment; 一実施形態に係る固体撮像素子の構成例を示すブロック図。1 is a block diagram showing a configuration example of a solid-state imaging device according to one embodiment; FIG. 一実施形態に係る画素回路の構成例を示す回路図。1 is a circuit diagram showing a configuration example of a pixel circuit according to one embodiment; FIG. 一実施形態に係る定電流源部の構成例を示すブロック図。3 is a block diagram showing a configuration example of a constant current source section according to one embodiment; FIG. 一実施形態に係るアナログデジタル変換部の構成例を示すブロック図。FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment; 一実施形態に係るアナログデジタル変換部の構成例を示すブロック図。FIG. 2 is a block diagram showing a configuration example of an analog-to-digital converter according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 一実施形態に係るカラムアンプの構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a column amplifier according to one embodiment; 車両制御システムの概略的な構成の一例を示すブロック図である。1 is a block diagram showing an example of a schematic configuration of a vehicle control system; FIG. 車外情報検出部及び撮像部の設置位置の一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
　以下、図面を参照して本開示における実施形態の説明をする。図面は、説明のために用いるものであり、実際の装置における各部の構成の形状、サイズ、又は、他の構成とのサイズの比等が図に示されている通りである必要はない。また、図面は、簡略化して書かれているため、図に書かれている以外にも実装上必要な構成は、適切に備えるものとする。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation, and it is not necessary that the shapes, sizes, ratios, etc. of the configuration of each part in the actual apparatus are as shown in the drawings. In addition, since the drawings are drawn in a simplified manner, it is assumed that configurations necessary for mounting other than those shown in the drawings are appropriately provided.
　(第1実施形態)
　図1は、一実施形態に係る撮像装置100の構成の一例を示すブロック図である。撮像装置100は、画像データ(動画におけるフレームデータを含む)を撮像するための装置であり、光学部110と、固体撮像素子200と、DSP(Digital Signal Processing)回路120と、を備える。また、撮像装置100は、表示部130と、操作部140と、バス150と、フレームメモリ160と、記憶部170と、電源部180と、を備える。 (First Embodiment)
FIG. 1 is a block diagram showing an example of the configuration of an imaging device 100 according to one embodiment. The imaging device 100 is a device for capturing image data (including frame data in moving images), and includes an optical section 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 also includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 .
　撮像装置100は、限定されない例として、デジタルスチルカメラ等のデジタルカメラ、撮像機能を有するスマートフォン、パーソナルコンピュータ等の端末、また、車載カメラ等に実装されていてもよい。 The imaging device 100 may be implemented in, as non-limiting examples, a digital camera such as a digital still camera, a terminal such as a smartphone having an imaging function, a personal computer, or an in-vehicle camera.
　光学部110は、被写体からの光を制御して、固体撮像素子200に導く。 The optical unit 110 controls the light from the subject and guides it to the solid-state imaging device 200.
　固体撮像素子200は、垂直同期信号に同期し、光電変換により受光した光の強度に基づいたアナログ信号を取得し、ADCによりデジタル画像信号に変換して出力する。ここで、垂直同期信号は、撮像のタイミングを示す所定周波数の臭気信号である。固体撮像素子200は、生成した画像データをDSP回路120に信号線209を介して供給する。 The solid-state imaging device 200 acquires an analog signal based on the intensity of the received light through photoelectric conversion in synchronization with a vertical synchronization signal, converts it into a digital image signal by an ADC, and outputs it. Here, the vertical synchronization signal is an odor signal with a predetermined frequency that indicates the timing of imaging. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
　DSP回路120は、固体撮像素子200からの画像データに対して、所定の信号処理を実行する。このDSP回路120は、処理した画像データをバス150を介して適切な箇所、例えば、フレームメモリ160、記憶部170等に出力する。 The DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200. The DSP circuit 120 outputs the processed image data via the bus 150 to an appropriate location such as the frame memory 160, the storage unit 170, and the like.
　表示部130は、画像データを表示する。表示部130は、限定されない例として、液晶パネル、有機EL(Electro Luminescence)パネルであってもよい。 The display unit 130 displays image data. The display unit 130 may be a liquid crystal panel or an organic EL (Electro Luminescence) panel as non-limiting examples.
　操作部140は、ユーザの操作に基づいて操作信号を生成する。操作部140は、限定されない例として、タッチパネル、キーボード、マウス、マイクといった入力インタフェースを備えている。 The operation unit 140 generates an operation signal based on the user's operation. The operation unit 140 includes, as non-limiting examples, input interfaces such as a touch panel, keyboard, mouse, and microphone.
　バス150は、光学部110、固体撮像素子200、DSP回路120、表示部130、操作部140、フレームメモリ160、記憶部170及び電源部180が互いにデータを送受信するために共有する経路である。 A bus 150 is a path shared by the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 for mutual data transmission/reception.
　フレームメモリ160は、例えば、画像データを処理のために一時的に保持する。 The frame memory 160 temporarily holds image data for processing, for example.
　記憶部170は、画像データ等の種々のデータを記憶する。 The storage unit 170 stores various data such as image data.
　電源部180は、固体撮像素子200、DPS回路120、表示部130等に電源を供給する。 The power supply unit 180 supplies power to the solid-state imaging device 200, the DPS circuit 120, the display unit 130, and the like.
　図2は、一実施形態に係る固体撮像素子200の積層構造の一例を示す図である。固体撮像素子200は、画素チップ201と、回路チップ202と、を備える。図に示すように、画素チップ201と、回路チップ202とは、積層されたチップとして構成される。これらのチップは、ビア等の接続部を介して電気的に接続される。ビアではなく、限定されない例として、Cu-Cu接合、マイクロバンプ等により接続されてもよい。 FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to one embodiment. A solid-state imaging device 200 includes a pixel chip 201 and a circuit chip 202 . As shown in the figure, the pixel chip 201 and the circuit chip 202 are configured as stacked chips. These chips are electrically connected through connections such as vias. Instead of vias, they may be connected by Cu--Cu junctions, microbumps, or the like, as non-limiting examples.
　図3は、一実施形態に係る固体撮像素子200の限定されない一構成例を示すブロック図である。固体撮像素子200は、行選択部210と、DAC(Digital to Analog Converter)220と、タイミング制御回路230と、画素アレイ部240と、定電流源部300と、アナログデジタル変換部260と、水平転送走査部270と、画像処理部280と、を備える。 FIG. 3 is a block diagram showing a non-limiting configuration example of the solid-state imaging device 200 according to one embodiment. The solid-state imaging device 200 includes a row selection section 210, a DAC (Digital to Analog Converter) 220, a timing control circuit 230, a pixel array section 240, a constant current source section 300, an analog-to-digital conversion section 260, and a horizontal transfer section. A scanning unit 270 and an image processing unit 280 are provided.
　行選択部210は、行を順に選択して駆動し、アナログの画素信号を、定電流源部300を介してアナログデジタル変換部260に出力する。 The row selection unit 210 sequentially selects and drives rows, and outputs analog pixel signals to the analog-to-digital conversion unit 260 via the constant current source unit 300.
　DAC 220は、DA(Digital to Analog)変換により参照信号を生成し、アナログデジタル変換部260に供給する。参照信号として、限定されない例として、のこぎり波、矩形波等のランプ信号が用いられてもよい。 The DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the analog-to-digital converter 260. As a reference signal, a ramp signal such as a sawtooth wave, a square wave, etc. may be used as non-limiting examples.
　タイミング制御回路230は、垂直同期信号Vsyncに同期して、行選択部210、DAC 220、定電流源部300、アナログデジタル変換部260及び水平転送走査部270のそれぞれの動作タイミングを制御する。 The timing control circuit 230 controls the operation timings of the row selection section 210, the DAC 220, the constant current source section 300, the analog-to-digital conversion section 260, and the horizontal transfer scanning section 270 in synchronization with the vertical synchronization signal Vsync.
　画素アレイ部240は、複数の画素回路250が2次元格子状に配列される。以下、所定の水平方向に配列された画素回路250の集合を行(ライン)と記載し、水平方向に垂直な方向に配列された画素回路250の集合を列(カラム)と記載する。 In the pixel array section 240, a plurality of pixel circuits 250 are arranged in a two-dimensional lattice. Hereinafter, a set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a row (line), and a set of pixel circuits 250 arranged in a direction perpendicular to the horizontal direction is referred to as a column (column).
　画素回路250は、行選択部210の制御に基づいて、光電変換により、アナログの画素信号を生成する。画素回路250のそれぞれは、垂直信号線259を介して画素信号を定電流源部300に出力する。 The pixel circuit 250 generates an analog pixel signal by photoelectric conversion under the control of the row selection section 210. Each pixel circuit 250 outputs a pixel signal to the constant current source section 300 via a vertical signal line 259 .
　アナログデジタル変換部260は、DAC 220が出力する参照信号を用いて、カラムごとにアナログの入力信号をデジタル信号に変換する。アナログデジタル変換部260は、水平転送走査部270の制御に基づいてデジタル信号を画像処理部280に供給する。 The analog-to-digital converter 260 uses the reference signal output by the DAC 220 to convert the analog input signal into a digital signal for each column. The analog-to-digital conversion section 260 supplies digital signals to the image processing section 280 under the control of the horizontal transfer scanning section 270 .
　水平転送走査部270は、アナログデジタル変換部260を制御して、デジタル信号を順に出力する。 The horizontal transfer scanning unit 270 controls the analog-to-digital conversion unit 260 to sequentially output digital signals.
　画像処理部280は、デジタル信号を配列した画像データに対して所定の画像処理を実行する。この画像処理部280は、処理後の画像データをDSP回路120へと出力する。 The image processing unit 280 executes predetermined image processing on image data in which digital signals are arranged. The image processing unit 280 outputs the processed image data to the DSP circuit 120 .
　固体撮像素子200内の上述の回路は、画素チップ201と、回路チップ202と、に適切に分散して配置される。一例として、画素アレイ部240が画素チップ201に配置され、画素アレイ部240以外のアナログデジタル変換部260等の回路は、回路チップ202に配置されてもよい。画素チップ201と回路チップ202とのそれぞれに配置する回路は、この組み合わせに限定されない。例えば、画素アレイ部240と、定電流源部300と、アナログデジタル変換部260内のコンパレータとを画素チップ201に配置し、それ以外の回路を回路チップ202に配置することもできる。 The above-described circuits in the solid-state imaging device 200 are appropriately dispersed and arranged in the pixel chip 201 and the circuit chip 202 . As an example, the pixel array section 240 may be arranged on the pixel chip 201 , and circuits other than the pixel array section 240 , such as the analog-to-digital conversion section 260 , may be arranged on the circuit chip 202 . The circuits arranged in each of the pixel chip 201 and the circuit chip 202 are not limited to this combination. For example, the pixel array section 240, the constant current source section 300, and the comparator in the analog-to-digital conversion section 260 can be arranged on the pixel chip 201, and the other circuits can be arranged on the circuit chip 202. FIG.
　図4は、一実施形態に係る画素回路250の一例を示す回路図である。画素回路250は、光電変換素子251と、転送トランジスタ252と、リセットトランジスタ253と、浮遊拡散層254と、増幅トランジスタ255と、選択トランジスタ256と、を備える。 FIG. 4 is a circuit diagram showing an example of the pixel circuit 250 according to one embodiment. The pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256.
　光電変換素子251は、入射光を光電変換して電荷を生成するものである。光電変換素子251は、限定されない例として、フォトダイオード、有機光電変換膜を備えて構成される。 The photoelectric conversion element 251 photoelectrically converts incident light to generate charges. The photoelectric conversion element 251 includes, as non-limiting examples, a photodiode and an organic photoelectric conversion film.
　転送トランジスタ252は、行選択部210からの転送信号TRGに従って、光電変換素子251から浮遊拡散層254へと電荷を転送するトランジスタである。 The transfer transistor 252 is a transistor that transfers charges from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with the transfer signal TRG from the row selection section 210 .
　リセットトランジスタ253は、行選択部210からのリセット信号RSTに従って、浮遊拡散層254に保持されている電荷を初期化する。 The reset transistor 253 initializes the charge held in the floating diffusion layer 254 according to the reset signal RST from the row selection section 210.
　浮遊拡散層254は、電荷を蓄積し、電荷量に応じた電圧を生成する。 The floating diffusion layer 254 accumulates charges and generates a voltage according to the amount of charges.
　増幅トランジスタ255は、浮遊拡散層254の電圧を増減するトランジスタである。 The amplification transistor 255 is a transistor that increases or decreases the voltage of the floating diffusion layer 254.
　選択トランジスタ256は、行選択部210からの選択信号SELに従って、増幅された電圧の信号を画素信号SIGとして出力するトランジスタである。列数をN(N: 整数)として、第n(n: [1, N]の整数)列の画素信号は、垂直信号線259-nを介して定電流源部300に伝送される。 The selection transistor 256 is a transistor that outputs an amplified voltage signal as the pixel signal SIG in accordance with the selection signal SEL from the row selection unit 210 . Assuming that the number of columns is N (N: integer), the pixel signals of the n-th (n: integer of [1, N]) column are transmitted to the constant current source section 300 via the vertical signal line 259-n.
　なお、画素回路250の回路は、光電変換により画素信号を適切に生成することができるものであれば、同図に例示したものに限定されない回路として構成されてもよい。 It should be noted that the circuit of the pixel circuit 250 may be configured as a circuit that is not limited to the one illustrated in the figure as long as it can appropriately generate a pixel signal by photoelectric conversion.
　図5は、一実施形態に係る定電流源部300の限定されない一例を示すブロック図である。定電流源部300には、カラムごとにカラムアンプ310が配置される。列数をNとすると、N個のカラムアンプ310が配置される。 FIG. 5 is a block diagram showing a non-limiting example of the constant current source section 300 according to one embodiment. A column amplifier 310 is arranged for each column in the constant current source section 300 . Assuming that the number of columns is N, N column amplifiers 310 are arranged.
　n個目のカラムアンプ310には、垂直信号線259-nを介して、対応する列の画素信号が入力される。カラムアンプ310は、その画素信号の電圧を増幅し、信号線309-nを介してアナログデジタル変換部260へと出力する。以下、画素信号の増幅前の電圧を入力電圧Vinとし、増幅後の電圧を出力電圧Voutとする。また、カラムアンプ310はタイミング制御回路230からのオートゼロ信号AZにより初期化される。 A pixel signal of the corresponding column is input to the n-th column amplifier 310 via the vertical signal line 259-n. The column amplifier 310 amplifies the voltage of the pixel signal and outputs it to the analog-to-digital converter 260 via the signal line 309-n. Hereinafter, the voltage of the pixel signal before amplification is referred to as input voltage Vin, and the voltage after amplification is referred to as output voltage Vout. Also, the column amplifier 310 is initialized by the auto-zero signal AZ from the timing control circuit 230 .
　図6は、一実施形態に係るアナログデジタル変換部260の限定されない一例を示すブロック図である。アナログデジタル変換部260は、カラムごとに、ADC 261と、ラッチ回路266と、が備えられる。列数をNとすると、ADC 261及びラッチ回路266は、N個ずつ配置される。 FIG. 6 is a block diagram showing a non-limiting example of the analog-to-digital converter 260 according to one embodiment. The analog-to-digital converter 260 includes an ADC 261 and a latch circuit 266 for each column. Assuming that the number of columns is N, N ADCs 261 and N latch circuits 266 are arranged.
　ADC 261は、アナログの画素信号をデジタル信号に変換する回路である。このADC 261は、キャパシタ262、263と、コンパレータ264と、カウンタ265と、を備える。ADC 261によりCDS(Correlated Double Sampling)処理がさらに実行される。 ADC 261 is a circuit that converts analog pixel signals into digital signals. This ADC 261 comprises capacitors 262 , 263 , a comparator 264 and a counter 265 . ADC 261 further performs CDS (Correlated Double Sampling) processing.
　コンパレータ264は、DAC 220から出力される参照信号と、対応する列の画素信号とを比較する比較器である。コンパレータ264は、一対の入力端子がもうけられ、それらの一方にキャパシタ262を介して参照信号が入力され、他方にキャパシタ263を介して画素信号が入力される。コンパレータ264は、比較結果をカウンタ265に供給する。 The comparator 264 is a comparator that compares the reference signal output from the DAC 220 and the pixel signal of the corresponding column. The comparator 264 has a pair of input terminals, one of which receives the reference signal via the capacitor 262 and the other receives the pixel signal via the capacitor 263 . Comparator 264 supplies the comparison result to counter 265 .
　カウンタ265は、タイミング制御回路230の制御に従い、比較結果が反転するまでの期間にわたり、計数値を係数するものである。カウンタ265は、計数値を示す信号をデジタル信号としてラッチ回路266に出力する。 The counter 265, under the control of the timing control circuit 230, counts the count value over the period until the comparison result is inverted. Counter 265 outputs a signal indicating the count value to latch circuit 266 as a digital signal.
　ラッチ回路266は、デジタル信号を保持する回路である。ラッチ回路266は、水平転送走査部270から出力される同期信号に同期して、デジタル信号を画像処理部280に出力する。 A latch circuit 266 is a circuit that holds a digital signal. The latch circuit 266 outputs the digital signal to the image processing section 280 in synchronization with the synchronization signal output from the horizontal transfer scanning section 270 .
　なお、図7に例示するように、ADC 261において、コンパレータ264の入力端子の一方(反転入力端子等)にキャパシタ262、263を並列に接続することもできる。これにより、コンパレータ264の入力振幅を図6と比較して低下させることもできる。 As illustrated in FIG. 7, in ADC 261, capacitors 262 and 263 can be connected in parallel to one of the input terminals of comparator 264 (inverting input terminal, etc.). This also allows the input amplitude of comparator 264 to be reduced compared to FIG.
　図8は、一実施形態に係るカラムアンプ310の一構成例を示す回路図である。カラムアンプ310は、電流リユースカラムアンプ320と、アンプ350と、を備える。以下、電流リユースカラムアンプ320をCRCA(Current Reuse Column Amplifier)と記載する。特に、本図に例示する電流リユースカラムアンプ320をFC-CRCA(Folded Cascode-CRCA)と記載する。このFC-CRCAは、入力段321と、フォールデッド段340と、を備える。 FIG. 8 is a circuit diagram showing one configuration example of the column amplifier 310 according to one embodiment. Column amplifier 310 includes current reuse column amplifier 320 and amplifier 350 . The current reuse column amplifier 320 is hereinafter referred to as CRCA (Current Reuse Column Amplifier). In particular, the current reuse column amplifier 320 illustrated in this figure is referred to as FC-CRCA (Folded Cascode-CRCA). This FC-CRCA comprises an input stage 321 and a folded stage 340 .
　入力段321は、入力トランジスタ322と、入力側オートゼロスイッチ324と、帰還キャパシタ325と、基準側キャパシタ326と、基準側電流源トランジスタ327と、を備える。本図において、垂直信号線259-nに接続されたVSLキャパシタ400は、垂直信号線259-nと、基準電圧(接地電圧等)との間の配線容量を表す。 The input stage 321 includes an input transistor 322 , an input side auto-zero switch 324 , a feedback capacitor 325 , a reference side capacitor 326 and a reference side current source transistor 327 . In this figure, a VSL capacitor 400 connected to the vertical signal line 259-n represents wiring capacitance between the vertical signal line 259-n and a reference voltage (eg, ground voltage).
　入力トランジスタ322は、例えば、pMOS(p-channel Metal-Oxide Semiconductor Field-Effect Transistor)が用いられる。入力トランジスタ322は、ソースが垂直信号線259-nに接続され、ドレインが基準側電流源トランジスタ327のドレインに接続される。画素回路250は、光電変換により画素信号を生成し、この電圧を入力電圧Vinとして垂直信号線259-nを介して入力トランジスタ322のソースに入力する。 For the input transistor 322, for example, pMOS (p-channel Metal-Oxide Semiconductor Field-Effect Transistor) is used. The input transistor 322 has a source connected to the vertical signal line 259 - n and a drain connected to the drain of the reference side current source transistor 327 . The pixel circuit 250 generates a pixel signal by photoelectric conversion, and inputs this voltage as an input voltage Vin to the source of the input transistor 322 via the vertical signal line 259-n.
　入力側オートゼロスイッチ324は、オートゼロ信号AZに従い、入力トランジスタ322のゲートとドレインとの間の経路を開閉するトランジスタである。 The input-side auto-zero switch 324 is a transistor that opens and closes the path between the gate and drain of the input transistor 322 according to the auto-zero signal AZ.
　帰還キャパシタ325は、入力トランジスタ322のゲートと出力側オートゼロスイッチ344、中間スイッチ346の間に接続される。 A feedback capacitor 325 is connected between the gate of the input transistor 322 and the output side auto-zero switch 344 and intermediate switch 346 .
　基準側キャパシタ326は、入力トランジスタ322のゲートと、所定の基準電圧(例えば、接地電圧)の基準ノードとの間に配置される。 A reference-side capacitor 326 is arranged between the gate of the input transistor 322 and a reference node of a predetermined reference voltage (eg, ground voltage).
　基準側電流源トランジスタ327は、ソースが所定の基準電圧(例えば、接地電圧)の基準ノードに接続される。基準側電流源トランジスタ327は、ゲートに所定のバイアス電圧nbiasが印加され、このバイス電圧nbiasに応じた所定のバイアス電流を供給する。なお、基準側電流源トランジスタ327は、基準側電流源の一例である。 A reference-side current source transistor 327 has a source connected to a reference node of a predetermined reference voltage (eg, ground voltage). A predetermined bias voltage nbias is applied to the gate of the reference-side current source transistor 327, and a predetermined bias current is supplied according to this bias voltage nbias. Note that the reference-side current source transistor 327 is an example of a reference-side current source.
　フォールデッド段340は、電源側電流源トランジスタ342と、カスコードトランジスタ343、345と、出力側オートゼロスイッチ344と、中間スイッチ346と、が備えられる。 The folded stage 340 includes a power supply side current source transistor 342, cascode transistors 343 and 345, an output side auto-zero switch 344, and an intermediate switch 346.
　電源側電流源トランジスタ342及びカスコードトランジスタ343は、例えば、pMOSであり、電源ノードに直列して接続される。電源側電流源トランジスタ342は、ゲートにバイアス電圧pbiasが印加され、カスコードトランジスタ343は、ゲートにバイアス電圧pcasが印加される。この電源側電流源トランジスタ342は、電源側電流源の一例である。 The power supply side current source transistor 342 and the cascode transistor 343 are, for example, pMOS, and are connected in series to the power supply node. A bias voltage pbias is applied to the gate of the current source transistor 342 on the power supply side, and a bias voltage pcas is applied to the gate of the cascode transistor 343 . The power-side current source transistor 342 is an example of a power-side current source.
　出力側オートゼロスイッチ344は、入力段321と、出力ノード328との間に備えられる。 The output side auto-zero switch 344 is provided between the input stage 321 and the output node 328 .
　カスコードトランジスタ345は、カスコードトランジスタ343と基準側電流源トランジスタ327との間に備えられる。カスコードトランジスタ343と、カスコードトランジスタ345は、ドレインを共有して直列接続される。また、カスコードトランジスタ345は、ゲートに所定のバイアス電圧ncasが印加される。 A cascode transistor 345 is provided between the cascode transistor 343 and the reference side current source transistor 327 . The cascode transistor 343 and the cascode transistor 345 share a drain and are connected in series. A predetermined bias voltage ncas is applied to the gate of the cascode transistor 345 .
　カスコードトランジスタ343、345の間のノードがCRCAの出力ノード328として用いられる。 A node between the cascode transistors 343 and 345 is used as the output node 328 of the CRCA.
　出力側オートゼロスイッチ344は、帰還キャパシタ325と、所定の基準電圧との間に配置される。この所定の基準電圧は、例えば、基準側キャパシタ326及び基準側電流源トランジスタ327が接続する基準電圧とは異なる基準電圧VRであってもよい。以下の図においても同様である。 The output side auto-zero switch 344 is arranged between the feedback capacitor 325 and a predetermined reference voltage. This predetermined reference voltage may be, for example, a reference voltage VR different from the reference voltage to which the reference-side capacitor 326 and the reference-side current source transistor 327 are connected. The same applies to the following figures.
　中間スイッチ346は、帰還キャパシタ325と、出力ノード328との間に配置される。中間スイッチ346は、入力側オートゼロスイッチ324及び出力側オートゼロスイッチ344に印加されるAZの反転信号xAZが印加され、このxAZに従って開閉するスイッチである。 Intermediate switch 346 is placed between feedback capacitor 325 and output node 328 . The intermediate switch 346 is a switch to which an inverted signal xAZ of AZ applied to the input-side auto-zero switch 324 and the output-side auto-zero switch 344 is applied and which opens and closes according to this xAZ.
　すなわち、中間スイッチ346は、入力側オートゼロスイッチ324及び出力側オートゼロスイッチ344と排他的に開閉する。この結果、オートゼロ信号により適切にキャパシタに蓄積されている電荷をリセットし、画素信号を読み取るタイミングにおいては、適切にリセット状態を解除する。 That is, the intermediate switch 346 opens and closes exclusively with the input-side auto-zero switch 324 and the output-side auto-zero switch 344 . As a result, the electric charge accumulated in the capacitor is appropriately reset by the auto-zero signal, and the reset state is appropriately released at the timing of reading the pixel signal.
　フォールデッド段340の図によれば、上記の入力側オートゼロスイッチ324は、入力トランジスタ322と出力ノード328との間の経路を開閉し、帰還キャパシタ325は、入力トランジスタ322と出力ノード328との間に配置されている。 According to the diagram of folded stage 340, the input side autozero switch 324 opens and closes the path between the input transistor 322 and the output node 328, and the feedback capacitor 325 opens and closes the path between the input transistor 322 and the output node 328. are placed in
　FC-CRCAでは、フォールデッド段340に流す電流が入力段321に追加される。この電流は、入力段321の電流と比較して小さくすることができる。電源側電流源トランジスタ342の入力換算ノイズも電流を減らした方が小さくなるため、電流は減らした方がよい。 In FC-CRCA, the current flowing through the folded stage 340 is added to the input stage 321. This current can be small compared to the input stage 321 current. Since the input conversion noise of the power-side current source transistor 342 also becomes smaller as the current is reduced, it is better to reduce the current.
　FC-CRCAの出力ノード328からの出力は、アンプ350に接続される。 The output from FC-CRCA output node 328 is connected to amplifier 350 .
　フォールデッド段340がないCRCAと比較すると、フォールデッド段340を備えることにより、カスコードの形態のトランジスタが追加されることにより、出力信号のレンジを拡大することが可能である。 　Compared to the CRCA without the folded stage 340, the provision of the folded stage 340 makes it possible to expand the range of the output signal by adding transistors in the form of cascodes.
　アンプ350は、増幅回路であり、出力ノード328とアナログデジタル変換部260との間に接続される。アンプ350は、出力ノード328から出力された信号を、CF-CRCAにフィードバックすることなく増幅して出力する。カラムアンプ310は、この出力された信号を、信号線309-nを介してアナログデジタル変換部260へと入力する。すなわち、アンプ350に入力される信号及びアンプ350が出力する信号は、ともにアナログ信号である。 The amplifier 350 is an amplification circuit and is connected between the output node 328 and the analog-to-digital converter 260 . Amplifier 350 amplifies and outputs the signal output from output node 328 without feeding it back to CF-CRCA. The column amplifier 310 inputs this output signal to the analog-to-digital converter 260 via the signal line 309-n. That is, both the signal input to the amplifier 350 and the signal output from the amplifier 350 are analog signals.
　このアンプ350は、例えば、ソースフォロアで構成されていてもよい。 This amplifier 350 may be composed of, for example, a source follower.
　以上のように、本実施形態のカラムアンプ310によれば、アンプ350によってCF-CRCAの出力と出力容量を切り離すことでVSLから見た実効容量を減らすことができる。このため、オートゼロ信号AZによるリセットタイミングから固体撮像素子200からの信号をアナログデジタル変換部260へと出力するタイミングのセトリング時間を短くすることが可能となる。 As described above, according to the column amplifier 310 of the present embodiment, the amplifier 350 separates the output of the CF-CRCA from the output capacitance, thereby reducing the effective capacitance seen from the VSL. Therefore, it is possible to shorten the settling time of the timing of outputting the signal from the solid-state imaging device 200 to the analog-to-digital converter 260 from the reset timing by the auto-zero signal AZ.
　(第2実施形態)
　フォールデッド段340に対して出力にアンプを備える一方で、第1実施形態とは異なり、この出力を入力段321へとフィードバックさせて出力ノードから出力される信号を増幅させてもよい。 (Second embodiment)
While an amplifier is provided at the output of the folded stage 340, unlike the first embodiment, this output may be fed back to the input stage 321 to amplify the signal output from the output node.
　図9は、一実施形態に係るカラムアンプ310を示す回路図である。カラムアンプ310は、前述の第1実施形態の構成にさらに、アンプ350から出力された信号をフィードバックするためのブースト側キャパシタ351を備える。 FIG. 9 is a circuit diagram showing the column amplifier 310 according to one embodiment. The column amplifier 310 further includes a boost-side capacitor 351 for feeding back the signal output from the amplifier 350 in addition to the configuration of the first embodiment described above.
　アンプ350は、正相の増幅器である。すなわち、アンプ350は、結果を反転することなく信号の増幅を実現する回路として構成される。このようにアンプ350が正相の増幅器である場合には、アンプ350の出力を入力段321へとフィードバックしてもよい。 The amplifier 350 is a positive phase amplifier. That is, amplifier 350 is configured as a circuit that achieves signal amplification without inverting the result. Thus, if amplifier 350 is a positive phase amplifier, the output of amplifier 350 may be fed back to input stage 321 .
　ブースト側キャパシタ351は、正相のアンプ350が出力する信号を入力段321へとフィードバックするためのキャパシタである。正相の増幅器と、ブースト側キャパシタ351を備えることにより、VSLから見える実効容量を削減することが可能となる。 The boost-side capacitor 351 is a capacitor for feeding back the signal output by the positive-phase amplifier 350 to the input stage 321 . By providing the positive phase amplifier and the boost side capacitor 351, it is possible to reduce the effective capacitance seen from the VSL.
　図10は、正相のアンプ350の限定されない一例としてnチャネルのソースフォロアを用いた回路図である。正相のアンプ350は、ブーストトランジスタ352と、ブースト側電流源トランジスタ354と、を備える。 FIG. 10 is a circuit diagram using an n-channel source follower as a non-limiting example of the positive-phase amplifier 350. FIG. The positive phase amplifier 350 includes a boost transistor 352 and a boost side current source transistor 354 .
　ブーストトランジスタ352は、出力ノード328から出力される信号がゲートに印加されるnMOSであり、ドレインが電源電圧VDDHに接続され、ソースがブースト側電流源トランジスタ354のドレインと接続される。 The boost transistor 352 is an nMOS to the gate of which the signal output from the output node 328 is applied, the drain is connected to the power supply voltage VDDH, and the source is connected to the drain of the boost side current source transistor 354 .
　ブースト側電流源トランジスタ354は、バイアス電圧nbiasがゲートに印加されるnMOSであり、ドレインがブーストトランジスタ352のソースと接続され、ドレインが基準電圧に接続される。このドレインが接続する基準電圧は、基準側キャパシタ326及び基準側電流源トランジスタ327が接続する基準電圧と同じ基準電圧であってもよい。以下、図11、図12においても同様である。 The boost-side current source transistor 354 is an nMOS with a bias voltage nbias applied to its gate, its drain connected to the source of the boost transistor 352, and its drain connected to the reference voltage. The reference voltage to which the drain is connected may be the same reference voltage as the reference voltage to which the reference side capacitor 326 and the reference side current source transistor 327 are connected. The same applies to FIGS. 11 and 12 below.
　アンプ350は、これら2つのトランジスタにより、nチャネルのソースフォロアを構成する。ブースト側キャパシタ351は、ブーストトランジスタ352のソースと、ブースト側電流源トランジスタ354のドレインとの接続ノード、すなわち、ブーストトランジスタ352のゲートに印加された信号を増幅した信号が出力されるノードと、入力トランジスタ322のソースとの間に接続される。 The amplifier 350 forms an n-channel source follower with these two transistors. The boost-side capacitor 351 is connected to a connection node between the source of the boost transistor 352 and the drain of the boost-side current source transistor 354, that is, a node outputting a signal obtained by amplifying the signal applied to the gate of the boost transistor 352, and an input Connected between the source of transistor 322 .
　ここで、入力トランジスタ322のソース電位をVvsl、アンプ350の出力電圧をVbst、ブースト側キャパシタ351の静電容量をCbst、入力トランジスタ322のソースからブースト側キャパシタ351へと流れる電流をIbstとおくと、以下の式が成立する。Aは、CRCAとアンプ350の閉ループゲインとする。
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000003
 Let Vvsl be the source potential of the input transistor 322, Vbst be the output voltage of the amplifier 350, Cbst be the capacitance of the boost capacitor 351, and Ibst be the current flowing from the source of the input transistor 322 to the boost capacitor 351. , the following formula holds: Let A be the closed loop gain of CRCA and amplifier 350 .
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000003
　式(3)からわかるように、本実施形態のようにnチャネルのソースフォロアを備えて形成されるアンプ350の出力を入力トランジスタ322にフィードバックすることにより、VSLから見てCbstを負性容量として見せることができる。正相のアンプ350を用いることにより、VSLから見える実効容量を減らすことができる。 As can be seen from the equation (3), by feeding back the output of the amplifier 350 formed with an n-channel source follower as in this embodiment to the input transistor 322, Cbst can be regarded as a negative capacitance from the viewpoint of VSL. I can show you. By using positive phase amplifier 350, the effective capacitance seen by VSL can be reduced.
　pチャネルのソースフォロアの場合には、ブーストトランジスタのVdsと、pチャネルのソースフォロアのVgsとで出力上限が決定されるが、nチャネルのソースフォロアとすることにより、この制限にとらわれずにレンジを拡大することができる。なお、制限内で増幅させる場合であれば、pチャネルのソースフォロアであってもかまわない。 In the case of a p-channel source follower, the upper limit of the output is determined by the Vds of the boost transistor and the Vgs of the p-channel source follower. can be expanded. A p-channel source follower may be used as long as it is amplified within the limits.
　(変形例)
　図11、図12は、前述した第2実施形態の変形例に係る形態である。例えば、図11に示すように、アンプ350の出力を、カラムアンプ310の出力としてもよい。同様に、図12に示すように、ソースフォロアの出力を、カラムアンプ310の出力としてもよい。このようなカラムアンプの場合、出力先の負荷容量(出力容量)がCRCAと切り離される。 (Modification)
11 and 12 show a modification of the second embodiment described above. For example, the output of amplifier 350 may be the output of column amplifier 310, as shown in FIG. Similarly, the output of the source follower may be the output of the column amplifier 310, as shown in FIG. In the case of such a column amplifier, the load capacitance (output capacitance) of the output destination is separated from the CRCA.
　このため、図11、図12に示すように、ソースフォロアを含む、正相のアンプ350の増幅後の信号を、カラムアンプ310の出力とすることもできる。なお、第2実施形態と同様に、pチャネルのソースフォロアを限定されない一例として用いてもよい。 Therefore, as shown in FIGS. 11 and 12, the signal amplified by the positive-phase amplifier 350 including the source follower can also be used as the output of the column amplifier 310. As in the second embodiment, a p-channel source follower may be used as a non-limiting example.
　(第3実施形態)
　前述の第2実施形態においては、アンプ350の帰還先を、入力トランジスタ322のソースとしたが、この形態に限られるものではない。前述の各実施形態と同様に、VSLから見て負性容量となる構成であれば他の帰還先であってもかまわない。 (Third Embodiment)
In the second embodiment described above, the feedback destination of the amplifier 350 is the source of the input transistor 322, but it is not limited to this form. As in each of the above-described embodiments, other feedback destinations may be used as long as they have a negative capacitance when viewed from VSL.
　図13は、帰還先の限定されない他の一例を示す回路図である。正相のアンプ350は、ブースト側キャパシタ355を介して、カスコードトランジスタ345のソースに接続されてもよい。この場合、入力トランジスタ322のソースに帰還する場合よりも、小さな帰還容量で同等の効果を奏することができる。 FIG. 13 is a circuit diagram showing another example of an unlimited feedback destination. The positive phase amplifier 350 may be connected to the source of the cascode transistor 345 via the boost side capacitor 355 . In this case, compared to the case of feedback to the source of the input transistor 322, the same effect can be achieved with a smaller feedback capacitance.
　図14は、帰還先の限定されない他の一例を示す回路図である。正相のアンプ350は、ブースト側キャパシタ356を介して、電源側電流源トランジスタ342のドレインと、カスコードトランジスタ345のソースとの間のノードに接続されてもよい。この場合も、入力トランジスタ322のソースに帰還する場合よりも、小さな帰還容量で同等の効果を奏することが可能である。 FIG. 14 is a circuit diagram showing another example of an unlimited feedback destination. The positive-phase amplifier 350 may be connected to a node between the drain of the power-side current source transistor 342 and the source of the cascode transistor 345 via a boost-side capacitor 356 . In this case as well, it is possible to achieve the same effect with a smaller feedback capacitance than in the case of feedback to the source of the input transistor 322 .
　図15は、帰還先の限定されない他の一例を示す回路図である。正相のアンプ350は、ブースト側キャパシタ357を介して、基準側電流源トランジスタ327と、基準側電流源トランジスタ327’との間に接続されてもよい。図15の例においては、入力段321における基準側電流源トランジスタが、2つに分割されている。この2つのトランジスタは、同じ性能を有するnMOSであってもよい。それぞれのトランジスタには、それぞれのトランジスタを駆動するためのバイアス電圧nbias1、nbias2が印加される。例えば、2つのトランジスタのゲートに印加させるバイアス電圧が同等でも、2つのトランジスタが飽和動作可能な場合には、バイアス電圧nbias1、nbias2は、短絡していてもよい。 FIG. 15 is a circuit diagram showing another example of an unlimited feedback destination. A positive phase amplifier 350 may be connected between the reference side current source transistor 327 and the reference side current source transistor 327' via a boost side capacitor 357. FIG. In the example of FIG. 15, the reference side current source transistor in input stage 321 is split into two. The two transistors may be nMOS with the same performance. Bias voltages nbias1 and nbias2 for driving the respective transistors are applied to the respective transistors. For example, even if the bias voltages applied to the gates of the two transistors are the same, the bias voltages nbias1 and nbias2 may be short-circuited if the two transistors are capable of saturation operation.
　この場合にも、図13、14の場合と同様に、入力トランジスタ322のソースに帰還するよりも小さな帰還容量で同等の効果を奏することが可能である。 　In this case as well, similar to the case of FIGS.
　図13から図15の例においては、正相のアンプ350としたが、これはもちろんソースフォロア、特にnチャネルのソースフォロアであってもよい。 Although the positive phase amplifier 350 is used in the examples of FIGS. 13 to 15, it may of course be a source follower, particularly an n-channel source follower.
　これらの場合には、以下の式が成立する。
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000006
 この式(6)から、前述のように入力トランジスタ322のソースに帰還させるよりも、負性容量が大きくなり、VSLから見える実効容量が削減可能であることがわかる。 In these cases, the following formula holds.
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000006
 From this equation (6), it can be seen that the negative capacitance becomes larger and the effective capacitance seen from VSL can be reduced compared to feedback to the source of the input transistor 322 as described above.
　移動体への応用例
　本開示に係る技術（本技術）は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。 Application Examples to Mobile Objects The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
　図16は、本開示に係る技術が適用され得る移動体制御システムの一例である車両制御システムの概略的な構成例を示すブロック図である。 FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
　車両制御システム１２０００は、通信ネットワーク１２００１を介して接続された複数の電子制御ユニットを備える。図16に示した例では、車両制御システム１２０００は、駆動系制御ユニット１２０１０、ボディ系制御ユニット１２０２０、車外情報検出ユニット１２０３０、車内情報検出ユニット１２０４０、及び統合制御ユニット１２０５０を備える。また、統合制御ユニット１２０５０の機能構成として、マイクロコンピュータ１２０５１、音声画像出力部１２０５２、及び車載ネットワークＩ／Ｆ（Interface）１２０５３が図示されている。 A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 16, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
　駆動系制御ユニット１２０１０は、各種プログラムにしたがって車両の駆動系に関連する装置の動作を制御する。例えば、駆動系制御ユニット１２０１０は、内燃機関又は駆動用モータ等の車両の駆動力を発生させるための駆動力発生装置、駆動力を車輪に伝達するための駆動力伝達機構、車両の舵角を調節するステアリング機構、及び、車両の制動力を発生させる制動装置等の制御装置として機能する。 The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
　ボディ系制御ユニット１２０２０は、各種プログラムにしたがって車体に装備された各種装置の動作を制御する。例えば、ボディ系制御ユニット１２０２０は、キーレスエントリシステム、スマートキーシステム、パワーウィンドウ装置、あるいは、ヘッドランプ、バックランプ、ブレーキランプ、ウィンカー又はフォグランプ等の各種ランプの制御装置として機能する。この場合、ボディ系制御ユニット１２０２０には、鍵を代替する携帯機から発信される電波又は各種スイッチの信号が入力され得る。ボディ系制御ユニット１２０２０は、これらの電波又は信号の入力を受け付け、車両のドアロック装置、パワーウィンドウ装置、ランプ等を制御する。 The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
　車外情報検出ユニット１２０３０は、車両制御システム１２０００を搭載した車両の外部の情報を検出する。例えば、車外情報検出ユニット１２０３０には、撮像部１２０３１が接続される。車外情報検出ユニット１２０３０は、撮像部１２０３１に車外の画像を撮像させるとともに、撮像された画像を受信する。車外情報検出ユニット１２０３０は、受信した画像に基づいて、人、車、障害物、標識又は路面上の文字等の物体検出処理又は距離検出処理を行ってもよい。 The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
　撮像部１２０３１は、光を受光し、その光の受光量に応じた電気信号を出力する光センサである。撮像部１２０３１は、電気信号を画像として出力することもできるし、測距の情報として出力することもできる。また、撮像部１２０３１が受光する光は、可視光であっても良いし、赤外線等の非可視光であっても良い。 The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
　車内情報検出ユニット１２０４０は、車内の情報を検出する。車内情報検出ユニット１２０４０には、例えば、運転者の状態を検出する運転者状態検出部１２０４１が接続される。運転者状態検出部１２０４１は、例えば運転者を撮像するカメラを含み、車内情報検出ユニット１２０４０は、運転者状態検出部１２０４１から入力される検出情報に基づいて、運転者の疲労度合い又は集中度合いを算出してもよいし、運転者が居眠りをしていないかを判別してもよい。 The in-vehicle information detection unit 12040 detects in-vehicle information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
　マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車内外の情報に基づいて、駆動力発生装置、ステアリング機構又は制動装置の制御目標値を演算し、駆動系制御ユニット１２０１０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車両の衝突回避あるいは衝撃緩和、車間距離に基づく追従走行、車速維持走行、車両の衝突警告、又は車両のレーン逸脱警告等を含むＡＤＡＳ（Advanced Driver Assistance System）の機能実現を目的とした協調制御を行うことができる。 The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０又は車内情報検出ユニット１２０４０で取得される車両の周囲の情報に基づいて駆動力発生装置、ステアリング機構又は制動装置等を制御することにより、運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
　また、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で取得される車外の情報に基づいて、ボディ系制御ユニット１２０３０に対して制御指令を出力することができる。例えば、マイクロコンピュータ１２０５１は、車外情報検出ユニット１２０３０で検知した先行車又は対向車の位置に応じてヘッドランプを制御し、ハイビームをロービームに切り替える等の防眩を図ることを目的とした協調制御を行うことができる。 Also, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
　音声画像出力部１２０５２は、車両の搭乗者又は車外に対して、視覚的又は聴覚的に情報を通知することが可能な出力装置へ音声及び画像のうちの少なくとも一方の出力信号を送信する。図16の例では、出力装置として、オーディオスピーカ１２０６１、表示部１２０６２及びインストルメントパネル１２０６３が例示されている。表示部１２０６２は、例えば、オンボードディスプレイ及びヘッドアップディスプレイの少なくとも一つを含んでいてもよい。 The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.
　図17は、撮像部１２０３１の設置位置の例を示す図である。 FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.
　図17では、撮像部１２０３１として、撮像部１２１０１、１２１０２、１２１０３、１２１０４、１２１０５を有する。 In FIG. 17, the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
　撮像部１２１０１、１２１０２、１２１０３、１２１０４、１２１０５は、例えば、車両１２１００のフロントノーズ、サイドミラー、リアバンパ、バックドア及び車室内のフロントガラスの上部等の位置に設けられる。フロントノーズに備えられる撮像部１２１０１及び車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として車両１２１００の前方の画像を取得する。サイドミラーに備えられる撮像部１２１０２、１２１０３は、主として車両１２１００の側方の画像を取得する。リアバンパ又はバックドアに備えられる撮像部１２１０４は、主として車両１２１００の後方の画像を取得する。車室内のフロントガラスの上部に備えられる撮像部１２１０５は、主として先行車両又は、歩行者、障害物、信号機、交通標識又は車線等の検出に用いられる。 The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
　なお、図17には、撮像部１２１０１ないし１２１０４の撮影範囲の一例が示されている。撮像範囲１２１１１は、フロントノーズに設けられた撮像部１２１０１の撮像範囲を示し、撮像範囲１２１１２，１２１１３は、それぞれサイドミラーに設けられた撮像部１２１０２，１２１０３の撮像範囲を示し、撮像範囲１２１１４は、リアバンパ又はバックドアに設けられた撮像部１２１０４の撮像範囲を示す。例えば、撮像部１２１０１ないし１２１０４で撮像された画像データが重ね合わせられることにより、車両１２１００を上方から見た俯瞰画像が得られる。 Note that FIG. 17 shows an example of the imaging range of the imaging units 12101 to 12104. FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、距離情報を取得する機能を有していてもよい。例えば、撮像部１２１０１ないし１２１０４の少なくとも１つは、複数の撮像素子からなるステレオカメラであってもよいし、位相差検出用の画素を有する撮像素子であってもよい。 At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を基に、撮像範囲１２１１１ないし１２１１４内における各立体物までの距離と、この距離の時間的変化（車両１２１００に対する相対速度）を求めることにより、特に車両１２１００の進行路上にある最も近い立体物で、車両１２１００と略同じ方向に所定の速度（例えば、０km/h以上）で走行する立体物を先行車として抽出することができる。さらに、マイクロコンピュータ１２０５１は、先行車の手前に予め確保すべき車間距離を設定し、自動ブレーキ制御（追従停止制御も含む）や自動加速制御（追従発進制御も含む）等を行うことができる。このように運転者の操作に拠らずに自律的に走行する自動運転等を目的とした協調制御を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
　例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４から得られた距離情報を元に、立体物に関する立体物データを、２輪車、普通車両、大型車両、歩行者、電柱等その他の立体物に分類して抽出し、障害物の自動回避に用いることができる。例えば、マイクロコンピュータ１２０５１は、車両１２１００の周辺の障害物を、車両１２１００のドライバが視認可能な障害物と視認困難な障害物とに識別する。そして、マイクロコンピュータ１２０５１は、各障害物との衝突の危険度を示す衝突リスクを判断し、衝突リスクが設定値以上で衝突可能性がある状況であるときには、オーディオスピーカ１２０６１や表示部１２０６２を介してドライバに警報を出力することや、駆動系制御ユニット１２０１０を介して強制減速や回避操舵を行うことで、衝突回避のための運転支援を行うことができる。 For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
　撮像部１２１０１ないし１２１０４の少なくとも１つは、赤外線を検出する赤外線カメラであってもよい。例えば、マイクロコンピュータ１２０５１は、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在するか否かを判定することで歩行者を認識することができる。かかる歩行者の認識は、例えば赤外線カメラとしての撮像部１２１０１ないし１２１０４の撮像画像における特徴点を抽出する手順と、物体の輪郭を示す一連の特徴点にパターンマッチング処理を行って歩行者か否かを判別する手順によって行われる。マイクロコンピュータ１２０５１が、撮像部１２１０１ないし１２１０４の撮像画像中に歩行者が存在すると判定し、歩行者を認識すると、音声画像出力部１２０５２は、当該認識された歩行者に強調のための方形輪郭線を重畳表示するように、表示部１２０６２を制御する。また、音声画像出力部１２０５２は、歩行者を示すアイコン等を所望の位置に表示するように表示部１２０６２を制御してもよい。 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
　以上、本開示に係る技術が適用され得る車両制御システムの一例について説明した。本開示に係る技術は、以上説明した構成のうち、例えば、撮像部12031に適用され得る。具体的には、図1の撮像装置100は、撮像部12031に適用することができる。撮像部12031に本開示に係る技術を適用することにより、カラムアンプの消費電力を抑制することができるため、車両システム全体の消費電力を削減することが可能となる。 An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. FIG. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to suppress the power consumption of the column amplifier, so it is possible to reduce the power consumption of the entire vehicle system.
　前述した実施形態は、以下のような形態としてもよい。 The above-described embodiment may be in the following form.
(1)
　光電変換により入力電圧を生成する、画素回路と、
　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
　を有する帰還回路と、
　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
　を備える固体撮像素子。 (1)
a pixel circuit that generates an input voltage by photoelectric conversion;
an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
a reference-side capacitor connected between the gate of the input transistor and a reference node;
an input side auto-zero switch connected between the gate of the input transistor and the output node;
a feedback circuit having
a cascode transistor connected between the reference-side current source and the drain of the input transistor;
an intermediate switch connected between the feedback capacitor and the output node;
an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
A solid-state image sensor.
(2)
　前記出力ノードの出力をアナログ信号として出力する、
　(1)に記載の固体撮像素子。 (2)
outputting the output of the output node as an analog signal;
(1) The solid-state imaging device according to (1).
(3)
　前記アンプの出力をアナログ信号として出力する、
　(1)に記載の固体撮像素子。 (3)
outputting the output of the amplifier as an analog signal;
(1) The solid-state imaging device according to (1).
(4)
　前記アンプの出力は、ブースト側キャパシタを介して前記入力トランジスタのソースに接続される、
　(1)から(3)のいずれかに記載の固体撮像素子。 (Four)
the output of the amplifier is connected to the source of the input transistor via a boost capacitor;
The solid-state imaging device according to any one of (1) to (3).
(5)
　前記カスコードトランジスタは、直列に接続された2つのトランジスタを備え、
　前記アンプの出力は、ブースト側キャパシタを介して前記2つのトランジスタの間のノードに接続される、
　(1)から(3)のいずれかに記載の固体撮像素子。 (Five)
the cascode transistor comprises two transistors connected in series;
the output of the amplifier is connected to a node between the two transistors through a boost capacitor;
The solid-state imaging device according to any one of (1) to (3).
(6)
　所定電源電圧の電源ノードに接続される、電源側電流源と、
　前記電源側電流源と、前記基準側電流源と、の間に接続される、一対のカスコードトランジスタと、
　をさらに備え、
　前記出力ノードは、前記一対のカスコードトランジスタの間のノードである、
　(1)から(5)のいずれかに記載の固体撮像素子。 (6)
a power supply side current source connected to a power supply node of a predetermined power supply voltage;
a pair of cascode transistors connected between the power-side current source and the reference-side current source;
further comprising
the output node is a node between the pair of cascode transistors;
The solid-state imaging device according to any one of (1) to (5).
(7)
　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記基準側電流源との間のノードに接続される、
　(6)に記載の固体撮像素子。 (7)
the output of the amplifier is connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor;
The solid-state imaging device according to (6).
(8)
　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記電源側電流源との間のノードに接続される、
　(6)に記載の固体撮像素子。 (8)
The output of the amplifier is connected to a node between the pair of cascode transistors and the power-side current source via a boost-side capacitor.
The solid-state imaging device according to (6).
(9)
　光電変換により入力電圧を生成する、画素回路と、
　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
　を有する帰還回路と、
　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
　前記出力ノードから出力される電圧、又は、前記アンプから出力される電圧を、デジタル信号に変換するアナログデジタル変換器と、
　を備える固体撮像装置。 (9)
a pixel circuit that generates an input voltage by photoelectric conversion;
an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
a reference-side capacitor connected between the gate of the input transistor and a reference node;
an input side auto-zero switch connected between the gate of the input transistor and the output node;
a feedback circuit having
a cascode transistor connected between the reference-side current source and the drain of the input transistor;
an intermediate switch connected between the feedback capacitor and the output node;
an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
an analog-to-digital converter that converts the voltage output from the output node or the voltage output from the amplifier into a digital signal;
A solid-state imaging device.
　本開示の態様は、前述した実施形態に限定されるものではなく、想到しうる種々の変形も含むものであり、本開示の効果も前述の内容に限定されるものではない。各実施形態における構成要素は、適切に組み合わされて適用されてもよい。すなわち、特許請求の範囲に規定された内容及びその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。 The aspects of the present disclosure are not limited to the above-described embodiments, but include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.
100: 撮像装置、
110: 光学部、
120: DSP回路、
130: 表示部、
140: 操作部、
150: バス、
160: フレームメモリ、
170: 記憶部、
180: 電源部、
200: 固体撮像素子、
201: 画素チップ、
202: 回路チップ、
210: 行選択部、
220: DAC、
230: タイミング制御回路、
240: 画素アレイ部、
250: 画素回路、
251: 光電変換素子、
252: 転送トランジスタ、
253: リセットトランジスタ、
254: 浮遊拡散層、
255: 増幅トランジスタ、
256: 選択トランジスタ、
260: アナログデジタル変換部、
261: ADC、
262、263: キャパシタ、
264: コンパレータ、
265: カウンタ、
266: ラッチ回路、
270: 水平転送走査部、
280: 画像処理部、
300: 定電流源部、
310: カラムアンプ、
320: 電流リユースカラムアンプ、
321: 入力段、
322: 入力トランジスタ、
324: 入力側オートゼロスイッチ、
325: 帰還キャパシタ、
326: 基準側キャパシタ、
327、327’: 基準側電流源トランジスタ、
330、346: 中間スイッチ、
343、345: カスコードトランジスタ、
340: フォールデッド段、
342: 電源側電流源トランジスタ、
344: 出力側オートゼロスイッチ、
350: アンプ、
351、355、356、357: ブースト側キャパシタ、
352: ブーストトランジスタ、
354: ブースト側電流源トランジスタ、
12031: 撮像部 100: Imager,
110: optics,
120: DSP circuit,
130: Display,
140: Operation unit,
150: bus,
160: frame memory,
170: Memory,
180: power supply,
200: Solid-state image sensor,
201: pixel chip,
202: Circuit Chip,
210: row selection unit,
220: DACs,
230: timing control circuit,
240: Pixel array section,
250: pixel circuit,
251: photoelectric conversion element,
252: transfer transistor,
253: reset transistor,
254: Floating Diffusion Layer,
255: amplification transistor,
256: select transistor,
260: analog-to-digital converter,
261: ADC,
262, 263: Capacitor,
264: Comparator,
265: Counter,
266: Latch circuit,
270: horizontal transfer scanning unit,
280: image processing unit,
300: constant current source,
310: column amplifier,
320: current reuse column amplifier,
321: input stage,
322: input transistor,
324: Input side auto-zero switch,
325: feedback capacitor,
326: reference side capacitor,
327, 327': reference side current source transistor,
330, 346: middle switch,
343, 345: cascode transistors,
340: Folded stage,
342: power side current source transistor,
344: Output side auto-zero switch,
350: amplifier,
351, 355, 356, 357: Boost side capacitor,
352: boost transistor,
354: Boost side current source transistor,
12031: Imaging unit

Claims (9)

  1. 　光電変換により入力電圧を生成する、画素回路と、
    　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
    　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
    　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
    　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
    　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
    　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
    　を有する帰還回路と、
    　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
    　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
    　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
    　を備える固体撮像素子。     a pixel circuit that generates an input voltage by photoelectric conversion;
    an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
    a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
    A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
    a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
    a reference-side capacitor connected between the gate of the input transistor and a reference node;
    an input side auto-zero switch connected between the gate of the input transistor and the output node;
    a feedback circuit having
    a cascode transistor connected between the reference-side current source and the drain of the input transistor;
    an intermediate switch connected between the feedback capacitor and the output node;
    an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
    A solid-state image sensor.
  2. 　前記出力ノードの出力をアナログ信号として出力する、
    　請求項1に記載の固体撮像素子。     outputting the output of the output node as an analog signal;
    2. The solid-state imaging device according to claim 1.
  3. 　前記アンプの出力をアナログ信号として出力する、
    　請求項1に記載の固体撮像素子。     outputting the output of the amplifier as an analog signal;
    2. The solid-state imaging device according to claim 1.
  4. 　前記アンプの出力は、ブースト側キャパシタを介して前記入力トランジスタのソースに接続される、
    　請求項1に記載の固体撮像素子。     the output of the amplifier is connected to the source of the input transistor via a boost capacitor;
    2. The solid-state imaging device according to claim 1.
  5. 　前記カスコードトランジスタは、直列に接続された2つのトランジスタを備え、
    　前記アンプの出力は、ブースト側キャパシタを介して前記2つのトランジスタの間のノードに接続される、
    　請求項1に記載の固体撮像素子。     the cascode transistor comprises two transistors connected in series;
    the output of the amplifier is connected to a node between the two transistors through a boost capacitor;
    2. The solid-state imaging device according to claim 1.
  6. 　所定電源電圧の電源ノードに接続される、電源側電流源と、
    　前記電源側電流源と、前記基準側電流源と、の間に接続される、一対のカスコードトランジスタと、
    　をさらに備え、
    　前記出力ノードは、前記一対のカスコードトランジスタの間のノードである、
    　請求項1に記載の固体撮像素子。     a power supply side current source connected to a power supply node of a predetermined power supply voltage;
    a pair of cascode transistors connected between the power-side current source and the reference-side current source;
    further comprising
    the output node is a node between the pair of cascode transistors;
    2. The solid-state imaging device according to claim 1.
  7. 　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記基準側電流源との間のノードに接続される、
    　請求項６に記載の固体撮像素子。     the output of the amplifier is connected to a node between the pair of cascode transistors and the reference current source via a boost capacitor;
    7. The solid-state imaging device according to claim 6.
  8. 　前記アンプの出力は、ブースト側キャパシタを介して前記一対のカスコードトランジスタと前記電源側電流源との間のノードに接続される、
    　請求項6に記載の固体撮像素子。     The output of the amplifier is connected to a node between the pair of cascode transistors and the power-side current source via a boost-side capacitor.
    7. The solid-state imaging device according to claim 6.
  9. 　光電変換により入力電圧を生成する、画素回路と、
    　ソースに前記入力電圧が印加され、ソースとゲートとの間に電圧に応じた出力電圧をドレインから出力する、入力トランジスタと、
    　所定基準電圧の基準ノードに接続され、所定電流を供給する、基準側電流源と、
    　前記所定電流の一部を前記入力トランジスタのゲートに帰還させる、帰還回路であって、
    　　前記出力電圧が出力される出力ノードと前記入力トランジスタのゲートとの間に接続される、帰還キャパシタと、
    　　前記入力トランジスタのゲートと基準ノードとの間に接続される、基準側キャパシタと、
    　　前記入力トランジスタのゲートと前記出力ノードとの間に接続される、入力側オートゼロスイッチと、
    　を有する帰還回路と、
    　前記基準側電流源と、前記入力トランジスタのドレインとの間に接続される、カスコードトランジスタと、
    　前記帰還キャパシタと、前記出力ノードとの間に接続される、中間スイッチと、
    　前記出力ノードから出力される信号を増幅する正相の増幅器を有する、アンプと、
    　前記出力ノードから出力される電圧、又は、前記アンプから出力される電圧を、デジタル信号に変換するアナログデジタル変換器と、
    　を備える固体撮像装置。     a pixel circuit that generates an input voltage by photoelectric conversion;
    an input transistor having a source to which the input voltage is applied and outputting from a drain an output voltage corresponding to the voltage between the source and the gate;
    a reference-side current source connected to a reference node of a predetermined reference voltage and supplying a predetermined current;
    A feedback circuit that feeds back a portion of the predetermined current to the gate of the input transistor,
    a feedback capacitor connected between an output node to which the output voltage is output and the gate of the input transistor;
    a reference-side capacitor connected between the gate of the input transistor and a reference node;
    an input side auto-zero switch connected between the gate of the input transistor and the output node;
    a feedback circuit having
    a cascode transistor connected between the reference-side current source and the drain of the input transistor;
    an intermediate switch connected between the feedback capacitor and the output node;
    an amplifier having a positive-phase amplifier that amplifies a signal output from the output node;
    an analog-to-digital converter that converts the voltage output from the output node or the voltage output from the amplifier into a digital signal;
    A solid-state imaging device.
PCT/JP2022/001634 2021-03-15 2022-01-18 Solid-state imaging sensor and imaging device WO2022196079A1 (en)

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JP2015119340A (en) * 2013-12-18 2015-06-25 キヤノン株式会社 Photoelectric conversion device drive method
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